1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if_bridge.h> 32 #include <net/dsa.h> 33 34 #include "b53_regs.h" 35 #include "b53_priv.h" 36 37 struct b53_mib_desc { 38 u8 size; 39 u8 offset; 40 const char *name; 41 }; 42 43 /* BCM5365 MIB counters */ 44 static const struct b53_mib_desc b53_mibs_65[] = { 45 { 8, 0x00, "TxOctets" }, 46 { 4, 0x08, "TxDropPkts" }, 47 { 4, 0x10, "TxBroadcastPkts" }, 48 { 4, 0x14, "TxMulticastPkts" }, 49 { 4, 0x18, "TxUnicastPkts" }, 50 { 4, 0x1c, "TxCollisions" }, 51 { 4, 0x20, "TxSingleCollision" }, 52 { 4, 0x24, "TxMultipleCollision" }, 53 { 4, 0x28, "TxDeferredTransmit" }, 54 { 4, 0x2c, "TxLateCollision" }, 55 { 4, 0x30, "TxExcessiveCollision" }, 56 { 4, 0x38, "TxPausePkts" }, 57 { 8, 0x44, "RxOctets" }, 58 { 4, 0x4c, "RxUndersizePkts" }, 59 { 4, 0x50, "RxPausePkts" }, 60 { 4, 0x54, "Pkts64Octets" }, 61 { 4, 0x58, "Pkts65to127Octets" }, 62 { 4, 0x5c, "Pkts128to255Octets" }, 63 { 4, 0x60, "Pkts256to511Octets" }, 64 { 4, 0x64, "Pkts512to1023Octets" }, 65 { 4, 0x68, "Pkts1024to1522Octets" }, 66 { 4, 0x6c, "RxOversizePkts" }, 67 { 4, 0x70, "RxJabbers" }, 68 { 4, 0x74, "RxAlignmentErrors" }, 69 { 4, 0x78, "RxFCSErrors" }, 70 { 8, 0x7c, "RxGoodOctets" }, 71 { 4, 0x84, "RxDropPkts" }, 72 { 4, 0x88, "RxUnicastPkts" }, 73 { 4, 0x8c, "RxMulticastPkts" }, 74 { 4, 0x90, "RxBroadcastPkts" }, 75 { 4, 0x94, "RxSAChanges" }, 76 { 4, 0x98, "RxFragments" }, 77 }; 78 79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 80 81 /* BCM63xx MIB counters */ 82 static const struct b53_mib_desc b53_mibs_63xx[] = { 83 { 8, 0x00, "TxOctets" }, 84 { 4, 0x08, "TxDropPkts" }, 85 { 4, 0x0c, "TxQoSPkts" }, 86 { 4, 0x10, "TxBroadcastPkts" }, 87 { 4, 0x14, "TxMulticastPkts" }, 88 { 4, 0x18, "TxUnicastPkts" }, 89 { 4, 0x1c, "TxCollisions" }, 90 { 4, 0x20, "TxSingleCollision" }, 91 { 4, 0x24, "TxMultipleCollision" }, 92 { 4, 0x28, "TxDeferredTransmit" }, 93 { 4, 0x2c, "TxLateCollision" }, 94 { 4, 0x30, "TxExcessiveCollision" }, 95 { 4, 0x38, "TxPausePkts" }, 96 { 8, 0x3c, "TxQoSOctets" }, 97 { 8, 0x44, "RxOctets" }, 98 { 4, 0x4c, "RxUndersizePkts" }, 99 { 4, 0x50, "RxPausePkts" }, 100 { 4, 0x54, "Pkts64Octets" }, 101 { 4, 0x58, "Pkts65to127Octets" }, 102 { 4, 0x5c, "Pkts128to255Octets" }, 103 { 4, 0x60, "Pkts256to511Octets" }, 104 { 4, 0x64, "Pkts512to1023Octets" }, 105 { 4, 0x68, "Pkts1024to1522Octets" }, 106 { 4, 0x6c, "RxOversizePkts" }, 107 { 4, 0x70, "RxJabbers" }, 108 { 4, 0x74, "RxAlignmentErrors" }, 109 { 4, 0x78, "RxFCSErrors" }, 110 { 8, 0x7c, "RxGoodOctets" }, 111 { 4, 0x84, "RxDropPkts" }, 112 { 4, 0x88, "RxUnicastPkts" }, 113 { 4, 0x8c, "RxMulticastPkts" }, 114 { 4, 0x90, "RxBroadcastPkts" }, 115 { 4, 0x94, "RxSAChanges" }, 116 { 4, 0x98, "RxFragments" }, 117 { 4, 0xa0, "RxSymbolErrors" }, 118 { 4, 0xa4, "RxQoSPkts" }, 119 { 8, 0xa8, "RxQoSOctets" }, 120 { 4, 0xb0, "Pkts1523to2047Octets" }, 121 { 4, 0xb4, "Pkts2048to4095Octets" }, 122 { 4, 0xb8, "Pkts4096to8191Octets" }, 123 { 4, 0xbc, "Pkts8192to9728Octets" }, 124 { 4, 0xc0, "RxDiscarded" }, 125 }; 126 127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 128 129 /* MIB counters */ 130 static const struct b53_mib_desc b53_mibs[] = { 131 { 8, 0x00, "TxOctets" }, 132 { 4, 0x08, "TxDropPkts" }, 133 { 4, 0x10, "TxBroadcastPkts" }, 134 { 4, 0x14, "TxMulticastPkts" }, 135 { 4, 0x18, "TxUnicastPkts" }, 136 { 4, 0x1c, "TxCollisions" }, 137 { 4, 0x20, "TxSingleCollision" }, 138 { 4, 0x24, "TxMultipleCollision" }, 139 { 4, 0x28, "TxDeferredTransmit" }, 140 { 4, 0x2c, "TxLateCollision" }, 141 { 4, 0x30, "TxExcessiveCollision" }, 142 { 4, 0x38, "TxPausePkts" }, 143 { 8, 0x50, "RxOctets" }, 144 { 4, 0x58, "RxUndersizePkts" }, 145 { 4, 0x5c, "RxPausePkts" }, 146 { 4, 0x60, "Pkts64Octets" }, 147 { 4, 0x64, "Pkts65to127Octets" }, 148 { 4, 0x68, "Pkts128to255Octets" }, 149 { 4, 0x6c, "Pkts256to511Octets" }, 150 { 4, 0x70, "Pkts512to1023Octets" }, 151 { 4, 0x74, "Pkts1024to1522Octets" }, 152 { 4, 0x78, "RxOversizePkts" }, 153 { 4, 0x7c, "RxJabbers" }, 154 { 4, 0x80, "RxAlignmentErrors" }, 155 { 4, 0x84, "RxFCSErrors" }, 156 { 8, 0x88, "RxGoodOctets" }, 157 { 4, 0x90, "RxDropPkts" }, 158 { 4, 0x94, "RxUnicastPkts" }, 159 { 4, 0x98, "RxMulticastPkts" }, 160 { 4, 0x9c, "RxBroadcastPkts" }, 161 { 4, 0xa0, "RxSAChanges" }, 162 { 4, 0xa4, "RxFragments" }, 163 { 4, 0xa8, "RxJumboPkts" }, 164 { 4, 0xac, "RxSymbolErrors" }, 165 { 4, 0xc0, "RxDiscarded" }, 166 }; 167 168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 169 170 static const struct b53_mib_desc b53_mibs_58xx[] = { 171 { 8, 0x00, "TxOctets" }, 172 { 4, 0x08, "TxDropPkts" }, 173 { 4, 0x0c, "TxQPKTQ0" }, 174 { 4, 0x10, "TxBroadcastPkts" }, 175 { 4, 0x14, "TxMulticastPkts" }, 176 { 4, 0x18, "TxUnicastPKts" }, 177 { 4, 0x1c, "TxCollisions" }, 178 { 4, 0x20, "TxSingleCollision" }, 179 { 4, 0x24, "TxMultipleCollision" }, 180 { 4, 0x28, "TxDeferredCollision" }, 181 { 4, 0x2c, "TxLateCollision" }, 182 { 4, 0x30, "TxExcessiveCollision" }, 183 { 4, 0x34, "TxFrameInDisc" }, 184 { 4, 0x38, "TxPausePkts" }, 185 { 4, 0x3c, "TxQPKTQ1" }, 186 { 4, 0x40, "TxQPKTQ2" }, 187 { 4, 0x44, "TxQPKTQ3" }, 188 { 4, 0x48, "TxQPKTQ4" }, 189 { 4, 0x4c, "TxQPKTQ5" }, 190 { 8, 0x50, "RxOctets" }, 191 { 4, 0x58, "RxUndersizePkts" }, 192 { 4, 0x5c, "RxPausePkts" }, 193 { 4, 0x60, "RxPkts64Octets" }, 194 { 4, 0x64, "RxPkts65to127Octets" }, 195 { 4, 0x68, "RxPkts128to255Octets" }, 196 { 4, 0x6c, "RxPkts256to511Octets" }, 197 { 4, 0x70, "RxPkts512to1023Octets" }, 198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 199 { 4, 0x78, "RxOversizePkts" }, 200 { 4, 0x7c, "RxJabbers" }, 201 { 4, 0x80, "RxAlignmentErrors" }, 202 { 4, 0x84, "RxFCSErrors" }, 203 { 8, 0x88, "RxGoodOctets" }, 204 { 4, 0x90, "RxDropPkts" }, 205 { 4, 0x94, "RxUnicastPkts" }, 206 { 4, 0x98, "RxMulticastPkts" }, 207 { 4, 0x9c, "RxBroadcastPkts" }, 208 { 4, 0xa0, "RxSAChanges" }, 209 { 4, 0xa4, "RxFragments" }, 210 { 4, 0xa8, "RxJumboPkt" }, 211 { 4, 0xac, "RxSymblErr" }, 212 { 4, 0xb0, "InRangeErrCount" }, 213 { 4, 0xb4, "OutRangeErrCount" }, 214 { 4, 0xb8, "EEELpiEvent" }, 215 { 4, 0xbc, "EEELpiDuration" }, 216 { 4, 0xc0, "RxDiscard" }, 217 { 4, 0xc8, "TxQPKTQ6" }, 218 { 4, 0xcc, "TxQPKTQ7" }, 219 { 4, 0xd0, "TxPkts64Octets" }, 220 { 4, 0xd4, "TxPkts65to127Octets" }, 221 { 4, 0xd8, "TxPkts128to255Octets" }, 222 { 4, 0xdc, "TxPkts256to511Ocets" }, 223 { 4, 0xe0, "TxPkts512to1023Ocets" }, 224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 225 }; 226 227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 228 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 230 { 231 unsigned int i; 232 233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 234 235 for (i = 0; i < 10; i++) { 236 u8 vta; 237 238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 239 if (!(vta & VTA_START_CMD)) 240 return 0; 241 242 usleep_range(100, 200); 243 } 244 245 return -EIO; 246 } 247 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 249 struct b53_vlan *vlan) 250 { 251 if (is5325(dev)) { 252 u32 entry = 0; 253 254 if (vlan->members) { 255 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 256 VA_UNTAG_S_25) | vlan->members; 257 if (dev->core_rev >= 3) 258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 259 else 260 entry |= VA_VALID_25; 261 } 262 263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 265 VTA_RW_STATE_WR | VTA_RW_OP_EN); 266 } else if (is5365(dev)) { 267 u16 entry = 0; 268 269 if (vlan->members) 270 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 272 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 275 VTA_RW_STATE_WR | VTA_RW_OP_EN); 276 } else { 277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 279 (vlan->untag << VTE_UNTAG_S) | vlan->members); 280 281 b53_do_vlan_op(dev, VTA_CMD_WRITE); 282 } 283 284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 285 vid, vlan->members, vlan->untag); 286 } 287 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 289 struct b53_vlan *vlan) 290 { 291 if (is5325(dev)) { 292 u32 entry = 0; 293 294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 295 VTA_RW_STATE_RD | VTA_RW_OP_EN); 296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 297 298 if (dev->core_rev >= 3) 299 vlan->valid = !!(entry & VA_VALID_25_R4); 300 else 301 vlan->valid = !!(entry & VA_VALID_25); 302 vlan->members = entry & VA_MEMBER_MASK; 303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 304 305 } else if (is5365(dev)) { 306 u16 entry = 0; 307 308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 309 VTA_RW_STATE_WR | VTA_RW_OP_EN); 310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 311 312 vlan->valid = !!(entry & VA_VALID_65); 313 vlan->members = entry & VA_MEMBER_MASK; 314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 315 } else { 316 u32 entry = 0; 317 318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 319 b53_do_vlan_op(dev, VTA_CMD_READ); 320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 321 vlan->members = entry & VTE_MEMBERS; 322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 323 vlan->valid = true; 324 } 325 } 326 327 static void b53_set_forwarding(struct b53_device *dev, int enable) 328 { 329 u8 mgmt; 330 331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 332 333 if (enable) 334 mgmt |= SM_SW_FWD_EN; 335 else 336 mgmt &= ~SM_SW_FWD_EN; 337 338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 339 340 /* Include IMP port in dumb forwarding mode 341 */ 342 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 343 mgmt |= B53_MII_DUMB_FWDG_EN; 344 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 345 } 346 347 static void b53_enable_vlan(struct b53_device *dev, bool enable) 348 { 349 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 350 351 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 352 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 353 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 354 355 if (is5325(dev) || is5365(dev)) { 356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 358 } else if (is63xx(dev)) { 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 361 } else { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 364 } 365 366 mgmt &= ~SM_SW_FWD_MODE; 367 368 if (enable) { 369 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 370 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 371 vc4 &= ~VC4_ING_VID_CHECK_MASK; 372 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 373 vc5 |= VC5_DROP_VTABLE_MISS; 374 375 if (is5325(dev)) 376 vc0 &= ~VC0_RESERVED_1; 377 378 if (is5325(dev) || is5365(dev)) 379 vc1 |= VC1_RX_MCST_TAG_EN; 380 381 } else { 382 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 383 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 384 vc4 &= ~VC4_ING_VID_CHECK_MASK; 385 vc5 &= ~VC5_DROP_VTABLE_MISS; 386 387 if (is5325(dev) || is5365(dev)) 388 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 389 else 390 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 391 392 if (is5325(dev) || is5365(dev)) 393 vc1 &= ~VC1_RX_MCST_TAG_EN; 394 } 395 396 if (!is5325(dev) && !is5365(dev)) 397 vc5 &= ~VC5_VID_FFF_EN; 398 399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 400 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 401 402 if (is5325(dev) || is5365(dev)) { 403 /* enable the high 8 bit vid check on 5325 */ 404 if (is5325(dev) && enable) 405 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 406 VC3_HIGH_8BIT_EN); 407 else 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 409 410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 412 } else if (is63xx(dev)) { 413 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 415 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 416 } else { 417 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 420 } 421 422 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 423 } 424 425 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 426 { 427 u32 port_mask = 0; 428 u16 max_size = JMS_MIN_SIZE; 429 430 if (is5325(dev) || is5365(dev)) 431 return -EINVAL; 432 433 if (enable) { 434 port_mask = dev->enabled_ports; 435 max_size = JMS_MAX_SIZE; 436 if (allow_10_100) 437 port_mask |= JPM_10_100_JUMBO_EN; 438 } 439 440 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 441 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 442 } 443 444 static int b53_flush_arl(struct b53_device *dev, u8 mask) 445 { 446 unsigned int i; 447 448 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 449 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 450 451 for (i = 0; i < 10; i++) { 452 u8 fast_age_ctrl; 453 454 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 455 &fast_age_ctrl); 456 457 if (!(fast_age_ctrl & FAST_AGE_DONE)) 458 goto out; 459 460 msleep(1); 461 } 462 463 return -ETIMEDOUT; 464 out: 465 /* Only age dynamic entries (default behavior) */ 466 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 467 return 0; 468 } 469 470 static int b53_fast_age_port(struct b53_device *dev, int port) 471 { 472 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 473 474 return b53_flush_arl(dev, FAST_AGE_PORT); 475 } 476 477 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 478 { 479 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 480 481 return b53_flush_arl(dev, FAST_AGE_VLAN); 482 } 483 484 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 485 { 486 struct b53_device *dev = ds->priv; 487 unsigned int i; 488 u16 pvlan; 489 490 /* Enable the IMP port to be in the same VLAN as the other ports 491 * on a per-port basis such that we only have Port i and IMP in 492 * the same VLAN. 493 */ 494 b53_for_each_port(dev, i) { 495 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 496 pvlan |= BIT(cpu_port); 497 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 498 } 499 } 500 EXPORT_SYMBOL(b53_imp_vlan_setup); 501 502 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 503 { 504 struct b53_device *dev = ds->priv; 505 unsigned int cpu_port = ds->ports[port].cpu_dp->index; 506 int ret = 0; 507 u16 pvlan; 508 509 if (dev->ops->irq_enable) 510 ret = dev->ops->irq_enable(dev, port); 511 if (ret) 512 return ret; 513 514 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 515 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 516 517 /* Set this port, and only this one to be in the default VLAN, 518 * if member of a bridge, restore its membership prior to 519 * bringing down this port. 520 */ 521 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 522 pvlan &= ~0x1ff; 523 pvlan |= BIT(port); 524 pvlan |= dev->ports[port].vlan_ctl_mask; 525 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 526 527 b53_imp_vlan_setup(ds, cpu_port); 528 529 /* If EEE was enabled, restore it */ 530 if (dev->ports[port].eee.eee_enabled) 531 b53_eee_enable_set(ds, port, true); 532 533 return 0; 534 } 535 EXPORT_SYMBOL(b53_enable_port); 536 537 void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 538 { 539 struct b53_device *dev = ds->priv; 540 u8 reg; 541 542 /* Disable Tx/Rx for the port */ 543 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 544 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 545 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 546 547 if (dev->ops->irq_disable) 548 dev->ops->irq_disable(dev, port); 549 } 550 EXPORT_SYMBOL(b53_disable_port); 551 552 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 553 { 554 bool tag_en = !(ds->ops->get_tag_protocol(ds, port) == 555 DSA_TAG_PROTO_NONE); 556 struct b53_device *dev = ds->priv; 557 u8 hdr_ctl, val; 558 u16 reg; 559 560 /* Resolve which bit controls the Broadcom tag */ 561 switch (port) { 562 case 8: 563 val = BRCM_HDR_P8_EN; 564 break; 565 case 7: 566 val = BRCM_HDR_P7_EN; 567 break; 568 case 5: 569 val = BRCM_HDR_P5_EN; 570 break; 571 default: 572 val = 0; 573 break; 574 } 575 576 /* Enable Broadcom tags for IMP port */ 577 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 578 if (tag_en) 579 hdr_ctl |= val; 580 else 581 hdr_ctl &= ~val; 582 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 583 584 /* Registers below are only accessible on newer devices */ 585 if (!is58xx(dev)) 586 return; 587 588 /* Enable reception Broadcom tag for CPU TX (switch RX) to 589 * allow us to tag outgoing frames 590 */ 591 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 592 if (tag_en) 593 reg &= ~BIT(port); 594 else 595 reg |= BIT(port); 596 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 597 598 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 599 * allow delivering frames to the per-port net_devices 600 */ 601 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 602 if (tag_en) 603 reg &= ~BIT(port); 604 else 605 reg |= BIT(port); 606 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 607 } 608 EXPORT_SYMBOL(b53_brcm_hdr_setup); 609 610 static void b53_enable_cpu_port(struct b53_device *dev, int port) 611 { 612 u8 port_ctrl; 613 614 /* BCM5325 CPU port is at 8 */ 615 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 616 port = B53_CPU_PORT; 617 618 port_ctrl = PORT_CTRL_RX_BCST_EN | 619 PORT_CTRL_RX_MCST_EN | 620 PORT_CTRL_RX_UCST_EN; 621 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 622 623 b53_brcm_hdr_setup(dev->ds, port); 624 } 625 626 static void b53_enable_mib(struct b53_device *dev) 627 { 628 u8 gc; 629 630 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 631 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 632 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 633 } 634 635 int b53_configure_vlan(struct dsa_switch *ds) 636 { 637 struct b53_device *dev = ds->priv; 638 struct b53_vlan vl = { 0 }; 639 int i; 640 641 /* clear all vlan entries */ 642 if (is5325(dev) || is5365(dev)) { 643 for (i = 1; i < dev->num_vlans; i++) 644 b53_set_vlan_entry(dev, i, &vl); 645 } else { 646 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 647 } 648 649 b53_enable_vlan(dev, false); 650 651 b53_for_each_port(dev, i) 652 b53_write16(dev, B53_VLAN_PAGE, 653 B53_VLAN_PORT_DEF_TAG(i), 1); 654 655 if (!is5325(dev) && !is5365(dev)) 656 b53_set_jumbo(dev, dev->enable_jumbo, false); 657 658 return 0; 659 } 660 EXPORT_SYMBOL(b53_configure_vlan); 661 662 static void b53_switch_reset_gpio(struct b53_device *dev) 663 { 664 int gpio = dev->reset_gpio; 665 666 if (gpio < 0) 667 return; 668 669 /* Reset sequence: RESET low(50ms)->high(20ms) 670 */ 671 gpio_set_value(gpio, 0); 672 mdelay(50); 673 674 gpio_set_value(gpio, 1); 675 mdelay(20); 676 677 dev->current_page = 0xff; 678 } 679 680 static int b53_switch_reset(struct b53_device *dev) 681 { 682 unsigned int timeout = 1000; 683 u8 mgmt, reg; 684 685 b53_switch_reset_gpio(dev); 686 687 if (is539x(dev)) { 688 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 689 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 690 } 691 692 /* This is specific to 58xx devices here, do not use is58xx() which 693 * covers the larger Starfigther 2 family, including 7445/7278 which 694 * still use this driver as a library and need to perform the reset 695 * earlier. 696 */ 697 if (dev->chip_id == BCM58XX_DEVICE_ID || 698 dev->chip_id == BCM583XX_DEVICE_ID) { 699 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 700 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 701 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 702 703 do { 704 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 705 if (!(reg & SW_RST)) 706 break; 707 708 usleep_range(1000, 2000); 709 } while (timeout-- > 0); 710 711 if (timeout == 0) 712 return -ETIMEDOUT; 713 } 714 715 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 716 717 if (!(mgmt & SM_SW_FWD_EN)) { 718 mgmt &= ~SM_SW_FWD_MODE; 719 mgmt |= SM_SW_FWD_EN; 720 721 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 722 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 723 724 if (!(mgmt & SM_SW_FWD_EN)) { 725 dev_err(dev->dev, "Failed to enable switch!\n"); 726 return -EINVAL; 727 } 728 } 729 730 b53_enable_mib(dev); 731 732 return b53_flush_arl(dev, FAST_AGE_STATIC); 733 } 734 735 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 736 { 737 struct b53_device *priv = ds->priv; 738 u16 value = 0; 739 int ret; 740 741 if (priv->ops->phy_read16) 742 ret = priv->ops->phy_read16(priv, addr, reg, &value); 743 else 744 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 745 reg * 2, &value); 746 747 return ret ? ret : value; 748 } 749 750 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 751 { 752 struct b53_device *priv = ds->priv; 753 754 if (priv->ops->phy_write16) 755 return priv->ops->phy_write16(priv, addr, reg, val); 756 757 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 758 } 759 760 static int b53_reset_switch(struct b53_device *priv) 761 { 762 /* reset vlans */ 763 priv->enable_jumbo = false; 764 765 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 766 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 767 768 priv->serdes_lane = B53_INVALID_LANE; 769 770 return b53_switch_reset(priv); 771 } 772 773 static int b53_apply_config(struct b53_device *priv) 774 { 775 /* disable switching */ 776 b53_set_forwarding(priv, 0); 777 778 b53_configure_vlan(priv->ds); 779 780 /* enable switching */ 781 b53_set_forwarding(priv, 1); 782 783 return 0; 784 } 785 786 static void b53_reset_mib(struct b53_device *priv) 787 { 788 u8 gc; 789 790 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 791 792 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 793 msleep(1); 794 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 795 msleep(1); 796 } 797 798 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 799 { 800 if (is5365(dev)) 801 return b53_mibs_65; 802 else if (is63xx(dev)) 803 return b53_mibs_63xx; 804 else if (is58xx(dev)) 805 return b53_mibs_58xx; 806 else 807 return b53_mibs; 808 } 809 810 static unsigned int b53_get_mib_size(struct b53_device *dev) 811 { 812 if (is5365(dev)) 813 return B53_MIBS_65_SIZE; 814 else if (is63xx(dev)) 815 return B53_MIBS_63XX_SIZE; 816 else if (is58xx(dev)) 817 return B53_MIBS_58XX_SIZE; 818 else 819 return B53_MIBS_SIZE; 820 } 821 822 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 823 { 824 /* These ports typically do not have built-in PHYs */ 825 switch (port) { 826 case B53_CPU_PORT_25: 827 case 7: 828 case B53_CPU_PORT: 829 return NULL; 830 } 831 832 return mdiobus_get_phy(ds->slave_mii_bus, port); 833 } 834 835 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 836 uint8_t *data) 837 { 838 struct b53_device *dev = ds->priv; 839 const struct b53_mib_desc *mibs = b53_get_mib(dev); 840 unsigned int mib_size = b53_get_mib_size(dev); 841 struct phy_device *phydev; 842 unsigned int i; 843 844 if (stringset == ETH_SS_STATS) { 845 for (i = 0; i < mib_size; i++) 846 strlcpy(data + i * ETH_GSTRING_LEN, 847 mibs[i].name, ETH_GSTRING_LEN); 848 } else if (stringset == ETH_SS_PHY_STATS) { 849 phydev = b53_get_phy_device(ds, port); 850 if (!phydev) 851 return; 852 853 phy_ethtool_get_strings(phydev, data); 854 } 855 } 856 EXPORT_SYMBOL(b53_get_strings); 857 858 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 859 { 860 struct b53_device *dev = ds->priv; 861 const struct b53_mib_desc *mibs = b53_get_mib(dev); 862 unsigned int mib_size = b53_get_mib_size(dev); 863 const struct b53_mib_desc *s; 864 unsigned int i; 865 u64 val = 0; 866 867 if (is5365(dev) && port == 5) 868 port = 8; 869 870 mutex_lock(&dev->stats_mutex); 871 872 for (i = 0; i < mib_size; i++) { 873 s = &mibs[i]; 874 875 if (s->size == 8) { 876 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 877 } else { 878 u32 val32; 879 880 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 881 &val32); 882 val = val32; 883 } 884 data[i] = (u64)val; 885 } 886 887 mutex_unlock(&dev->stats_mutex); 888 } 889 EXPORT_SYMBOL(b53_get_ethtool_stats); 890 891 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 892 { 893 struct phy_device *phydev; 894 895 phydev = b53_get_phy_device(ds, port); 896 if (!phydev) 897 return; 898 899 phy_ethtool_get_stats(phydev, NULL, data); 900 } 901 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 902 903 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 904 { 905 struct b53_device *dev = ds->priv; 906 struct phy_device *phydev; 907 908 if (sset == ETH_SS_STATS) { 909 return b53_get_mib_size(dev); 910 } else if (sset == ETH_SS_PHY_STATS) { 911 phydev = b53_get_phy_device(ds, port); 912 if (!phydev) 913 return 0; 914 915 return phy_ethtool_get_sset_count(phydev); 916 } 917 918 return 0; 919 } 920 EXPORT_SYMBOL(b53_get_sset_count); 921 922 static int b53_setup(struct dsa_switch *ds) 923 { 924 struct b53_device *dev = ds->priv; 925 unsigned int port; 926 int ret; 927 928 ret = b53_reset_switch(dev); 929 if (ret) { 930 dev_err(ds->dev, "failed to reset switch\n"); 931 return ret; 932 } 933 934 b53_reset_mib(dev); 935 936 ret = b53_apply_config(dev); 937 if (ret) 938 dev_err(ds->dev, "failed to apply configuration\n"); 939 940 /* Configure IMP/CPU port, disable unused ports. Enabled 941 * ports will be configured with .port_enable 942 */ 943 for (port = 0; port < dev->num_ports; port++) { 944 if (dsa_is_cpu_port(ds, port)) 945 b53_enable_cpu_port(dev, port); 946 else if (dsa_is_unused_port(ds, port)) 947 b53_disable_port(ds, port, NULL); 948 } 949 950 return ret; 951 } 952 953 static void b53_force_link(struct b53_device *dev, int port, int link) 954 { 955 u8 reg, val, off; 956 957 /* Override the port settings */ 958 if (port == dev->cpu_port) { 959 off = B53_PORT_OVERRIDE_CTRL; 960 val = PORT_OVERRIDE_EN; 961 } else { 962 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 963 val = GMII_PO_EN; 964 } 965 966 b53_read8(dev, B53_CTRL_PAGE, off, ®); 967 reg |= val; 968 if (link) 969 reg |= PORT_OVERRIDE_LINK; 970 else 971 reg &= ~PORT_OVERRIDE_LINK; 972 b53_write8(dev, B53_CTRL_PAGE, off, reg); 973 } 974 975 static void b53_force_port_config(struct b53_device *dev, int port, 976 int speed, int duplex, int pause) 977 { 978 u8 reg, val, off; 979 980 /* Override the port settings */ 981 if (port == dev->cpu_port) { 982 off = B53_PORT_OVERRIDE_CTRL; 983 val = PORT_OVERRIDE_EN; 984 } else { 985 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 986 val = GMII_PO_EN; 987 } 988 989 b53_read8(dev, B53_CTRL_PAGE, off, ®); 990 reg |= val; 991 if (duplex == DUPLEX_FULL) 992 reg |= PORT_OVERRIDE_FULL_DUPLEX; 993 else 994 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 995 996 switch (speed) { 997 case 2000: 998 reg |= PORT_OVERRIDE_SPEED_2000M; 999 /* fallthrough */ 1000 case SPEED_1000: 1001 reg |= PORT_OVERRIDE_SPEED_1000M; 1002 break; 1003 case SPEED_100: 1004 reg |= PORT_OVERRIDE_SPEED_100M; 1005 break; 1006 case SPEED_10: 1007 reg |= PORT_OVERRIDE_SPEED_10M; 1008 break; 1009 default: 1010 dev_err(dev->dev, "unknown speed: %d\n", speed); 1011 return; 1012 } 1013 1014 if (pause & MLO_PAUSE_RX) 1015 reg |= PORT_OVERRIDE_RX_FLOW; 1016 if (pause & MLO_PAUSE_TX) 1017 reg |= PORT_OVERRIDE_TX_FLOW; 1018 1019 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1020 } 1021 1022 static void b53_adjust_link(struct dsa_switch *ds, int port, 1023 struct phy_device *phydev) 1024 { 1025 struct b53_device *dev = ds->priv; 1026 struct ethtool_eee *p = &dev->ports[port].eee; 1027 u8 rgmii_ctrl = 0, reg = 0, off; 1028 int pause; 1029 1030 if (!phy_is_pseudo_fixed_link(phydev)) 1031 return; 1032 1033 /* Enable flow control on BCM5301x's CPU port */ 1034 if (is5301x(dev) && port == dev->cpu_port) 1035 pause = MLO_PAUSE_TXRX_MASK; 1036 1037 if (phydev->pause) { 1038 if (phydev->asym_pause) 1039 pause |= MLO_PAUSE_TX; 1040 pause |= MLO_PAUSE_RX; 1041 } 1042 1043 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause); 1044 b53_force_link(dev, port, phydev->link); 1045 1046 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1047 if (port == 8) 1048 off = B53_RGMII_CTRL_IMP; 1049 else 1050 off = B53_RGMII_CTRL_P(port); 1051 1052 /* Configure the port RGMII clock delay by DLL disabled and 1053 * tx_clk aligned timing (restoring to reset defaults) 1054 */ 1055 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1056 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1057 RGMII_CTRL_TIMING_SEL); 1058 1059 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1060 * sure that we enable the port TX clock internal delay to 1061 * account for this internal delay that is inserted, otherwise 1062 * the switch won't be able to receive correctly. 1063 * 1064 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1065 * any delay neither on transmission nor reception, so the 1066 * BCM53125 must also be configured accordingly to account for 1067 * the lack of delay and introduce 1068 * 1069 * The BCM53125 switch has its RX clock and TX clock control 1070 * swapped, hence the reason why we modify the TX clock path in 1071 * the "RGMII" case 1072 */ 1073 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1074 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1075 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1076 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1077 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1078 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1079 1080 dev_info(ds->dev, "Configured port %d for %s\n", port, 1081 phy_modes(phydev->interface)); 1082 } 1083 1084 /* configure MII port if necessary */ 1085 if (is5325(dev)) { 1086 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1087 ®); 1088 1089 /* reverse mii needs to be enabled */ 1090 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1091 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1092 reg | PORT_OVERRIDE_RV_MII_25); 1093 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1094 ®); 1095 1096 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1097 dev_err(ds->dev, 1098 "Failed to enable reverse MII mode\n"); 1099 return; 1100 } 1101 } 1102 } else if (is5301x(dev)) { 1103 if (port != dev->cpu_port) { 1104 b53_force_port_config(dev, dev->cpu_port, 2000, 1105 DUPLEX_FULL, MLO_PAUSE_TXRX_MASK); 1106 b53_force_link(dev, dev->cpu_port, 1); 1107 } 1108 } 1109 1110 /* Re-negotiate EEE if it was enabled already */ 1111 p->eee_enabled = b53_eee_init(ds, port, phydev); 1112 } 1113 1114 void b53_port_event(struct dsa_switch *ds, int port) 1115 { 1116 struct b53_device *dev = ds->priv; 1117 bool link; 1118 u16 sts; 1119 1120 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1121 link = !!(sts & BIT(port)); 1122 dsa_port_phylink_mac_change(ds, port, link); 1123 } 1124 EXPORT_SYMBOL(b53_port_event); 1125 1126 void b53_phylink_validate(struct dsa_switch *ds, int port, 1127 unsigned long *supported, 1128 struct phylink_link_state *state) 1129 { 1130 struct b53_device *dev = ds->priv; 1131 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1132 1133 if (dev->ops->serdes_phylink_validate) 1134 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1135 1136 /* Allow all the expected bits */ 1137 phylink_set(mask, Autoneg); 1138 phylink_set_port_modes(mask); 1139 phylink_set(mask, Pause); 1140 phylink_set(mask, Asym_Pause); 1141 1142 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1143 * support Gigabit, including Half duplex. 1144 */ 1145 if (state->interface != PHY_INTERFACE_MODE_MII && 1146 state->interface != PHY_INTERFACE_MODE_REVMII && 1147 !phy_interface_mode_is_8023z(state->interface) && 1148 !(is5325(dev) || is5365(dev))) { 1149 phylink_set(mask, 1000baseT_Full); 1150 phylink_set(mask, 1000baseT_Half); 1151 } 1152 1153 if (!phy_interface_mode_is_8023z(state->interface)) { 1154 phylink_set(mask, 10baseT_Half); 1155 phylink_set(mask, 10baseT_Full); 1156 phylink_set(mask, 100baseT_Half); 1157 phylink_set(mask, 100baseT_Full); 1158 } 1159 1160 bitmap_and(supported, supported, mask, 1161 __ETHTOOL_LINK_MODE_MASK_NBITS); 1162 bitmap_and(state->advertising, state->advertising, mask, 1163 __ETHTOOL_LINK_MODE_MASK_NBITS); 1164 1165 phylink_helper_basex_speed(state); 1166 } 1167 EXPORT_SYMBOL(b53_phylink_validate); 1168 1169 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1170 struct phylink_link_state *state) 1171 { 1172 struct b53_device *dev = ds->priv; 1173 int ret = -EOPNOTSUPP; 1174 1175 if (phy_interface_mode_is_8023z(state->interface) && 1176 dev->ops->serdes_link_state) 1177 ret = dev->ops->serdes_link_state(dev, port, state); 1178 1179 return ret; 1180 } 1181 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1182 1183 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1184 unsigned int mode, 1185 const struct phylink_link_state *state) 1186 { 1187 struct b53_device *dev = ds->priv; 1188 1189 if (mode == MLO_AN_PHY) 1190 return; 1191 1192 if (mode == MLO_AN_FIXED) { 1193 b53_force_port_config(dev, port, state->speed, 1194 state->duplex, state->pause); 1195 return; 1196 } 1197 1198 if (phy_interface_mode_is_8023z(state->interface) && 1199 dev->ops->serdes_config) 1200 dev->ops->serdes_config(dev, port, mode, state); 1201 } 1202 EXPORT_SYMBOL(b53_phylink_mac_config); 1203 1204 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1205 { 1206 struct b53_device *dev = ds->priv; 1207 1208 if (dev->ops->serdes_an_restart) 1209 dev->ops->serdes_an_restart(dev, port); 1210 } 1211 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1212 1213 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1214 unsigned int mode, 1215 phy_interface_t interface) 1216 { 1217 struct b53_device *dev = ds->priv; 1218 1219 if (mode == MLO_AN_PHY) 1220 return; 1221 1222 if (mode == MLO_AN_FIXED) { 1223 b53_force_link(dev, port, false); 1224 return; 1225 } 1226 1227 if (phy_interface_mode_is_8023z(interface) && 1228 dev->ops->serdes_link_set) 1229 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1230 } 1231 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1232 1233 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1234 unsigned int mode, 1235 phy_interface_t interface, 1236 struct phy_device *phydev) 1237 { 1238 struct b53_device *dev = ds->priv; 1239 1240 if (mode == MLO_AN_PHY) 1241 return; 1242 1243 if (mode == MLO_AN_FIXED) { 1244 b53_force_link(dev, port, true); 1245 return; 1246 } 1247 1248 if (phy_interface_mode_is_8023z(interface) && 1249 dev->ops->serdes_link_set) 1250 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1251 } 1252 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1253 1254 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 1255 { 1256 return 0; 1257 } 1258 EXPORT_SYMBOL(b53_vlan_filtering); 1259 1260 int b53_vlan_prepare(struct dsa_switch *ds, int port, 1261 const struct switchdev_obj_port_vlan *vlan) 1262 { 1263 struct b53_device *dev = ds->priv; 1264 1265 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 1266 return -EOPNOTSUPP; 1267 1268 if (vlan->vid_end > dev->num_vlans) 1269 return -ERANGE; 1270 1271 b53_enable_vlan(dev, true); 1272 1273 return 0; 1274 } 1275 EXPORT_SYMBOL(b53_vlan_prepare); 1276 1277 void b53_vlan_add(struct dsa_switch *ds, int port, 1278 const struct switchdev_obj_port_vlan *vlan) 1279 { 1280 struct b53_device *dev = ds->priv; 1281 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1282 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1283 struct b53_vlan *vl; 1284 u16 vid; 1285 1286 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1287 vl = &dev->vlans[vid]; 1288 1289 b53_get_vlan_entry(dev, vid, vl); 1290 1291 vl->members |= BIT(port); 1292 if (untagged) 1293 vl->untag |= BIT(port); 1294 else 1295 vl->untag &= ~BIT(port); 1296 1297 b53_set_vlan_entry(dev, vid, vl); 1298 b53_fast_age_vlan(dev, vid); 1299 } 1300 1301 if (pvid) { 1302 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1303 vlan->vid_end); 1304 b53_fast_age_vlan(dev, vid); 1305 } 1306 } 1307 EXPORT_SYMBOL(b53_vlan_add); 1308 1309 int b53_vlan_del(struct dsa_switch *ds, int port, 1310 const struct switchdev_obj_port_vlan *vlan) 1311 { 1312 struct b53_device *dev = ds->priv; 1313 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1314 struct b53_vlan *vl; 1315 u16 vid; 1316 u16 pvid; 1317 1318 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1319 1320 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1321 vl = &dev->vlans[vid]; 1322 1323 b53_get_vlan_entry(dev, vid, vl); 1324 1325 vl->members &= ~BIT(port); 1326 1327 if (pvid == vid) { 1328 if (is5325(dev) || is5365(dev)) 1329 pvid = 1; 1330 else 1331 pvid = 0; 1332 } 1333 1334 if (untagged) 1335 vl->untag &= ~(BIT(port)); 1336 1337 b53_set_vlan_entry(dev, vid, vl); 1338 b53_fast_age_vlan(dev, vid); 1339 } 1340 1341 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1342 b53_fast_age_vlan(dev, pvid); 1343 1344 return 0; 1345 } 1346 EXPORT_SYMBOL(b53_vlan_del); 1347 1348 /* Address Resolution Logic routines */ 1349 static int b53_arl_op_wait(struct b53_device *dev) 1350 { 1351 unsigned int timeout = 10; 1352 u8 reg; 1353 1354 do { 1355 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1356 if (!(reg & ARLTBL_START_DONE)) 1357 return 0; 1358 1359 usleep_range(1000, 2000); 1360 } while (timeout--); 1361 1362 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1363 1364 return -ETIMEDOUT; 1365 } 1366 1367 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1368 { 1369 u8 reg; 1370 1371 if (op > ARLTBL_RW) 1372 return -EINVAL; 1373 1374 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1375 reg |= ARLTBL_START_DONE; 1376 if (op) 1377 reg |= ARLTBL_RW; 1378 else 1379 reg &= ~ARLTBL_RW; 1380 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1381 1382 return b53_arl_op_wait(dev); 1383 } 1384 1385 static int b53_arl_read(struct b53_device *dev, u64 mac, 1386 u16 vid, struct b53_arl_entry *ent, u8 *idx, 1387 bool is_valid) 1388 { 1389 unsigned int i; 1390 int ret; 1391 1392 ret = b53_arl_op_wait(dev); 1393 if (ret) 1394 return ret; 1395 1396 /* Read the bins */ 1397 for (i = 0; i < dev->num_arl_entries; i++) { 1398 u64 mac_vid; 1399 u32 fwd_entry; 1400 1401 b53_read64(dev, B53_ARLIO_PAGE, 1402 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1403 b53_read32(dev, B53_ARLIO_PAGE, 1404 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1405 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1406 1407 if (!(fwd_entry & ARLTBL_VALID)) 1408 continue; 1409 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1410 continue; 1411 *idx = i; 1412 } 1413 1414 return -ENOENT; 1415 } 1416 1417 static int b53_arl_op(struct b53_device *dev, int op, int port, 1418 const unsigned char *addr, u16 vid, bool is_valid) 1419 { 1420 struct b53_arl_entry ent; 1421 u32 fwd_entry; 1422 u64 mac, mac_vid = 0; 1423 u8 idx = 0; 1424 int ret; 1425 1426 /* Convert the array into a 64-bit MAC */ 1427 mac = ether_addr_to_u64(addr); 1428 1429 /* Perform a read for the given MAC and VID */ 1430 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1431 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1432 1433 /* Issue a read operation for this MAC */ 1434 ret = b53_arl_rw_op(dev, 1); 1435 if (ret) 1436 return ret; 1437 1438 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid); 1439 /* If this is a read, just finish now */ 1440 if (op) 1441 return ret; 1442 1443 /* We could not find a matching MAC, so reset to a new entry */ 1444 if (ret) { 1445 fwd_entry = 0; 1446 idx = 1; 1447 } 1448 1449 memset(&ent, 0, sizeof(ent)); 1450 ent.port = port; 1451 ent.is_valid = is_valid; 1452 ent.vid = vid; 1453 ent.is_static = true; 1454 memcpy(ent.mac, addr, ETH_ALEN); 1455 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1456 1457 b53_write64(dev, B53_ARLIO_PAGE, 1458 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1459 b53_write32(dev, B53_ARLIO_PAGE, 1460 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1461 1462 return b53_arl_rw_op(dev, 0); 1463 } 1464 1465 int b53_fdb_add(struct dsa_switch *ds, int port, 1466 const unsigned char *addr, u16 vid) 1467 { 1468 struct b53_device *priv = ds->priv; 1469 1470 /* 5325 and 5365 require some more massaging, but could 1471 * be supported eventually 1472 */ 1473 if (is5325(priv) || is5365(priv)) 1474 return -EOPNOTSUPP; 1475 1476 return b53_arl_op(priv, 0, port, addr, vid, true); 1477 } 1478 EXPORT_SYMBOL(b53_fdb_add); 1479 1480 int b53_fdb_del(struct dsa_switch *ds, int port, 1481 const unsigned char *addr, u16 vid) 1482 { 1483 struct b53_device *priv = ds->priv; 1484 1485 return b53_arl_op(priv, 0, port, addr, vid, false); 1486 } 1487 EXPORT_SYMBOL(b53_fdb_del); 1488 1489 static int b53_arl_search_wait(struct b53_device *dev) 1490 { 1491 unsigned int timeout = 1000; 1492 u8 reg; 1493 1494 do { 1495 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1496 if (!(reg & ARL_SRCH_STDN)) 1497 return 0; 1498 1499 if (reg & ARL_SRCH_VLID) 1500 return 0; 1501 1502 usleep_range(1000, 2000); 1503 } while (timeout--); 1504 1505 return -ETIMEDOUT; 1506 } 1507 1508 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1509 struct b53_arl_entry *ent) 1510 { 1511 u64 mac_vid; 1512 u32 fwd_entry; 1513 1514 b53_read64(dev, B53_ARLIO_PAGE, 1515 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1516 b53_read32(dev, B53_ARLIO_PAGE, 1517 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1518 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1519 } 1520 1521 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1522 dsa_fdb_dump_cb_t *cb, void *data) 1523 { 1524 if (!ent->is_valid) 1525 return 0; 1526 1527 if (port != ent->port) 1528 return 0; 1529 1530 return cb(ent->mac, ent->vid, ent->is_static, data); 1531 } 1532 1533 int b53_fdb_dump(struct dsa_switch *ds, int port, 1534 dsa_fdb_dump_cb_t *cb, void *data) 1535 { 1536 struct b53_device *priv = ds->priv; 1537 struct b53_arl_entry results[2]; 1538 unsigned int count = 0; 1539 int ret; 1540 u8 reg; 1541 1542 /* Start search operation */ 1543 reg = ARL_SRCH_STDN; 1544 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1545 1546 do { 1547 ret = b53_arl_search_wait(priv); 1548 if (ret) 1549 return ret; 1550 1551 b53_arl_search_rd(priv, 0, &results[0]); 1552 ret = b53_fdb_copy(port, &results[0], cb, data); 1553 if (ret) 1554 return ret; 1555 1556 if (priv->num_arl_entries > 2) { 1557 b53_arl_search_rd(priv, 1, &results[1]); 1558 ret = b53_fdb_copy(port, &results[1], cb, data); 1559 if (ret) 1560 return ret; 1561 1562 if (!results[0].is_valid && !results[1].is_valid) 1563 break; 1564 } 1565 1566 } while (count++ < 1024); 1567 1568 return 0; 1569 } 1570 EXPORT_SYMBOL(b53_fdb_dump); 1571 1572 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1573 { 1574 struct b53_device *dev = ds->priv; 1575 s8 cpu_port = ds->ports[port].cpu_dp->index; 1576 u16 pvlan, reg; 1577 unsigned int i; 1578 1579 /* Make this port leave the all VLANs join since we will have proper 1580 * VLAN entries from now on 1581 */ 1582 if (is58xx(dev)) { 1583 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1584 reg &= ~BIT(port); 1585 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1586 reg &= ~BIT(cpu_port); 1587 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1588 } 1589 1590 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1591 1592 b53_for_each_port(dev, i) { 1593 if (dsa_to_port(ds, i)->bridge_dev != br) 1594 continue; 1595 1596 /* Add this local port to the remote port VLAN control 1597 * membership and update the remote port bitmask 1598 */ 1599 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1600 reg |= BIT(port); 1601 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1602 dev->ports[i].vlan_ctl_mask = reg; 1603 1604 pvlan |= BIT(i); 1605 } 1606 1607 /* Configure the local port VLAN control membership to include 1608 * remote ports and update the local port bitmask 1609 */ 1610 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1611 dev->ports[port].vlan_ctl_mask = pvlan; 1612 1613 return 0; 1614 } 1615 EXPORT_SYMBOL(b53_br_join); 1616 1617 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1618 { 1619 struct b53_device *dev = ds->priv; 1620 struct b53_vlan *vl = &dev->vlans[0]; 1621 s8 cpu_port = ds->ports[port].cpu_dp->index; 1622 unsigned int i; 1623 u16 pvlan, reg, pvid; 1624 1625 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1626 1627 b53_for_each_port(dev, i) { 1628 /* Don't touch the remaining ports */ 1629 if (dsa_to_port(ds, i)->bridge_dev != br) 1630 continue; 1631 1632 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1633 reg &= ~BIT(port); 1634 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1635 dev->ports[port].vlan_ctl_mask = reg; 1636 1637 /* Prevent self removal to preserve isolation */ 1638 if (port != i) 1639 pvlan &= ~BIT(i); 1640 } 1641 1642 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1643 dev->ports[port].vlan_ctl_mask = pvlan; 1644 1645 if (is5325(dev) || is5365(dev)) 1646 pvid = 1; 1647 else 1648 pvid = 0; 1649 1650 /* Make this port join all VLANs without VLAN entries */ 1651 if (is58xx(dev)) { 1652 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1653 reg |= BIT(port); 1654 if (!(reg & BIT(cpu_port))) 1655 reg |= BIT(cpu_port); 1656 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1657 } else { 1658 b53_get_vlan_entry(dev, pvid, vl); 1659 vl->members |= BIT(port) | BIT(cpu_port); 1660 vl->untag |= BIT(port) | BIT(cpu_port); 1661 b53_set_vlan_entry(dev, pvid, vl); 1662 } 1663 } 1664 EXPORT_SYMBOL(b53_br_leave); 1665 1666 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1667 { 1668 struct b53_device *dev = ds->priv; 1669 u8 hw_state; 1670 u8 reg; 1671 1672 switch (state) { 1673 case BR_STATE_DISABLED: 1674 hw_state = PORT_CTRL_DIS_STATE; 1675 break; 1676 case BR_STATE_LISTENING: 1677 hw_state = PORT_CTRL_LISTEN_STATE; 1678 break; 1679 case BR_STATE_LEARNING: 1680 hw_state = PORT_CTRL_LEARN_STATE; 1681 break; 1682 case BR_STATE_FORWARDING: 1683 hw_state = PORT_CTRL_FWD_STATE; 1684 break; 1685 case BR_STATE_BLOCKING: 1686 hw_state = PORT_CTRL_BLOCK_STATE; 1687 break; 1688 default: 1689 dev_err(ds->dev, "invalid STP state: %d\n", state); 1690 return; 1691 } 1692 1693 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1694 reg &= ~PORT_CTRL_STP_STATE_MASK; 1695 reg |= hw_state; 1696 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1697 } 1698 EXPORT_SYMBOL(b53_br_set_stp_state); 1699 1700 void b53_br_fast_age(struct dsa_switch *ds, int port) 1701 { 1702 struct b53_device *dev = ds->priv; 1703 1704 if (b53_fast_age_port(dev, port)) 1705 dev_err(ds->dev, "fast ageing failed\n"); 1706 } 1707 EXPORT_SYMBOL(b53_br_fast_age); 1708 1709 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 1710 { 1711 /* Broadcom switches will accept enabling Broadcom tags on the 1712 * following ports: 5, 7 and 8, any other port is not supported 1713 */ 1714 switch (port) { 1715 case B53_CPU_PORT_25: 1716 case 7: 1717 case B53_CPU_PORT: 1718 return true; 1719 } 1720 1721 return false; 1722 } 1723 1724 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port) 1725 { 1726 bool ret = b53_possible_cpu_port(ds, port); 1727 1728 if (!ret) 1729 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 1730 port); 1731 return ret; 1732 } 1733 1734 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port) 1735 { 1736 struct b53_device *dev = ds->priv; 1737 1738 /* Older models (5325, 5365) support a different tag format that we do 1739 * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed 1740 * mode to be turned on which means we need to specifically manage ARL 1741 * misses on multicast addresses (TBD). 1742 */ 1743 if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) || 1744 !b53_can_enable_brcm_tags(ds, port)) 1745 return DSA_TAG_PROTO_NONE; 1746 1747 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 1748 * which requires us to use the prepended Broadcom tag type 1749 */ 1750 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) 1751 return DSA_TAG_PROTO_BRCM_PREPEND; 1752 1753 return DSA_TAG_PROTO_BRCM; 1754 } 1755 EXPORT_SYMBOL(b53_get_tag_protocol); 1756 1757 int b53_mirror_add(struct dsa_switch *ds, int port, 1758 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1759 { 1760 struct b53_device *dev = ds->priv; 1761 u16 reg, loc; 1762 1763 if (ingress) 1764 loc = B53_IG_MIR_CTL; 1765 else 1766 loc = B53_EG_MIR_CTL; 1767 1768 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1769 reg &= ~MIRROR_MASK; 1770 reg |= BIT(port); 1771 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1772 1773 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1774 reg &= ~CAP_PORT_MASK; 1775 reg |= mirror->to_local_port; 1776 reg |= MIRROR_EN; 1777 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1778 1779 return 0; 1780 } 1781 EXPORT_SYMBOL(b53_mirror_add); 1782 1783 void b53_mirror_del(struct dsa_switch *ds, int port, 1784 struct dsa_mall_mirror_tc_entry *mirror) 1785 { 1786 struct b53_device *dev = ds->priv; 1787 bool loc_disable = false, other_loc_disable = false; 1788 u16 reg, loc; 1789 1790 if (mirror->ingress) 1791 loc = B53_IG_MIR_CTL; 1792 else 1793 loc = B53_EG_MIR_CTL; 1794 1795 /* Update the desired ingress/egress register */ 1796 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1797 reg &= ~BIT(port); 1798 if (!(reg & MIRROR_MASK)) 1799 loc_disable = true; 1800 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1801 1802 /* Now look at the other one to know if we can disable mirroring 1803 * entirely 1804 */ 1805 if (mirror->ingress) 1806 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 1807 else 1808 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 1809 if (!(reg & MIRROR_MASK)) 1810 other_loc_disable = true; 1811 1812 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1813 /* Both no longer have ports, let's disable mirroring */ 1814 if (loc_disable && other_loc_disable) { 1815 reg &= ~MIRROR_EN; 1816 reg &= ~mirror->to_local_port; 1817 } 1818 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1819 } 1820 EXPORT_SYMBOL(b53_mirror_del); 1821 1822 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 1823 { 1824 struct b53_device *dev = ds->priv; 1825 u16 reg; 1826 1827 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 1828 if (enable) 1829 reg |= BIT(port); 1830 else 1831 reg &= ~BIT(port); 1832 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 1833 } 1834 EXPORT_SYMBOL(b53_eee_enable_set); 1835 1836 1837 /* Returns 0 if EEE was not enabled, or 1 otherwise 1838 */ 1839 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 1840 { 1841 int ret; 1842 1843 ret = phy_init_eee(phy, 0); 1844 if (ret) 1845 return 0; 1846 1847 b53_eee_enable_set(ds, port, true); 1848 1849 return 1; 1850 } 1851 EXPORT_SYMBOL(b53_eee_init); 1852 1853 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1854 { 1855 struct b53_device *dev = ds->priv; 1856 struct ethtool_eee *p = &dev->ports[port].eee; 1857 u16 reg; 1858 1859 if (is5325(dev) || is5365(dev)) 1860 return -EOPNOTSUPP; 1861 1862 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 1863 e->eee_enabled = p->eee_enabled; 1864 e->eee_active = !!(reg & BIT(port)); 1865 1866 return 0; 1867 } 1868 EXPORT_SYMBOL(b53_get_mac_eee); 1869 1870 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1871 { 1872 struct b53_device *dev = ds->priv; 1873 struct ethtool_eee *p = &dev->ports[port].eee; 1874 1875 if (is5325(dev) || is5365(dev)) 1876 return -EOPNOTSUPP; 1877 1878 p->eee_enabled = e->eee_enabled; 1879 b53_eee_enable_set(ds, port, e->eee_enabled); 1880 1881 return 0; 1882 } 1883 EXPORT_SYMBOL(b53_set_mac_eee); 1884 1885 static const struct dsa_switch_ops b53_switch_ops = { 1886 .get_tag_protocol = b53_get_tag_protocol, 1887 .setup = b53_setup, 1888 .get_strings = b53_get_strings, 1889 .get_ethtool_stats = b53_get_ethtool_stats, 1890 .get_sset_count = b53_get_sset_count, 1891 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1892 .phy_read = b53_phy_read16, 1893 .phy_write = b53_phy_write16, 1894 .adjust_link = b53_adjust_link, 1895 .phylink_validate = b53_phylink_validate, 1896 .phylink_mac_link_state = b53_phylink_mac_link_state, 1897 .phylink_mac_config = b53_phylink_mac_config, 1898 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 1899 .phylink_mac_link_down = b53_phylink_mac_link_down, 1900 .phylink_mac_link_up = b53_phylink_mac_link_up, 1901 .port_enable = b53_enable_port, 1902 .port_disable = b53_disable_port, 1903 .get_mac_eee = b53_get_mac_eee, 1904 .set_mac_eee = b53_set_mac_eee, 1905 .port_bridge_join = b53_br_join, 1906 .port_bridge_leave = b53_br_leave, 1907 .port_stp_state_set = b53_br_set_stp_state, 1908 .port_fast_age = b53_br_fast_age, 1909 .port_vlan_filtering = b53_vlan_filtering, 1910 .port_vlan_prepare = b53_vlan_prepare, 1911 .port_vlan_add = b53_vlan_add, 1912 .port_vlan_del = b53_vlan_del, 1913 .port_fdb_dump = b53_fdb_dump, 1914 .port_fdb_add = b53_fdb_add, 1915 .port_fdb_del = b53_fdb_del, 1916 .port_mirror_add = b53_mirror_add, 1917 .port_mirror_del = b53_mirror_del, 1918 }; 1919 1920 struct b53_chip_data { 1921 u32 chip_id; 1922 const char *dev_name; 1923 u16 vlans; 1924 u16 enabled_ports; 1925 u8 cpu_port; 1926 u8 vta_regs[3]; 1927 u8 arl_entries; 1928 u8 duplex_reg; 1929 u8 jumbo_pm_reg; 1930 u8 jumbo_size_reg; 1931 }; 1932 1933 #define B53_VTA_REGS \ 1934 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 1935 #define B53_VTA_REGS_9798 \ 1936 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 1937 #define B53_VTA_REGS_63XX \ 1938 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 1939 1940 static const struct b53_chip_data b53_switch_chips[] = { 1941 { 1942 .chip_id = BCM5325_DEVICE_ID, 1943 .dev_name = "BCM5325", 1944 .vlans = 16, 1945 .enabled_ports = 0x1f, 1946 .arl_entries = 2, 1947 .cpu_port = B53_CPU_PORT_25, 1948 .duplex_reg = B53_DUPLEX_STAT_FE, 1949 }, 1950 { 1951 .chip_id = BCM5365_DEVICE_ID, 1952 .dev_name = "BCM5365", 1953 .vlans = 256, 1954 .enabled_ports = 0x1f, 1955 .arl_entries = 2, 1956 .cpu_port = B53_CPU_PORT_25, 1957 .duplex_reg = B53_DUPLEX_STAT_FE, 1958 }, 1959 { 1960 .chip_id = BCM5389_DEVICE_ID, 1961 .dev_name = "BCM5389", 1962 .vlans = 4096, 1963 .enabled_ports = 0x1f, 1964 .arl_entries = 4, 1965 .cpu_port = B53_CPU_PORT, 1966 .vta_regs = B53_VTA_REGS, 1967 .duplex_reg = B53_DUPLEX_STAT_GE, 1968 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1969 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1970 }, 1971 { 1972 .chip_id = BCM5395_DEVICE_ID, 1973 .dev_name = "BCM5395", 1974 .vlans = 4096, 1975 .enabled_ports = 0x1f, 1976 .arl_entries = 4, 1977 .cpu_port = B53_CPU_PORT, 1978 .vta_regs = B53_VTA_REGS, 1979 .duplex_reg = B53_DUPLEX_STAT_GE, 1980 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1981 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1982 }, 1983 { 1984 .chip_id = BCM5397_DEVICE_ID, 1985 .dev_name = "BCM5397", 1986 .vlans = 4096, 1987 .enabled_ports = 0x1f, 1988 .arl_entries = 4, 1989 .cpu_port = B53_CPU_PORT, 1990 .vta_regs = B53_VTA_REGS_9798, 1991 .duplex_reg = B53_DUPLEX_STAT_GE, 1992 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1993 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1994 }, 1995 { 1996 .chip_id = BCM5398_DEVICE_ID, 1997 .dev_name = "BCM5398", 1998 .vlans = 4096, 1999 .enabled_ports = 0x7f, 2000 .arl_entries = 4, 2001 .cpu_port = B53_CPU_PORT, 2002 .vta_regs = B53_VTA_REGS_9798, 2003 .duplex_reg = B53_DUPLEX_STAT_GE, 2004 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2005 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2006 }, 2007 { 2008 .chip_id = BCM53115_DEVICE_ID, 2009 .dev_name = "BCM53115", 2010 .vlans = 4096, 2011 .enabled_ports = 0x1f, 2012 .arl_entries = 4, 2013 .vta_regs = B53_VTA_REGS, 2014 .cpu_port = B53_CPU_PORT, 2015 .duplex_reg = B53_DUPLEX_STAT_GE, 2016 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2017 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2018 }, 2019 { 2020 .chip_id = BCM53125_DEVICE_ID, 2021 .dev_name = "BCM53125", 2022 .vlans = 4096, 2023 .enabled_ports = 0xff, 2024 .arl_entries = 4, 2025 .cpu_port = B53_CPU_PORT, 2026 .vta_regs = B53_VTA_REGS, 2027 .duplex_reg = B53_DUPLEX_STAT_GE, 2028 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2029 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2030 }, 2031 { 2032 .chip_id = BCM53128_DEVICE_ID, 2033 .dev_name = "BCM53128", 2034 .vlans = 4096, 2035 .enabled_ports = 0x1ff, 2036 .arl_entries = 4, 2037 .cpu_port = B53_CPU_PORT, 2038 .vta_regs = B53_VTA_REGS, 2039 .duplex_reg = B53_DUPLEX_STAT_GE, 2040 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2041 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2042 }, 2043 { 2044 .chip_id = BCM63XX_DEVICE_ID, 2045 .dev_name = "BCM63xx", 2046 .vlans = 4096, 2047 .enabled_ports = 0, /* pdata must provide them */ 2048 .arl_entries = 4, 2049 .cpu_port = B53_CPU_PORT, 2050 .vta_regs = B53_VTA_REGS_63XX, 2051 .duplex_reg = B53_DUPLEX_STAT_63XX, 2052 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2053 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2054 }, 2055 { 2056 .chip_id = BCM53010_DEVICE_ID, 2057 .dev_name = "BCM53010", 2058 .vlans = 4096, 2059 .enabled_ports = 0x1f, 2060 .arl_entries = 4, 2061 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2062 .vta_regs = B53_VTA_REGS, 2063 .duplex_reg = B53_DUPLEX_STAT_GE, 2064 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2065 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2066 }, 2067 { 2068 .chip_id = BCM53011_DEVICE_ID, 2069 .dev_name = "BCM53011", 2070 .vlans = 4096, 2071 .enabled_ports = 0x1bf, 2072 .arl_entries = 4, 2073 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2074 .vta_regs = B53_VTA_REGS, 2075 .duplex_reg = B53_DUPLEX_STAT_GE, 2076 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2077 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2078 }, 2079 { 2080 .chip_id = BCM53012_DEVICE_ID, 2081 .dev_name = "BCM53012", 2082 .vlans = 4096, 2083 .enabled_ports = 0x1bf, 2084 .arl_entries = 4, 2085 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2086 .vta_regs = B53_VTA_REGS, 2087 .duplex_reg = B53_DUPLEX_STAT_GE, 2088 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2089 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2090 }, 2091 { 2092 .chip_id = BCM53018_DEVICE_ID, 2093 .dev_name = "BCM53018", 2094 .vlans = 4096, 2095 .enabled_ports = 0x1f, 2096 .arl_entries = 4, 2097 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2098 .vta_regs = B53_VTA_REGS, 2099 .duplex_reg = B53_DUPLEX_STAT_GE, 2100 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2101 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2102 }, 2103 { 2104 .chip_id = BCM53019_DEVICE_ID, 2105 .dev_name = "BCM53019", 2106 .vlans = 4096, 2107 .enabled_ports = 0x1f, 2108 .arl_entries = 4, 2109 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2110 .vta_regs = B53_VTA_REGS, 2111 .duplex_reg = B53_DUPLEX_STAT_GE, 2112 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2113 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2114 }, 2115 { 2116 .chip_id = BCM58XX_DEVICE_ID, 2117 .dev_name = "BCM585xx/586xx/88312", 2118 .vlans = 4096, 2119 .enabled_ports = 0x1ff, 2120 .arl_entries = 4, 2121 .cpu_port = B53_CPU_PORT, 2122 .vta_regs = B53_VTA_REGS, 2123 .duplex_reg = B53_DUPLEX_STAT_GE, 2124 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2125 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2126 }, 2127 { 2128 .chip_id = BCM583XX_DEVICE_ID, 2129 .dev_name = "BCM583xx/11360", 2130 .vlans = 4096, 2131 .enabled_ports = 0x103, 2132 .arl_entries = 4, 2133 .cpu_port = B53_CPU_PORT, 2134 .vta_regs = B53_VTA_REGS, 2135 .duplex_reg = B53_DUPLEX_STAT_GE, 2136 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2137 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2138 }, 2139 { 2140 .chip_id = BCM7445_DEVICE_ID, 2141 .dev_name = "BCM7445", 2142 .vlans = 4096, 2143 .enabled_ports = 0x1ff, 2144 .arl_entries = 4, 2145 .cpu_port = B53_CPU_PORT, 2146 .vta_regs = B53_VTA_REGS, 2147 .duplex_reg = B53_DUPLEX_STAT_GE, 2148 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2149 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2150 }, 2151 { 2152 .chip_id = BCM7278_DEVICE_ID, 2153 .dev_name = "BCM7278", 2154 .vlans = 4096, 2155 .enabled_ports = 0x1ff, 2156 .arl_entries= 4, 2157 .cpu_port = B53_CPU_PORT, 2158 .vta_regs = B53_VTA_REGS, 2159 .duplex_reg = B53_DUPLEX_STAT_GE, 2160 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2161 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2162 }, 2163 }; 2164 2165 static int b53_switch_init(struct b53_device *dev) 2166 { 2167 unsigned int i; 2168 int ret; 2169 2170 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2171 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2172 2173 if (chip->chip_id == dev->chip_id) { 2174 if (!dev->enabled_ports) 2175 dev->enabled_ports = chip->enabled_ports; 2176 dev->name = chip->dev_name; 2177 dev->duplex_reg = chip->duplex_reg; 2178 dev->vta_regs[0] = chip->vta_regs[0]; 2179 dev->vta_regs[1] = chip->vta_regs[1]; 2180 dev->vta_regs[2] = chip->vta_regs[2]; 2181 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2182 dev->cpu_port = chip->cpu_port; 2183 dev->num_vlans = chip->vlans; 2184 dev->num_arl_entries = chip->arl_entries; 2185 break; 2186 } 2187 } 2188 2189 /* check which BCM5325x version we have */ 2190 if (is5325(dev)) { 2191 u8 vc4; 2192 2193 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2194 2195 /* check reserved bits */ 2196 switch (vc4 & 3) { 2197 case 1: 2198 /* BCM5325E */ 2199 break; 2200 case 3: 2201 /* BCM5325F - do not use port 4 */ 2202 dev->enabled_ports &= ~BIT(4); 2203 break; 2204 default: 2205 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2206 #ifndef CONFIG_BCM47XX 2207 /* BCM5325M */ 2208 return -EINVAL; 2209 #else 2210 break; 2211 #endif 2212 } 2213 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2214 u64 strap_value; 2215 2216 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2217 /* use second IMP port if GMII is enabled */ 2218 if (strap_value & SV_GMII_CTRL_115) 2219 dev->cpu_port = 5; 2220 } 2221 2222 /* cpu port is always last */ 2223 dev->num_ports = dev->cpu_port + 1; 2224 dev->enabled_ports |= BIT(dev->cpu_port); 2225 2226 /* Include non standard CPU port built-in PHYs to be probed */ 2227 if (is539x(dev) || is531x5(dev)) { 2228 for (i = 0; i < dev->num_ports; i++) { 2229 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2230 !b53_possible_cpu_port(dev->ds, i)) 2231 dev->ds->phys_mii_mask |= BIT(i); 2232 } 2233 } 2234 2235 dev->ports = devm_kcalloc(dev->dev, 2236 dev->num_ports, sizeof(struct b53_port), 2237 GFP_KERNEL); 2238 if (!dev->ports) 2239 return -ENOMEM; 2240 2241 dev->vlans = devm_kcalloc(dev->dev, 2242 dev->num_vlans, sizeof(struct b53_vlan), 2243 GFP_KERNEL); 2244 if (!dev->vlans) 2245 return -ENOMEM; 2246 2247 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2248 if (dev->reset_gpio >= 0) { 2249 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2250 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2251 if (ret) 2252 return ret; 2253 } 2254 2255 return 0; 2256 } 2257 2258 struct b53_device *b53_switch_alloc(struct device *base, 2259 const struct b53_io_ops *ops, 2260 void *priv) 2261 { 2262 struct dsa_switch *ds; 2263 struct b53_device *dev; 2264 2265 ds = dsa_switch_alloc(base, DSA_MAX_PORTS); 2266 if (!ds) 2267 return NULL; 2268 2269 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2270 if (!dev) 2271 return NULL; 2272 2273 ds->priv = dev; 2274 dev->dev = base; 2275 2276 dev->ds = ds; 2277 dev->priv = priv; 2278 dev->ops = ops; 2279 ds->ops = &b53_switch_ops; 2280 mutex_init(&dev->reg_mutex); 2281 mutex_init(&dev->stats_mutex); 2282 2283 return dev; 2284 } 2285 EXPORT_SYMBOL(b53_switch_alloc); 2286 2287 int b53_switch_detect(struct b53_device *dev) 2288 { 2289 u32 id32; 2290 u16 tmp; 2291 u8 id8; 2292 int ret; 2293 2294 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2295 if (ret) 2296 return ret; 2297 2298 switch (id8) { 2299 case 0: 2300 /* BCM5325 and BCM5365 do not have this register so reads 2301 * return 0. But the read operation did succeed, so assume this 2302 * is one of them. 2303 * 2304 * Next check if we can write to the 5325's VTA register; for 2305 * 5365 it is read only. 2306 */ 2307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2309 2310 if (tmp == 0xf) 2311 dev->chip_id = BCM5325_DEVICE_ID; 2312 else 2313 dev->chip_id = BCM5365_DEVICE_ID; 2314 break; 2315 case BCM5389_DEVICE_ID: 2316 case BCM5395_DEVICE_ID: 2317 case BCM5397_DEVICE_ID: 2318 case BCM5398_DEVICE_ID: 2319 dev->chip_id = id8; 2320 break; 2321 default: 2322 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2323 if (ret) 2324 return ret; 2325 2326 switch (id32) { 2327 case BCM53115_DEVICE_ID: 2328 case BCM53125_DEVICE_ID: 2329 case BCM53128_DEVICE_ID: 2330 case BCM53010_DEVICE_ID: 2331 case BCM53011_DEVICE_ID: 2332 case BCM53012_DEVICE_ID: 2333 case BCM53018_DEVICE_ID: 2334 case BCM53019_DEVICE_ID: 2335 dev->chip_id = id32; 2336 break; 2337 default: 2338 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 2339 id8, id32); 2340 return -ENODEV; 2341 } 2342 } 2343 2344 if (dev->chip_id == BCM5325_DEVICE_ID) 2345 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2346 &dev->core_rev); 2347 else 2348 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2349 &dev->core_rev); 2350 } 2351 EXPORT_SYMBOL(b53_switch_detect); 2352 2353 int b53_switch_register(struct b53_device *dev) 2354 { 2355 int ret; 2356 2357 if (dev->pdata) { 2358 dev->chip_id = dev->pdata->chip_id; 2359 dev->enabled_ports = dev->pdata->enabled_ports; 2360 } 2361 2362 if (!dev->chip_id && b53_switch_detect(dev)) 2363 return -EINVAL; 2364 2365 ret = b53_switch_init(dev); 2366 if (ret) 2367 return ret; 2368 2369 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 2370 2371 return dsa_register_switch(dev->ds); 2372 } 2373 EXPORT_SYMBOL(b53_switch_register); 2374 2375 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2376 MODULE_DESCRIPTION("B53 switch library"); 2377 MODULE_LICENSE("Dual BSD/GPL"); 2378