1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <net/dsa.h> 31 32 #include "b53_regs.h" 33 #include "b53_priv.h" 34 35 struct b53_mib_desc { 36 u8 size; 37 u8 offset; 38 const char *name; 39 }; 40 41 /* BCM5365 MIB counters */ 42 static const struct b53_mib_desc b53_mibs_65[] = { 43 { 8, 0x00, "TxOctets" }, 44 { 4, 0x08, "TxDropPkts" }, 45 { 4, 0x10, "TxBroadcastPkts" }, 46 { 4, 0x14, "TxMulticastPkts" }, 47 { 4, 0x18, "TxUnicastPkts" }, 48 { 4, 0x1c, "TxCollisions" }, 49 { 4, 0x20, "TxSingleCollision" }, 50 { 4, 0x24, "TxMultipleCollision" }, 51 { 4, 0x28, "TxDeferredTransmit" }, 52 { 4, 0x2c, "TxLateCollision" }, 53 { 4, 0x30, "TxExcessiveCollision" }, 54 { 4, 0x38, "TxPausePkts" }, 55 { 8, 0x44, "RxOctets" }, 56 { 4, 0x4c, "RxUndersizePkts" }, 57 { 4, 0x50, "RxPausePkts" }, 58 { 4, 0x54, "Pkts64Octets" }, 59 { 4, 0x58, "Pkts65to127Octets" }, 60 { 4, 0x5c, "Pkts128to255Octets" }, 61 { 4, 0x60, "Pkts256to511Octets" }, 62 { 4, 0x64, "Pkts512to1023Octets" }, 63 { 4, 0x68, "Pkts1024to1522Octets" }, 64 { 4, 0x6c, "RxOversizePkts" }, 65 { 4, 0x70, "RxJabbers" }, 66 { 4, 0x74, "RxAlignmentErrors" }, 67 { 4, 0x78, "RxFCSErrors" }, 68 { 8, 0x7c, "RxGoodOctets" }, 69 { 4, 0x84, "RxDropPkts" }, 70 { 4, 0x88, "RxUnicastPkts" }, 71 { 4, 0x8c, "RxMulticastPkts" }, 72 { 4, 0x90, "RxBroadcastPkts" }, 73 { 4, 0x94, "RxSAChanges" }, 74 { 4, 0x98, "RxFragments" }, 75 }; 76 77 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 78 79 /* BCM63xx MIB counters */ 80 static const struct b53_mib_desc b53_mibs_63xx[] = { 81 { 8, 0x00, "TxOctets" }, 82 { 4, 0x08, "TxDropPkts" }, 83 { 4, 0x0c, "TxQoSPkts" }, 84 { 4, 0x10, "TxBroadcastPkts" }, 85 { 4, 0x14, "TxMulticastPkts" }, 86 { 4, 0x18, "TxUnicastPkts" }, 87 { 4, 0x1c, "TxCollisions" }, 88 { 4, 0x20, "TxSingleCollision" }, 89 { 4, 0x24, "TxMultipleCollision" }, 90 { 4, 0x28, "TxDeferredTransmit" }, 91 { 4, 0x2c, "TxLateCollision" }, 92 { 4, 0x30, "TxExcessiveCollision" }, 93 { 4, 0x38, "TxPausePkts" }, 94 { 8, 0x3c, "TxQoSOctets" }, 95 { 8, 0x44, "RxOctets" }, 96 { 4, 0x4c, "RxUndersizePkts" }, 97 { 4, 0x50, "RxPausePkts" }, 98 { 4, 0x54, "Pkts64Octets" }, 99 { 4, 0x58, "Pkts65to127Octets" }, 100 { 4, 0x5c, "Pkts128to255Octets" }, 101 { 4, 0x60, "Pkts256to511Octets" }, 102 { 4, 0x64, "Pkts512to1023Octets" }, 103 { 4, 0x68, "Pkts1024to1522Octets" }, 104 { 4, 0x6c, "RxOversizePkts" }, 105 { 4, 0x70, "RxJabbers" }, 106 { 4, 0x74, "RxAlignmentErrors" }, 107 { 4, 0x78, "RxFCSErrors" }, 108 { 8, 0x7c, "RxGoodOctets" }, 109 { 4, 0x84, "RxDropPkts" }, 110 { 4, 0x88, "RxUnicastPkts" }, 111 { 4, 0x8c, "RxMulticastPkts" }, 112 { 4, 0x90, "RxBroadcastPkts" }, 113 { 4, 0x94, "RxSAChanges" }, 114 { 4, 0x98, "RxFragments" }, 115 { 4, 0xa0, "RxSymbolErrors" }, 116 { 4, 0xa4, "RxQoSPkts" }, 117 { 8, 0xa8, "RxQoSOctets" }, 118 { 4, 0xb0, "Pkts1523to2047Octets" }, 119 { 4, 0xb4, "Pkts2048to4095Octets" }, 120 { 4, 0xb8, "Pkts4096to8191Octets" }, 121 { 4, 0xbc, "Pkts8192to9728Octets" }, 122 { 4, 0xc0, "RxDiscarded" }, 123 }; 124 125 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 126 127 /* MIB counters */ 128 static const struct b53_mib_desc b53_mibs[] = { 129 { 8, 0x00, "TxOctets" }, 130 { 4, 0x08, "TxDropPkts" }, 131 { 4, 0x10, "TxBroadcastPkts" }, 132 { 4, 0x14, "TxMulticastPkts" }, 133 { 4, 0x18, "TxUnicastPkts" }, 134 { 4, 0x1c, "TxCollisions" }, 135 { 4, 0x20, "TxSingleCollision" }, 136 { 4, 0x24, "TxMultipleCollision" }, 137 { 4, 0x28, "TxDeferredTransmit" }, 138 { 4, 0x2c, "TxLateCollision" }, 139 { 4, 0x30, "TxExcessiveCollision" }, 140 { 4, 0x38, "TxPausePkts" }, 141 { 8, 0x50, "RxOctets" }, 142 { 4, 0x58, "RxUndersizePkts" }, 143 { 4, 0x5c, "RxPausePkts" }, 144 { 4, 0x60, "Pkts64Octets" }, 145 { 4, 0x64, "Pkts65to127Octets" }, 146 { 4, 0x68, "Pkts128to255Octets" }, 147 { 4, 0x6c, "Pkts256to511Octets" }, 148 { 4, 0x70, "Pkts512to1023Octets" }, 149 { 4, 0x74, "Pkts1024to1522Octets" }, 150 { 4, 0x78, "RxOversizePkts" }, 151 { 4, 0x7c, "RxJabbers" }, 152 { 4, 0x80, "RxAlignmentErrors" }, 153 { 4, 0x84, "RxFCSErrors" }, 154 { 8, 0x88, "RxGoodOctets" }, 155 { 4, 0x90, "RxDropPkts" }, 156 { 4, 0x94, "RxUnicastPkts" }, 157 { 4, 0x98, "RxMulticastPkts" }, 158 { 4, 0x9c, "RxBroadcastPkts" }, 159 { 4, 0xa0, "RxSAChanges" }, 160 { 4, 0xa4, "RxFragments" }, 161 { 4, 0xa8, "RxJumboPkts" }, 162 { 4, 0xac, "RxSymbolErrors" }, 163 { 4, 0xc0, "RxDiscarded" }, 164 }; 165 166 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 167 168 static const struct b53_mib_desc b53_mibs_58xx[] = { 169 { 8, 0x00, "TxOctets" }, 170 { 4, 0x08, "TxDropPkts" }, 171 { 4, 0x0c, "TxQPKTQ0" }, 172 { 4, 0x10, "TxBroadcastPkts" }, 173 { 4, 0x14, "TxMulticastPkts" }, 174 { 4, 0x18, "TxUnicastPKts" }, 175 { 4, 0x1c, "TxCollisions" }, 176 { 4, 0x20, "TxSingleCollision" }, 177 { 4, 0x24, "TxMultipleCollision" }, 178 { 4, 0x28, "TxDeferredCollision" }, 179 { 4, 0x2c, "TxLateCollision" }, 180 { 4, 0x30, "TxExcessiveCollision" }, 181 { 4, 0x34, "TxFrameInDisc" }, 182 { 4, 0x38, "TxPausePkts" }, 183 { 4, 0x3c, "TxQPKTQ1" }, 184 { 4, 0x40, "TxQPKTQ2" }, 185 { 4, 0x44, "TxQPKTQ3" }, 186 { 4, 0x48, "TxQPKTQ4" }, 187 { 4, 0x4c, "TxQPKTQ5" }, 188 { 8, 0x50, "RxOctets" }, 189 { 4, 0x58, "RxUndersizePkts" }, 190 { 4, 0x5c, "RxPausePkts" }, 191 { 4, 0x60, "RxPkts64Octets" }, 192 { 4, 0x64, "RxPkts65to127Octets" }, 193 { 4, 0x68, "RxPkts128to255Octets" }, 194 { 4, 0x6c, "RxPkts256to511Octets" }, 195 { 4, 0x70, "RxPkts512to1023Octets" }, 196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 197 { 4, 0x78, "RxOversizePkts" }, 198 { 4, 0x7c, "RxJabbers" }, 199 { 4, 0x80, "RxAlignmentErrors" }, 200 { 4, 0x84, "RxFCSErrors" }, 201 { 8, 0x88, "RxGoodOctets" }, 202 { 4, 0x90, "RxDropPkts" }, 203 { 4, 0x94, "RxUnicastPkts" }, 204 { 4, 0x98, "RxMulticastPkts" }, 205 { 4, 0x9c, "RxBroadcastPkts" }, 206 { 4, 0xa0, "RxSAChanges" }, 207 { 4, 0xa4, "RxFragments" }, 208 { 4, 0xa8, "RxJumboPkt" }, 209 { 4, 0xac, "RxSymblErr" }, 210 { 4, 0xb0, "InRangeErrCount" }, 211 { 4, 0xb4, "OutRangeErrCount" }, 212 { 4, 0xb8, "EEELpiEvent" }, 213 { 4, 0xbc, "EEELpiDuration" }, 214 { 4, 0xc0, "RxDiscard" }, 215 { 4, 0xc8, "TxQPKTQ6" }, 216 { 4, 0xcc, "TxQPKTQ7" }, 217 { 4, 0xd0, "TxPkts64Octets" }, 218 { 4, 0xd4, "TxPkts65to127Octets" }, 219 { 4, 0xd8, "TxPkts128to255Octets" }, 220 { 4, 0xdc, "TxPkts256to511Ocets" }, 221 { 4, 0xe0, "TxPkts512to1023Ocets" }, 222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 223 }; 224 225 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 226 227 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 228 { 229 unsigned int i; 230 231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 232 233 for (i = 0; i < 10; i++) { 234 u8 vta; 235 236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 237 if (!(vta & VTA_START_CMD)) 238 return 0; 239 240 usleep_range(100, 200); 241 } 242 243 return -EIO; 244 } 245 246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 247 struct b53_vlan *vlan) 248 { 249 if (is5325(dev)) { 250 u32 entry = 0; 251 252 if (vlan->members) { 253 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 254 VA_UNTAG_S_25) | vlan->members; 255 if (dev->core_rev >= 3) 256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 257 else 258 entry |= VA_VALID_25; 259 } 260 261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 263 VTA_RW_STATE_WR | VTA_RW_OP_EN); 264 } else if (is5365(dev)) { 265 u16 entry = 0; 266 267 if (vlan->members) 268 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 270 271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 273 VTA_RW_STATE_WR | VTA_RW_OP_EN); 274 } else { 275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 277 (vlan->untag << VTE_UNTAG_S) | vlan->members); 278 279 b53_do_vlan_op(dev, VTA_CMD_WRITE); 280 } 281 282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 283 vid, vlan->members, vlan->untag); 284 } 285 286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 287 struct b53_vlan *vlan) 288 { 289 if (is5325(dev)) { 290 u32 entry = 0; 291 292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 293 VTA_RW_STATE_RD | VTA_RW_OP_EN); 294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 295 296 if (dev->core_rev >= 3) 297 vlan->valid = !!(entry & VA_VALID_25_R4); 298 else 299 vlan->valid = !!(entry & VA_VALID_25); 300 vlan->members = entry & VA_MEMBER_MASK; 301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 302 303 } else if (is5365(dev)) { 304 u16 entry = 0; 305 306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 307 VTA_RW_STATE_WR | VTA_RW_OP_EN); 308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 309 310 vlan->valid = !!(entry & VA_VALID_65); 311 vlan->members = entry & VA_MEMBER_MASK; 312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 313 } else { 314 u32 entry = 0; 315 316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 317 b53_do_vlan_op(dev, VTA_CMD_READ); 318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 319 vlan->members = entry & VTE_MEMBERS; 320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 321 vlan->valid = true; 322 } 323 } 324 325 static void b53_set_forwarding(struct b53_device *dev, int enable) 326 { 327 u8 mgmt; 328 329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 330 331 if (enable) 332 mgmt |= SM_SW_FWD_EN; 333 else 334 mgmt &= ~SM_SW_FWD_EN; 335 336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 337 338 /* Include IMP port in dumb forwarding mode 339 */ 340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 341 mgmt |= B53_MII_DUMB_FWDG_EN; 342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 343 344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 345 * frames should be flooded or not. 346 */ 347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 350 } 351 352 static void b53_enable_vlan(struct b53_device *dev, bool enable, 353 bool enable_filtering) 354 { 355 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 356 357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 360 361 if (is5325(dev) || is5365(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 364 } else if (is63xx(dev)) { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 367 } else { 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 370 } 371 372 if (enable) { 373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 375 vc4 &= ~VC4_ING_VID_CHECK_MASK; 376 if (enable_filtering) { 377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 378 vc5 |= VC5_DROP_VTABLE_MISS; 379 } else { 380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 381 vc5 &= ~VC5_DROP_VTABLE_MISS; 382 } 383 384 if (is5325(dev)) 385 vc0 &= ~VC0_RESERVED_1; 386 387 if (is5325(dev) || is5365(dev)) 388 vc1 |= VC1_RX_MCST_TAG_EN; 389 390 } else { 391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 393 vc4 &= ~VC4_ING_VID_CHECK_MASK; 394 vc5 &= ~VC5_DROP_VTABLE_MISS; 395 396 if (is5325(dev) || is5365(dev)) 397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 398 else 399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 400 401 if (is5325(dev) || is5365(dev)) 402 vc1 &= ~VC1_RX_MCST_TAG_EN; 403 } 404 405 if (!is5325(dev) && !is5365(dev)) 406 vc5 &= ~VC5_VID_FFF_EN; 407 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 410 411 if (is5325(dev) || is5365(dev)) { 412 /* enable the high 8 bit vid check on 5325 */ 413 if (is5325(dev) && enable) 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 415 VC3_HIGH_8BIT_EN); 416 else 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 418 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 421 } else if (is63xx(dev)) { 422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 425 } else { 426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 429 } 430 431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 432 433 dev->vlan_enabled = enable; 434 } 435 436 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 437 { 438 u32 port_mask = 0; 439 u16 max_size = JMS_MIN_SIZE; 440 441 if (is5325(dev) || is5365(dev)) 442 return -EINVAL; 443 444 if (enable) { 445 port_mask = dev->enabled_ports; 446 max_size = JMS_MAX_SIZE; 447 if (allow_10_100) 448 port_mask |= JPM_10_100_JUMBO_EN; 449 } 450 451 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 452 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 453 } 454 455 static int b53_flush_arl(struct b53_device *dev, u8 mask) 456 { 457 unsigned int i; 458 459 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 460 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 461 462 for (i = 0; i < 10; i++) { 463 u8 fast_age_ctrl; 464 465 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 466 &fast_age_ctrl); 467 468 if (!(fast_age_ctrl & FAST_AGE_DONE)) 469 goto out; 470 471 msleep(1); 472 } 473 474 return -ETIMEDOUT; 475 out: 476 /* Only age dynamic entries (default behavior) */ 477 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 478 return 0; 479 } 480 481 static int b53_fast_age_port(struct b53_device *dev, int port) 482 { 483 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 484 485 return b53_flush_arl(dev, FAST_AGE_PORT); 486 } 487 488 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 489 { 490 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 491 492 return b53_flush_arl(dev, FAST_AGE_VLAN); 493 } 494 495 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 496 { 497 struct b53_device *dev = ds->priv; 498 unsigned int i; 499 u16 pvlan; 500 501 /* Enable the IMP port to be in the same VLAN as the other ports 502 * on a per-port basis such that we only have Port i and IMP in 503 * the same VLAN. 504 */ 505 b53_for_each_port(dev, i) { 506 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 507 pvlan |= BIT(cpu_port); 508 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 509 } 510 } 511 EXPORT_SYMBOL(b53_imp_vlan_setup); 512 513 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 514 bool unicast) 515 { 516 u16 uc; 517 518 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 519 if (unicast) 520 uc |= BIT(port); 521 else 522 uc &= ~BIT(port); 523 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 524 } 525 526 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 527 bool multicast) 528 { 529 u16 mc; 530 531 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 532 if (multicast) 533 mc |= BIT(port); 534 else 535 mc &= ~BIT(port); 536 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 537 538 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 539 if (multicast) 540 mc |= BIT(port); 541 else 542 mc &= ~BIT(port); 543 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 544 } 545 546 static void b53_port_set_learning(struct b53_device *dev, int port, 547 bool learning) 548 { 549 u16 reg; 550 551 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 552 if (learning) 553 reg &= ~BIT(port); 554 else 555 reg |= BIT(port); 556 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 557 } 558 559 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 560 { 561 struct b53_device *dev = ds->priv; 562 unsigned int cpu_port; 563 int ret = 0; 564 u16 pvlan; 565 566 if (!dsa_is_user_port(ds, port)) 567 return 0; 568 569 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 570 571 b53_port_set_ucast_flood(dev, port, true); 572 b53_port_set_mcast_flood(dev, port, true); 573 b53_port_set_learning(dev, port, false); 574 575 if (dev->ops->irq_enable) 576 ret = dev->ops->irq_enable(dev, port); 577 if (ret) 578 return ret; 579 580 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 581 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 582 583 /* Set this port, and only this one to be in the default VLAN, 584 * if member of a bridge, restore its membership prior to 585 * bringing down this port. 586 */ 587 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 588 pvlan &= ~0x1ff; 589 pvlan |= BIT(port); 590 pvlan |= dev->ports[port].vlan_ctl_mask; 591 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 592 593 b53_imp_vlan_setup(ds, cpu_port); 594 595 /* If EEE was enabled, restore it */ 596 if (dev->ports[port].eee.eee_enabled) 597 b53_eee_enable_set(ds, port, true); 598 599 return 0; 600 } 601 EXPORT_SYMBOL(b53_enable_port); 602 603 void b53_disable_port(struct dsa_switch *ds, int port) 604 { 605 struct b53_device *dev = ds->priv; 606 u8 reg; 607 608 /* Disable Tx/Rx for the port */ 609 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 610 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 611 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 612 613 if (dev->ops->irq_disable) 614 dev->ops->irq_disable(dev, port); 615 } 616 EXPORT_SYMBOL(b53_disable_port); 617 618 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 619 { 620 struct b53_device *dev = ds->priv; 621 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 622 u8 hdr_ctl, val; 623 u16 reg; 624 625 /* Resolve which bit controls the Broadcom tag */ 626 switch (port) { 627 case 8: 628 val = BRCM_HDR_P8_EN; 629 break; 630 case 7: 631 val = BRCM_HDR_P7_EN; 632 break; 633 case 5: 634 val = BRCM_HDR_P5_EN; 635 break; 636 default: 637 val = 0; 638 break; 639 } 640 641 /* Enable management mode if tagging is requested */ 642 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 643 if (tag_en) 644 hdr_ctl |= SM_SW_FWD_MODE; 645 else 646 hdr_ctl &= ~SM_SW_FWD_MODE; 647 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 648 649 /* Configure the appropriate IMP port */ 650 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 651 if (port == 8) 652 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 653 else if (port == 5) 654 hdr_ctl |= GC_FRM_MGMT_PORT_M; 655 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 656 657 /* Enable Broadcom tags for IMP port */ 658 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 659 if (tag_en) 660 hdr_ctl |= val; 661 else 662 hdr_ctl &= ~val; 663 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 664 665 /* Registers below are only accessible on newer devices */ 666 if (!is58xx(dev)) 667 return; 668 669 /* Enable reception Broadcom tag for CPU TX (switch RX) to 670 * allow us to tag outgoing frames 671 */ 672 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 673 if (tag_en) 674 reg &= ~BIT(port); 675 else 676 reg |= BIT(port); 677 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 678 679 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 680 * allow delivering frames to the per-port net_devices 681 */ 682 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 683 if (tag_en) 684 reg &= ~BIT(port); 685 else 686 reg |= BIT(port); 687 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 688 } 689 EXPORT_SYMBOL(b53_brcm_hdr_setup); 690 691 static void b53_enable_cpu_port(struct b53_device *dev, int port) 692 { 693 u8 port_ctrl; 694 695 /* BCM5325 CPU port is at 8 */ 696 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 697 port = B53_CPU_PORT; 698 699 port_ctrl = PORT_CTRL_RX_BCST_EN | 700 PORT_CTRL_RX_MCST_EN | 701 PORT_CTRL_RX_UCST_EN; 702 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 703 704 b53_brcm_hdr_setup(dev->ds, port); 705 706 b53_port_set_ucast_flood(dev, port, true); 707 b53_port_set_mcast_flood(dev, port, true); 708 b53_port_set_learning(dev, port, false); 709 } 710 711 static void b53_enable_mib(struct b53_device *dev) 712 { 713 u8 gc; 714 715 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 716 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 717 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 718 } 719 720 static u16 b53_default_pvid(struct b53_device *dev) 721 { 722 if (is5325(dev) || is5365(dev)) 723 return 1; 724 else 725 return 0; 726 } 727 728 int b53_configure_vlan(struct dsa_switch *ds) 729 { 730 struct b53_device *dev = ds->priv; 731 struct b53_vlan vl = { 0 }; 732 struct b53_vlan *v; 733 int i, def_vid; 734 u16 vid; 735 736 def_vid = b53_default_pvid(dev); 737 738 /* clear all vlan entries */ 739 if (is5325(dev) || is5365(dev)) { 740 for (i = def_vid; i < dev->num_vlans; i++) 741 b53_set_vlan_entry(dev, i, &vl); 742 } else { 743 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 744 } 745 746 b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering); 747 748 b53_for_each_port(dev, i) 749 b53_write16(dev, B53_VLAN_PAGE, 750 B53_VLAN_PORT_DEF_TAG(i), def_vid); 751 752 /* Upon initial call we have not set-up any VLANs, but upon 753 * system resume, we need to restore all VLAN entries. 754 */ 755 for (vid = def_vid; vid < dev->num_vlans; vid++) { 756 v = &dev->vlans[vid]; 757 758 if (!v->members) 759 continue; 760 761 b53_set_vlan_entry(dev, vid, v); 762 b53_fast_age_vlan(dev, vid); 763 } 764 765 return 0; 766 } 767 EXPORT_SYMBOL(b53_configure_vlan); 768 769 static void b53_switch_reset_gpio(struct b53_device *dev) 770 { 771 int gpio = dev->reset_gpio; 772 773 if (gpio < 0) 774 return; 775 776 /* Reset sequence: RESET low(50ms)->high(20ms) 777 */ 778 gpio_set_value(gpio, 0); 779 mdelay(50); 780 781 gpio_set_value(gpio, 1); 782 mdelay(20); 783 784 dev->current_page = 0xff; 785 } 786 787 static int b53_switch_reset(struct b53_device *dev) 788 { 789 unsigned int timeout = 1000; 790 u8 mgmt, reg; 791 792 b53_switch_reset_gpio(dev); 793 794 if (is539x(dev)) { 795 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 796 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 797 } 798 799 /* This is specific to 58xx devices here, do not use is58xx() which 800 * covers the larger Starfigther 2 family, including 7445/7278 which 801 * still use this driver as a library and need to perform the reset 802 * earlier. 803 */ 804 if (dev->chip_id == BCM58XX_DEVICE_ID || 805 dev->chip_id == BCM583XX_DEVICE_ID) { 806 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 807 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 808 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 809 810 do { 811 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 812 if (!(reg & SW_RST)) 813 break; 814 815 usleep_range(1000, 2000); 816 } while (timeout-- > 0); 817 818 if (timeout == 0) { 819 dev_err(dev->dev, 820 "Timeout waiting for SW_RST to clear!\n"); 821 return -ETIMEDOUT; 822 } 823 } 824 825 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 826 827 if (!(mgmt & SM_SW_FWD_EN)) { 828 mgmt &= ~SM_SW_FWD_MODE; 829 mgmt |= SM_SW_FWD_EN; 830 831 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 832 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 833 834 if (!(mgmt & SM_SW_FWD_EN)) { 835 dev_err(dev->dev, "Failed to enable switch!\n"); 836 return -EINVAL; 837 } 838 } 839 840 b53_enable_mib(dev); 841 842 return b53_flush_arl(dev, FAST_AGE_STATIC); 843 } 844 845 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 846 { 847 struct b53_device *priv = ds->priv; 848 u16 value = 0; 849 int ret; 850 851 if (priv->ops->phy_read16) 852 ret = priv->ops->phy_read16(priv, addr, reg, &value); 853 else 854 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 855 reg * 2, &value); 856 857 return ret ? ret : value; 858 } 859 860 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 861 { 862 struct b53_device *priv = ds->priv; 863 864 if (priv->ops->phy_write16) 865 return priv->ops->phy_write16(priv, addr, reg, val); 866 867 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 868 } 869 870 static int b53_reset_switch(struct b53_device *priv) 871 { 872 /* reset vlans */ 873 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 874 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 875 876 priv->serdes_lane = B53_INVALID_LANE; 877 878 return b53_switch_reset(priv); 879 } 880 881 static int b53_apply_config(struct b53_device *priv) 882 { 883 /* disable switching */ 884 b53_set_forwarding(priv, 0); 885 886 b53_configure_vlan(priv->ds); 887 888 /* enable switching */ 889 b53_set_forwarding(priv, 1); 890 891 return 0; 892 } 893 894 static void b53_reset_mib(struct b53_device *priv) 895 { 896 u8 gc; 897 898 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 899 900 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 901 msleep(1); 902 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 903 msleep(1); 904 } 905 906 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 907 { 908 if (is5365(dev)) 909 return b53_mibs_65; 910 else if (is63xx(dev)) 911 return b53_mibs_63xx; 912 else if (is58xx(dev)) 913 return b53_mibs_58xx; 914 else 915 return b53_mibs; 916 } 917 918 static unsigned int b53_get_mib_size(struct b53_device *dev) 919 { 920 if (is5365(dev)) 921 return B53_MIBS_65_SIZE; 922 else if (is63xx(dev)) 923 return B53_MIBS_63XX_SIZE; 924 else if (is58xx(dev)) 925 return B53_MIBS_58XX_SIZE; 926 else 927 return B53_MIBS_SIZE; 928 } 929 930 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 931 { 932 /* These ports typically do not have built-in PHYs */ 933 switch (port) { 934 case B53_CPU_PORT_25: 935 case 7: 936 case B53_CPU_PORT: 937 return NULL; 938 } 939 940 return mdiobus_get_phy(ds->slave_mii_bus, port); 941 } 942 943 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 944 uint8_t *data) 945 { 946 struct b53_device *dev = ds->priv; 947 const struct b53_mib_desc *mibs = b53_get_mib(dev); 948 unsigned int mib_size = b53_get_mib_size(dev); 949 struct phy_device *phydev; 950 unsigned int i; 951 952 if (stringset == ETH_SS_STATS) { 953 for (i = 0; i < mib_size; i++) 954 strlcpy(data + i * ETH_GSTRING_LEN, 955 mibs[i].name, ETH_GSTRING_LEN); 956 } else if (stringset == ETH_SS_PHY_STATS) { 957 phydev = b53_get_phy_device(ds, port); 958 if (!phydev) 959 return; 960 961 phy_ethtool_get_strings(phydev, data); 962 } 963 } 964 EXPORT_SYMBOL(b53_get_strings); 965 966 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 967 { 968 struct b53_device *dev = ds->priv; 969 const struct b53_mib_desc *mibs = b53_get_mib(dev); 970 unsigned int mib_size = b53_get_mib_size(dev); 971 const struct b53_mib_desc *s; 972 unsigned int i; 973 u64 val = 0; 974 975 if (is5365(dev) && port == 5) 976 port = 8; 977 978 mutex_lock(&dev->stats_mutex); 979 980 for (i = 0; i < mib_size; i++) { 981 s = &mibs[i]; 982 983 if (s->size == 8) { 984 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 985 } else { 986 u32 val32; 987 988 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 989 &val32); 990 val = val32; 991 } 992 data[i] = (u64)val; 993 } 994 995 mutex_unlock(&dev->stats_mutex); 996 } 997 EXPORT_SYMBOL(b53_get_ethtool_stats); 998 999 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1000 { 1001 struct phy_device *phydev; 1002 1003 phydev = b53_get_phy_device(ds, port); 1004 if (!phydev) 1005 return; 1006 1007 phy_ethtool_get_stats(phydev, NULL, data); 1008 } 1009 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1010 1011 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1012 { 1013 struct b53_device *dev = ds->priv; 1014 struct phy_device *phydev; 1015 1016 if (sset == ETH_SS_STATS) { 1017 return b53_get_mib_size(dev); 1018 } else if (sset == ETH_SS_PHY_STATS) { 1019 phydev = b53_get_phy_device(ds, port); 1020 if (!phydev) 1021 return 0; 1022 1023 return phy_ethtool_get_sset_count(phydev); 1024 } 1025 1026 return 0; 1027 } 1028 EXPORT_SYMBOL(b53_get_sset_count); 1029 1030 enum b53_devlink_resource_id { 1031 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1032 }; 1033 1034 static u64 b53_devlink_vlan_table_get(void *priv) 1035 { 1036 struct b53_device *dev = priv; 1037 struct b53_vlan *vl; 1038 unsigned int i; 1039 u64 count = 0; 1040 1041 for (i = 0; i < dev->num_vlans; i++) { 1042 vl = &dev->vlans[i]; 1043 if (vl->members) 1044 count++; 1045 } 1046 1047 return count; 1048 } 1049 1050 int b53_setup_devlink_resources(struct dsa_switch *ds) 1051 { 1052 struct devlink_resource_size_params size_params; 1053 struct b53_device *dev = ds->priv; 1054 int err; 1055 1056 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1057 dev->num_vlans, 1058 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1059 1060 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1061 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1062 DEVLINK_RESOURCE_ID_PARENT_TOP, 1063 &size_params); 1064 if (err) 1065 goto out; 1066 1067 dsa_devlink_resource_occ_get_register(ds, 1068 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1069 b53_devlink_vlan_table_get, dev); 1070 1071 return 0; 1072 out: 1073 dsa_devlink_resources_unregister(ds); 1074 return err; 1075 } 1076 EXPORT_SYMBOL(b53_setup_devlink_resources); 1077 1078 static int b53_setup(struct dsa_switch *ds) 1079 { 1080 struct b53_device *dev = ds->priv; 1081 unsigned int port; 1082 int ret; 1083 1084 ret = b53_reset_switch(dev); 1085 if (ret) { 1086 dev_err(ds->dev, "failed to reset switch\n"); 1087 return ret; 1088 } 1089 1090 b53_reset_mib(dev); 1091 1092 ret = b53_apply_config(dev); 1093 if (ret) { 1094 dev_err(ds->dev, "failed to apply configuration\n"); 1095 return ret; 1096 } 1097 1098 /* Configure IMP/CPU port, disable all other ports. Enabled 1099 * ports will be configured with .port_enable 1100 */ 1101 for (port = 0; port < dev->num_ports; port++) { 1102 if (dsa_is_cpu_port(ds, port)) 1103 b53_enable_cpu_port(dev, port); 1104 else 1105 b53_disable_port(ds, port); 1106 } 1107 1108 /* Let DSA handle the case were multiple bridges span the same switch 1109 * device and different VLAN awareness settings are requested, which 1110 * would be breaking filtering semantics for any of the other bridge 1111 * devices. (not hardware supported) 1112 */ 1113 ds->vlan_filtering_is_global = true; 1114 1115 return b53_setup_devlink_resources(ds); 1116 } 1117 1118 static void b53_teardown(struct dsa_switch *ds) 1119 { 1120 dsa_devlink_resources_unregister(ds); 1121 } 1122 1123 static void b53_force_link(struct b53_device *dev, int port, int link) 1124 { 1125 u8 reg, val, off; 1126 1127 /* Override the port settings */ 1128 if (port == dev->cpu_port) { 1129 off = B53_PORT_OVERRIDE_CTRL; 1130 val = PORT_OVERRIDE_EN; 1131 } else { 1132 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1133 val = GMII_PO_EN; 1134 } 1135 1136 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1137 reg |= val; 1138 if (link) 1139 reg |= PORT_OVERRIDE_LINK; 1140 else 1141 reg &= ~PORT_OVERRIDE_LINK; 1142 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1143 } 1144 1145 static void b53_force_port_config(struct b53_device *dev, int port, 1146 int speed, int duplex, 1147 bool tx_pause, bool rx_pause) 1148 { 1149 u8 reg, val, off; 1150 1151 /* Override the port settings */ 1152 if (port == dev->cpu_port) { 1153 off = B53_PORT_OVERRIDE_CTRL; 1154 val = PORT_OVERRIDE_EN; 1155 } else { 1156 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1157 val = GMII_PO_EN; 1158 } 1159 1160 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1161 reg |= val; 1162 if (duplex == DUPLEX_FULL) 1163 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1164 else 1165 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1166 1167 switch (speed) { 1168 case 2000: 1169 reg |= PORT_OVERRIDE_SPEED_2000M; 1170 fallthrough; 1171 case SPEED_1000: 1172 reg |= PORT_OVERRIDE_SPEED_1000M; 1173 break; 1174 case SPEED_100: 1175 reg |= PORT_OVERRIDE_SPEED_100M; 1176 break; 1177 case SPEED_10: 1178 reg |= PORT_OVERRIDE_SPEED_10M; 1179 break; 1180 default: 1181 dev_err(dev->dev, "unknown speed: %d\n", speed); 1182 return; 1183 } 1184 1185 if (rx_pause) 1186 reg |= PORT_OVERRIDE_RX_FLOW; 1187 if (tx_pause) 1188 reg |= PORT_OVERRIDE_TX_FLOW; 1189 1190 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1191 } 1192 1193 static void b53_adjust_link(struct dsa_switch *ds, int port, 1194 struct phy_device *phydev) 1195 { 1196 struct b53_device *dev = ds->priv; 1197 struct ethtool_eee *p = &dev->ports[port].eee; 1198 u8 rgmii_ctrl = 0, reg = 0, off; 1199 bool tx_pause = false; 1200 bool rx_pause = false; 1201 1202 if (!phy_is_pseudo_fixed_link(phydev)) 1203 return; 1204 1205 /* Enable flow control on BCM5301x's CPU port */ 1206 if (is5301x(dev) && port == dev->cpu_port) 1207 tx_pause = rx_pause = true; 1208 1209 if (phydev->pause) { 1210 if (phydev->asym_pause) 1211 tx_pause = true; 1212 rx_pause = true; 1213 } 1214 1215 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, 1216 tx_pause, rx_pause); 1217 b53_force_link(dev, port, phydev->link); 1218 1219 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1220 if (port == 8) 1221 off = B53_RGMII_CTRL_IMP; 1222 else 1223 off = B53_RGMII_CTRL_P(port); 1224 1225 /* Configure the port RGMII clock delay by DLL disabled and 1226 * tx_clk aligned timing (restoring to reset defaults) 1227 */ 1228 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1229 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1230 RGMII_CTRL_TIMING_SEL); 1231 1232 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1233 * sure that we enable the port TX clock internal delay to 1234 * account for this internal delay that is inserted, otherwise 1235 * the switch won't be able to receive correctly. 1236 * 1237 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1238 * any delay neither on transmission nor reception, so the 1239 * BCM53125 must also be configured accordingly to account for 1240 * the lack of delay and introduce 1241 * 1242 * The BCM53125 switch has its RX clock and TX clock control 1243 * swapped, hence the reason why we modify the TX clock path in 1244 * the "RGMII" case 1245 */ 1246 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1247 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1248 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1249 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1250 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1251 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1252 1253 dev_info(ds->dev, "Configured port %d for %s\n", port, 1254 phy_modes(phydev->interface)); 1255 } 1256 1257 /* configure MII port if necessary */ 1258 if (is5325(dev)) { 1259 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1260 ®); 1261 1262 /* reverse mii needs to be enabled */ 1263 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1264 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1265 reg | PORT_OVERRIDE_RV_MII_25); 1266 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1267 ®); 1268 1269 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1270 dev_err(ds->dev, 1271 "Failed to enable reverse MII mode\n"); 1272 return; 1273 } 1274 } 1275 } else if (is5301x(dev)) { 1276 if (port != dev->cpu_port) { 1277 b53_force_port_config(dev, dev->cpu_port, 2000, 1278 DUPLEX_FULL, true, true); 1279 b53_force_link(dev, dev->cpu_port, 1); 1280 } 1281 } 1282 1283 /* Re-negotiate EEE if it was enabled already */ 1284 p->eee_enabled = b53_eee_init(ds, port, phydev); 1285 } 1286 1287 void b53_port_event(struct dsa_switch *ds, int port) 1288 { 1289 struct b53_device *dev = ds->priv; 1290 bool link; 1291 u16 sts; 1292 1293 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1294 link = !!(sts & BIT(port)); 1295 dsa_port_phylink_mac_change(ds, port, link); 1296 } 1297 EXPORT_SYMBOL(b53_port_event); 1298 1299 void b53_phylink_validate(struct dsa_switch *ds, int port, 1300 unsigned long *supported, 1301 struct phylink_link_state *state) 1302 { 1303 struct b53_device *dev = ds->priv; 1304 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1305 1306 if (dev->ops->serdes_phylink_validate) 1307 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1308 1309 /* Allow all the expected bits */ 1310 phylink_set(mask, Autoneg); 1311 phylink_set_port_modes(mask); 1312 phylink_set(mask, Pause); 1313 phylink_set(mask, Asym_Pause); 1314 1315 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1316 * support Gigabit, including Half duplex. 1317 */ 1318 if (state->interface != PHY_INTERFACE_MODE_MII && 1319 state->interface != PHY_INTERFACE_MODE_REVMII && 1320 !phy_interface_mode_is_8023z(state->interface) && 1321 !(is5325(dev) || is5365(dev))) { 1322 phylink_set(mask, 1000baseT_Full); 1323 phylink_set(mask, 1000baseT_Half); 1324 } 1325 1326 if (!phy_interface_mode_is_8023z(state->interface)) { 1327 phylink_set(mask, 10baseT_Half); 1328 phylink_set(mask, 10baseT_Full); 1329 phylink_set(mask, 100baseT_Half); 1330 phylink_set(mask, 100baseT_Full); 1331 } 1332 1333 bitmap_and(supported, supported, mask, 1334 __ETHTOOL_LINK_MODE_MASK_NBITS); 1335 bitmap_and(state->advertising, state->advertising, mask, 1336 __ETHTOOL_LINK_MODE_MASK_NBITS); 1337 1338 phylink_helper_basex_speed(state); 1339 } 1340 EXPORT_SYMBOL(b53_phylink_validate); 1341 1342 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1343 struct phylink_link_state *state) 1344 { 1345 struct b53_device *dev = ds->priv; 1346 int ret = -EOPNOTSUPP; 1347 1348 if ((phy_interface_mode_is_8023z(state->interface) || 1349 state->interface == PHY_INTERFACE_MODE_SGMII) && 1350 dev->ops->serdes_link_state) 1351 ret = dev->ops->serdes_link_state(dev, port, state); 1352 1353 return ret; 1354 } 1355 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1356 1357 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1358 unsigned int mode, 1359 const struct phylink_link_state *state) 1360 { 1361 struct b53_device *dev = ds->priv; 1362 1363 if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED) 1364 return; 1365 1366 if ((phy_interface_mode_is_8023z(state->interface) || 1367 state->interface == PHY_INTERFACE_MODE_SGMII) && 1368 dev->ops->serdes_config) 1369 dev->ops->serdes_config(dev, port, mode, state); 1370 } 1371 EXPORT_SYMBOL(b53_phylink_mac_config); 1372 1373 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1374 { 1375 struct b53_device *dev = ds->priv; 1376 1377 if (dev->ops->serdes_an_restart) 1378 dev->ops->serdes_an_restart(dev, port); 1379 } 1380 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1381 1382 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1383 unsigned int mode, 1384 phy_interface_t interface) 1385 { 1386 struct b53_device *dev = ds->priv; 1387 1388 if (mode == MLO_AN_PHY) 1389 return; 1390 1391 if (mode == MLO_AN_FIXED) { 1392 b53_force_link(dev, port, false); 1393 return; 1394 } 1395 1396 if (phy_interface_mode_is_8023z(interface) && 1397 dev->ops->serdes_link_set) 1398 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1399 } 1400 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1401 1402 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1403 unsigned int mode, 1404 phy_interface_t interface, 1405 struct phy_device *phydev, 1406 int speed, int duplex, 1407 bool tx_pause, bool rx_pause) 1408 { 1409 struct b53_device *dev = ds->priv; 1410 1411 if (mode == MLO_AN_PHY) 1412 return; 1413 1414 if (mode == MLO_AN_FIXED) { 1415 b53_force_port_config(dev, port, speed, duplex, 1416 tx_pause, rx_pause); 1417 b53_force_link(dev, port, true); 1418 return; 1419 } 1420 1421 if (phy_interface_mode_is_8023z(interface) && 1422 dev->ops->serdes_link_set) 1423 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1424 } 1425 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1426 1427 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1428 struct netlink_ext_ack *extack) 1429 { 1430 struct b53_device *dev = ds->priv; 1431 1432 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering); 1433 1434 return 0; 1435 } 1436 EXPORT_SYMBOL(b53_vlan_filtering); 1437 1438 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1439 const struct switchdev_obj_port_vlan *vlan) 1440 { 1441 struct b53_device *dev = ds->priv; 1442 1443 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1444 return -EOPNOTSUPP; 1445 1446 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1447 * receiving VLAN tagged frames at all, we can still allow the port to 1448 * be configured for egress untagged. 1449 */ 1450 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1451 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1452 return -EINVAL; 1453 1454 if (vlan->vid >= dev->num_vlans) 1455 return -ERANGE; 1456 1457 b53_enable_vlan(dev, true, ds->vlan_filtering); 1458 1459 return 0; 1460 } 1461 1462 int b53_vlan_add(struct dsa_switch *ds, int port, 1463 const struct switchdev_obj_port_vlan *vlan, 1464 struct netlink_ext_ack *extack) 1465 { 1466 struct b53_device *dev = ds->priv; 1467 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1468 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1469 struct b53_vlan *vl; 1470 int err; 1471 1472 err = b53_vlan_prepare(ds, port, vlan); 1473 if (err) 1474 return err; 1475 1476 vl = &dev->vlans[vlan->vid]; 1477 1478 b53_get_vlan_entry(dev, vlan->vid, vl); 1479 1480 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1481 untagged = true; 1482 1483 vl->members |= BIT(port); 1484 if (untagged && !dsa_is_cpu_port(ds, port)) 1485 vl->untag |= BIT(port); 1486 else 1487 vl->untag &= ~BIT(port); 1488 1489 b53_set_vlan_entry(dev, vlan->vid, vl); 1490 b53_fast_age_vlan(dev, vlan->vid); 1491 1492 if (pvid && !dsa_is_cpu_port(ds, port)) { 1493 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1494 vlan->vid); 1495 b53_fast_age_vlan(dev, vlan->vid); 1496 } 1497 1498 return 0; 1499 } 1500 EXPORT_SYMBOL(b53_vlan_add); 1501 1502 int b53_vlan_del(struct dsa_switch *ds, int port, 1503 const struct switchdev_obj_port_vlan *vlan) 1504 { 1505 struct b53_device *dev = ds->priv; 1506 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1507 struct b53_vlan *vl; 1508 u16 pvid; 1509 1510 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1511 1512 vl = &dev->vlans[vlan->vid]; 1513 1514 b53_get_vlan_entry(dev, vlan->vid, vl); 1515 1516 vl->members &= ~BIT(port); 1517 1518 if (pvid == vlan->vid) 1519 pvid = b53_default_pvid(dev); 1520 1521 if (untagged && !dsa_is_cpu_port(ds, port)) 1522 vl->untag &= ~(BIT(port)); 1523 1524 b53_set_vlan_entry(dev, vlan->vid, vl); 1525 b53_fast_age_vlan(dev, vlan->vid); 1526 1527 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1528 b53_fast_age_vlan(dev, pvid); 1529 1530 return 0; 1531 } 1532 EXPORT_SYMBOL(b53_vlan_del); 1533 1534 /* Address Resolution Logic routines */ 1535 static int b53_arl_op_wait(struct b53_device *dev) 1536 { 1537 unsigned int timeout = 10; 1538 u8 reg; 1539 1540 do { 1541 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1542 if (!(reg & ARLTBL_START_DONE)) 1543 return 0; 1544 1545 usleep_range(1000, 2000); 1546 } while (timeout--); 1547 1548 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1549 1550 return -ETIMEDOUT; 1551 } 1552 1553 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1554 { 1555 u8 reg; 1556 1557 if (op > ARLTBL_RW) 1558 return -EINVAL; 1559 1560 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1561 reg |= ARLTBL_START_DONE; 1562 if (op) 1563 reg |= ARLTBL_RW; 1564 else 1565 reg &= ~ARLTBL_RW; 1566 if (dev->vlan_enabled) 1567 reg &= ~ARLTBL_IVL_SVL_SELECT; 1568 else 1569 reg |= ARLTBL_IVL_SVL_SELECT; 1570 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1571 1572 return b53_arl_op_wait(dev); 1573 } 1574 1575 static int b53_arl_read(struct b53_device *dev, u64 mac, 1576 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1577 { 1578 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1579 unsigned int i; 1580 int ret; 1581 1582 ret = b53_arl_op_wait(dev); 1583 if (ret) 1584 return ret; 1585 1586 bitmap_zero(free_bins, dev->num_arl_bins); 1587 1588 /* Read the bins */ 1589 for (i = 0; i < dev->num_arl_bins; i++) { 1590 u64 mac_vid; 1591 u32 fwd_entry; 1592 1593 b53_read64(dev, B53_ARLIO_PAGE, 1594 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1595 b53_read32(dev, B53_ARLIO_PAGE, 1596 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1597 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1598 1599 if (!(fwd_entry & ARLTBL_VALID)) { 1600 set_bit(i, free_bins); 1601 continue; 1602 } 1603 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1604 continue; 1605 if (dev->vlan_enabled && 1606 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1607 continue; 1608 *idx = i; 1609 return 0; 1610 } 1611 1612 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0) 1613 return -ENOSPC; 1614 1615 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1616 1617 return -ENOENT; 1618 } 1619 1620 static int b53_arl_op(struct b53_device *dev, int op, int port, 1621 const unsigned char *addr, u16 vid, bool is_valid) 1622 { 1623 struct b53_arl_entry ent; 1624 u32 fwd_entry; 1625 u64 mac, mac_vid = 0; 1626 u8 idx = 0; 1627 int ret; 1628 1629 /* Convert the array into a 64-bit MAC */ 1630 mac = ether_addr_to_u64(addr); 1631 1632 /* Perform a read for the given MAC and VID */ 1633 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1634 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1635 1636 /* Issue a read operation for this MAC */ 1637 ret = b53_arl_rw_op(dev, 1); 1638 if (ret) 1639 return ret; 1640 1641 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1642 1643 /* If this is a read, just finish now */ 1644 if (op) 1645 return ret; 1646 1647 switch (ret) { 1648 case -ETIMEDOUT: 1649 return ret; 1650 case -ENOSPC: 1651 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1652 addr, vid); 1653 return is_valid ? ret : 0; 1654 case -ENOENT: 1655 /* We could not find a matching MAC, so reset to a new entry */ 1656 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1657 addr, vid, idx); 1658 fwd_entry = 0; 1659 break; 1660 default: 1661 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1662 addr, vid, idx); 1663 break; 1664 } 1665 1666 /* For multicast address, the port is a bitmask and the validity 1667 * is determined by having at least one port being still active 1668 */ 1669 if (!is_multicast_ether_addr(addr)) { 1670 ent.port = port; 1671 ent.is_valid = is_valid; 1672 } else { 1673 if (is_valid) 1674 ent.port |= BIT(port); 1675 else 1676 ent.port &= ~BIT(port); 1677 1678 ent.is_valid = !!(ent.port); 1679 } 1680 1681 ent.vid = vid; 1682 ent.is_static = true; 1683 ent.is_age = false; 1684 memcpy(ent.mac, addr, ETH_ALEN); 1685 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1686 1687 b53_write64(dev, B53_ARLIO_PAGE, 1688 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1689 b53_write32(dev, B53_ARLIO_PAGE, 1690 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1691 1692 return b53_arl_rw_op(dev, 0); 1693 } 1694 1695 int b53_fdb_add(struct dsa_switch *ds, int port, 1696 const unsigned char *addr, u16 vid) 1697 { 1698 struct b53_device *priv = ds->priv; 1699 1700 /* 5325 and 5365 require some more massaging, but could 1701 * be supported eventually 1702 */ 1703 if (is5325(priv) || is5365(priv)) 1704 return -EOPNOTSUPP; 1705 1706 return b53_arl_op(priv, 0, port, addr, vid, true); 1707 } 1708 EXPORT_SYMBOL(b53_fdb_add); 1709 1710 int b53_fdb_del(struct dsa_switch *ds, int port, 1711 const unsigned char *addr, u16 vid) 1712 { 1713 struct b53_device *priv = ds->priv; 1714 1715 return b53_arl_op(priv, 0, port, addr, vid, false); 1716 } 1717 EXPORT_SYMBOL(b53_fdb_del); 1718 1719 static int b53_arl_search_wait(struct b53_device *dev) 1720 { 1721 unsigned int timeout = 1000; 1722 u8 reg; 1723 1724 do { 1725 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1726 if (!(reg & ARL_SRCH_STDN)) 1727 return 0; 1728 1729 if (reg & ARL_SRCH_VLID) 1730 return 0; 1731 1732 usleep_range(1000, 2000); 1733 } while (timeout--); 1734 1735 return -ETIMEDOUT; 1736 } 1737 1738 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1739 struct b53_arl_entry *ent) 1740 { 1741 u64 mac_vid; 1742 u32 fwd_entry; 1743 1744 b53_read64(dev, B53_ARLIO_PAGE, 1745 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1746 b53_read32(dev, B53_ARLIO_PAGE, 1747 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1748 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1749 } 1750 1751 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1752 dsa_fdb_dump_cb_t *cb, void *data) 1753 { 1754 if (!ent->is_valid) 1755 return 0; 1756 1757 if (port != ent->port) 1758 return 0; 1759 1760 return cb(ent->mac, ent->vid, ent->is_static, data); 1761 } 1762 1763 int b53_fdb_dump(struct dsa_switch *ds, int port, 1764 dsa_fdb_dump_cb_t *cb, void *data) 1765 { 1766 struct b53_device *priv = ds->priv; 1767 struct b53_arl_entry results[2]; 1768 unsigned int count = 0; 1769 int ret; 1770 u8 reg; 1771 1772 /* Start search operation */ 1773 reg = ARL_SRCH_STDN; 1774 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1775 1776 do { 1777 ret = b53_arl_search_wait(priv); 1778 if (ret) 1779 return ret; 1780 1781 b53_arl_search_rd(priv, 0, &results[0]); 1782 ret = b53_fdb_copy(port, &results[0], cb, data); 1783 if (ret) 1784 return ret; 1785 1786 if (priv->num_arl_bins > 2) { 1787 b53_arl_search_rd(priv, 1, &results[1]); 1788 ret = b53_fdb_copy(port, &results[1], cb, data); 1789 if (ret) 1790 return ret; 1791 1792 if (!results[0].is_valid && !results[1].is_valid) 1793 break; 1794 } 1795 1796 } while (count++ < b53_max_arl_entries(priv) / 2); 1797 1798 return 0; 1799 } 1800 EXPORT_SYMBOL(b53_fdb_dump); 1801 1802 int b53_mdb_add(struct dsa_switch *ds, int port, 1803 const struct switchdev_obj_port_mdb *mdb) 1804 { 1805 struct b53_device *priv = ds->priv; 1806 1807 /* 5325 and 5365 require some more massaging, but could 1808 * be supported eventually 1809 */ 1810 if (is5325(priv) || is5365(priv)) 1811 return -EOPNOTSUPP; 1812 1813 return b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1814 } 1815 EXPORT_SYMBOL(b53_mdb_add); 1816 1817 int b53_mdb_del(struct dsa_switch *ds, int port, 1818 const struct switchdev_obj_port_mdb *mdb) 1819 { 1820 struct b53_device *priv = ds->priv; 1821 int ret; 1822 1823 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1824 if (ret) 1825 dev_err(ds->dev, "failed to delete MDB entry\n"); 1826 1827 return ret; 1828 } 1829 EXPORT_SYMBOL(b53_mdb_del); 1830 1831 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1832 { 1833 struct b53_device *dev = ds->priv; 1834 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1835 u16 pvlan, reg; 1836 unsigned int i; 1837 1838 /* On 7278, port 7 which connects to the ASP should only receive 1839 * traffic from matching CFP rules. 1840 */ 1841 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1842 return -EINVAL; 1843 1844 /* Make this port leave the all VLANs join since we will have proper 1845 * VLAN entries from now on 1846 */ 1847 if (is58xx(dev)) { 1848 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1849 reg &= ~BIT(port); 1850 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1851 reg &= ~BIT(cpu_port); 1852 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1853 } 1854 1855 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1856 1857 b53_for_each_port(dev, i) { 1858 if (dsa_to_port(ds, i)->bridge_dev != br) 1859 continue; 1860 1861 /* Add this local port to the remote port VLAN control 1862 * membership and update the remote port bitmask 1863 */ 1864 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1865 reg |= BIT(port); 1866 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1867 dev->ports[i].vlan_ctl_mask = reg; 1868 1869 pvlan |= BIT(i); 1870 } 1871 1872 /* Configure the local port VLAN control membership to include 1873 * remote ports and update the local port bitmask 1874 */ 1875 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1876 dev->ports[port].vlan_ctl_mask = pvlan; 1877 1878 return 0; 1879 } 1880 EXPORT_SYMBOL(b53_br_join); 1881 1882 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1883 { 1884 struct b53_device *dev = ds->priv; 1885 struct b53_vlan *vl = &dev->vlans[0]; 1886 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1887 unsigned int i; 1888 u16 pvlan, reg, pvid; 1889 1890 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1891 1892 b53_for_each_port(dev, i) { 1893 /* Don't touch the remaining ports */ 1894 if (dsa_to_port(ds, i)->bridge_dev != br) 1895 continue; 1896 1897 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1898 reg &= ~BIT(port); 1899 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1900 dev->ports[port].vlan_ctl_mask = reg; 1901 1902 /* Prevent self removal to preserve isolation */ 1903 if (port != i) 1904 pvlan &= ~BIT(i); 1905 } 1906 1907 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1908 dev->ports[port].vlan_ctl_mask = pvlan; 1909 1910 pvid = b53_default_pvid(dev); 1911 1912 /* Make this port join all VLANs without VLAN entries */ 1913 if (is58xx(dev)) { 1914 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1915 reg |= BIT(port); 1916 if (!(reg & BIT(cpu_port))) 1917 reg |= BIT(cpu_port); 1918 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1919 } else { 1920 b53_get_vlan_entry(dev, pvid, vl); 1921 vl->members |= BIT(port) | BIT(cpu_port); 1922 vl->untag |= BIT(port) | BIT(cpu_port); 1923 b53_set_vlan_entry(dev, pvid, vl); 1924 } 1925 } 1926 EXPORT_SYMBOL(b53_br_leave); 1927 1928 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1929 { 1930 struct b53_device *dev = ds->priv; 1931 u8 hw_state; 1932 u8 reg; 1933 1934 switch (state) { 1935 case BR_STATE_DISABLED: 1936 hw_state = PORT_CTRL_DIS_STATE; 1937 break; 1938 case BR_STATE_LISTENING: 1939 hw_state = PORT_CTRL_LISTEN_STATE; 1940 break; 1941 case BR_STATE_LEARNING: 1942 hw_state = PORT_CTRL_LEARN_STATE; 1943 break; 1944 case BR_STATE_FORWARDING: 1945 hw_state = PORT_CTRL_FWD_STATE; 1946 break; 1947 case BR_STATE_BLOCKING: 1948 hw_state = PORT_CTRL_BLOCK_STATE; 1949 break; 1950 default: 1951 dev_err(ds->dev, "invalid STP state: %d\n", state); 1952 return; 1953 } 1954 1955 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1956 reg &= ~PORT_CTRL_STP_STATE_MASK; 1957 reg |= hw_state; 1958 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1959 } 1960 EXPORT_SYMBOL(b53_br_set_stp_state); 1961 1962 void b53_br_fast_age(struct dsa_switch *ds, int port) 1963 { 1964 struct b53_device *dev = ds->priv; 1965 1966 if (b53_fast_age_port(dev, port)) 1967 dev_err(ds->dev, "fast ageing failed\n"); 1968 } 1969 EXPORT_SYMBOL(b53_br_fast_age); 1970 1971 int b53_br_flags_pre(struct dsa_switch *ds, int port, 1972 struct switchdev_brport_flags flags, 1973 struct netlink_ext_ack *extack) 1974 { 1975 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 1976 return -EINVAL; 1977 1978 return 0; 1979 } 1980 EXPORT_SYMBOL(b53_br_flags_pre); 1981 1982 int b53_br_flags(struct dsa_switch *ds, int port, 1983 struct switchdev_brport_flags flags, 1984 struct netlink_ext_ack *extack) 1985 { 1986 if (flags.mask & BR_FLOOD) 1987 b53_port_set_ucast_flood(ds->priv, port, 1988 !!(flags.val & BR_FLOOD)); 1989 if (flags.mask & BR_MCAST_FLOOD) 1990 b53_port_set_mcast_flood(ds->priv, port, 1991 !!(flags.val & BR_MCAST_FLOOD)); 1992 if (flags.mask & BR_LEARNING) 1993 b53_port_set_learning(ds->priv, port, 1994 !!(flags.val & BR_LEARNING)); 1995 1996 return 0; 1997 } 1998 EXPORT_SYMBOL(b53_br_flags); 1999 2000 int b53_set_mrouter(struct dsa_switch *ds, int port, bool mrouter, 2001 struct netlink_ext_ack *extack) 2002 { 2003 b53_port_set_mcast_flood(ds->priv, port, mrouter); 2004 2005 return 0; 2006 } 2007 EXPORT_SYMBOL(b53_set_mrouter); 2008 2009 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2010 { 2011 /* Broadcom switches will accept enabling Broadcom tags on the 2012 * following ports: 5, 7 and 8, any other port is not supported 2013 */ 2014 switch (port) { 2015 case B53_CPU_PORT_25: 2016 case 7: 2017 case B53_CPU_PORT: 2018 return true; 2019 } 2020 2021 return false; 2022 } 2023 2024 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2025 enum dsa_tag_protocol tag_protocol) 2026 { 2027 bool ret = b53_possible_cpu_port(ds, port); 2028 2029 if (!ret) { 2030 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2031 port); 2032 return ret; 2033 } 2034 2035 switch (tag_protocol) { 2036 case DSA_TAG_PROTO_BRCM: 2037 case DSA_TAG_PROTO_BRCM_PREPEND: 2038 dev_warn(ds->dev, 2039 "Port %d is stacked to Broadcom tag switch\n", port); 2040 ret = false; 2041 break; 2042 default: 2043 ret = true; 2044 break; 2045 } 2046 2047 return ret; 2048 } 2049 2050 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2051 enum dsa_tag_protocol mprot) 2052 { 2053 struct b53_device *dev = ds->priv; 2054 2055 /* Older models (5325, 5365) support a different tag format that we do 2056 * not support in net/dsa/tag_brcm.c yet. 2057 */ 2058 if (is5325(dev) || is5365(dev) || 2059 !b53_can_enable_brcm_tags(ds, port, mprot)) { 2060 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2061 goto out; 2062 } 2063 2064 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2065 * which requires us to use the prepended Broadcom tag type 2066 */ 2067 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2068 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2069 goto out; 2070 } 2071 2072 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2073 out: 2074 return dev->tag_protocol; 2075 } 2076 EXPORT_SYMBOL(b53_get_tag_protocol); 2077 2078 int b53_mirror_add(struct dsa_switch *ds, int port, 2079 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 2080 { 2081 struct b53_device *dev = ds->priv; 2082 u16 reg, loc; 2083 2084 if (ingress) 2085 loc = B53_IG_MIR_CTL; 2086 else 2087 loc = B53_EG_MIR_CTL; 2088 2089 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2090 reg |= BIT(port); 2091 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2092 2093 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2094 reg &= ~CAP_PORT_MASK; 2095 reg |= mirror->to_local_port; 2096 reg |= MIRROR_EN; 2097 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2098 2099 return 0; 2100 } 2101 EXPORT_SYMBOL(b53_mirror_add); 2102 2103 void b53_mirror_del(struct dsa_switch *ds, int port, 2104 struct dsa_mall_mirror_tc_entry *mirror) 2105 { 2106 struct b53_device *dev = ds->priv; 2107 bool loc_disable = false, other_loc_disable = false; 2108 u16 reg, loc; 2109 2110 if (mirror->ingress) 2111 loc = B53_IG_MIR_CTL; 2112 else 2113 loc = B53_EG_MIR_CTL; 2114 2115 /* Update the desired ingress/egress register */ 2116 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2117 reg &= ~BIT(port); 2118 if (!(reg & MIRROR_MASK)) 2119 loc_disable = true; 2120 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2121 2122 /* Now look at the other one to know if we can disable mirroring 2123 * entirely 2124 */ 2125 if (mirror->ingress) 2126 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2127 else 2128 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2129 if (!(reg & MIRROR_MASK)) 2130 other_loc_disable = true; 2131 2132 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2133 /* Both no longer have ports, let's disable mirroring */ 2134 if (loc_disable && other_loc_disable) { 2135 reg &= ~MIRROR_EN; 2136 reg &= ~mirror->to_local_port; 2137 } 2138 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2139 } 2140 EXPORT_SYMBOL(b53_mirror_del); 2141 2142 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 2143 { 2144 struct b53_device *dev = ds->priv; 2145 u16 reg; 2146 2147 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 2148 if (enable) 2149 reg |= BIT(port); 2150 else 2151 reg &= ~BIT(port); 2152 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 2153 } 2154 EXPORT_SYMBOL(b53_eee_enable_set); 2155 2156 2157 /* Returns 0 if EEE was not enabled, or 1 otherwise 2158 */ 2159 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2160 { 2161 int ret; 2162 2163 ret = phy_init_eee(phy, 0); 2164 if (ret) 2165 return 0; 2166 2167 b53_eee_enable_set(ds, port, true); 2168 2169 return 1; 2170 } 2171 EXPORT_SYMBOL(b53_eee_init); 2172 2173 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2174 { 2175 struct b53_device *dev = ds->priv; 2176 struct ethtool_eee *p = &dev->ports[port].eee; 2177 u16 reg; 2178 2179 if (is5325(dev) || is5365(dev)) 2180 return -EOPNOTSUPP; 2181 2182 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 2183 e->eee_enabled = p->eee_enabled; 2184 e->eee_active = !!(reg & BIT(port)); 2185 2186 return 0; 2187 } 2188 EXPORT_SYMBOL(b53_get_mac_eee); 2189 2190 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2191 { 2192 struct b53_device *dev = ds->priv; 2193 struct ethtool_eee *p = &dev->ports[port].eee; 2194 2195 if (is5325(dev) || is5365(dev)) 2196 return -EOPNOTSUPP; 2197 2198 p->eee_enabled = e->eee_enabled; 2199 b53_eee_enable_set(ds, port, e->eee_enabled); 2200 2201 return 0; 2202 } 2203 EXPORT_SYMBOL(b53_set_mac_eee); 2204 2205 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2206 { 2207 struct b53_device *dev = ds->priv; 2208 bool enable_jumbo; 2209 bool allow_10_100; 2210 2211 if (is5325(dev) || is5365(dev)) 2212 return -EOPNOTSUPP; 2213 2214 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2215 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2216 2217 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2218 } 2219 2220 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2221 { 2222 return JMS_MAX_SIZE; 2223 } 2224 2225 static const struct dsa_switch_ops b53_switch_ops = { 2226 .get_tag_protocol = b53_get_tag_protocol, 2227 .setup = b53_setup, 2228 .teardown = b53_teardown, 2229 .get_strings = b53_get_strings, 2230 .get_ethtool_stats = b53_get_ethtool_stats, 2231 .get_sset_count = b53_get_sset_count, 2232 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2233 .phy_read = b53_phy_read16, 2234 .phy_write = b53_phy_write16, 2235 .adjust_link = b53_adjust_link, 2236 .phylink_validate = b53_phylink_validate, 2237 .phylink_mac_link_state = b53_phylink_mac_link_state, 2238 .phylink_mac_config = b53_phylink_mac_config, 2239 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 2240 .phylink_mac_link_down = b53_phylink_mac_link_down, 2241 .phylink_mac_link_up = b53_phylink_mac_link_up, 2242 .port_enable = b53_enable_port, 2243 .port_disable = b53_disable_port, 2244 .get_mac_eee = b53_get_mac_eee, 2245 .set_mac_eee = b53_set_mac_eee, 2246 .port_bridge_join = b53_br_join, 2247 .port_bridge_leave = b53_br_leave, 2248 .port_pre_bridge_flags = b53_br_flags_pre, 2249 .port_bridge_flags = b53_br_flags, 2250 .port_set_mrouter = b53_set_mrouter, 2251 .port_stp_state_set = b53_br_set_stp_state, 2252 .port_fast_age = b53_br_fast_age, 2253 .port_vlan_filtering = b53_vlan_filtering, 2254 .port_vlan_add = b53_vlan_add, 2255 .port_vlan_del = b53_vlan_del, 2256 .port_fdb_dump = b53_fdb_dump, 2257 .port_fdb_add = b53_fdb_add, 2258 .port_fdb_del = b53_fdb_del, 2259 .port_mirror_add = b53_mirror_add, 2260 .port_mirror_del = b53_mirror_del, 2261 .port_mdb_add = b53_mdb_add, 2262 .port_mdb_del = b53_mdb_del, 2263 .port_max_mtu = b53_get_max_mtu, 2264 .port_change_mtu = b53_change_mtu, 2265 }; 2266 2267 struct b53_chip_data { 2268 u32 chip_id; 2269 const char *dev_name; 2270 u16 vlans; 2271 u16 enabled_ports; 2272 u8 cpu_port; 2273 u8 vta_regs[3]; 2274 u8 arl_bins; 2275 u16 arl_buckets; 2276 u8 duplex_reg; 2277 u8 jumbo_pm_reg; 2278 u8 jumbo_size_reg; 2279 }; 2280 2281 #define B53_VTA_REGS \ 2282 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2283 #define B53_VTA_REGS_9798 \ 2284 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2285 #define B53_VTA_REGS_63XX \ 2286 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2287 2288 static const struct b53_chip_data b53_switch_chips[] = { 2289 { 2290 .chip_id = BCM5325_DEVICE_ID, 2291 .dev_name = "BCM5325", 2292 .vlans = 16, 2293 .enabled_ports = 0x1f, 2294 .arl_bins = 2, 2295 .arl_buckets = 1024, 2296 .cpu_port = B53_CPU_PORT_25, 2297 .duplex_reg = B53_DUPLEX_STAT_FE, 2298 }, 2299 { 2300 .chip_id = BCM5365_DEVICE_ID, 2301 .dev_name = "BCM5365", 2302 .vlans = 256, 2303 .enabled_ports = 0x1f, 2304 .arl_bins = 2, 2305 .arl_buckets = 1024, 2306 .cpu_port = B53_CPU_PORT_25, 2307 .duplex_reg = B53_DUPLEX_STAT_FE, 2308 }, 2309 { 2310 .chip_id = BCM5389_DEVICE_ID, 2311 .dev_name = "BCM5389", 2312 .vlans = 4096, 2313 .enabled_ports = 0x1f, 2314 .arl_bins = 4, 2315 .arl_buckets = 1024, 2316 .cpu_port = B53_CPU_PORT, 2317 .vta_regs = B53_VTA_REGS, 2318 .duplex_reg = B53_DUPLEX_STAT_GE, 2319 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2320 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2321 }, 2322 { 2323 .chip_id = BCM5395_DEVICE_ID, 2324 .dev_name = "BCM5395", 2325 .vlans = 4096, 2326 .enabled_ports = 0x1f, 2327 .arl_bins = 4, 2328 .arl_buckets = 1024, 2329 .cpu_port = B53_CPU_PORT, 2330 .vta_regs = B53_VTA_REGS, 2331 .duplex_reg = B53_DUPLEX_STAT_GE, 2332 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2333 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2334 }, 2335 { 2336 .chip_id = BCM5397_DEVICE_ID, 2337 .dev_name = "BCM5397", 2338 .vlans = 4096, 2339 .enabled_ports = 0x1f, 2340 .arl_bins = 4, 2341 .arl_buckets = 1024, 2342 .cpu_port = B53_CPU_PORT, 2343 .vta_regs = B53_VTA_REGS_9798, 2344 .duplex_reg = B53_DUPLEX_STAT_GE, 2345 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2346 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2347 }, 2348 { 2349 .chip_id = BCM5398_DEVICE_ID, 2350 .dev_name = "BCM5398", 2351 .vlans = 4096, 2352 .enabled_ports = 0x7f, 2353 .arl_bins = 4, 2354 .arl_buckets = 1024, 2355 .cpu_port = B53_CPU_PORT, 2356 .vta_regs = B53_VTA_REGS_9798, 2357 .duplex_reg = B53_DUPLEX_STAT_GE, 2358 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2359 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2360 }, 2361 { 2362 .chip_id = BCM53115_DEVICE_ID, 2363 .dev_name = "BCM53115", 2364 .vlans = 4096, 2365 .enabled_ports = 0x1f, 2366 .arl_bins = 4, 2367 .arl_buckets = 1024, 2368 .vta_regs = B53_VTA_REGS, 2369 .cpu_port = B53_CPU_PORT, 2370 .duplex_reg = B53_DUPLEX_STAT_GE, 2371 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2372 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2373 }, 2374 { 2375 .chip_id = BCM53125_DEVICE_ID, 2376 .dev_name = "BCM53125", 2377 .vlans = 4096, 2378 .enabled_ports = 0xff, 2379 .arl_bins = 4, 2380 .arl_buckets = 1024, 2381 .cpu_port = B53_CPU_PORT, 2382 .vta_regs = B53_VTA_REGS, 2383 .duplex_reg = B53_DUPLEX_STAT_GE, 2384 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2385 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2386 }, 2387 { 2388 .chip_id = BCM53128_DEVICE_ID, 2389 .dev_name = "BCM53128", 2390 .vlans = 4096, 2391 .enabled_ports = 0x1ff, 2392 .arl_bins = 4, 2393 .arl_buckets = 1024, 2394 .cpu_port = B53_CPU_PORT, 2395 .vta_regs = B53_VTA_REGS, 2396 .duplex_reg = B53_DUPLEX_STAT_GE, 2397 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2398 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2399 }, 2400 { 2401 .chip_id = BCM63XX_DEVICE_ID, 2402 .dev_name = "BCM63xx", 2403 .vlans = 4096, 2404 .enabled_ports = 0, /* pdata must provide them */ 2405 .arl_bins = 4, 2406 .arl_buckets = 1024, 2407 .cpu_port = B53_CPU_PORT, 2408 .vta_regs = B53_VTA_REGS_63XX, 2409 .duplex_reg = B53_DUPLEX_STAT_63XX, 2410 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2411 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2412 }, 2413 { 2414 .chip_id = BCM53010_DEVICE_ID, 2415 .dev_name = "BCM53010", 2416 .vlans = 4096, 2417 .enabled_ports = 0x1f, 2418 .arl_bins = 4, 2419 .arl_buckets = 1024, 2420 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2421 .vta_regs = B53_VTA_REGS, 2422 .duplex_reg = B53_DUPLEX_STAT_GE, 2423 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2424 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2425 }, 2426 { 2427 .chip_id = BCM53011_DEVICE_ID, 2428 .dev_name = "BCM53011", 2429 .vlans = 4096, 2430 .enabled_ports = 0x1bf, 2431 .arl_bins = 4, 2432 .arl_buckets = 1024, 2433 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2434 .vta_regs = B53_VTA_REGS, 2435 .duplex_reg = B53_DUPLEX_STAT_GE, 2436 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2437 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2438 }, 2439 { 2440 .chip_id = BCM53012_DEVICE_ID, 2441 .dev_name = "BCM53012", 2442 .vlans = 4096, 2443 .enabled_ports = 0x1bf, 2444 .arl_bins = 4, 2445 .arl_buckets = 1024, 2446 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2447 .vta_regs = B53_VTA_REGS, 2448 .duplex_reg = B53_DUPLEX_STAT_GE, 2449 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2450 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2451 }, 2452 { 2453 .chip_id = BCM53018_DEVICE_ID, 2454 .dev_name = "BCM53018", 2455 .vlans = 4096, 2456 .enabled_ports = 0x1f, 2457 .arl_bins = 4, 2458 .arl_buckets = 1024, 2459 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2460 .vta_regs = B53_VTA_REGS, 2461 .duplex_reg = B53_DUPLEX_STAT_GE, 2462 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2463 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2464 }, 2465 { 2466 .chip_id = BCM53019_DEVICE_ID, 2467 .dev_name = "BCM53019", 2468 .vlans = 4096, 2469 .enabled_ports = 0x1f, 2470 .arl_bins = 4, 2471 .arl_buckets = 1024, 2472 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2473 .vta_regs = B53_VTA_REGS, 2474 .duplex_reg = B53_DUPLEX_STAT_GE, 2475 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2476 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2477 }, 2478 { 2479 .chip_id = BCM58XX_DEVICE_ID, 2480 .dev_name = "BCM585xx/586xx/88312", 2481 .vlans = 4096, 2482 .enabled_ports = 0x1ff, 2483 .arl_bins = 4, 2484 .arl_buckets = 1024, 2485 .cpu_port = B53_CPU_PORT, 2486 .vta_regs = B53_VTA_REGS, 2487 .duplex_reg = B53_DUPLEX_STAT_GE, 2488 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2489 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2490 }, 2491 { 2492 .chip_id = BCM583XX_DEVICE_ID, 2493 .dev_name = "BCM583xx/11360", 2494 .vlans = 4096, 2495 .enabled_ports = 0x103, 2496 .arl_bins = 4, 2497 .arl_buckets = 1024, 2498 .cpu_port = B53_CPU_PORT, 2499 .vta_regs = B53_VTA_REGS, 2500 .duplex_reg = B53_DUPLEX_STAT_GE, 2501 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2502 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2503 }, 2504 /* Starfighter 2 */ 2505 { 2506 .chip_id = BCM4908_DEVICE_ID, 2507 .dev_name = "BCM4908", 2508 .vlans = 4096, 2509 .enabled_ports = 0x1bf, 2510 .arl_bins = 4, 2511 .arl_buckets = 256, 2512 .cpu_port = 8, /* TODO: ports 4, 5, 8 */ 2513 .vta_regs = B53_VTA_REGS, 2514 .duplex_reg = B53_DUPLEX_STAT_GE, 2515 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2516 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2517 }, 2518 { 2519 .chip_id = BCM7445_DEVICE_ID, 2520 .dev_name = "BCM7445", 2521 .vlans = 4096, 2522 .enabled_ports = 0x1ff, 2523 .arl_bins = 4, 2524 .arl_buckets = 1024, 2525 .cpu_port = B53_CPU_PORT, 2526 .vta_regs = B53_VTA_REGS, 2527 .duplex_reg = B53_DUPLEX_STAT_GE, 2528 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2529 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2530 }, 2531 { 2532 .chip_id = BCM7278_DEVICE_ID, 2533 .dev_name = "BCM7278", 2534 .vlans = 4096, 2535 .enabled_ports = 0x1ff, 2536 .arl_bins = 4, 2537 .arl_buckets = 256, 2538 .cpu_port = B53_CPU_PORT, 2539 .vta_regs = B53_VTA_REGS, 2540 .duplex_reg = B53_DUPLEX_STAT_GE, 2541 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2542 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2543 }, 2544 }; 2545 2546 static int b53_switch_init(struct b53_device *dev) 2547 { 2548 unsigned int i; 2549 int ret; 2550 2551 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2552 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2553 2554 if (chip->chip_id == dev->chip_id) { 2555 if (!dev->enabled_ports) 2556 dev->enabled_ports = chip->enabled_ports; 2557 dev->name = chip->dev_name; 2558 dev->duplex_reg = chip->duplex_reg; 2559 dev->vta_regs[0] = chip->vta_regs[0]; 2560 dev->vta_regs[1] = chip->vta_regs[1]; 2561 dev->vta_regs[2] = chip->vta_regs[2]; 2562 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2563 dev->cpu_port = chip->cpu_port; 2564 dev->num_vlans = chip->vlans; 2565 dev->num_arl_bins = chip->arl_bins; 2566 dev->num_arl_buckets = chip->arl_buckets; 2567 break; 2568 } 2569 } 2570 2571 /* check which BCM5325x version we have */ 2572 if (is5325(dev)) { 2573 u8 vc4; 2574 2575 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2576 2577 /* check reserved bits */ 2578 switch (vc4 & 3) { 2579 case 1: 2580 /* BCM5325E */ 2581 break; 2582 case 3: 2583 /* BCM5325F - do not use port 4 */ 2584 dev->enabled_ports &= ~BIT(4); 2585 break; 2586 default: 2587 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2588 #ifndef CONFIG_BCM47XX 2589 /* BCM5325M */ 2590 return -EINVAL; 2591 #else 2592 break; 2593 #endif 2594 } 2595 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2596 u64 strap_value; 2597 2598 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2599 /* use second IMP port if GMII is enabled */ 2600 if (strap_value & SV_GMII_CTRL_115) 2601 dev->cpu_port = 5; 2602 } 2603 2604 /* cpu port is always last */ 2605 dev->num_ports = dev->cpu_port + 1; 2606 dev->enabled_ports |= BIT(dev->cpu_port); 2607 2608 /* Include non standard CPU port built-in PHYs to be probed */ 2609 if (is539x(dev) || is531x5(dev)) { 2610 for (i = 0; i < dev->num_ports; i++) { 2611 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2612 !b53_possible_cpu_port(dev->ds, i)) 2613 dev->ds->phys_mii_mask |= BIT(i); 2614 } 2615 } 2616 2617 dev->ports = devm_kcalloc(dev->dev, 2618 dev->num_ports, sizeof(struct b53_port), 2619 GFP_KERNEL); 2620 if (!dev->ports) 2621 return -ENOMEM; 2622 2623 dev->vlans = devm_kcalloc(dev->dev, 2624 dev->num_vlans, sizeof(struct b53_vlan), 2625 GFP_KERNEL); 2626 if (!dev->vlans) 2627 return -ENOMEM; 2628 2629 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2630 if (dev->reset_gpio >= 0) { 2631 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2632 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2633 if (ret) 2634 return ret; 2635 } 2636 2637 return 0; 2638 } 2639 2640 struct b53_device *b53_switch_alloc(struct device *base, 2641 const struct b53_io_ops *ops, 2642 void *priv) 2643 { 2644 struct dsa_switch *ds; 2645 struct b53_device *dev; 2646 2647 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2648 if (!ds) 2649 return NULL; 2650 2651 ds->dev = base; 2652 ds->num_ports = DSA_MAX_PORTS; 2653 2654 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2655 if (!dev) 2656 return NULL; 2657 2658 ds->priv = dev; 2659 dev->dev = base; 2660 2661 dev->ds = ds; 2662 dev->priv = priv; 2663 dev->ops = ops; 2664 ds->ops = &b53_switch_ops; 2665 ds->untag_bridge_pvid = true; 2666 dev->vlan_enabled = true; 2667 mutex_init(&dev->reg_mutex); 2668 mutex_init(&dev->stats_mutex); 2669 2670 return dev; 2671 } 2672 EXPORT_SYMBOL(b53_switch_alloc); 2673 2674 int b53_switch_detect(struct b53_device *dev) 2675 { 2676 u32 id32; 2677 u16 tmp; 2678 u8 id8; 2679 int ret; 2680 2681 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2682 if (ret) 2683 return ret; 2684 2685 switch (id8) { 2686 case 0: 2687 /* BCM5325 and BCM5365 do not have this register so reads 2688 * return 0. But the read operation did succeed, so assume this 2689 * is one of them. 2690 * 2691 * Next check if we can write to the 5325's VTA register; for 2692 * 5365 it is read only. 2693 */ 2694 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2695 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2696 2697 if (tmp == 0xf) 2698 dev->chip_id = BCM5325_DEVICE_ID; 2699 else 2700 dev->chip_id = BCM5365_DEVICE_ID; 2701 break; 2702 case BCM5389_DEVICE_ID: 2703 case BCM5395_DEVICE_ID: 2704 case BCM5397_DEVICE_ID: 2705 case BCM5398_DEVICE_ID: 2706 dev->chip_id = id8; 2707 break; 2708 default: 2709 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2710 if (ret) 2711 return ret; 2712 2713 switch (id32) { 2714 case BCM53115_DEVICE_ID: 2715 case BCM53125_DEVICE_ID: 2716 case BCM53128_DEVICE_ID: 2717 case BCM53010_DEVICE_ID: 2718 case BCM53011_DEVICE_ID: 2719 case BCM53012_DEVICE_ID: 2720 case BCM53018_DEVICE_ID: 2721 case BCM53019_DEVICE_ID: 2722 dev->chip_id = id32; 2723 break; 2724 default: 2725 dev_err(dev->dev, 2726 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2727 id8, id32); 2728 return -ENODEV; 2729 } 2730 } 2731 2732 if (dev->chip_id == BCM5325_DEVICE_ID) 2733 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2734 &dev->core_rev); 2735 else 2736 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2737 &dev->core_rev); 2738 } 2739 EXPORT_SYMBOL(b53_switch_detect); 2740 2741 int b53_switch_register(struct b53_device *dev) 2742 { 2743 int ret; 2744 2745 if (dev->pdata) { 2746 dev->chip_id = dev->pdata->chip_id; 2747 dev->enabled_ports = dev->pdata->enabled_ports; 2748 } 2749 2750 if (!dev->chip_id && b53_switch_detect(dev)) 2751 return -EINVAL; 2752 2753 ret = b53_switch_init(dev); 2754 if (ret) 2755 return ret; 2756 2757 dev_info(dev->dev, "found switch: %s, rev %i\n", 2758 dev->name, dev->core_rev); 2759 2760 return dsa_register_switch(dev->ds); 2761 } 2762 EXPORT_SYMBOL(b53_switch_register); 2763 2764 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2765 MODULE_DESCRIPTION("B53 switch library"); 2766 MODULE_LICENSE("Dual BSD/GPL"); 2767