1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if_bridge.h> 32 #include <net/dsa.h> 33 34 #include "b53_regs.h" 35 #include "b53_priv.h" 36 37 struct b53_mib_desc { 38 u8 size; 39 u8 offset; 40 const char *name; 41 }; 42 43 /* BCM5365 MIB counters */ 44 static const struct b53_mib_desc b53_mibs_65[] = { 45 { 8, 0x00, "TxOctets" }, 46 { 4, 0x08, "TxDropPkts" }, 47 { 4, 0x10, "TxBroadcastPkts" }, 48 { 4, 0x14, "TxMulticastPkts" }, 49 { 4, 0x18, "TxUnicastPkts" }, 50 { 4, 0x1c, "TxCollisions" }, 51 { 4, 0x20, "TxSingleCollision" }, 52 { 4, 0x24, "TxMultipleCollision" }, 53 { 4, 0x28, "TxDeferredTransmit" }, 54 { 4, 0x2c, "TxLateCollision" }, 55 { 4, 0x30, "TxExcessiveCollision" }, 56 { 4, 0x38, "TxPausePkts" }, 57 { 8, 0x44, "RxOctets" }, 58 { 4, 0x4c, "RxUndersizePkts" }, 59 { 4, 0x50, "RxPausePkts" }, 60 { 4, 0x54, "Pkts64Octets" }, 61 { 4, 0x58, "Pkts65to127Octets" }, 62 { 4, 0x5c, "Pkts128to255Octets" }, 63 { 4, 0x60, "Pkts256to511Octets" }, 64 { 4, 0x64, "Pkts512to1023Octets" }, 65 { 4, 0x68, "Pkts1024to1522Octets" }, 66 { 4, 0x6c, "RxOversizePkts" }, 67 { 4, 0x70, "RxJabbers" }, 68 { 4, 0x74, "RxAlignmentErrors" }, 69 { 4, 0x78, "RxFCSErrors" }, 70 { 8, 0x7c, "RxGoodOctets" }, 71 { 4, 0x84, "RxDropPkts" }, 72 { 4, 0x88, "RxUnicastPkts" }, 73 { 4, 0x8c, "RxMulticastPkts" }, 74 { 4, 0x90, "RxBroadcastPkts" }, 75 { 4, 0x94, "RxSAChanges" }, 76 { 4, 0x98, "RxFragments" }, 77 }; 78 79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 80 81 /* BCM63xx MIB counters */ 82 static const struct b53_mib_desc b53_mibs_63xx[] = { 83 { 8, 0x00, "TxOctets" }, 84 { 4, 0x08, "TxDropPkts" }, 85 { 4, 0x0c, "TxQoSPkts" }, 86 { 4, 0x10, "TxBroadcastPkts" }, 87 { 4, 0x14, "TxMulticastPkts" }, 88 { 4, 0x18, "TxUnicastPkts" }, 89 { 4, 0x1c, "TxCollisions" }, 90 { 4, 0x20, "TxSingleCollision" }, 91 { 4, 0x24, "TxMultipleCollision" }, 92 { 4, 0x28, "TxDeferredTransmit" }, 93 { 4, 0x2c, "TxLateCollision" }, 94 { 4, 0x30, "TxExcessiveCollision" }, 95 { 4, 0x38, "TxPausePkts" }, 96 { 8, 0x3c, "TxQoSOctets" }, 97 { 8, 0x44, "RxOctets" }, 98 { 4, 0x4c, "RxUndersizePkts" }, 99 { 4, 0x50, "RxPausePkts" }, 100 { 4, 0x54, "Pkts64Octets" }, 101 { 4, 0x58, "Pkts65to127Octets" }, 102 { 4, 0x5c, "Pkts128to255Octets" }, 103 { 4, 0x60, "Pkts256to511Octets" }, 104 { 4, 0x64, "Pkts512to1023Octets" }, 105 { 4, 0x68, "Pkts1024to1522Octets" }, 106 { 4, 0x6c, "RxOversizePkts" }, 107 { 4, 0x70, "RxJabbers" }, 108 { 4, 0x74, "RxAlignmentErrors" }, 109 { 4, 0x78, "RxFCSErrors" }, 110 { 8, 0x7c, "RxGoodOctets" }, 111 { 4, 0x84, "RxDropPkts" }, 112 { 4, 0x88, "RxUnicastPkts" }, 113 { 4, 0x8c, "RxMulticastPkts" }, 114 { 4, 0x90, "RxBroadcastPkts" }, 115 { 4, 0x94, "RxSAChanges" }, 116 { 4, 0x98, "RxFragments" }, 117 { 4, 0xa0, "RxSymbolErrors" }, 118 { 4, 0xa4, "RxQoSPkts" }, 119 { 8, 0xa8, "RxQoSOctets" }, 120 { 4, 0xb0, "Pkts1523to2047Octets" }, 121 { 4, 0xb4, "Pkts2048to4095Octets" }, 122 { 4, 0xb8, "Pkts4096to8191Octets" }, 123 { 4, 0xbc, "Pkts8192to9728Octets" }, 124 { 4, 0xc0, "RxDiscarded" }, 125 }; 126 127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 128 129 /* MIB counters */ 130 static const struct b53_mib_desc b53_mibs[] = { 131 { 8, 0x00, "TxOctets" }, 132 { 4, 0x08, "TxDropPkts" }, 133 { 4, 0x10, "TxBroadcastPkts" }, 134 { 4, 0x14, "TxMulticastPkts" }, 135 { 4, 0x18, "TxUnicastPkts" }, 136 { 4, 0x1c, "TxCollisions" }, 137 { 4, 0x20, "TxSingleCollision" }, 138 { 4, 0x24, "TxMultipleCollision" }, 139 { 4, 0x28, "TxDeferredTransmit" }, 140 { 4, 0x2c, "TxLateCollision" }, 141 { 4, 0x30, "TxExcessiveCollision" }, 142 { 4, 0x38, "TxPausePkts" }, 143 { 8, 0x50, "RxOctets" }, 144 { 4, 0x58, "RxUndersizePkts" }, 145 { 4, 0x5c, "RxPausePkts" }, 146 { 4, 0x60, "Pkts64Octets" }, 147 { 4, 0x64, "Pkts65to127Octets" }, 148 { 4, 0x68, "Pkts128to255Octets" }, 149 { 4, 0x6c, "Pkts256to511Octets" }, 150 { 4, 0x70, "Pkts512to1023Octets" }, 151 { 4, 0x74, "Pkts1024to1522Octets" }, 152 { 4, 0x78, "RxOversizePkts" }, 153 { 4, 0x7c, "RxJabbers" }, 154 { 4, 0x80, "RxAlignmentErrors" }, 155 { 4, 0x84, "RxFCSErrors" }, 156 { 8, 0x88, "RxGoodOctets" }, 157 { 4, 0x90, "RxDropPkts" }, 158 { 4, 0x94, "RxUnicastPkts" }, 159 { 4, 0x98, "RxMulticastPkts" }, 160 { 4, 0x9c, "RxBroadcastPkts" }, 161 { 4, 0xa0, "RxSAChanges" }, 162 { 4, 0xa4, "RxFragments" }, 163 { 4, 0xa8, "RxJumboPkts" }, 164 { 4, 0xac, "RxSymbolErrors" }, 165 { 4, 0xc0, "RxDiscarded" }, 166 }; 167 168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 169 170 static const struct b53_mib_desc b53_mibs_58xx[] = { 171 { 8, 0x00, "TxOctets" }, 172 { 4, 0x08, "TxDropPkts" }, 173 { 4, 0x0c, "TxQPKTQ0" }, 174 { 4, 0x10, "TxBroadcastPkts" }, 175 { 4, 0x14, "TxMulticastPkts" }, 176 { 4, 0x18, "TxUnicastPKts" }, 177 { 4, 0x1c, "TxCollisions" }, 178 { 4, 0x20, "TxSingleCollision" }, 179 { 4, 0x24, "TxMultipleCollision" }, 180 { 4, 0x28, "TxDeferredCollision" }, 181 { 4, 0x2c, "TxLateCollision" }, 182 { 4, 0x30, "TxExcessiveCollision" }, 183 { 4, 0x34, "TxFrameInDisc" }, 184 { 4, 0x38, "TxPausePkts" }, 185 { 4, 0x3c, "TxQPKTQ1" }, 186 { 4, 0x40, "TxQPKTQ2" }, 187 { 4, 0x44, "TxQPKTQ3" }, 188 { 4, 0x48, "TxQPKTQ4" }, 189 { 4, 0x4c, "TxQPKTQ5" }, 190 { 8, 0x50, "RxOctets" }, 191 { 4, 0x58, "RxUndersizePkts" }, 192 { 4, 0x5c, "RxPausePkts" }, 193 { 4, 0x60, "RxPkts64Octets" }, 194 { 4, 0x64, "RxPkts65to127Octets" }, 195 { 4, 0x68, "RxPkts128to255Octets" }, 196 { 4, 0x6c, "RxPkts256to511Octets" }, 197 { 4, 0x70, "RxPkts512to1023Octets" }, 198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 199 { 4, 0x78, "RxOversizePkts" }, 200 { 4, 0x7c, "RxJabbers" }, 201 { 4, 0x80, "RxAlignmentErrors" }, 202 { 4, 0x84, "RxFCSErrors" }, 203 { 8, 0x88, "RxGoodOctets" }, 204 { 4, 0x90, "RxDropPkts" }, 205 { 4, 0x94, "RxUnicastPkts" }, 206 { 4, 0x98, "RxMulticastPkts" }, 207 { 4, 0x9c, "RxBroadcastPkts" }, 208 { 4, 0xa0, "RxSAChanges" }, 209 { 4, 0xa4, "RxFragments" }, 210 { 4, 0xa8, "RxJumboPkt" }, 211 { 4, 0xac, "RxSymblErr" }, 212 { 4, 0xb0, "InRangeErrCount" }, 213 { 4, 0xb4, "OutRangeErrCount" }, 214 { 4, 0xb8, "EEELpiEvent" }, 215 { 4, 0xbc, "EEELpiDuration" }, 216 { 4, 0xc0, "RxDiscard" }, 217 { 4, 0xc8, "TxQPKTQ6" }, 218 { 4, 0xcc, "TxQPKTQ7" }, 219 { 4, 0xd0, "TxPkts64Octets" }, 220 { 4, 0xd4, "TxPkts65to127Octets" }, 221 { 4, 0xd8, "TxPkts128to255Octets" }, 222 { 4, 0xdc, "TxPkts256to511Ocets" }, 223 { 4, 0xe0, "TxPkts512to1023Ocets" }, 224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 225 }; 226 227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 228 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 230 { 231 unsigned int i; 232 233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 234 235 for (i = 0; i < 10; i++) { 236 u8 vta; 237 238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 239 if (!(vta & VTA_START_CMD)) 240 return 0; 241 242 usleep_range(100, 200); 243 } 244 245 return -EIO; 246 } 247 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 249 struct b53_vlan *vlan) 250 { 251 if (is5325(dev)) { 252 u32 entry = 0; 253 254 if (vlan->members) { 255 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 256 VA_UNTAG_S_25) | vlan->members; 257 if (dev->core_rev >= 3) 258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 259 else 260 entry |= VA_VALID_25; 261 } 262 263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 265 VTA_RW_STATE_WR | VTA_RW_OP_EN); 266 } else if (is5365(dev)) { 267 u16 entry = 0; 268 269 if (vlan->members) 270 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 272 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 275 VTA_RW_STATE_WR | VTA_RW_OP_EN); 276 } else { 277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 279 (vlan->untag << VTE_UNTAG_S) | vlan->members); 280 281 b53_do_vlan_op(dev, VTA_CMD_WRITE); 282 } 283 284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 285 vid, vlan->members, vlan->untag); 286 } 287 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 289 struct b53_vlan *vlan) 290 { 291 if (is5325(dev)) { 292 u32 entry = 0; 293 294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 295 VTA_RW_STATE_RD | VTA_RW_OP_EN); 296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 297 298 if (dev->core_rev >= 3) 299 vlan->valid = !!(entry & VA_VALID_25_R4); 300 else 301 vlan->valid = !!(entry & VA_VALID_25); 302 vlan->members = entry & VA_MEMBER_MASK; 303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 304 305 } else if (is5365(dev)) { 306 u16 entry = 0; 307 308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 309 VTA_RW_STATE_WR | VTA_RW_OP_EN); 310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 311 312 vlan->valid = !!(entry & VA_VALID_65); 313 vlan->members = entry & VA_MEMBER_MASK; 314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 315 } else { 316 u32 entry = 0; 317 318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 319 b53_do_vlan_op(dev, VTA_CMD_READ); 320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 321 vlan->members = entry & VTE_MEMBERS; 322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 323 vlan->valid = true; 324 } 325 } 326 327 static void b53_set_forwarding(struct b53_device *dev, int enable) 328 { 329 u8 mgmt; 330 331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 332 333 if (enable) 334 mgmt |= SM_SW_FWD_EN; 335 else 336 mgmt &= ~SM_SW_FWD_EN; 337 338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 339 340 /* Include IMP port in dumb forwarding mode 341 */ 342 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 343 mgmt |= B53_MII_DUMB_FWDG_EN; 344 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 345 346 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 347 * frames should be flooded or not. 348 */ 349 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 350 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 351 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 352 } 353 354 static void b53_enable_vlan(struct b53_device *dev, bool enable, 355 bool enable_filtering) 356 { 357 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 358 359 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 362 363 if (is5325(dev) || is5365(dev)) { 364 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 366 } else if (is63xx(dev)) { 367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 369 } else { 370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 371 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 372 } 373 374 if (enable) { 375 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 376 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 377 vc4 &= ~VC4_ING_VID_CHECK_MASK; 378 if (enable_filtering) { 379 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 380 vc5 |= VC5_DROP_VTABLE_MISS; 381 } else { 382 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 383 vc5 &= ~VC5_DROP_VTABLE_MISS; 384 } 385 386 if (is5325(dev)) 387 vc0 &= ~VC0_RESERVED_1; 388 389 if (is5325(dev) || is5365(dev)) 390 vc1 |= VC1_RX_MCST_TAG_EN; 391 392 } else { 393 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 394 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 395 vc4 &= ~VC4_ING_VID_CHECK_MASK; 396 vc5 &= ~VC5_DROP_VTABLE_MISS; 397 398 if (is5325(dev) || is5365(dev)) 399 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 400 else 401 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 402 403 if (is5325(dev) || is5365(dev)) 404 vc1 &= ~VC1_RX_MCST_TAG_EN; 405 } 406 407 if (!is5325(dev) && !is5365(dev)) 408 vc5 &= ~VC5_VID_FFF_EN; 409 410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 412 413 if (is5325(dev) || is5365(dev)) { 414 /* enable the high 8 bit vid check on 5325 */ 415 if (is5325(dev) && enable) 416 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 417 VC3_HIGH_8BIT_EN); 418 else 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 420 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 423 } else if (is63xx(dev)) { 424 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 425 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 426 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 427 } else { 428 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 429 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 430 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 431 } 432 433 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 434 435 dev->vlan_enabled = enable; 436 } 437 438 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 439 { 440 u32 port_mask = 0; 441 u16 max_size = JMS_MIN_SIZE; 442 443 if (is5325(dev) || is5365(dev)) 444 return -EINVAL; 445 446 if (enable) { 447 port_mask = dev->enabled_ports; 448 max_size = JMS_MAX_SIZE; 449 if (allow_10_100) 450 port_mask |= JPM_10_100_JUMBO_EN; 451 } 452 453 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 454 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 455 } 456 457 static int b53_flush_arl(struct b53_device *dev, u8 mask) 458 { 459 unsigned int i; 460 461 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 462 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 463 464 for (i = 0; i < 10; i++) { 465 u8 fast_age_ctrl; 466 467 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 468 &fast_age_ctrl); 469 470 if (!(fast_age_ctrl & FAST_AGE_DONE)) 471 goto out; 472 473 msleep(1); 474 } 475 476 return -ETIMEDOUT; 477 out: 478 /* Only age dynamic entries (default behavior) */ 479 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 480 return 0; 481 } 482 483 static int b53_fast_age_port(struct b53_device *dev, int port) 484 { 485 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 486 487 return b53_flush_arl(dev, FAST_AGE_PORT); 488 } 489 490 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 491 { 492 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 493 494 return b53_flush_arl(dev, FAST_AGE_VLAN); 495 } 496 497 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 498 { 499 struct b53_device *dev = ds->priv; 500 unsigned int i; 501 u16 pvlan; 502 503 /* Enable the IMP port to be in the same VLAN as the other ports 504 * on a per-port basis such that we only have Port i and IMP in 505 * the same VLAN. 506 */ 507 b53_for_each_port(dev, i) { 508 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 509 pvlan |= BIT(cpu_port); 510 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 511 } 512 } 513 EXPORT_SYMBOL(b53_imp_vlan_setup); 514 515 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 516 { 517 struct b53_device *dev = ds->priv; 518 unsigned int cpu_port; 519 int ret = 0; 520 u16 pvlan; 521 522 if (!dsa_is_user_port(ds, port)) 523 return 0; 524 525 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 526 527 b53_br_egress_floods(ds, port, true, true); 528 529 if (dev->ops->irq_enable) 530 ret = dev->ops->irq_enable(dev, port); 531 if (ret) 532 return ret; 533 534 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 535 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 536 537 /* Set this port, and only this one to be in the default VLAN, 538 * if member of a bridge, restore its membership prior to 539 * bringing down this port. 540 */ 541 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 542 pvlan &= ~0x1ff; 543 pvlan |= BIT(port); 544 pvlan |= dev->ports[port].vlan_ctl_mask; 545 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 546 547 b53_imp_vlan_setup(ds, cpu_port); 548 549 /* If EEE was enabled, restore it */ 550 if (dev->ports[port].eee.eee_enabled) 551 b53_eee_enable_set(ds, port, true); 552 553 return 0; 554 } 555 EXPORT_SYMBOL(b53_enable_port); 556 557 void b53_disable_port(struct dsa_switch *ds, int port) 558 { 559 struct b53_device *dev = ds->priv; 560 u8 reg; 561 562 /* Disable Tx/Rx for the port */ 563 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 564 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 565 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 566 567 if (dev->ops->irq_disable) 568 dev->ops->irq_disable(dev, port); 569 } 570 EXPORT_SYMBOL(b53_disable_port); 571 572 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 573 { 574 struct b53_device *dev = ds->priv; 575 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 576 u8 hdr_ctl, val; 577 u16 reg; 578 579 /* Resolve which bit controls the Broadcom tag */ 580 switch (port) { 581 case 8: 582 val = BRCM_HDR_P8_EN; 583 break; 584 case 7: 585 val = BRCM_HDR_P7_EN; 586 break; 587 case 5: 588 val = BRCM_HDR_P5_EN; 589 break; 590 default: 591 val = 0; 592 break; 593 } 594 595 /* Enable management mode if tagging is requested */ 596 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 597 if (tag_en) 598 hdr_ctl |= SM_SW_FWD_MODE; 599 else 600 hdr_ctl &= ~SM_SW_FWD_MODE; 601 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 602 603 /* Configure the appropriate IMP port */ 604 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 605 if (port == 8) 606 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 607 else if (port == 5) 608 hdr_ctl |= GC_FRM_MGMT_PORT_M; 609 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 610 611 /* Enable Broadcom tags for IMP port */ 612 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 613 if (tag_en) 614 hdr_ctl |= val; 615 else 616 hdr_ctl &= ~val; 617 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 618 619 /* Registers below are only accessible on newer devices */ 620 if (!is58xx(dev)) 621 return; 622 623 /* Enable reception Broadcom tag for CPU TX (switch RX) to 624 * allow us to tag outgoing frames 625 */ 626 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 627 if (tag_en) 628 reg &= ~BIT(port); 629 else 630 reg |= BIT(port); 631 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 632 633 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 634 * allow delivering frames to the per-port net_devices 635 */ 636 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 637 if (tag_en) 638 reg &= ~BIT(port); 639 else 640 reg |= BIT(port); 641 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 642 } 643 EXPORT_SYMBOL(b53_brcm_hdr_setup); 644 645 static void b53_enable_cpu_port(struct b53_device *dev, int port) 646 { 647 u8 port_ctrl; 648 649 /* BCM5325 CPU port is at 8 */ 650 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 651 port = B53_CPU_PORT; 652 653 port_ctrl = PORT_CTRL_RX_BCST_EN | 654 PORT_CTRL_RX_MCST_EN | 655 PORT_CTRL_RX_UCST_EN; 656 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 657 658 b53_brcm_hdr_setup(dev->ds, port); 659 660 b53_br_egress_floods(dev->ds, port, true, true); 661 } 662 663 static void b53_enable_mib(struct b53_device *dev) 664 { 665 u8 gc; 666 667 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 668 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 669 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 670 } 671 672 static u16 b53_default_pvid(struct b53_device *dev) 673 { 674 if (is5325(dev) || is5365(dev)) 675 return 1; 676 else 677 return 0; 678 } 679 680 int b53_configure_vlan(struct dsa_switch *ds) 681 { 682 struct b53_device *dev = ds->priv; 683 struct b53_vlan vl = { 0 }; 684 struct b53_vlan *v; 685 int i, def_vid; 686 u16 vid; 687 688 def_vid = b53_default_pvid(dev); 689 690 /* clear all vlan entries */ 691 if (is5325(dev) || is5365(dev)) { 692 for (i = def_vid; i < dev->num_vlans; i++) 693 b53_set_vlan_entry(dev, i, &vl); 694 } else { 695 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 696 } 697 698 b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering); 699 700 b53_for_each_port(dev, i) 701 b53_write16(dev, B53_VLAN_PAGE, 702 B53_VLAN_PORT_DEF_TAG(i), def_vid); 703 704 /* Upon initial call we have not set-up any VLANs, but upon 705 * system resume, we need to restore all VLAN entries. 706 */ 707 for (vid = def_vid; vid < dev->num_vlans; vid++) { 708 v = &dev->vlans[vid]; 709 710 if (!v->members) 711 continue; 712 713 b53_set_vlan_entry(dev, vid, v); 714 b53_fast_age_vlan(dev, vid); 715 } 716 717 return 0; 718 } 719 EXPORT_SYMBOL(b53_configure_vlan); 720 721 static void b53_switch_reset_gpio(struct b53_device *dev) 722 { 723 int gpio = dev->reset_gpio; 724 725 if (gpio < 0) 726 return; 727 728 /* Reset sequence: RESET low(50ms)->high(20ms) 729 */ 730 gpio_set_value(gpio, 0); 731 mdelay(50); 732 733 gpio_set_value(gpio, 1); 734 mdelay(20); 735 736 dev->current_page = 0xff; 737 } 738 739 static int b53_switch_reset(struct b53_device *dev) 740 { 741 unsigned int timeout = 1000; 742 u8 mgmt, reg; 743 744 b53_switch_reset_gpio(dev); 745 746 if (is539x(dev)) { 747 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 748 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 749 } 750 751 /* This is specific to 58xx devices here, do not use is58xx() which 752 * covers the larger Starfigther 2 family, including 7445/7278 which 753 * still use this driver as a library and need to perform the reset 754 * earlier. 755 */ 756 if (dev->chip_id == BCM58XX_DEVICE_ID || 757 dev->chip_id == BCM583XX_DEVICE_ID) { 758 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 759 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 760 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 761 762 do { 763 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 764 if (!(reg & SW_RST)) 765 break; 766 767 usleep_range(1000, 2000); 768 } while (timeout-- > 0); 769 770 if (timeout == 0) 771 return -ETIMEDOUT; 772 } 773 774 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 775 776 if (!(mgmt & SM_SW_FWD_EN)) { 777 mgmt &= ~SM_SW_FWD_MODE; 778 mgmt |= SM_SW_FWD_EN; 779 780 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 781 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 782 783 if (!(mgmt & SM_SW_FWD_EN)) { 784 dev_err(dev->dev, "Failed to enable switch!\n"); 785 return -EINVAL; 786 } 787 } 788 789 b53_enable_mib(dev); 790 791 return b53_flush_arl(dev, FAST_AGE_STATIC); 792 } 793 794 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 795 { 796 struct b53_device *priv = ds->priv; 797 u16 value = 0; 798 int ret; 799 800 if (priv->ops->phy_read16) 801 ret = priv->ops->phy_read16(priv, addr, reg, &value); 802 else 803 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 804 reg * 2, &value); 805 806 return ret ? ret : value; 807 } 808 809 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 810 { 811 struct b53_device *priv = ds->priv; 812 813 if (priv->ops->phy_write16) 814 return priv->ops->phy_write16(priv, addr, reg, val); 815 816 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 817 } 818 819 static int b53_reset_switch(struct b53_device *priv) 820 { 821 /* reset vlans */ 822 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 823 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 824 825 priv->serdes_lane = B53_INVALID_LANE; 826 827 return b53_switch_reset(priv); 828 } 829 830 static int b53_apply_config(struct b53_device *priv) 831 { 832 /* disable switching */ 833 b53_set_forwarding(priv, 0); 834 835 b53_configure_vlan(priv->ds); 836 837 /* enable switching */ 838 b53_set_forwarding(priv, 1); 839 840 return 0; 841 } 842 843 static void b53_reset_mib(struct b53_device *priv) 844 { 845 u8 gc; 846 847 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 848 849 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 850 msleep(1); 851 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 852 msleep(1); 853 } 854 855 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 856 { 857 if (is5365(dev)) 858 return b53_mibs_65; 859 else if (is63xx(dev)) 860 return b53_mibs_63xx; 861 else if (is58xx(dev)) 862 return b53_mibs_58xx; 863 else 864 return b53_mibs; 865 } 866 867 static unsigned int b53_get_mib_size(struct b53_device *dev) 868 { 869 if (is5365(dev)) 870 return B53_MIBS_65_SIZE; 871 else if (is63xx(dev)) 872 return B53_MIBS_63XX_SIZE; 873 else if (is58xx(dev)) 874 return B53_MIBS_58XX_SIZE; 875 else 876 return B53_MIBS_SIZE; 877 } 878 879 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 880 { 881 /* These ports typically do not have built-in PHYs */ 882 switch (port) { 883 case B53_CPU_PORT_25: 884 case 7: 885 case B53_CPU_PORT: 886 return NULL; 887 } 888 889 return mdiobus_get_phy(ds->slave_mii_bus, port); 890 } 891 892 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 893 uint8_t *data) 894 { 895 struct b53_device *dev = ds->priv; 896 const struct b53_mib_desc *mibs = b53_get_mib(dev); 897 unsigned int mib_size = b53_get_mib_size(dev); 898 struct phy_device *phydev; 899 unsigned int i; 900 901 if (stringset == ETH_SS_STATS) { 902 for (i = 0; i < mib_size; i++) 903 strlcpy(data + i * ETH_GSTRING_LEN, 904 mibs[i].name, ETH_GSTRING_LEN); 905 } else if (stringset == ETH_SS_PHY_STATS) { 906 phydev = b53_get_phy_device(ds, port); 907 if (!phydev) 908 return; 909 910 phy_ethtool_get_strings(phydev, data); 911 } 912 } 913 EXPORT_SYMBOL(b53_get_strings); 914 915 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 916 { 917 struct b53_device *dev = ds->priv; 918 const struct b53_mib_desc *mibs = b53_get_mib(dev); 919 unsigned int mib_size = b53_get_mib_size(dev); 920 const struct b53_mib_desc *s; 921 unsigned int i; 922 u64 val = 0; 923 924 if (is5365(dev) && port == 5) 925 port = 8; 926 927 mutex_lock(&dev->stats_mutex); 928 929 for (i = 0; i < mib_size; i++) { 930 s = &mibs[i]; 931 932 if (s->size == 8) { 933 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 934 } else { 935 u32 val32; 936 937 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 938 &val32); 939 val = val32; 940 } 941 data[i] = (u64)val; 942 } 943 944 mutex_unlock(&dev->stats_mutex); 945 } 946 EXPORT_SYMBOL(b53_get_ethtool_stats); 947 948 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 949 { 950 struct phy_device *phydev; 951 952 phydev = b53_get_phy_device(ds, port); 953 if (!phydev) 954 return; 955 956 phy_ethtool_get_stats(phydev, NULL, data); 957 } 958 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 959 960 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 961 { 962 struct b53_device *dev = ds->priv; 963 struct phy_device *phydev; 964 965 if (sset == ETH_SS_STATS) { 966 return b53_get_mib_size(dev); 967 } else if (sset == ETH_SS_PHY_STATS) { 968 phydev = b53_get_phy_device(ds, port); 969 if (!phydev) 970 return 0; 971 972 return phy_ethtool_get_sset_count(phydev); 973 } 974 975 return 0; 976 } 977 EXPORT_SYMBOL(b53_get_sset_count); 978 979 static int b53_setup(struct dsa_switch *ds) 980 { 981 struct b53_device *dev = ds->priv; 982 unsigned int port; 983 int ret; 984 985 ret = b53_reset_switch(dev); 986 if (ret) { 987 dev_err(ds->dev, "failed to reset switch\n"); 988 return ret; 989 } 990 991 b53_reset_mib(dev); 992 993 ret = b53_apply_config(dev); 994 if (ret) 995 dev_err(ds->dev, "failed to apply configuration\n"); 996 997 /* Configure IMP/CPU port, disable all other ports. Enabled 998 * ports will be configured with .port_enable 999 */ 1000 for (port = 0; port < dev->num_ports; port++) { 1001 if (dsa_is_cpu_port(ds, port)) 1002 b53_enable_cpu_port(dev, port); 1003 else 1004 b53_disable_port(ds, port); 1005 } 1006 1007 /* Let DSA handle the case were multiple bridges span the same switch 1008 * device and different VLAN awareness settings are requested, which 1009 * would be breaking filtering semantics for any of the other bridge 1010 * devices. (not hardware supported) 1011 */ 1012 ds->vlan_filtering_is_global = true; 1013 1014 return ret; 1015 } 1016 1017 static void b53_force_link(struct b53_device *dev, int port, int link) 1018 { 1019 u8 reg, val, off; 1020 1021 /* Override the port settings */ 1022 if (port == dev->cpu_port) { 1023 off = B53_PORT_OVERRIDE_CTRL; 1024 val = PORT_OVERRIDE_EN; 1025 } else { 1026 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1027 val = GMII_PO_EN; 1028 } 1029 1030 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1031 reg |= val; 1032 if (link) 1033 reg |= PORT_OVERRIDE_LINK; 1034 else 1035 reg &= ~PORT_OVERRIDE_LINK; 1036 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1037 } 1038 1039 static void b53_force_port_config(struct b53_device *dev, int port, 1040 int speed, int duplex, int pause) 1041 { 1042 u8 reg, val, off; 1043 1044 /* Override the port settings */ 1045 if (port == dev->cpu_port) { 1046 off = B53_PORT_OVERRIDE_CTRL; 1047 val = PORT_OVERRIDE_EN; 1048 } else { 1049 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1050 val = GMII_PO_EN; 1051 } 1052 1053 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1054 reg |= val; 1055 if (duplex == DUPLEX_FULL) 1056 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1057 else 1058 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1059 1060 switch (speed) { 1061 case 2000: 1062 reg |= PORT_OVERRIDE_SPEED_2000M; 1063 /* fallthrough */ 1064 case SPEED_1000: 1065 reg |= PORT_OVERRIDE_SPEED_1000M; 1066 break; 1067 case SPEED_100: 1068 reg |= PORT_OVERRIDE_SPEED_100M; 1069 break; 1070 case SPEED_10: 1071 reg |= PORT_OVERRIDE_SPEED_10M; 1072 break; 1073 default: 1074 dev_err(dev->dev, "unknown speed: %d\n", speed); 1075 return; 1076 } 1077 1078 if (pause & MLO_PAUSE_RX) 1079 reg |= PORT_OVERRIDE_RX_FLOW; 1080 if (pause & MLO_PAUSE_TX) 1081 reg |= PORT_OVERRIDE_TX_FLOW; 1082 1083 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1084 } 1085 1086 static void b53_adjust_link(struct dsa_switch *ds, int port, 1087 struct phy_device *phydev) 1088 { 1089 struct b53_device *dev = ds->priv; 1090 struct ethtool_eee *p = &dev->ports[port].eee; 1091 u8 rgmii_ctrl = 0, reg = 0, off; 1092 int pause = 0; 1093 1094 if (!phy_is_pseudo_fixed_link(phydev)) 1095 return; 1096 1097 /* Enable flow control on BCM5301x's CPU port */ 1098 if (is5301x(dev) && port == dev->cpu_port) 1099 pause = MLO_PAUSE_TXRX_MASK; 1100 1101 if (phydev->pause) { 1102 if (phydev->asym_pause) 1103 pause |= MLO_PAUSE_TX; 1104 pause |= MLO_PAUSE_RX; 1105 } 1106 1107 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause); 1108 b53_force_link(dev, port, phydev->link); 1109 1110 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1111 if (port == 8) 1112 off = B53_RGMII_CTRL_IMP; 1113 else 1114 off = B53_RGMII_CTRL_P(port); 1115 1116 /* Configure the port RGMII clock delay by DLL disabled and 1117 * tx_clk aligned timing (restoring to reset defaults) 1118 */ 1119 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1120 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1121 RGMII_CTRL_TIMING_SEL); 1122 1123 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1124 * sure that we enable the port TX clock internal delay to 1125 * account for this internal delay that is inserted, otherwise 1126 * the switch won't be able to receive correctly. 1127 * 1128 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1129 * any delay neither on transmission nor reception, so the 1130 * BCM53125 must also be configured accordingly to account for 1131 * the lack of delay and introduce 1132 * 1133 * The BCM53125 switch has its RX clock and TX clock control 1134 * swapped, hence the reason why we modify the TX clock path in 1135 * the "RGMII" case 1136 */ 1137 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1138 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1139 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1140 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1141 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1142 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1143 1144 dev_info(ds->dev, "Configured port %d for %s\n", port, 1145 phy_modes(phydev->interface)); 1146 } 1147 1148 /* configure MII port if necessary */ 1149 if (is5325(dev)) { 1150 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1151 ®); 1152 1153 /* reverse mii needs to be enabled */ 1154 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1155 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1156 reg | PORT_OVERRIDE_RV_MII_25); 1157 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1158 ®); 1159 1160 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1161 dev_err(ds->dev, 1162 "Failed to enable reverse MII mode\n"); 1163 return; 1164 } 1165 } 1166 } else if (is5301x(dev)) { 1167 if (port != dev->cpu_port) { 1168 b53_force_port_config(dev, dev->cpu_port, 2000, 1169 DUPLEX_FULL, MLO_PAUSE_TXRX_MASK); 1170 b53_force_link(dev, dev->cpu_port, 1); 1171 } 1172 } 1173 1174 /* Re-negotiate EEE if it was enabled already */ 1175 p->eee_enabled = b53_eee_init(ds, port, phydev); 1176 } 1177 1178 void b53_port_event(struct dsa_switch *ds, int port) 1179 { 1180 struct b53_device *dev = ds->priv; 1181 bool link; 1182 u16 sts; 1183 1184 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1185 link = !!(sts & BIT(port)); 1186 dsa_port_phylink_mac_change(ds, port, link); 1187 } 1188 EXPORT_SYMBOL(b53_port_event); 1189 1190 void b53_phylink_validate(struct dsa_switch *ds, int port, 1191 unsigned long *supported, 1192 struct phylink_link_state *state) 1193 { 1194 struct b53_device *dev = ds->priv; 1195 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1196 1197 if (dev->ops->serdes_phylink_validate) 1198 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1199 1200 /* Allow all the expected bits */ 1201 phylink_set(mask, Autoneg); 1202 phylink_set_port_modes(mask); 1203 phylink_set(mask, Pause); 1204 phylink_set(mask, Asym_Pause); 1205 1206 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1207 * support Gigabit, including Half duplex. 1208 */ 1209 if (state->interface != PHY_INTERFACE_MODE_MII && 1210 state->interface != PHY_INTERFACE_MODE_REVMII && 1211 !phy_interface_mode_is_8023z(state->interface) && 1212 !(is5325(dev) || is5365(dev))) { 1213 phylink_set(mask, 1000baseT_Full); 1214 phylink_set(mask, 1000baseT_Half); 1215 } 1216 1217 if (!phy_interface_mode_is_8023z(state->interface)) { 1218 phylink_set(mask, 10baseT_Half); 1219 phylink_set(mask, 10baseT_Full); 1220 phylink_set(mask, 100baseT_Half); 1221 phylink_set(mask, 100baseT_Full); 1222 } 1223 1224 bitmap_and(supported, supported, mask, 1225 __ETHTOOL_LINK_MODE_MASK_NBITS); 1226 bitmap_and(state->advertising, state->advertising, mask, 1227 __ETHTOOL_LINK_MODE_MASK_NBITS); 1228 1229 phylink_helper_basex_speed(state); 1230 } 1231 EXPORT_SYMBOL(b53_phylink_validate); 1232 1233 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1234 struct phylink_link_state *state) 1235 { 1236 struct b53_device *dev = ds->priv; 1237 int ret = -EOPNOTSUPP; 1238 1239 if ((phy_interface_mode_is_8023z(state->interface) || 1240 state->interface == PHY_INTERFACE_MODE_SGMII) && 1241 dev->ops->serdes_link_state) 1242 ret = dev->ops->serdes_link_state(dev, port, state); 1243 1244 return ret; 1245 } 1246 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1247 1248 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1249 unsigned int mode, 1250 const struct phylink_link_state *state) 1251 { 1252 struct b53_device *dev = ds->priv; 1253 1254 if (mode == MLO_AN_PHY) 1255 return; 1256 1257 if (mode == MLO_AN_FIXED) { 1258 b53_force_port_config(dev, port, state->speed, 1259 state->duplex, state->pause); 1260 return; 1261 } 1262 1263 if ((phy_interface_mode_is_8023z(state->interface) || 1264 state->interface == PHY_INTERFACE_MODE_SGMII) && 1265 dev->ops->serdes_config) 1266 dev->ops->serdes_config(dev, port, mode, state); 1267 } 1268 EXPORT_SYMBOL(b53_phylink_mac_config); 1269 1270 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1271 { 1272 struct b53_device *dev = ds->priv; 1273 1274 if (dev->ops->serdes_an_restart) 1275 dev->ops->serdes_an_restart(dev, port); 1276 } 1277 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1278 1279 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1280 unsigned int mode, 1281 phy_interface_t interface) 1282 { 1283 struct b53_device *dev = ds->priv; 1284 1285 if (mode == MLO_AN_PHY) 1286 return; 1287 1288 if (mode == MLO_AN_FIXED) { 1289 b53_force_link(dev, port, false); 1290 return; 1291 } 1292 1293 if (phy_interface_mode_is_8023z(interface) && 1294 dev->ops->serdes_link_set) 1295 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1296 } 1297 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1298 1299 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1300 unsigned int mode, 1301 phy_interface_t interface, 1302 struct phy_device *phydev, 1303 int speed, int duplex, 1304 bool tx_pause, bool rx_pause) 1305 { 1306 struct b53_device *dev = ds->priv; 1307 1308 if (mode == MLO_AN_PHY) 1309 return; 1310 1311 if (mode == MLO_AN_FIXED) { 1312 b53_force_link(dev, port, true); 1313 return; 1314 } 1315 1316 if (phy_interface_mode_is_8023z(interface) && 1317 dev->ops->serdes_link_set) 1318 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1319 } 1320 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1321 1322 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 1323 { 1324 struct b53_device *dev = ds->priv; 1325 u16 pvid, new_pvid; 1326 1327 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1328 if (!vlan_filtering) { 1329 /* Filtering is currently enabled, use the default PVID since 1330 * the bridge does not expect tagging anymore 1331 */ 1332 dev->ports[port].pvid = pvid; 1333 new_pvid = b53_default_pvid(dev); 1334 } else { 1335 /* Filtering is currently disabled, restore the previous PVID */ 1336 new_pvid = dev->ports[port].pvid; 1337 } 1338 1339 if (pvid != new_pvid) 1340 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1341 new_pvid); 1342 1343 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering); 1344 1345 return 0; 1346 } 1347 EXPORT_SYMBOL(b53_vlan_filtering); 1348 1349 int b53_vlan_prepare(struct dsa_switch *ds, int port, 1350 const struct switchdev_obj_port_vlan *vlan) 1351 { 1352 struct b53_device *dev = ds->priv; 1353 1354 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 1355 return -EOPNOTSUPP; 1356 1357 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1358 * receiving VLAN tagged frames at all, we can still allow the port to 1359 * be configured for egress untagged. 1360 */ 1361 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1362 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1363 return -EINVAL; 1364 1365 if (vlan->vid_end > dev->num_vlans) 1366 return -ERANGE; 1367 1368 b53_enable_vlan(dev, true, ds->vlan_filtering); 1369 1370 return 0; 1371 } 1372 EXPORT_SYMBOL(b53_vlan_prepare); 1373 1374 void b53_vlan_add(struct dsa_switch *ds, int port, 1375 const struct switchdev_obj_port_vlan *vlan) 1376 { 1377 struct b53_device *dev = ds->priv; 1378 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1379 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1380 struct b53_vlan *vl; 1381 u16 vid; 1382 1383 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1384 vl = &dev->vlans[vid]; 1385 1386 b53_get_vlan_entry(dev, vid, vl); 1387 1388 if (vid == 0 && vid == b53_default_pvid(dev)) 1389 untagged = true; 1390 1391 vl->members |= BIT(port); 1392 if (untagged && !dsa_is_cpu_port(ds, port)) 1393 vl->untag |= BIT(port); 1394 else 1395 vl->untag &= ~BIT(port); 1396 1397 b53_set_vlan_entry(dev, vid, vl); 1398 b53_fast_age_vlan(dev, vid); 1399 } 1400 1401 if (pvid && !dsa_is_cpu_port(ds, port)) { 1402 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1403 vlan->vid_end); 1404 b53_fast_age_vlan(dev, vid); 1405 } 1406 } 1407 EXPORT_SYMBOL(b53_vlan_add); 1408 1409 int b53_vlan_del(struct dsa_switch *ds, int port, 1410 const struct switchdev_obj_port_vlan *vlan) 1411 { 1412 struct b53_device *dev = ds->priv; 1413 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1414 struct b53_vlan *vl; 1415 u16 vid; 1416 u16 pvid; 1417 1418 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1419 1420 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1421 vl = &dev->vlans[vid]; 1422 1423 b53_get_vlan_entry(dev, vid, vl); 1424 1425 vl->members &= ~BIT(port); 1426 1427 if (pvid == vid) 1428 pvid = b53_default_pvid(dev); 1429 1430 if (untagged && !dsa_is_cpu_port(ds, port)) 1431 vl->untag &= ~(BIT(port)); 1432 1433 b53_set_vlan_entry(dev, vid, vl); 1434 b53_fast_age_vlan(dev, vid); 1435 } 1436 1437 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1438 b53_fast_age_vlan(dev, pvid); 1439 1440 return 0; 1441 } 1442 EXPORT_SYMBOL(b53_vlan_del); 1443 1444 /* Address Resolution Logic routines */ 1445 static int b53_arl_op_wait(struct b53_device *dev) 1446 { 1447 unsigned int timeout = 10; 1448 u8 reg; 1449 1450 do { 1451 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1452 if (!(reg & ARLTBL_START_DONE)) 1453 return 0; 1454 1455 usleep_range(1000, 2000); 1456 } while (timeout--); 1457 1458 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1459 1460 return -ETIMEDOUT; 1461 } 1462 1463 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1464 { 1465 u8 reg; 1466 1467 if (op > ARLTBL_RW) 1468 return -EINVAL; 1469 1470 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1471 reg |= ARLTBL_START_DONE; 1472 if (op) 1473 reg |= ARLTBL_RW; 1474 else 1475 reg &= ~ARLTBL_RW; 1476 if (dev->vlan_enabled) 1477 reg &= ~ARLTBL_IVL_SVL_SELECT; 1478 else 1479 reg |= ARLTBL_IVL_SVL_SELECT; 1480 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1481 1482 return b53_arl_op_wait(dev); 1483 } 1484 1485 static int b53_arl_read(struct b53_device *dev, u64 mac, 1486 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1487 { 1488 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1489 unsigned int i; 1490 int ret; 1491 1492 ret = b53_arl_op_wait(dev); 1493 if (ret) 1494 return ret; 1495 1496 bitmap_zero(free_bins, dev->num_arl_bins); 1497 1498 /* Read the bins */ 1499 for (i = 0; i < dev->num_arl_bins; i++) { 1500 u64 mac_vid; 1501 u32 fwd_entry; 1502 1503 b53_read64(dev, B53_ARLIO_PAGE, 1504 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1505 b53_read32(dev, B53_ARLIO_PAGE, 1506 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1507 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1508 1509 if (!(fwd_entry & ARLTBL_VALID)) { 1510 set_bit(i, free_bins); 1511 continue; 1512 } 1513 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1514 continue; 1515 if (dev->vlan_enabled && 1516 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1517 continue; 1518 *idx = i; 1519 return 0; 1520 } 1521 1522 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0) 1523 return -ENOSPC; 1524 1525 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1526 1527 return -ENOENT; 1528 } 1529 1530 static int b53_arl_op(struct b53_device *dev, int op, int port, 1531 const unsigned char *addr, u16 vid, bool is_valid) 1532 { 1533 struct b53_arl_entry ent; 1534 u32 fwd_entry; 1535 u64 mac, mac_vid = 0; 1536 u8 idx = 0; 1537 int ret; 1538 1539 /* Convert the array into a 64-bit MAC */ 1540 mac = ether_addr_to_u64(addr); 1541 1542 /* Perform a read for the given MAC and VID */ 1543 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1544 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1545 1546 /* Issue a read operation for this MAC */ 1547 ret = b53_arl_rw_op(dev, 1); 1548 if (ret) 1549 return ret; 1550 1551 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1552 1553 /* If this is a read, just finish now */ 1554 if (op) 1555 return ret; 1556 1557 switch (ret) { 1558 case -ENOSPC: 1559 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1560 addr, vid); 1561 return is_valid ? ret : 0; 1562 case -ENOENT: 1563 /* We could not find a matching MAC, so reset to a new entry */ 1564 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1565 addr, vid, idx); 1566 fwd_entry = 0; 1567 break; 1568 default: 1569 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1570 addr, vid, idx); 1571 break; 1572 } 1573 1574 /* For multicast address, the port is a bitmask and the validity 1575 * is determined by having at least one port being still active 1576 */ 1577 if (!is_multicast_ether_addr(addr)) { 1578 ent.port = port; 1579 ent.is_valid = is_valid; 1580 } else { 1581 if (is_valid) 1582 ent.port |= BIT(port); 1583 else 1584 ent.port &= ~BIT(port); 1585 1586 ent.is_valid = !!(ent.port); 1587 } 1588 1589 ent.vid = vid; 1590 ent.is_static = true; 1591 ent.is_age = false; 1592 memcpy(ent.mac, addr, ETH_ALEN); 1593 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1594 1595 b53_write64(dev, B53_ARLIO_PAGE, 1596 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1597 b53_write32(dev, B53_ARLIO_PAGE, 1598 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1599 1600 return b53_arl_rw_op(dev, 0); 1601 } 1602 1603 int b53_fdb_add(struct dsa_switch *ds, int port, 1604 const unsigned char *addr, u16 vid) 1605 { 1606 struct b53_device *priv = ds->priv; 1607 1608 /* 5325 and 5365 require some more massaging, but could 1609 * be supported eventually 1610 */ 1611 if (is5325(priv) || is5365(priv)) 1612 return -EOPNOTSUPP; 1613 1614 return b53_arl_op(priv, 0, port, addr, vid, true); 1615 } 1616 EXPORT_SYMBOL(b53_fdb_add); 1617 1618 int b53_fdb_del(struct dsa_switch *ds, int port, 1619 const unsigned char *addr, u16 vid) 1620 { 1621 struct b53_device *priv = ds->priv; 1622 1623 return b53_arl_op(priv, 0, port, addr, vid, false); 1624 } 1625 EXPORT_SYMBOL(b53_fdb_del); 1626 1627 static int b53_arl_search_wait(struct b53_device *dev) 1628 { 1629 unsigned int timeout = 1000; 1630 u8 reg; 1631 1632 do { 1633 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1634 if (!(reg & ARL_SRCH_STDN)) 1635 return 0; 1636 1637 if (reg & ARL_SRCH_VLID) 1638 return 0; 1639 1640 usleep_range(1000, 2000); 1641 } while (timeout--); 1642 1643 return -ETIMEDOUT; 1644 } 1645 1646 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1647 struct b53_arl_entry *ent) 1648 { 1649 u64 mac_vid; 1650 u32 fwd_entry; 1651 1652 b53_read64(dev, B53_ARLIO_PAGE, 1653 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1654 b53_read32(dev, B53_ARLIO_PAGE, 1655 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1656 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1657 } 1658 1659 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1660 dsa_fdb_dump_cb_t *cb, void *data) 1661 { 1662 if (!ent->is_valid) 1663 return 0; 1664 1665 if (port != ent->port) 1666 return 0; 1667 1668 return cb(ent->mac, ent->vid, ent->is_static, data); 1669 } 1670 1671 int b53_fdb_dump(struct dsa_switch *ds, int port, 1672 dsa_fdb_dump_cb_t *cb, void *data) 1673 { 1674 struct b53_device *priv = ds->priv; 1675 struct b53_arl_entry results[2]; 1676 unsigned int count = 0; 1677 int ret; 1678 u8 reg; 1679 1680 /* Start search operation */ 1681 reg = ARL_SRCH_STDN; 1682 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1683 1684 do { 1685 ret = b53_arl_search_wait(priv); 1686 if (ret) 1687 return ret; 1688 1689 b53_arl_search_rd(priv, 0, &results[0]); 1690 ret = b53_fdb_copy(port, &results[0], cb, data); 1691 if (ret) 1692 return ret; 1693 1694 if (priv->num_arl_bins > 2) { 1695 b53_arl_search_rd(priv, 1, &results[1]); 1696 ret = b53_fdb_copy(port, &results[1], cb, data); 1697 if (ret) 1698 return ret; 1699 1700 if (!results[0].is_valid && !results[1].is_valid) 1701 break; 1702 } 1703 1704 } while (count++ < b53_max_arl_entries(priv) / 2); 1705 1706 return 0; 1707 } 1708 EXPORT_SYMBOL(b53_fdb_dump); 1709 1710 int b53_mdb_prepare(struct dsa_switch *ds, int port, 1711 const struct switchdev_obj_port_mdb *mdb) 1712 { 1713 struct b53_device *priv = ds->priv; 1714 1715 /* 5325 and 5365 require some more massaging, but could 1716 * be supported eventually 1717 */ 1718 if (is5325(priv) || is5365(priv)) 1719 return -EOPNOTSUPP; 1720 1721 return 0; 1722 } 1723 EXPORT_SYMBOL(b53_mdb_prepare); 1724 1725 void b53_mdb_add(struct dsa_switch *ds, int port, 1726 const struct switchdev_obj_port_mdb *mdb) 1727 { 1728 struct b53_device *priv = ds->priv; 1729 int ret; 1730 1731 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1732 if (ret) 1733 dev_err(ds->dev, "failed to add MDB entry\n"); 1734 } 1735 EXPORT_SYMBOL(b53_mdb_add); 1736 1737 int b53_mdb_del(struct dsa_switch *ds, int port, 1738 const struct switchdev_obj_port_mdb *mdb) 1739 { 1740 struct b53_device *priv = ds->priv; 1741 int ret; 1742 1743 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1744 if (ret) 1745 dev_err(ds->dev, "failed to delete MDB entry\n"); 1746 1747 return ret; 1748 } 1749 EXPORT_SYMBOL(b53_mdb_del); 1750 1751 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1752 { 1753 struct b53_device *dev = ds->priv; 1754 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1755 u16 pvlan, reg; 1756 unsigned int i; 1757 1758 /* On 7278, port 7 which connects to the ASP should only receive 1759 * traffic from matching CFP rules. 1760 */ 1761 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1762 return -EINVAL; 1763 1764 /* Make this port leave the all VLANs join since we will have proper 1765 * VLAN entries from now on 1766 */ 1767 if (is58xx(dev)) { 1768 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1769 reg &= ~BIT(port); 1770 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1771 reg &= ~BIT(cpu_port); 1772 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1773 } 1774 1775 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1776 1777 b53_for_each_port(dev, i) { 1778 if (dsa_to_port(ds, i)->bridge_dev != br) 1779 continue; 1780 1781 /* Add this local port to the remote port VLAN control 1782 * membership and update the remote port bitmask 1783 */ 1784 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1785 reg |= BIT(port); 1786 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1787 dev->ports[i].vlan_ctl_mask = reg; 1788 1789 pvlan |= BIT(i); 1790 } 1791 1792 /* Configure the local port VLAN control membership to include 1793 * remote ports and update the local port bitmask 1794 */ 1795 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1796 dev->ports[port].vlan_ctl_mask = pvlan; 1797 1798 return 0; 1799 } 1800 EXPORT_SYMBOL(b53_br_join); 1801 1802 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1803 { 1804 struct b53_device *dev = ds->priv; 1805 struct b53_vlan *vl = &dev->vlans[0]; 1806 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1807 unsigned int i; 1808 u16 pvlan, reg, pvid; 1809 1810 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1811 1812 b53_for_each_port(dev, i) { 1813 /* Don't touch the remaining ports */ 1814 if (dsa_to_port(ds, i)->bridge_dev != br) 1815 continue; 1816 1817 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1818 reg &= ~BIT(port); 1819 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1820 dev->ports[port].vlan_ctl_mask = reg; 1821 1822 /* Prevent self removal to preserve isolation */ 1823 if (port != i) 1824 pvlan &= ~BIT(i); 1825 } 1826 1827 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1828 dev->ports[port].vlan_ctl_mask = pvlan; 1829 1830 pvid = b53_default_pvid(dev); 1831 1832 /* Make this port join all VLANs without VLAN entries */ 1833 if (is58xx(dev)) { 1834 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1835 reg |= BIT(port); 1836 if (!(reg & BIT(cpu_port))) 1837 reg |= BIT(cpu_port); 1838 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1839 } else { 1840 b53_get_vlan_entry(dev, pvid, vl); 1841 vl->members |= BIT(port) | BIT(cpu_port); 1842 vl->untag |= BIT(port) | BIT(cpu_port); 1843 b53_set_vlan_entry(dev, pvid, vl); 1844 } 1845 } 1846 EXPORT_SYMBOL(b53_br_leave); 1847 1848 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1849 { 1850 struct b53_device *dev = ds->priv; 1851 u8 hw_state; 1852 u8 reg; 1853 1854 switch (state) { 1855 case BR_STATE_DISABLED: 1856 hw_state = PORT_CTRL_DIS_STATE; 1857 break; 1858 case BR_STATE_LISTENING: 1859 hw_state = PORT_CTRL_LISTEN_STATE; 1860 break; 1861 case BR_STATE_LEARNING: 1862 hw_state = PORT_CTRL_LEARN_STATE; 1863 break; 1864 case BR_STATE_FORWARDING: 1865 hw_state = PORT_CTRL_FWD_STATE; 1866 break; 1867 case BR_STATE_BLOCKING: 1868 hw_state = PORT_CTRL_BLOCK_STATE; 1869 break; 1870 default: 1871 dev_err(ds->dev, "invalid STP state: %d\n", state); 1872 return; 1873 } 1874 1875 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1876 reg &= ~PORT_CTRL_STP_STATE_MASK; 1877 reg |= hw_state; 1878 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1879 } 1880 EXPORT_SYMBOL(b53_br_set_stp_state); 1881 1882 void b53_br_fast_age(struct dsa_switch *ds, int port) 1883 { 1884 struct b53_device *dev = ds->priv; 1885 1886 if (b53_fast_age_port(dev, port)) 1887 dev_err(ds->dev, "fast ageing failed\n"); 1888 } 1889 EXPORT_SYMBOL(b53_br_fast_age); 1890 1891 int b53_br_egress_floods(struct dsa_switch *ds, int port, 1892 bool unicast, bool multicast) 1893 { 1894 struct b53_device *dev = ds->priv; 1895 u16 uc, mc; 1896 1897 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 1898 if (unicast) 1899 uc |= BIT(port); 1900 else 1901 uc &= ~BIT(port); 1902 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 1903 1904 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 1905 if (multicast) 1906 mc |= BIT(port); 1907 else 1908 mc &= ~BIT(port); 1909 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 1910 1911 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 1912 if (multicast) 1913 mc |= BIT(port); 1914 else 1915 mc &= ~BIT(port); 1916 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 1917 1918 return 0; 1919 1920 } 1921 EXPORT_SYMBOL(b53_br_egress_floods); 1922 1923 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 1924 { 1925 /* Broadcom switches will accept enabling Broadcom tags on the 1926 * following ports: 5, 7 and 8, any other port is not supported 1927 */ 1928 switch (port) { 1929 case B53_CPU_PORT_25: 1930 case 7: 1931 case B53_CPU_PORT: 1932 return true; 1933 } 1934 1935 return false; 1936 } 1937 1938 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 1939 enum dsa_tag_protocol tag_protocol) 1940 { 1941 bool ret = b53_possible_cpu_port(ds, port); 1942 1943 if (!ret) { 1944 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 1945 port); 1946 return ret; 1947 } 1948 1949 switch (tag_protocol) { 1950 case DSA_TAG_PROTO_BRCM: 1951 case DSA_TAG_PROTO_BRCM_PREPEND: 1952 dev_warn(ds->dev, 1953 "Port %d is stacked to Broadcom tag switch\n", port); 1954 ret = false; 1955 break; 1956 default: 1957 ret = true; 1958 break; 1959 } 1960 1961 return ret; 1962 } 1963 1964 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 1965 enum dsa_tag_protocol mprot) 1966 { 1967 struct b53_device *dev = ds->priv; 1968 1969 /* Older models (5325, 5365) support a different tag format that we do 1970 * not support in net/dsa/tag_brcm.c yet. 1971 */ 1972 if (is5325(dev) || is5365(dev) || 1973 !b53_can_enable_brcm_tags(ds, port, mprot)) { 1974 dev->tag_protocol = DSA_TAG_PROTO_NONE; 1975 goto out; 1976 } 1977 1978 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 1979 * which requires us to use the prepended Broadcom tag type 1980 */ 1981 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 1982 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 1983 goto out; 1984 } 1985 1986 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 1987 out: 1988 return dev->tag_protocol; 1989 } 1990 EXPORT_SYMBOL(b53_get_tag_protocol); 1991 1992 int b53_mirror_add(struct dsa_switch *ds, int port, 1993 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1994 { 1995 struct b53_device *dev = ds->priv; 1996 u16 reg, loc; 1997 1998 if (ingress) 1999 loc = B53_IG_MIR_CTL; 2000 else 2001 loc = B53_EG_MIR_CTL; 2002 2003 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2004 reg |= BIT(port); 2005 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2006 2007 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2008 reg &= ~CAP_PORT_MASK; 2009 reg |= mirror->to_local_port; 2010 reg |= MIRROR_EN; 2011 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2012 2013 return 0; 2014 } 2015 EXPORT_SYMBOL(b53_mirror_add); 2016 2017 void b53_mirror_del(struct dsa_switch *ds, int port, 2018 struct dsa_mall_mirror_tc_entry *mirror) 2019 { 2020 struct b53_device *dev = ds->priv; 2021 bool loc_disable = false, other_loc_disable = false; 2022 u16 reg, loc; 2023 2024 if (mirror->ingress) 2025 loc = B53_IG_MIR_CTL; 2026 else 2027 loc = B53_EG_MIR_CTL; 2028 2029 /* Update the desired ingress/egress register */ 2030 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2031 reg &= ~BIT(port); 2032 if (!(reg & MIRROR_MASK)) 2033 loc_disable = true; 2034 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2035 2036 /* Now look at the other one to know if we can disable mirroring 2037 * entirely 2038 */ 2039 if (mirror->ingress) 2040 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2041 else 2042 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2043 if (!(reg & MIRROR_MASK)) 2044 other_loc_disable = true; 2045 2046 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2047 /* Both no longer have ports, let's disable mirroring */ 2048 if (loc_disable && other_loc_disable) { 2049 reg &= ~MIRROR_EN; 2050 reg &= ~mirror->to_local_port; 2051 } 2052 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2053 } 2054 EXPORT_SYMBOL(b53_mirror_del); 2055 2056 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 2057 { 2058 struct b53_device *dev = ds->priv; 2059 u16 reg; 2060 2061 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 2062 if (enable) 2063 reg |= BIT(port); 2064 else 2065 reg &= ~BIT(port); 2066 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 2067 } 2068 EXPORT_SYMBOL(b53_eee_enable_set); 2069 2070 2071 /* Returns 0 if EEE was not enabled, or 1 otherwise 2072 */ 2073 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2074 { 2075 int ret; 2076 2077 ret = phy_init_eee(phy, 0); 2078 if (ret) 2079 return 0; 2080 2081 b53_eee_enable_set(ds, port, true); 2082 2083 return 1; 2084 } 2085 EXPORT_SYMBOL(b53_eee_init); 2086 2087 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2088 { 2089 struct b53_device *dev = ds->priv; 2090 struct ethtool_eee *p = &dev->ports[port].eee; 2091 u16 reg; 2092 2093 if (is5325(dev) || is5365(dev)) 2094 return -EOPNOTSUPP; 2095 2096 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 2097 e->eee_enabled = p->eee_enabled; 2098 e->eee_active = !!(reg & BIT(port)); 2099 2100 return 0; 2101 } 2102 EXPORT_SYMBOL(b53_get_mac_eee); 2103 2104 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2105 { 2106 struct b53_device *dev = ds->priv; 2107 struct ethtool_eee *p = &dev->ports[port].eee; 2108 2109 if (is5325(dev) || is5365(dev)) 2110 return -EOPNOTSUPP; 2111 2112 p->eee_enabled = e->eee_enabled; 2113 b53_eee_enable_set(ds, port, e->eee_enabled); 2114 2115 return 0; 2116 } 2117 EXPORT_SYMBOL(b53_set_mac_eee); 2118 2119 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2120 { 2121 struct b53_device *dev = ds->priv; 2122 bool enable_jumbo; 2123 bool allow_10_100; 2124 2125 if (is5325(dev) || is5365(dev)) 2126 return -EOPNOTSUPP; 2127 2128 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2129 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2130 2131 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2132 } 2133 2134 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2135 { 2136 return JMS_MAX_SIZE; 2137 } 2138 2139 static const struct dsa_switch_ops b53_switch_ops = { 2140 .get_tag_protocol = b53_get_tag_protocol, 2141 .setup = b53_setup, 2142 .get_strings = b53_get_strings, 2143 .get_ethtool_stats = b53_get_ethtool_stats, 2144 .get_sset_count = b53_get_sset_count, 2145 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2146 .phy_read = b53_phy_read16, 2147 .phy_write = b53_phy_write16, 2148 .adjust_link = b53_adjust_link, 2149 .phylink_validate = b53_phylink_validate, 2150 .phylink_mac_link_state = b53_phylink_mac_link_state, 2151 .phylink_mac_config = b53_phylink_mac_config, 2152 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 2153 .phylink_mac_link_down = b53_phylink_mac_link_down, 2154 .phylink_mac_link_up = b53_phylink_mac_link_up, 2155 .port_enable = b53_enable_port, 2156 .port_disable = b53_disable_port, 2157 .get_mac_eee = b53_get_mac_eee, 2158 .set_mac_eee = b53_set_mac_eee, 2159 .port_bridge_join = b53_br_join, 2160 .port_bridge_leave = b53_br_leave, 2161 .port_stp_state_set = b53_br_set_stp_state, 2162 .port_fast_age = b53_br_fast_age, 2163 .port_egress_floods = b53_br_egress_floods, 2164 .port_vlan_filtering = b53_vlan_filtering, 2165 .port_vlan_prepare = b53_vlan_prepare, 2166 .port_vlan_add = b53_vlan_add, 2167 .port_vlan_del = b53_vlan_del, 2168 .port_fdb_dump = b53_fdb_dump, 2169 .port_fdb_add = b53_fdb_add, 2170 .port_fdb_del = b53_fdb_del, 2171 .port_mirror_add = b53_mirror_add, 2172 .port_mirror_del = b53_mirror_del, 2173 .port_mdb_prepare = b53_mdb_prepare, 2174 .port_mdb_add = b53_mdb_add, 2175 .port_mdb_del = b53_mdb_del, 2176 .port_max_mtu = b53_get_max_mtu, 2177 .port_change_mtu = b53_change_mtu, 2178 }; 2179 2180 struct b53_chip_data { 2181 u32 chip_id; 2182 const char *dev_name; 2183 u16 vlans; 2184 u16 enabled_ports; 2185 u8 cpu_port; 2186 u8 vta_regs[3]; 2187 u8 arl_bins; 2188 u16 arl_buckets; 2189 u8 duplex_reg; 2190 u8 jumbo_pm_reg; 2191 u8 jumbo_size_reg; 2192 }; 2193 2194 #define B53_VTA_REGS \ 2195 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2196 #define B53_VTA_REGS_9798 \ 2197 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2198 #define B53_VTA_REGS_63XX \ 2199 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2200 2201 static const struct b53_chip_data b53_switch_chips[] = { 2202 { 2203 .chip_id = BCM5325_DEVICE_ID, 2204 .dev_name = "BCM5325", 2205 .vlans = 16, 2206 .enabled_ports = 0x1f, 2207 .arl_bins = 2, 2208 .arl_buckets = 1024, 2209 .cpu_port = B53_CPU_PORT_25, 2210 .duplex_reg = B53_DUPLEX_STAT_FE, 2211 }, 2212 { 2213 .chip_id = BCM5365_DEVICE_ID, 2214 .dev_name = "BCM5365", 2215 .vlans = 256, 2216 .enabled_ports = 0x1f, 2217 .arl_bins = 2, 2218 .arl_buckets = 1024, 2219 .cpu_port = B53_CPU_PORT_25, 2220 .duplex_reg = B53_DUPLEX_STAT_FE, 2221 }, 2222 { 2223 .chip_id = BCM5389_DEVICE_ID, 2224 .dev_name = "BCM5389", 2225 .vlans = 4096, 2226 .enabled_ports = 0x1f, 2227 .arl_bins = 4, 2228 .arl_buckets = 1024, 2229 .cpu_port = B53_CPU_PORT, 2230 .vta_regs = B53_VTA_REGS, 2231 .duplex_reg = B53_DUPLEX_STAT_GE, 2232 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2233 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2234 }, 2235 { 2236 .chip_id = BCM5395_DEVICE_ID, 2237 .dev_name = "BCM5395", 2238 .vlans = 4096, 2239 .enabled_ports = 0x1f, 2240 .arl_bins = 4, 2241 .arl_buckets = 1024, 2242 .cpu_port = B53_CPU_PORT, 2243 .vta_regs = B53_VTA_REGS, 2244 .duplex_reg = B53_DUPLEX_STAT_GE, 2245 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2246 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2247 }, 2248 { 2249 .chip_id = BCM5397_DEVICE_ID, 2250 .dev_name = "BCM5397", 2251 .vlans = 4096, 2252 .enabled_ports = 0x1f, 2253 .arl_bins = 4, 2254 .arl_buckets = 1024, 2255 .cpu_port = B53_CPU_PORT, 2256 .vta_regs = B53_VTA_REGS_9798, 2257 .duplex_reg = B53_DUPLEX_STAT_GE, 2258 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2259 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2260 }, 2261 { 2262 .chip_id = BCM5398_DEVICE_ID, 2263 .dev_name = "BCM5398", 2264 .vlans = 4096, 2265 .enabled_ports = 0x7f, 2266 .arl_bins = 4, 2267 .arl_buckets = 1024, 2268 .cpu_port = B53_CPU_PORT, 2269 .vta_regs = B53_VTA_REGS_9798, 2270 .duplex_reg = B53_DUPLEX_STAT_GE, 2271 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2272 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2273 }, 2274 { 2275 .chip_id = BCM53115_DEVICE_ID, 2276 .dev_name = "BCM53115", 2277 .vlans = 4096, 2278 .enabled_ports = 0x1f, 2279 .arl_bins = 4, 2280 .arl_buckets = 1024, 2281 .vta_regs = B53_VTA_REGS, 2282 .cpu_port = B53_CPU_PORT, 2283 .duplex_reg = B53_DUPLEX_STAT_GE, 2284 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2285 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2286 }, 2287 { 2288 .chip_id = BCM53125_DEVICE_ID, 2289 .dev_name = "BCM53125", 2290 .vlans = 4096, 2291 .enabled_ports = 0xff, 2292 .arl_bins = 4, 2293 .arl_buckets = 1024, 2294 .cpu_port = B53_CPU_PORT, 2295 .vta_regs = B53_VTA_REGS, 2296 .duplex_reg = B53_DUPLEX_STAT_GE, 2297 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2298 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2299 }, 2300 { 2301 .chip_id = BCM53128_DEVICE_ID, 2302 .dev_name = "BCM53128", 2303 .vlans = 4096, 2304 .enabled_ports = 0x1ff, 2305 .arl_bins = 4, 2306 .arl_buckets = 1024, 2307 .cpu_port = B53_CPU_PORT, 2308 .vta_regs = B53_VTA_REGS, 2309 .duplex_reg = B53_DUPLEX_STAT_GE, 2310 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2311 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2312 }, 2313 { 2314 .chip_id = BCM63XX_DEVICE_ID, 2315 .dev_name = "BCM63xx", 2316 .vlans = 4096, 2317 .enabled_ports = 0, /* pdata must provide them */ 2318 .arl_bins = 4, 2319 .arl_buckets = 1024, 2320 .cpu_port = B53_CPU_PORT, 2321 .vta_regs = B53_VTA_REGS_63XX, 2322 .duplex_reg = B53_DUPLEX_STAT_63XX, 2323 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2324 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2325 }, 2326 { 2327 .chip_id = BCM53010_DEVICE_ID, 2328 .dev_name = "BCM53010", 2329 .vlans = 4096, 2330 .enabled_ports = 0x1f, 2331 .arl_bins = 4, 2332 .arl_buckets = 1024, 2333 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2334 .vta_regs = B53_VTA_REGS, 2335 .duplex_reg = B53_DUPLEX_STAT_GE, 2336 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2337 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2338 }, 2339 { 2340 .chip_id = BCM53011_DEVICE_ID, 2341 .dev_name = "BCM53011", 2342 .vlans = 4096, 2343 .enabled_ports = 0x1bf, 2344 .arl_bins = 4, 2345 .arl_buckets = 1024, 2346 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2347 .vta_regs = B53_VTA_REGS, 2348 .duplex_reg = B53_DUPLEX_STAT_GE, 2349 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2350 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2351 }, 2352 { 2353 .chip_id = BCM53012_DEVICE_ID, 2354 .dev_name = "BCM53012", 2355 .vlans = 4096, 2356 .enabled_ports = 0x1bf, 2357 .arl_bins = 4, 2358 .arl_buckets = 1024, 2359 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2360 .vta_regs = B53_VTA_REGS, 2361 .duplex_reg = B53_DUPLEX_STAT_GE, 2362 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2363 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2364 }, 2365 { 2366 .chip_id = BCM53018_DEVICE_ID, 2367 .dev_name = "BCM53018", 2368 .vlans = 4096, 2369 .enabled_ports = 0x1f, 2370 .arl_bins = 4, 2371 .arl_buckets = 1024, 2372 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2373 .vta_regs = B53_VTA_REGS, 2374 .duplex_reg = B53_DUPLEX_STAT_GE, 2375 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2376 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2377 }, 2378 { 2379 .chip_id = BCM53019_DEVICE_ID, 2380 .dev_name = "BCM53019", 2381 .vlans = 4096, 2382 .enabled_ports = 0x1f, 2383 .arl_bins = 4, 2384 .arl_buckets = 1024, 2385 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2386 .vta_regs = B53_VTA_REGS, 2387 .duplex_reg = B53_DUPLEX_STAT_GE, 2388 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2389 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2390 }, 2391 { 2392 .chip_id = BCM58XX_DEVICE_ID, 2393 .dev_name = "BCM585xx/586xx/88312", 2394 .vlans = 4096, 2395 .enabled_ports = 0x1ff, 2396 .arl_bins = 4, 2397 .arl_buckets = 1024, 2398 .cpu_port = B53_CPU_PORT, 2399 .vta_regs = B53_VTA_REGS, 2400 .duplex_reg = B53_DUPLEX_STAT_GE, 2401 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2402 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2403 }, 2404 { 2405 .chip_id = BCM583XX_DEVICE_ID, 2406 .dev_name = "BCM583xx/11360", 2407 .vlans = 4096, 2408 .enabled_ports = 0x103, 2409 .arl_bins = 4, 2410 .arl_buckets = 1024, 2411 .cpu_port = B53_CPU_PORT, 2412 .vta_regs = B53_VTA_REGS, 2413 .duplex_reg = B53_DUPLEX_STAT_GE, 2414 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2415 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2416 }, 2417 { 2418 .chip_id = BCM7445_DEVICE_ID, 2419 .dev_name = "BCM7445", 2420 .vlans = 4096, 2421 .enabled_ports = 0x1ff, 2422 .arl_bins = 4, 2423 .arl_buckets = 1024, 2424 .cpu_port = B53_CPU_PORT, 2425 .vta_regs = B53_VTA_REGS, 2426 .duplex_reg = B53_DUPLEX_STAT_GE, 2427 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2428 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2429 }, 2430 { 2431 .chip_id = BCM7278_DEVICE_ID, 2432 .dev_name = "BCM7278", 2433 .vlans = 4096, 2434 .enabled_ports = 0x1ff, 2435 .arl_bins = 4, 2436 .arl_buckets = 256, 2437 .cpu_port = B53_CPU_PORT, 2438 .vta_regs = B53_VTA_REGS, 2439 .duplex_reg = B53_DUPLEX_STAT_GE, 2440 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2441 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2442 }, 2443 }; 2444 2445 static int b53_switch_init(struct b53_device *dev) 2446 { 2447 unsigned int i; 2448 int ret; 2449 2450 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2451 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2452 2453 if (chip->chip_id == dev->chip_id) { 2454 if (!dev->enabled_ports) 2455 dev->enabled_ports = chip->enabled_ports; 2456 dev->name = chip->dev_name; 2457 dev->duplex_reg = chip->duplex_reg; 2458 dev->vta_regs[0] = chip->vta_regs[0]; 2459 dev->vta_regs[1] = chip->vta_regs[1]; 2460 dev->vta_regs[2] = chip->vta_regs[2]; 2461 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2462 dev->cpu_port = chip->cpu_port; 2463 dev->num_vlans = chip->vlans; 2464 dev->num_arl_bins = chip->arl_bins; 2465 dev->num_arl_buckets = chip->arl_buckets; 2466 break; 2467 } 2468 } 2469 2470 /* check which BCM5325x version we have */ 2471 if (is5325(dev)) { 2472 u8 vc4; 2473 2474 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2475 2476 /* check reserved bits */ 2477 switch (vc4 & 3) { 2478 case 1: 2479 /* BCM5325E */ 2480 break; 2481 case 3: 2482 /* BCM5325F - do not use port 4 */ 2483 dev->enabled_ports &= ~BIT(4); 2484 break; 2485 default: 2486 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2487 #ifndef CONFIG_BCM47XX 2488 /* BCM5325M */ 2489 return -EINVAL; 2490 #else 2491 break; 2492 #endif 2493 } 2494 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2495 u64 strap_value; 2496 2497 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2498 /* use second IMP port if GMII is enabled */ 2499 if (strap_value & SV_GMII_CTRL_115) 2500 dev->cpu_port = 5; 2501 } 2502 2503 /* cpu port is always last */ 2504 dev->num_ports = dev->cpu_port + 1; 2505 dev->enabled_ports |= BIT(dev->cpu_port); 2506 2507 /* Include non standard CPU port built-in PHYs to be probed */ 2508 if (is539x(dev) || is531x5(dev)) { 2509 for (i = 0; i < dev->num_ports; i++) { 2510 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2511 !b53_possible_cpu_port(dev->ds, i)) 2512 dev->ds->phys_mii_mask |= BIT(i); 2513 } 2514 } 2515 2516 dev->ports = devm_kcalloc(dev->dev, 2517 dev->num_ports, sizeof(struct b53_port), 2518 GFP_KERNEL); 2519 if (!dev->ports) 2520 return -ENOMEM; 2521 2522 dev->vlans = devm_kcalloc(dev->dev, 2523 dev->num_vlans, sizeof(struct b53_vlan), 2524 GFP_KERNEL); 2525 if (!dev->vlans) 2526 return -ENOMEM; 2527 2528 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2529 if (dev->reset_gpio >= 0) { 2530 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2531 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2532 if (ret) 2533 return ret; 2534 } 2535 2536 return 0; 2537 } 2538 2539 struct b53_device *b53_switch_alloc(struct device *base, 2540 const struct b53_io_ops *ops, 2541 void *priv) 2542 { 2543 struct dsa_switch *ds; 2544 struct b53_device *dev; 2545 2546 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2547 if (!ds) 2548 return NULL; 2549 2550 ds->dev = base; 2551 ds->num_ports = DSA_MAX_PORTS; 2552 2553 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2554 if (!dev) 2555 return NULL; 2556 2557 ds->priv = dev; 2558 dev->dev = base; 2559 2560 dev->ds = ds; 2561 dev->priv = priv; 2562 dev->ops = ops; 2563 ds->ops = &b53_switch_ops; 2564 mutex_init(&dev->reg_mutex); 2565 mutex_init(&dev->stats_mutex); 2566 2567 return dev; 2568 } 2569 EXPORT_SYMBOL(b53_switch_alloc); 2570 2571 int b53_switch_detect(struct b53_device *dev) 2572 { 2573 u32 id32; 2574 u16 tmp; 2575 u8 id8; 2576 int ret; 2577 2578 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2579 if (ret) 2580 return ret; 2581 2582 switch (id8) { 2583 case 0: 2584 /* BCM5325 and BCM5365 do not have this register so reads 2585 * return 0. But the read operation did succeed, so assume this 2586 * is one of them. 2587 * 2588 * Next check if we can write to the 5325's VTA register; for 2589 * 5365 it is read only. 2590 */ 2591 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2592 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2593 2594 if (tmp == 0xf) 2595 dev->chip_id = BCM5325_DEVICE_ID; 2596 else 2597 dev->chip_id = BCM5365_DEVICE_ID; 2598 break; 2599 case BCM5389_DEVICE_ID: 2600 case BCM5395_DEVICE_ID: 2601 case BCM5397_DEVICE_ID: 2602 case BCM5398_DEVICE_ID: 2603 dev->chip_id = id8; 2604 break; 2605 default: 2606 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2607 if (ret) 2608 return ret; 2609 2610 switch (id32) { 2611 case BCM53115_DEVICE_ID: 2612 case BCM53125_DEVICE_ID: 2613 case BCM53128_DEVICE_ID: 2614 case BCM53010_DEVICE_ID: 2615 case BCM53011_DEVICE_ID: 2616 case BCM53012_DEVICE_ID: 2617 case BCM53018_DEVICE_ID: 2618 case BCM53019_DEVICE_ID: 2619 dev->chip_id = id32; 2620 break; 2621 default: 2622 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 2623 id8, id32); 2624 return -ENODEV; 2625 } 2626 } 2627 2628 if (dev->chip_id == BCM5325_DEVICE_ID) 2629 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2630 &dev->core_rev); 2631 else 2632 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2633 &dev->core_rev); 2634 } 2635 EXPORT_SYMBOL(b53_switch_detect); 2636 2637 int b53_switch_register(struct b53_device *dev) 2638 { 2639 int ret; 2640 2641 if (dev->pdata) { 2642 dev->chip_id = dev->pdata->chip_id; 2643 dev->enabled_ports = dev->pdata->enabled_ports; 2644 } 2645 2646 if (!dev->chip_id && b53_switch_detect(dev)) 2647 return -EINVAL; 2648 2649 ret = b53_switch_init(dev); 2650 if (ret) 2651 return ret; 2652 2653 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 2654 2655 return dsa_register_switch(dev->ds); 2656 } 2657 EXPORT_SYMBOL(b53_switch_register); 2658 2659 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2660 MODULE_DESCRIPTION("B53 switch library"); 2661 MODULE_LICENSE("Dual BSD/GPL"); 2662