1 /* Xilinx CAN device driver 2 * 3 * Copyright (C) 2012 - 2014 Xilinx, Inc. 4 * Copyright (C) 2009 PetaLogix. All rights reserved. 5 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy 6 * 7 * Description: 8 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller. 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation, either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/clk.h> 21 #include <linux/errno.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/netdevice.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/platform_device.h> 31 #include <linux/skbuff.h> 32 #include <linux/spinlock.h> 33 #include <linux/string.h> 34 #include <linux/types.h> 35 #include <linux/can/dev.h> 36 #include <linux/can/error.h> 37 #include <linux/can/led.h> 38 #include <linux/pm_runtime.h> 39 40 #define DRIVER_NAME "xilinx_can" 41 42 /* CAN registers set */ 43 enum xcan_reg { 44 XCAN_SRR_OFFSET = 0x00, /* Software reset */ 45 XCAN_MSR_OFFSET = 0x04, /* Mode select */ 46 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */ 47 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */ 48 XCAN_ECR_OFFSET = 0x10, /* Error counter */ 49 XCAN_ESR_OFFSET = 0x14, /* Error status */ 50 XCAN_SR_OFFSET = 0x18, /* Status */ 51 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */ 52 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */ 53 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */ 54 55 /* not on CAN FD cores */ 56 XCAN_TXFIFO_OFFSET = 0x30, /* TX FIFO base */ 57 XCAN_RXFIFO_OFFSET = 0x50, /* RX FIFO base */ 58 XCAN_AFR_OFFSET = 0x60, /* Acceptance Filter */ 59 60 /* only on CAN FD cores */ 61 XCAN_TRR_OFFSET = 0x0090, /* TX Buffer Ready Request */ 62 XCAN_AFR_EXT_OFFSET = 0x00E0, /* Acceptance Filter */ 63 XCAN_FSR_OFFSET = 0x00E8, /* RX FIFO Status */ 64 XCAN_TXMSG_BASE_OFFSET = 0x0100, /* TX Message Space */ 65 XCAN_RXMSG_BASE_OFFSET = 0x1100, /* RX Message Space */ 66 }; 67 68 #define XCAN_FRAME_ID_OFFSET(frame_base) ((frame_base) + 0x00) 69 #define XCAN_FRAME_DLC_OFFSET(frame_base) ((frame_base) + 0x04) 70 #define XCAN_FRAME_DW1_OFFSET(frame_base) ((frame_base) + 0x08) 71 #define XCAN_FRAME_DW2_OFFSET(frame_base) ((frame_base) + 0x0C) 72 73 #define XCAN_CANFD_FRAME_SIZE 0x48 74 #define XCAN_TXMSG_FRAME_OFFSET(n) (XCAN_TXMSG_BASE_OFFSET + \ 75 XCAN_CANFD_FRAME_SIZE * (n)) 76 #define XCAN_RXMSG_FRAME_OFFSET(n) (XCAN_RXMSG_BASE_OFFSET + \ 77 XCAN_CANFD_FRAME_SIZE * (n)) 78 79 /* the single TX mailbox used by this driver on CAN FD HW */ 80 #define XCAN_TX_MAILBOX_IDX 0 81 82 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */ 83 #define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */ 84 #define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */ 85 #define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */ 86 #define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */ 87 #define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */ 88 #define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */ 89 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */ 90 #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */ 91 #define XCAN_BTR_SJW_MASK_CANFD 0x000F0000 /* Synchronous jump width */ 92 #define XCAN_BTR_TS2_MASK_CANFD 0x00000F00 /* Time segment 2 */ 93 #define XCAN_BTR_TS1_MASK_CANFD 0x0000003F /* Time segment 1 */ 94 #define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */ 95 #define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */ 96 #define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */ 97 #define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */ 98 #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */ 99 #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */ 100 #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */ 101 #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */ 102 #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */ 103 #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */ 104 #define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */ 105 #define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */ 106 #define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */ 107 #define XCAN_IXR_RXMNF_MASK 0x00020000 /* RX match not finished */ 108 #define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */ 109 #define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */ 110 #define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */ 111 #define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */ 112 #define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */ 113 #define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */ 114 #define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */ 115 #define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */ 116 #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */ 117 #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */ 118 #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */ 119 #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ 120 #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ 121 #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ 122 #define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */ 123 #define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */ 124 #define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */ 125 #define XCAN_FSR_FL_MASK 0x00003F00 /* RX Fill Level */ 126 #define XCAN_FSR_IRI_MASK 0x00000080 /* RX Increment Read Index */ 127 #define XCAN_FSR_RI_MASK 0x0000001F /* RX Read Index */ 128 129 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */ 130 #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */ 131 #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */ 132 #define XCAN_BTR_SJW_SHIFT_CANFD 16 /* Synchronous jump width */ 133 #define XCAN_BTR_TS2_SHIFT_CANFD 8 /* Time segment 2 */ 134 #define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */ 135 #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */ 136 #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */ 137 #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */ 138 139 /* CAN frame length constants */ 140 #define XCAN_FRAME_MAX_DATA_LEN 8 141 #define XCAN_TIMEOUT (1 * HZ) 142 143 /* TX-FIFO-empty interrupt available */ 144 #define XCAN_FLAG_TXFEMP 0x0001 145 /* RX Match Not Finished interrupt available */ 146 #define XCAN_FLAG_RXMNF 0x0002 147 /* Extended acceptance filters with control at 0xE0 */ 148 #define XCAN_FLAG_EXT_FILTERS 0x0004 149 /* TX mailboxes instead of TX FIFO */ 150 #define XCAN_FLAG_TX_MAILBOXES 0x0008 151 /* RX FIFO with each buffer in separate registers at 0x1100 152 * instead of the regular FIFO at 0x50 153 */ 154 #define XCAN_FLAG_RX_FIFO_MULTI 0x0010 155 156 struct xcan_devtype_data { 157 unsigned int flags; 158 const struct can_bittiming_const *bittiming_const; 159 const char *bus_clk_name; 160 unsigned int btr_ts2_shift; 161 unsigned int btr_sjw_shift; 162 }; 163 164 /** 165 * struct xcan_priv - This definition define CAN driver instance 166 * @can: CAN private data structure. 167 * @tx_lock: Lock for synchronizing TX interrupt handling 168 * @tx_head: Tx CAN packets ready to send on the queue 169 * @tx_tail: Tx CAN packets successfully sended on the queue 170 * @tx_max: Maximum number packets the driver can send 171 * @napi: NAPI structure 172 * @read_reg: For reading data from CAN registers 173 * @write_reg: For writing data to CAN registers 174 * @dev: Network device data structure 175 * @reg_base: Ioremapped address to registers 176 * @irq_flags: For request_irq() 177 * @bus_clk: Pointer to struct clk 178 * @can_clk: Pointer to struct clk 179 * @devtype: Device type specific constants 180 */ 181 struct xcan_priv { 182 struct can_priv can; 183 spinlock_t tx_lock; 184 unsigned int tx_head; 185 unsigned int tx_tail; 186 unsigned int tx_max; 187 struct napi_struct napi; 188 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg); 189 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, 190 u32 val); 191 struct device *dev; 192 void __iomem *reg_base; 193 unsigned long irq_flags; 194 struct clk *bus_clk; 195 struct clk *can_clk; 196 struct xcan_devtype_data devtype; 197 }; 198 199 /* CAN Bittiming constants as per Xilinx CAN specs */ 200 static const struct can_bittiming_const xcan_bittiming_const = { 201 .name = DRIVER_NAME, 202 .tseg1_min = 1, 203 .tseg1_max = 16, 204 .tseg2_min = 1, 205 .tseg2_max = 8, 206 .sjw_max = 4, 207 .brp_min = 1, 208 .brp_max = 256, 209 .brp_inc = 1, 210 }; 211 212 static const struct can_bittiming_const xcan_bittiming_const_canfd = { 213 .name = DRIVER_NAME, 214 .tseg1_min = 1, 215 .tseg1_max = 64, 216 .tseg2_min = 1, 217 .tseg2_max = 16, 218 .sjw_max = 16, 219 .brp_min = 1, 220 .brp_max = 256, 221 .brp_inc = 1, 222 }; 223 224 /** 225 * xcan_write_reg_le - Write a value to the device register little endian 226 * @priv: Driver private data structure 227 * @reg: Register offset 228 * @val: Value to write at the Register offset 229 * 230 * Write data to the paricular CAN register 231 */ 232 static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg, 233 u32 val) 234 { 235 iowrite32(val, priv->reg_base + reg); 236 } 237 238 /** 239 * xcan_read_reg_le - Read a value from the device register little endian 240 * @priv: Driver private data structure 241 * @reg: Register offset 242 * 243 * Read data from the particular CAN register 244 * Return: value read from the CAN register 245 */ 246 static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg) 247 { 248 return ioread32(priv->reg_base + reg); 249 } 250 251 /** 252 * xcan_write_reg_be - Write a value to the device register big endian 253 * @priv: Driver private data structure 254 * @reg: Register offset 255 * @val: Value to write at the Register offset 256 * 257 * Write data to the paricular CAN register 258 */ 259 static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg, 260 u32 val) 261 { 262 iowrite32be(val, priv->reg_base + reg); 263 } 264 265 /** 266 * xcan_read_reg_be - Read a value from the device register big endian 267 * @priv: Driver private data structure 268 * @reg: Register offset 269 * 270 * Read data from the particular CAN register 271 * Return: value read from the CAN register 272 */ 273 static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg) 274 { 275 return ioread32be(priv->reg_base + reg); 276 } 277 278 /** 279 * xcan_rx_int_mask - Get the mask for the receive interrupt 280 * @priv: Driver private data structure 281 * 282 * Return: The receive interrupt mask used by the driver on this HW 283 */ 284 static u32 xcan_rx_int_mask(const struct xcan_priv *priv) 285 { 286 /* RXNEMP is better suited for our use case as it cannot be cleared 287 * while the FIFO is non-empty, but CAN FD HW does not have it 288 */ 289 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) 290 return XCAN_IXR_RXOK_MASK; 291 else 292 return XCAN_IXR_RXNEMP_MASK; 293 } 294 295 /** 296 * set_reset_mode - Resets the CAN device mode 297 * @ndev: Pointer to net_device structure 298 * 299 * This is the driver reset mode routine.The driver 300 * enters into configuration mode. 301 * 302 * Return: 0 on success and failure value on error 303 */ 304 static int set_reset_mode(struct net_device *ndev) 305 { 306 struct xcan_priv *priv = netdev_priv(ndev); 307 unsigned long timeout; 308 309 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); 310 311 timeout = jiffies + XCAN_TIMEOUT; 312 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { 313 if (time_after(jiffies, timeout)) { 314 netdev_warn(ndev, "timed out for config mode\n"); 315 return -ETIMEDOUT; 316 } 317 usleep_range(500, 10000); 318 } 319 320 /* reset clears FIFOs */ 321 priv->tx_head = 0; 322 priv->tx_tail = 0; 323 324 return 0; 325 } 326 327 /** 328 * xcan_set_bittiming - CAN set bit timing routine 329 * @ndev: Pointer to net_device structure 330 * 331 * This is the driver set bittiming routine. 332 * Return: 0 on success and failure value on error 333 */ 334 static int xcan_set_bittiming(struct net_device *ndev) 335 { 336 struct xcan_priv *priv = netdev_priv(ndev); 337 struct can_bittiming *bt = &priv->can.bittiming; 338 u32 btr0, btr1; 339 u32 is_config_mode; 340 341 /* Check whether Xilinx CAN is in configuration mode. 342 * It cannot set bit timing if Xilinx CAN is not in configuration mode. 343 */ 344 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & 345 XCAN_SR_CONFIG_MASK; 346 if (!is_config_mode) { 347 netdev_alert(ndev, 348 "BUG! Cannot set bittiming - CAN is not in config mode\n"); 349 return -EPERM; 350 } 351 352 /* Setting Baud Rate prescalar value in BRPR Register */ 353 btr0 = (bt->brp - 1); 354 355 /* Setting Time Segment 1 in BTR Register */ 356 btr1 = (bt->prop_seg + bt->phase_seg1 - 1); 357 358 /* Setting Time Segment 2 in BTR Register */ 359 btr1 |= (bt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; 360 361 /* Setting Synchronous jump width in BTR Register */ 362 btr1 |= (bt->sjw - 1) << priv->devtype.btr_sjw_shift; 363 364 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); 365 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); 366 367 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n", 368 priv->read_reg(priv, XCAN_BRPR_OFFSET), 369 priv->read_reg(priv, XCAN_BTR_OFFSET)); 370 371 return 0; 372 } 373 374 /** 375 * xcan_chip_start - This the drivers start routine 376 * @ndev: Pointer to net_device structure 377 * 378 * This is the drivers start routine. 379 * Based on the State of the CAN device it puts 380 * the CAN device into a proper mode. 381 * 382 * Return: 0 on success and failure value on error 383 */ 384 static int xcan_chip_start(struct net_device *ndev) 385 { 386 struct xcan_priv *priv = netdev_priv(ndev); 387 u32 reg_msr, reg_sr_mask; 388 int err; 389 unsigned long timeout; 390 u32 ier; 391 392 /* Check if it is in reset mode */ 393 err = set_reset_mode(ndev); 394 if (err < 0) 395 return err; 396 397 err = xcan_set_bittiming(ndev); 398 if (err < 0) 399 return err; 400 401 /* Enable interrupts */ 402 ier = XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK | 403 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | 404 XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | 405 XCAN_IXR_ARBLST_MASK | xcan_rx_int_mask(priv); 406 407 if (priv->devtype.flags & XCAN_FLAG_RXMNF) 408 ier |= XCAN_IXR_RXMNF_MASK; 409 410 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 411 412 /* Check whether it is loopback mode or normal mode */ 413 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 414 reg_msr = XCAN_MSR_LBACK_MASK; 415 reg_sr_mask = XCAN_SR_LBACK_MASK; 416 } else { 417 reg_msr = 0x0; 418 reg_sr_mask = XCAN_SR_NORMAL_MASK; 419 } 420 421 /* enable the first extended filter, if any, as cores with extended 422 * filtering default to non-receipt if all filters are disabled 423 */ 424 if (priv->devtype.flags & XCAN_FLAG_EXT_FILTERS) 425 priv->write_reg(priv, XCAN_AFR_EXT_OFFSET, 0x00000001); 426 427 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); 428 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); 429 430 timeout = jiffies + XCAN_TIMEOUT; 431 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) { 432 if (time_after(jiffies, timeout)) { 433 netdev_warn(ndev, 434 "timed out for correct mode\n"); 435 return -ETIMEDOUT; 436 } 437 } 438 netdev_dbg(ndev, "status:#x%08x\n", 439 priv->read_reg(priv, XCAN_SR_OFFSET)); 440 441 priv->can.state = CAN_STATE_ERROR_ACTIVE; 442 return 0; 443 } 444 445 /** 446 * xcan_do_set_mode - This sets the mode of the driver 447 * @ndev: Pointer to net_device structure 448 * @mode: Tells the mode of the driver 449 * 450 * This check the drivers state and calls the 451 * the corresponding modes to set. 452 * 453 * Return: 0 on success and failure value on error 454 */ 455 static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode) 456 { 457 int ret; 458 459 switch (mode) { 460 case CAN_MODE_START: 461 ret = xcan_chip_start(ndev); 462 if (ret < 0) { 463 netdev_err(ndev, "xcan_chip_start failed!\n"); 464 return ret; 465 } 466 netif_wake_queue(ndev); 467 break; 468 default: 469 ret = -EOPNOTSUPP; 470 break; 471 } 472 473 return ret; 474 } 475 476 /** 477 * xcan_write_frame - Write a frame to HW 478 * @skb: sk_buff pointer that contains data to be Txed 479 * @frame_offset: Register offset to write the frame to 480 */ 481 static void xcan_write_frame(struct xcan_priv *priv, struct sk_buff *skb, 482 int frame_offset) 483 { 484 u32 id, dlc, data[2] = {0, 0}; 485 struct can_frame *cf = (struct can_frame *)skb->data; 486 487 /* Watch carefully on the bit sequence */ 488 if (cf->can_id & CAN_EFF_FLAG) { 489 /* Extended CAN ID format */ 490 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) & 491 XCAN_IDR_ID2_MASK; 492 id |= (((cf->can_id & CAN_EFF_MASK) >> 493 (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) << 494 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK; 495 496 /* The substibute remote TX request bit should be "1" 497 * for extended frames as in the Xilinx CAN datasheet 498 */ 499 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK; 500 501 if (cf->can_id & CAN_RTR_FLAG) 502 /* Extended frames remote TX request */ 503 id |= XCAN_IDR_RTR_MASK; 504 } else { 505 /* Standard CAN ID format */ 506 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) & 507 XCAN_IDR_ID1_MASK; 508 509 if (cf->can_id & CAN_RTR_FLAG) 510 /* Standard frames remote TX request */ 511 id |= XCAN_IDR_SRR_MASK; 512 } 513 514 dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT; 515 516 if (cf->can_dlc > 0) 517 data[0] = be32_to_cpup((__be32 *)(cf->data + 0)); 518 if (cf->can_dlc > 4) 519 data[1] = be32_to_cpup((__be32 *)(cf->data + 4)); 520 521 priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id); 522 /* If the CAN frame is RTR frame this write triggers transmission 523 * (not on CAN FD) 524 */ 525 priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc); 526 if (!(cf->can_id & CAN_RTR_FLAG)) { 527 priv->write_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_offset), 528 data[0]); 529 /* If the CAN frame is Standard/Extended frame this 530 * write triggers transmission (not on CAN FD) 531 */ 532 priv->write_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_offset), 533 data[1]); 534 } 535 } 536 537 /** 538 * xcan_start_xmit_fifo - Starts the transmission (FIFO mode) 539 * 540 * Return: 0 on success, -ENOSPC if FIFO is full. 541 */ 542 static int xcan_start_xmit_fifo(struct sk_buff *skb, struct net_device *ndev) 543 { 544 struct xcan_priv *priv = netdev_priv(ndev); 545 unsigned long flags; 546 547 /* Check if the TX buffer is full */ 548 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & 549 XCAN_SR_TXFLL_MASK)) 550 return -ENOSPC; 551 552 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max); 553 554 spin_lock_irqsave(&priv->tx_lock, flags); 555 556 priv->tx_head++; 557 558 xcan_write_frame(priv, skb, XCAN_TXFIFO_OFFSET); 559 560 /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */ 561 if (priv->tx_max > 1) 562 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK); 563 564 /* Check if the TX buffer is full */ 565 if ((priv->tx_head - priv->tx_tail) == priv->tx_max) 566 netif_stop_queue(ndev); 567 568 spin_unlock_irqrestore(&priv->tx_lock, flags); 569 570 return 0; 571 } 572 573 /** 574 * xcan_start_xmit_mailbox - Starts the transmission (mailbox mode) 575 * 576 * Return: 0 on success, -ENOSPC if there is no space 577 */ 578 static int xcan_start_xmit_mailbox(struct sk_buff *skb, struct net_device *ndev) 579 { 580 struct xcan_priv *priv = netdev_priv(ndev); 581 unsigned long flags; 582 583 if (unlikely(priv->read_reg(priv, XCAN_TRR_OFFSET) & 584 BIT(XCAN_TX_MAILBOX_IDX))) 585 return -ENOSPC; 586 587 can_put_echo_skb(skb, ndev, 0); 588 589 spin_lock_irqsave(&priv->tx_lock, flags); 590 591 priv->tx_head++; 592 593 xcan_write_frame(priv, skb, 594 XCAN_TXMSG_FRAME_OFFSET(XCAN_TX_MAILBOX_IDX)); 595 596 /* Mark buffer as ready for transmit */ 597 priv->write_reg(priv, XCAN_TRR_OFFSET, BIT(XCAN_TX_MAILBOX_IDX)); 598 599 netif_stop_queue(ndev); 600 601 spin_unlock_irqrestore(&priv->tx_lock, flags); 602 603 return 0; 604 } 605 606 /** 607 * xcan_start_xmit - Starts the transmission 608 * @skb: sk_buff pointer that contains data to be Txed 609 * @ndev: Pointer to net_device structure 610 * 611 * This function is invoked from upper layers to initiate transmission. 612 * 613 * Return: NETDEV_TX_OK on success and NETDEV_TX_BUSY when the tx queue is full 614 */ 615 static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev) 616 { 617 struct xcan_priv *priv = netdev_priv(ndev); 618 int ret; 619 620 if (can_dropped_invalid_skb(ndev, skb)) 621 return NETDEV_TX_OK; 622 623 if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) 624 ret = xcan_start_xmit_mailbox(skb, ndev); 625 else 626 ret = xcan_start_xmit_fifo(skb, ndev); 627 628 if (ret < 0) { 629 netdev_err(ndev, "BUG!, TX full when queue awake!\n"); 630 netif_stop_queue(ndev); 631 return NETDEV_TX_BUSY; 632 } 633 634 return NETDEV_TX_OK; 635 } 636 637 /** 638 * xcan_rx - Is called from CAN isr to complete the received 639 * frame processing 640 * @ndev: Pointer to net_device structure 641 * @frame_base: Register offset to the frame to be read 642 * 643 * This function is invoked from the CAN isr(poll) to process the Rx frames. It 644 * does minimal processing and invokes "netif_receive_skb" to complete further 645 * processing. 646 * Return: 1 on success and 0 on failure. 647 */ 648 static int xcan_rx(struct net_device *ndev, int frame_base) 649 { 650 struct xcan_priv *priv = netdev_priv(ndev); 651 struct net_device_stats *stats = &ndev->stats; 652 struct can_frame *cf; 653 struct sk_buff *skb; 654 u32 id_xcan, dlc, data[2] = {0, 0}; 655 656 skb = alloc_can_skb(ndev, &cf); 657 if (unlikely(!skb)) { 658 stats->rx_dropped++; 659 return 0; 660 } 661 662 /* Read a frame from Xilinx zynq CANPS */ 663 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); 664 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)) >> 665 XCAN_DLCR_DLC_SHIFT; 666 667 /* Change Xilinx CAN data length format to socketCAN data format */ 668 cf->can_dlc = get_can_dlc(dlc); 669 670 /* Change Xilinx CAN ID format to socketCAN ID format */ 671 if (id_xcan & XCAN_IDR_IDE_MASK) { 672 /* The received frame is an Extended format frame */ 673 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; 674 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> 675 XCAN_IDR_ID2_SHIFT; 676 cf->can_id |= CAN_EFF_FLAG; 677 if (id_xcan & XCAN_IDR_RTR_MASK) 678 cf->can_id |= CAN_RTR_FLAG; 679 } else { 680 /* The received frame is a standard format frame */ 681 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 682 XCAN_IDR_ID1_SHIFT; 683 if (id_xcan & XCAN_IDR_SRR_MASK) 684 cf->can_id |= CAN_RTR_FLAG; 685 } 686 687 /* DW1/DW2 must always be read to remove message from RXFIFO */ 688 data[0] = priv->read_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_base)); 689 data[1] = priv->read_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_base)); 690 691 if (!(cf->can_id & CAN_RTR_FLAG)) { 692 /* Change Xilinx CAN data format to socketCAN data format */ 693 if (cf->can_dlc > 0) 694 *(__be32 *)(cf->data) = cpu_to_be32(data[0]); 695 if (cf->can_dlc > 4) 696 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]); 697 } 698 699 stats->rx_bytes += cf->can_dlc; 700 stats->rx_packets++; 701 netif_receive_skb(skb); 702 703 return 1; 704 } 705 706 /** 707 * xcan_current_error_state - Get current error state from HW 708 * @ndev: Pointer to net_device structure 709 * 710 * Checks the current CAN error state from the HW. Note that this 711 * only checks for ERROR_PASSIVE and ERROR_WARNING. 712 * 713 * Return: 714 * ERROR_PASSIVE or ERROR_WARNING if either is active, ERROR_ACTIVE 715 * otherwise. 716 */ 717 static enum can_state xcan_current_error_state(struct net_device *ndev) 718 { 719 struct xcan_priv *priv = netdev_priv(ndev); 720 u32 status = priv->read_reg(priv, XCAN_SR_OFFSET); 721 722 if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) 723 return CAN_STATE_ERROR_PASSIVE; 724 else if (status & XCAN_SR_ERRWRN_MASK) 725 return CAN_STATE_ERROR_WARNING; 726 else 727 return CAN_STATE_ERROR_ACTIVE; 728 } 729 730 /** 731 * xcan_set_error_state - Set new CAN error state 732 * @ndev: Pointer to net_device structure 733 * @new_state: The new CAN state to be set 734 * @cf: Error frame to be populated or NULL 735 * 736 * Set new CAN error state for the device, updating statistics and 737 * populating the error frame if given. 738 */ 739 static void xcan_set_error_state(struct net_device *ndev, 740 enum can_state new_state, 741 struct can_frame *cf) 742 { 743 struct xcan_priv *priv = netdev_priv(ndev); 744 u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET); 745 u32 txerr = ecr & XCAN_ECR_TEC_MASK; 746 u32 rxerr = (ecr & XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT; 747 enum can_state tx_state = txerr >= rxerr ? new_state : 0; 748 enum can_state rx_state = txerr <= rxerr ? new_state : 0; 749 750 /* non-ERROR states are handled elsewhere */ 751 if (WARN_ON(new_state > CAN_STATE_ERROR_PASSIVE)) 752 return; 753 754 can_change_state(ndev, cf, tx_state, rx_state); 755 756 if (cf) { 757 cf->data[6] = txerr; 758 cf->data[7] = rxerr; 759 } 760 } 761 762 /** 763 * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX 764 * @ndev: Pointer to net_device structure 765 * 766 * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if 767 * the performed RX/TX has caused it to drop to a lesser state and set 768 * the interface state accordingly. 769 */ 770 static void xcan_update_error_state_after_rxtx(struct net_device *ndev) 771 { 772 struct xcan_priv *priv = netdev_priv(ndev); 773 enum can_state old_state = priv->can.state; 774 enum can_state new_state; 775 776 /* changing error state due to successful frame RX/TX can only 777 * occur from these states 778 */ 779 if (old_state != CAN_STATE_ERROR_WARNING && 780 old_state != CAN_STATE_ERROR_PASSIVE) 781 return; 782 783 new_state = xcan_current_error_state(ndev); 784 785 if (new_state != old_state) { 786 struct sk_buff *skb; 787 struct can_frame *cf; 788 789 skb = alloc_can_err_skb(ndev, &cf); 790 791 xcan_set_error_state(ndev, new_state, skb ? cf : NULL); 792 793 if (skb) { 794 struct net_device_stats *stats = &ndev->stats; 795 796 stats->rx_packets++; 797 stats->rx_bytes += cf->can_dlc; 798 netif_rx(skb); 799 } 800 } 801 } 802 803 /** 804 * xcan_err_interrupt - error frame Isr 805 * @ndev: net_device pointer 806 * @isr: interrupt status register value 807 * 808 * This is the CAN error interrupt and it will 809 * check the the type of error and forward the error 810 * frame to upper layers. 811 */ 812 static void xcan_err_interrupt(struct net_device *ndev, u32 isr) 813 { 814 struct xcan_priv *priv = netdev_priv(ndev); 815 struct net_device_stats *stats = &ndev->stats; 816 struct can_frame *cf; 817 struct sk_buff *skb; 818 u32 err_status; 819 820 skb = alloc_can_err_skb(ndev, &cf); 821 822 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET); 823 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); 824 825 if (isr & XCAN_IXR_BSOFF_MASK) { 826 priv->can.state = CAN_STATE_BUS_OFF; 827 priv->can.can_stats.bus_off++; 828 /* Leave device in Config Mode in bus-off state */ 829 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); 830 can_bus_off(ndev); 831 if (skb) 832 cf->can_id |= CAN_ERR_BUSOFF; 833 } else { 834 enum can_state new_state = xcan_current_error_state(ndev); 835 836 if (new_state != priv->can.state) 837 xcan_set_error_state(ndev, new_state, skb ? cf : NULL); 838 } 839 840 /* Check for Arbitration lost interrupt */ 841 if (isr & XCAN_IXR_ARBLST_MASK) { 842 priv->can.can_stats.arbitration_lost++; 843 if (skb) { 844 cf->can_id |= CAN_ERR_LOSTARB; 845 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC; 846 } 847 } 848 849 /* Check for RX FIFO Overflow interrupt */ 850 if (isr & XCAN_IXR_RXOFLW_MASK) { 851 stats->rx_over_errors++; 852 stats->rx_errors++; 853 if (skb) { 854 cf->can_id |= CAN_ERR_CRTL; 855 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 856 } 857 } 858 859 /* Check for RX Match Not Finished interrupt */ 860 if (isr & XCAN_IXR_RXMNF_MASK) { 861 stats->rx_dropped++; 862 stats->rx_errors++; 863 netdev_err(ndev, "RX match not finished, frame discarded\n"); 864 if (skb) { 865 cf->can_id |= CAN_ERR_CRTL; 866 cf->data[1] |= CAN_ERR_CRTL_UNSPEC; 867 } 868 } 869 870 /* Check for error interrupt */ 871 if (isr & XCAN_IXR_ERROR_MASK) { 872 if (skb) 873 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 874 875 /* Check for Ack error interrupt */ 876 if (err_status & XCAN_ESR_ACKER_MASK) { 877 stats->tx_errors++; 878 if (skb) { 879 cf->can_id |= CAN_ERR_ACK; 880 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 881 } 882 } 883 884 /* Check for Bit error interrupt */ 885 if (err_status & XCAN_ESR_BERR_MASK) { 886 stats->tx_errors++; 887 if (skb) { 888 cf->can_id |= CAN_ERR_PROT; 889 cf->data[2] = CAN_ERR_PROT_BIT; 890 } 891 } 892 893 /* Check for Stuff error interrupt */ 894 if (err_status & XCAN_ESR_STER_MASK) { 895 stats->rx_errors++; 896 if (skb) { 897 cf->can_id |= CAN_ERR_PROT; 898 cf->data[2] = CAN_ERR_PROT_STUFF; 899 } 900 } 901 902 /* Check for Form error interrupt */ 903 if (err_status & XCAN_ESR_FMER_MASK) { 904 stats->rx_errors++; 905 if (skb) { 906 cf->can_id |= CAN_ERR_PROT; 907 cf->data[2] = CAN_ERR_PROT_FORM; 908 } 909 } 910 911 /* Check for CRC error interrupt */ 912 if (err_status & XCAN_ESR_CRCER_MASK) { 913 stats->rx_errors++; 914 if (skb) { 915 cf->can_id |= CAN_ERR_PROT; 916 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 917 } 918 } 919 priv->can.can_stats.bus_error++; 920 } 921 922 if (skb) { 923 stats->rx_packets++; 924 stats->rx_bytes += cf->can_dlc; 925 netif_rx(skb); 926 } 927 928 netdev_dbg(ndev, "%s: error status register:0x%x\n", 929 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET)); 930 } 931 932 /** 933 * xcan_state_interrupt - It will check the state of the CAN device 934 * @ndev: net_device pointer 935 * @isr: interrupt status register value 936 * 937 * This will checks the state of the CAN device 938 * and puts the device into appropriate state. 939 */ 940 static void xcan_state_interrupt(struct net_device *ndev, u32 isr) 941 { 942 struct xcan_priv *priv = netdev_priv(ndev); 943 944 /* Check for Sleep interrupt if set put CAN device in sleep state */ 945 if (isr & XCAN_IXR_SLP_MASK) 946 priv->can.state = CAN_STATE_SLEEPING; 947 948 /* Check for Wake up interrupt if set put CAN device in Active state */ 949 if (isr & XCAN_IXR_WKUP_MASK) 950 priv->can.state = CAN_STATE_ERROR_ACTIVE; 951 } 952 953 /** 954 * xcan_rx_fifo_get_next_frame - Get register offset of next RX frame 955 * 956 * Return: Register offset of the next frame in RX FIFO. 957 */ 958 static int xcan_rx_fifo_get_next_frame(struct xcan_priv *priv) 959 { 960 int offset; 961 962 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) { 963 u32 fsr; 964 965 /* clear RXOK before the is-empty check so that any newly 966 * received frame will reassert it without a race 967 */ 968 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXOK_MASK); 969 970 fsr = priv->read_reg(priv, XCAN_FSR_OFFSET); 971 972 /* check if RX FIFO is empty */ 973 if (!(fsr & XCAN_FSR_FL_MASK)) 974 return -ENOENT; 975 976 offset = XCAN_RXMSG_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK); 977 978 } else { 979 /* check if RX FIFO is empty */ 980 if (!(priv->read_reg(priv, XCAN_ISR_OFFSET) & 981 XCAN_IXR_RXNEMP_MASK)) 982 return -ENOENT; 983 984 /* frames are read from a static offset */ 985 offset = XCAN_RXFIFO_OFFSET; 986 } 987 988 return offset; 989 } 990 991 /** 992 * xcan_rx_poll - Poll routine for rx packets (NAPI) 993 * @napi: napi structure pointer 994 * @quota: Max number of rx packets to be processed. 995 * 996 * This is the poll routine for rx part. 997 * It will process the packets maximux quota value. 998 * 999 * Return: number of packets received 1000 */ 1001 static int xcan_rx_poll(struct napi_struct *napi, int quota) 1002 { 1003 struct net_device *ndev = napi->dev; 1004 struct xcan_priv *priv = netdev_priv(ndev); 1005 u32 ier; 1006 int work_done = 0; 1007 int frame_offset; 1008 1009 while ((frame_offset = xcan_rx_fifo_get_next_frame(priv)) >= 0 && 1010 (work_done < quota)) { 1011 work_done += xcan_rx(ndev, frame_offset); 1012 1013 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) 1014 /* increment read index */ 1015 priv->write_reg(priv, XCAN_FSR_OFFSET, 1016 XCAN_FSR_IRI_MASK); 1017 else 1018 /* clear rx-not-empty (will actually clear only if 1019 * empty) 1020 */ 1021 priv->write_reg(priv, XCAN_ICR_OFFSET, 1022 XCAN_IXR_RXNEMP_MASK); 1023 } 1024 1025 if (work_done) { 1026 can_led_event(ndev, CAN_LED_EVENT_RX); 1027 xcan_update_error_state_after_rxtx(ndev); 1028 } 1029 1030 if (work_done < quota) { 1031 napi_complete_done(napi, work_done); 1032 ier = priv->read_reg(priv, XCAN_IER_OFFSET); 1033 ier |= xcan_rx_int_mask(priv); 1034 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 1035 } 1036 return work_done; 1037 } 1038 1039 /** 1040 * xcan_tx_interrupt - Tx Done Isr 1041 * @ndev: net_device pointer 1042 * @isr: Interrupt status register value 1043 */ 1044 static void xcan_tx_interrupt(struct net_device *ndev, u32 isr) 1045 { 1046 struct xcan_priv *priv = netdev_priv(ndev); 1047 struct net_device_stats *stats = &ndev->stats; 1048 unsigned int frames_in_fifo; 1049 int frames_sent = 1; /* TXOK => at least 1 frame was sent */ 1050 unsigned long flags; 1051 int retries = 0; 1052 1053 /* Synchronize with xmit as we need to know the exact number 1054 * of frames in the FIFO to stay in sync due to the TXFEMP 1055 * handling. 1056 * This also prevents a race between netif_wake_queue() and 1057 * netif_stop_queue(). 1058 */ 1059 spin_lock_irqsave(&priv->tx_lock, flags); 1060 1061 frames_in_fifo = priv->tx_head - priv->tx_tail; 1062 1063 if (WARN_ON_ONCE(frames_in_fifo == 0)) { 1064 /* clear TXOK anyway to avoid getting back here */ 1065 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); 1066 spin_unlock_irqrestore(&priv->tx_lock, flags); 1067 return; 1068 } 1069 1070 /* Check if 2 frames were sent (TXOK only means that at least 1 1071 * frame was sent). 1072 */ 1073 if (frames_in_fifo > 1) { 1074 WARN_ON(frames_in_fifo > priv->tx_max); 1075 1076 /* Synchronize TXOK and isr so that after the loop: 1077 * (1) isr variable is up-to-date at least up to TXOK clear 1078 * time. This avoids us clearing a TXOK of a second frame 1079 * but not noticing that the FIFO is now empty and thus 1080 * marking only a single frame as sent. 1081 * (2) No TXOK is left. Having one could mean leaving a 1082 * stray TXOK as we might process the associated frame 1083 * via TXFEMP handling as we read TXFEMP *after* TXOK 1084 * clear to satisfy (1). 1085 */ 1086 while ((isr & XCAN_IXR_TXOK_MASK) && !WARN_ON(++retries == 100)) { 1087 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); 1088 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); 1089 } 1090 1091 if (isr & XCAN_IXR_TXFEMP_MASK) { 1092 /* nothing in FIFO anymore */ 1093 frames_sent = frames_in_fifo; 1094 } 1095 } else { 1096 /* single frame in fifo, just clear TXOK */ 1097 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); 1098 } 1099 1100 while (frames_sent--) { 1101 stats->tx_bytes += can_get_echo_skb(ndev, priv->tx_tail % 1102 priv->tx_max); 1103 priv->tx_tail++; 1104 stats->tx_packets++; 1105 } 1106 1107 netif_wake_queue(ndev); 1108 1109 spin_unlock_irqrestore(&priv->tx_lock, flags); 1110 1111 can_led_event(ndev, CAN_LED_EVENT_TX); 1112 xcan_update_error_state_after_rxtx(ndev); 1113 } 1114 1115 /** 1116 * xcan_interrupt - CAN Isr 1117 * @irq: irq number 1118 * @dev_id: device id poniter 1119 * 1120 * This is the xilinx CAN Isr. It checks for the type of interrupt 1121 * and invokes the corresponding ISR. 1122 * 1123 * Return: 1124 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise 1125 */ 1126 static irqreturn_t xcan_interrupt(int irq, void *dev_id) 1127 { 1128 struct net_device *ndev = (struct net_device *)dev_id; 1129 struct xcan_priv *priv = netdev_priv(ndev); 1130 u32 isr, ier; 1131 u32 isr_errors; 1132 u32 rx_int_mask = xcan_rx_int_mask(priv); 1133 1134 /* Get the interrupt status from Xilinx CAN */ 1135 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); 1136 if (!isr) 1137 return IRQ_NONE; 1138 1139 /* Check for the type of interrupt and Processing it */ 1140 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) { 1141 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | 1142 XCAN_IXR_WKUP_MASK)); 1143 xcan_state_interrupt(ndev, isr); 1144 } 1145 1146 /* Check for Tx interrupt and Processing it */ 1147 if (isr & XCAN_IXR_TXOK_MASK) 1148 xcan_tx_interrupt(ndev, isr); 1149 1150 /* Check for the type of error interrupt and Processing it */ 1151 isr_errors = isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | 1152 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | 1153 XCAN_IXR_RXMNF_MASK); 1154 if (isr_errors) { 1155 priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); 1156 xcan_err_interrupt(ndev, isr); 1157 } 1158 1159 /* Check for the type of receive interrupt and Processing it */ 1160 if (isr & rx_int_mask) { 1161 ier = priv->read_reg(priv, XCAN_IER_OFFSET); 1162 ier &= ~rx_int_mask; 1163 priv->write_reg(priv, XCAN_IER_OFFSET, ier); 1164 napi_schedule(&priv->napi); 1165 } 1166 return IRQ_HANDLED; 1167 } 1168 1169 /** 1170 * xcan_chip_stop - Driver stop routine 1171 * @ndev: Pointer to net_device structure 1172 * 1173 * This is the drivers stop routine. It will disable the 1174 * interrupts and put the device into configuration mode. 1175 */ 1176 static void xcan_chip_stop(struct net_device *ndev) 1177 { 1178 struct xcan_priv *priv = netdev_priv(ndev); 1179 1180 /* Disable interrupts and leave the can in configuration mode */ 1181 set_reset_mode(ndev); 1182 priv->can.state = CAN_STATE_STOPPED; 1183 } 1184 1185 /** 1186 * xcan_open - Driver open routine 1187 * @ndev: Pointer to net_device structure 1188 * 1189 * This is the driver open routine. 1190 * Return: 0 on success and failure value on error 1191 */ 1192 static int xcan_open(struct net_device *ndev) 1193 { 1194 struct xcan_priv *priv = netdev_priv(ndev); 1195 int ret; 1196 1197 ret = pm_runtime_get_sync(priv->dev); 1198 if (ret < 0) { 1199 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1200 __func__, ret); 1201 return ret; 1202 } 1203 1204 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, 1205 ndev->name, ndev); 1206 if (ret < 0) { 1207 netdev_err(ndev, "irq allocation for CAN failed\n"); 1208 goto err; 1209 } 1210 1211 /* Set chip into reset mode */ 1212 ret = set_reset_mode(ndev); 1213 if (ret < 0) { 1214 netdev_err(ndev, "mode resetting failed!\n"); 1215 goto err_irq; 1216 } 1217 1218 /* Common open */ 1219 ret = open_candev(ndev); 1220 if (ret) 1221 goto err_irq; 1222 1223 ret = xcan_chip_start(ndev); 1224 if (ret < 0) { 1225 netdev_err(ndev, "xcan_chip_start failed!\n"); 1226 goto err_candev; 1227 } 1228 1229 can_led_event(ndev, CAN_LED_EVENT_OPEN); 1230 napi_enable(&priv->napi); 1231 netif_start_queue(ndev); 1232 1233 return 0; 1234 1235 err_candev: 1236 close_candev(ndev); 1237 err_irq: 1238 free_irq(ndev->irq, ndev); 1239 err: 1240 pm_runtime_put(priv->dev); 1241 1242 return ret; 1243 } 1244 1245 /** 1246 * xcan_close - Driver close routine 1247 * @ndev: Pointer to net_device structure 1248 * 1249 * Return: 0 always 1250 */ 1251 static int xcan_close(struct net_device *ndev) 1252 { 1253 struct xcan_priv *priv = netdev_priv(ndev); 1254 1255 netif_stop_queue(ndev); 1256 napi_disable(&priv->napi); 1257 xcan_chip_stop(ndev); 1258 free_irq(ndev->irq, ndev); 1259 close_candev(ndev); 1260 1261 can_led_event(ndev, CAN_LED_EVENT_STOP); 1262 pm_runtime_put(priv->dev); 1263 1264 return 0; 1265 } 1266 1267 /** 1268 * xcan_get_berr_counter - error counter routine 1269 * @ndev: Pointer to net_device structure 1270 * @bec: Pointer to can_berr_counter structure 1271 * 1272 * This is the driver error counter routine. 1273 * Return: 0 on success and failure value on error 1274 */ 1275 static int xcan_get_berr_counter(const struct net_device *ndev, 1276 struct can_berr_counter *bec) 1277 { 1278 struct xcan_priv *priv = netdev_priv(ndev); 1279 int ret; 1280 1281 ret = pm_runtime_get_sync(priv->dev); 1282 if (ret < 0) { 1283 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1284 __func__, ret); 1285 return ret; 1286 } 1287 1288 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; 1289 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & 1290 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT); 1291 1292 pm_runtime_put(priv->dev); 1293 1294 return 0; 1295 } 1296 1297 1298 static const struct net_device_ops xcan_netdev_ops = { 1299 .ndo_open = xcan_open, 1300 .ndo_stop = xcan_close, 1301 .ndo_start_xmit = xcan_start_xmit, 1302 .ndo_change_mtu = can_change_mtu, 1303 }; 1304 1305 /** 1306 * xcan_suspend - Suspend method for the driver 1307 * @dev: Address of the device structure 1308 * 1309 * Put the driver into low power mode. 1310 * Return: 0 on success and failure value on error 1311 */ 1312 static int __maybe_unused xcan_suspend(struct device *dev) 1313 { 1314 struct net_device *ndev = dev_get_drvdata(dev); 1315 1316 if (netif_running(ndev)) { 1317 netif_stop_queue(ndev); 1318 netif_device_detach(ndev); 1319 xcan_chip_stop(ndev); 1320 } 1321 1322 return pm_runtime_force_suspend(dev); 1323 } 1324 1325 /** 1326 * xcan_resume - Resume from suspend 1327 * @dev: Address of the device structure 1328 * 1329 * Resume operation after suspend. 1330 * Return: 0 on success and failure value on error 1331 */ 1332 static int __maybe_unused xcan_resume(struct device *dev) 1333 { 1334 struct net_device *ndev = dev_get_drvdata(dev); 1335 int ret; 1336 1337 ret = pm_runtime_force_resume(dev); 1338 if (ret) { 1339 dev_err(dev, "pm_runtime_force_resume failed on resume\n"); 1340 return ret; 1341 } 1342 1343 if (netif_running(ndev)) { 1344 ret = xcan_chip_start(ndev); 1345 if (ret) { 1346 dev_err(dev, "xcan_chip_start failed on resume\n"); 1347 return ret; 1348 } 1349 1350 netif_device_attach(ndev); 1351 netif_start_queue(ndev); 1352 } 1353 1354 return 0; 1355 } 1356 1357 /** 1358 * xcan_runtime_suspend - Runtime suspend method for the driver 1359 * @dev: Address of the device structure 1360 * 1361 * Put the driver into low power mode. 1362 * Return: 0 always 1363 */ 1364 static int __maybe_unused xcan_runtime_suspend(struct device *dev) 1365 { 1366 struct net_device *ndev = dev_get_drvdata(dev); 1367 struct xcan_priv *priv = netdev_priv(ndev); 1368 1369 clk_disable_unprepare(priv->bus_clk); 1370 clk_disable_unprepare(priv->can_clk); 1371 1372 return 0; 1373 } 1374 1375 /** 1376 * xcan_runtime_resume - Runtime resume from suspend 1377 * @dev: Address of the device structure 1378 * 1379 * Resume operation after suspend. 1380 * Return: 0 on success and failure value on error 1381 */ 1382 static int __maybe_unused xcan_runtime_resume(struct device *dev) 1383 { 1384 struct net_device *ndev = dev_get_drvdata(dev); 1385 struct xcan_priv *priv = netdev_priv(ndev); 1386 int ret; 1387 1388 ret = clk_prepare_enable(priv->bus_clk); 1389 if (ret) { 1390 dev_err(dev, "Cannot enable clock.\n"); 1391 return ret; 1392 } 1393 ret = clk_prepare_enable(priv->can_clk); 1394 if (ret) { 1395 dev_err(dev, "Cannot enable clock.\n"); 1396 clk_disable_unprepare(priv->bus_clk); 1397 return ret; 1398 } 1399 1400 return 0; 1401 } 1402 1403 static const struct dev_pm_ops xcan_dev_pm_ops = { 1404 SET_SYSTEM_SLEEP_PM_OPS(xcan_suspend, xcan_resume) 1405 SET_RUNTIME_PM_OPS(xcan_runtime_suspend, xcan_runtime_resume, NULL) 1406 }; 1407 1408 static const struct xcan_devtype_data xcan_zynq_data = { 1409 .bittiming_const = &xcan_bittiming_const, 1410 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT, 1411 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT, 1412 .bus_clk_name = "pclk", 1413 }; 1414 1415 static const struct xcan_devtype_data xcan_axi_data = { 1416 .bittiming_const = &xcan_bittiming_const, 1417 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT, 1418 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT, 1419 .bus_clk_name = "s_axi_aclk", 1420 }; 1421 1422 static const struct xcan_devtype_data xcan_canfd_data = { 1423 .flags = XCAN_FLAG_EXT_FILTERS | 1424 XCAN_FLAG_RXMNF | 1425 XCAN_FLAG_TX_MAILBOXES | 1426 XCAN_FLAG_RX_FIFO_MULTI, 1427 .bittiming_const = &xcan_bittiming_const, 1428 .btr_ts2_shift = XCAN_BTR_TS2_SHIFT_CANFD, 1429 .btr_sjw_shift = XCAN_BTR_SJW_SHIFT_CANFD, 1430 .bus_clk_name = "s_axi_aclk", 1431 }; 1432 1433 /* Match table for OF platform binding */ 1434 static const struct of_device_id xcan_of_match[] = { 1435 { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data }, 1436 { .compatible = "xlnx,axi-can-1.00.a", .data = &xcan_axi_data }, 1437 { .compatible = "xlnx,canfd-1.0", .data = &xcan_canfd_data }, 1438 { /* end of list */ }, 1439 }; 1440 MODULE_DEVICE_TABLE(of, xcan_of_match); 1441 1442 /** 1443 * xcan_probe - Platform registration call 1444 * @pdev: Handle to the platform device structure 1445 * 1446 * This function does all the memory allocation and registration for the CAN 1447 * device. 1448 * 1449 * Return: 0 on success and failure value on error 1450 */ 1451 static int xcan_probe(struct platform_device *pdev) 1452 { 1453 struct resource *res; /* IO mem resources */ 1454 struct net_device *ndev; 1455 struct xcan_priv *priv; 1456 const struct of_device_id *of_id; 1457 const struct xcan_devtype_data *devtype = &xcan_axi_data; 1458 void __iomem *addr; 1459 int ret; 1460 int rx_max, tx_max; 1461 int hw_tx_max, hw_rx_max; 1462 const char *hw_tx_max_property; 1463 1464 /* Get the virtual base address for the device */ 1465 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1466 addr = devm_ioremap_resource(&pdev->dev, res); 1467 if (IS_ERR(addr)) { 1468 ret = PTR_ERR(addr); 1469 goto err; 1470 } 1471 1472 of_id = of_match_device(xcan_of_match, &pdev->dev); 1473 if (of_id && of_id->data) 1474 devtype = of_id->data; 1475 1476 hw_tx_max_property = devtype->flags & XCAN_FLAG_TX_MAILBOXES ? 1477 "tx-mailbox-count" : "tx-fifo-depth"; 1478 1479 ret = of_property_read_u32(pdev->dev.of_node, hw_tx_max_property, 1480 &hw_tx_max); 1481 if (ret < 0) { 1482 dev_err(&pdev->dev, "missing %s property\n", 1483 hw_tx_max_property); 1484 goto err; 1485 } 1486 1487 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", 1488 &hw_rx_max); 1489 if (ret < 0) { 1490 dev_err(&pdev->dev, 1491 "missing rx-fifo-depth property (mailbox mode is not supported)\n"); 1492 goto err; 1493 } 1494 1495 /* With TX FIFO: 1496 * 1497 * There is no way to directly figure out how many frames have been 1498 * sent when the TXOK interrupt is processed. If TXFEMP 1499 * is supported, we can have 2 frames in the FIFO and use TXFEMP 1500 * to determine if 1 or 2 frames have been sent. 1501 * Theoretically we should be able to use TXFWMEMP to determine up 1502 * to 3 frames, but it seems that after putting a second frame in the 1503 * FIFO, with watermark at 2 frames, it can happen that TXFWMEMP (less 1504 * than 2 frames in FIFO) is set anyway with no TXOK (a frame was 1505 * sent), which is not a sensible state - possibly TXFWMEMP is not 1506 * completely synchronized with the rest of the bits? 1507 * 1508 * With TX mailboxes: 1509 * 1510 * HW sends frames in CAN ID priority order. To preserve FIFO ordering 1511 * we submit frames one at a time. 1512 */ 1513 if (!(devtype->flags & XCAN_FLAG_TX_MAILBOXES) && 1514 (devtype->flags & XCAN_FLAG_TXFEMP)) 1515 tx_max = min(hw_tx_max, 2); 1516 else 1517 tx_max = 1; 1518 1519 rx_max = hw_rx_max; 1520 1521 /* Create a CAN device instance */ 1522 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max); 1523 if (!ndev) 1524 return -ENOMEM; 1525 1526 priv = netdev_priv(ndev); 1527 priv->dev = &pdev->dev; 1528 priv->can.bittiming_const = devtype->bittiming_const; 1529 priv->can.do_set_mode = xcan_do_set_mode; 1530 priv->can.do_get_berr_counter = xcan_get_berr_counter; 1531 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1532 CAN_CTRLMODE_BERR_REPORTING; 1533 priv->reg_base = addr; 1534 priv->tx_max = tx_max; 1535 priv->devtype = *devtype; 1536 spin_lock_init(&priv->tx_lock); 1537 1538 /* Get IRQ for the device */ 1539 ndev->irq = platform_get_irq(pdev, 0); 1540 ndev->flags |= IFF_ECHO; /* We support local echo */ 1541 1542 platform_set_drvdata(pdev, ndev); 1543 SET_NETDEV_DEV(ndev, &pdev->dev); 1544 ndev->netdev_ops = &xcan_netdev_ops; 1545 1546 /* Getting the CAN can_clk info */ 1547 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk"); 1548 if (IS_ERR(priv->can_clk)) { 1549 dev_err(&pdev->dev, "Device clock not found.\n"); 1550 ret = PTR_ERR(priv->can_clk); 1551 goto err_free; 1552 } 1553 1554 priv->bus_clk = devm_clk_get(&pdev->dev, devtype->bus_clk_name); 1555 if (IS_ERR(priv->bus_clk)) { 1556 dev_err(&pdev->dev, "bus clock not found\n"); 1557 ret = PTR_ERR(priv->bus_clk); 1558 goto err_free; 1559 } 1560 1561 priv->write_reg = xcan_write_reg_le; 1562 priv->read_reg = xcan_read_reg_le; 1563 1564 pm_runtime_enable(&pdev->dev); 1565 ret = pm_runtime_get_sync(&pdev->dev); 1566 if (ret < 0) { 1567 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1568 __func__, ret); 1569 goto err_pmdisable; 1570 } 1571 1572 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { 1573 priv->write_reg = xcan_write_reg_be; 1574 priv->read_reg = xcan_read_reg_be; 1575 } 1576 1577 priv->can.clock.freq = clk_get_rate(priv->can_clk); 1578 1579 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max); 1580 1581 ret = register_candev(ndev); 1582 if (ret) { 1583 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); 1584 goto err_disableclks; 1585 } 1586 1587 devm_can_led_init(ndev); 1588 1589 pm_runtime_put(&pdev->dev); 1590 1591 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx buffers: actual %d, using %d\n", 1592 priv->reg_base, ndev->irq, priv->can.clock.freq, 1593 hw_tx_max, priv->tx_max); 1594 1595 return 0; 1596 1597 err_disableclks: 1598 pm_runtime_put(priv->dev); 1599 err_pmdisable: 1600 pm_runtime_disable(&pdev->dev); 1601 err_free: 1602 free_candev(ndev); 1603 err: 1604 return ret; 1605 } 1606 1607 /** 1608 * xcan_remove - Unregister the device after releasing the resources 1609 * @pdev: Handle to the platform device structure 1610 * 1611 * This function frees all the resources allocated to the device. 1612 * Return: 0 always 1613 */ 1614 static int xcan_remove(struct platform_device *pdev) 1615 { 1616 struct net_device *ndev = platform_get_drvdata(pdev); 1617 struct xcan_priv *priv = netdev_priv(ndev); 1618 1619 unregister_candev(ndev); 1620 pm_runtime_disable(&pdev->dev); 1621 netif_napi_del(&priv->napi); 1622 free_candev(ndev); 1623 1624 return 0; 1625 } 1626 1627 static struct platform_driver xcan_driver = { 1628 .probe = xcan_probe, 1629 .remove = xcan_remove, 1630 .driver = { 1631 .name = DRIVER_NAME, 1632 .pm = &xcan_dev_pm_ops, 1633 .of_match_table = xcan_of_match, 1634 }, 1635 }; 1636 1637 module_platform_driver(xcan_driver); 1638 1639 MODULE_LICENSE("GPL"); 1640 MODULE_AUTHOR("Xilinx Inc"); 1641 MODULE_DESCRIPTION("Xilinx CAN interface"); 1642