xref: /openbmc/linux/drivers/net/can/ti_hecc.c (revision 4800cd83)
1 /*
2  * TI HECC (CAN) device driver
3  *
4  * This driver supports TI's HECC (High End CAN Controller module) and the
5  * specs for the same is available at <http://www.ti.com>
6  *
7  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation version 2.
12  *
13  * This program is distributed as is WITHOUT ANY WARRANTY of any
14  * kind, whether express or implied; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19 
20 /*
21  * Your platform definitions should specify module ram offsets and interrupt
22  * number to use as follows:
23  *
24  * static struct ti_hecc_platform_data am3517_evm_hecc_pdata = {
25  *         .scc_hecc_offset        = 0,
26  *         .scc_ram_offset         = 0x3000,
27  *         .hecc_ram_offset        = 0x3000,
28  *         .mbx_offset             = 0x2000,
29  *         .int_line               = 0,
30  *         .revision               = 1,
31  *         .transceiver_switch     = hecc_phy_control,
32  * };
33  *
34  * Please see include/linux/can/platform/ti_hecc.h for description of
35  * above fields.
36  *
37  */
38 
39 #include <linux/module.h>
40 #include <linux/init.h>
41 #include <linux/kernel.h>
42 #include <linux/types.h>
43 #include <linux/interrupt.h>
44 #include <linux/errno.h>
45 #include <linux/netdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/platform_device.h>
48 #include <linux/clk.h>
49 
50 #include <linux/can/dev.h>
51 #include <linux/can/error.h>
52 #include <linux/can/platform/ti_hecc.h>
53 
54 #define DRV_NAME "ti_hecc"
55 #define HECC_MODULE_VERSION     "0.7"
56 MODULE_VERSION(HECC_MODULE_VERSION);
57 #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
58 
59 /* TX / RX Mailbox Configuration */
60 #define HECC_MAX_MAILBOXES	32	/* hardware mailboxes - do not change */
61 #define MAX_TX_PRIO		0x3F	/* hardware value - do not change */
62 
63 /*
64  * Important Note: TX mailbox configuration
65  * TX mailboxes should be restricted to the number of SKB buffers to avoid
66  * maintaining SKB buffers separately. TX mailboxes should be a power of 2
67  * for the mailbox logic to work.  Top mailbox numbers are reserved for RX
68  * and lower mailboxes for TX.
69  *
70  * HECC_MAX_TX_MBOX	HECC_MB_TX_SHIFT
71  * 4 (default)		2
72  * 8			3
73  * 16			4
74  */
75 #define HECC_MB_TX_SHIFT	2 /* as per table above */
76 #define HECC_MAX_TX_MBOX	BIT(HECC_MB_TX_SHIFT)
77 
78 #define HECC_TX_PRIO_SHIFT	(HECC_MB_TX_SHIFT)
79 #define HECC_TX_PRIO_MASK	(MAX_TX_PRIO << HECC_MB_TX_SHIFT)
80 #define HECC_TX_MB_MASK		(HECC_MAX_TX_MBOX - 1)
81 #define HECC_TX_MASK		((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
82 #define HECC_TX_MBOX_MASK	(~(BIT(HECC_MAX_TX_MBOX) - 1))
83 #define HECC_DEF_NAPI_WEIGHT	HECC_MAX_RX_MBOX
84 
85 /*
86  * Important Note: RX mailbox configuration
87  * RX mailboxes are further logically split into two - main and buffer
88  * mailboxes. The goal is to get all packets into main mailboxes as
89  * driven by mailbox number and receive priority (higher to lower) and
90  * buffer mailboxes are used to receive pkts while main mailboxes are being
91  * processed. This ensures in-order packet reception.
92  *
93  * Here are the recommended values for buffer mailbox. Note that RX mailboxes
94  * start after TX mailboxes:
95  *
96  * HECC_MAX_RX_MBOX		HECC_RX_BUFFER_MBOX	No of buffer mailboxes
97  * 28				12			8
98  * 16				20			4
99  */
100 
101 #define HECC_MAX_RX_MBOX	(HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
102 #define HECC_RX_BUFFER_MBOX	12 /* as per table above */
103 #define HECC_RX_FIRST_MBOX	(HECC_MAX_MAILBOXES - 1)
104 #define HECC_RX_HIGH_MBOX_MASK	(~(BIT(HECC_RX_BUFFER_MBOX) - 1))
105 
106 /* TI HECC module registers */
107 #define HECC_CANME		0x0	/* Mailbox enable */
108 #define HECC_CANMD		0x4	/* Mailbox direction */
109 #define HECC_CANTRS		0x8	/* Transmit request set */
110 #define HECC_CANTRR		0xC	/* Transmit request */
111 #define HECC_CANTA		0x10	/* Transmission acknowledge */
112 #define HECC_CANAA		0x14	/* Abort acknowledge */
113 #define HECC_CANRMP		0x18	/* Receive message pending */
114 #define HECC_CANRML		0x1C	/* Remote message lost */
115 #define HECC_CANRFP		0x20	/* Remote frame pending */
116 #define HECC_CANGAM		0x24	/* SECC only:Global acceptance mask */
117 #define HECC_CANMC		0x28	/* Master control */
118 #define HECC_CANBTC		0x2C	/* Bit timing configuration */
119 #define HECC_CANES		0x30	/* Error and status */
120 #define HECC_CANTEC		0x34	/* Transmit error counter */
121 #define HECC_CANREC		0x38	/* Receive error counter */
122 #define HECC_CANGIF0		0x3C	/* Global interrupt flag 0 */
123 #define HECC_CANGIM		0x40	/* Global interrupt mask */
124 #define HECC_CANGIF1		0x44	/* Global interrupt flag 1 */
125 #define HECC_CANMIM		0x48	/* Mailbox interrupt mask */
126 #define HECC_CANMIL		0x4C	/* Mailbox interrupt level */
127 #define HECC_CANOPC		0x50	/* Overwrite protection control */
128 #define HECC_CANTIOC		0x54	/* Transmit I/O control */
129 #define HECC_CANRIOC		0x58	/* Receive I/O control */
130 #define HECC_CANLNT		0x5C	/* HECC only: Local network time */
131 #define HECC_CANTOC		0x60	/* HECC only: Time-out control */
132 #define HECC_CANTOS		0x64	/* HECC only: Time-out status */
133 #define HECC_CANTIOCE		0x68	/* SCC only:Enhanced TX I/O control */
134 #define HECC_CANRIOCE		0x6C	/* SCC only:Enhanced RX I/O control */
135 
136 /* Mailbox registers */
137 #define HECC_CANMID		0x0
138 #define HECC_CANMCF		0x4
139 #define HECC_CANMDL		0x8
140 #define HECC_CANMDH		0xC
141 
142 #define HECC_SET_REG		0xFFFFFFFF
143 #define HECC_CANID_MASK		0x3FF	/* 18 bits mask for extended id's */
144 #define HECC_CCE_WAIT_COUNT     100	/* Wait for ~1 sec for CCE bit */
145 
146 #define HECC_CANMC_SCM		BIT(13)	/* SCC compat mode */
147 #define HECC_CANMC_CCR		BIT(12)	/* Change config request */
148 #define HECC_CANMC_PDR		BIT(11)	/* Local Power down - for sleep mode */
149 #define HECC_CANMC_ABO		BIT(7)	/* Auto Bus On */
150 #define HECC_CANMC_STM		BIT(6)	/* Self test mode - loopback */
151 #define HECC_CANMC_SRES		BIT(5)	/* Software reset */
152 
153 #define HECC_CANTIOC_EN		BIT(3)	/* Enable CAN TX I/O pin */
154 #define HECC_CANRIOC_EN		BIT(3)	/* Enable CAN RX I/O pin */
155 
156 #define HECC_CANMID_IDE		BIT(31)	/* Extended frame format */
157 #define HECC_CANMID_AME		BIT(30)	/* Acceptance mask enable */
158 #define HECC_CANMID_AAM		BIT(29)	/* Auto answer mode */
159 
160 #define HECC_CANES_FE		BIT(24)	/* form error */
161 #define HECC_CANES_BE		BIT(23)	/* bit error */
162 #define HECC_CANES_SA1		BIT(22)	/* stuck at dominant error */
163 #define HECC_CANES_CRCE		BIT(21)	/* CRC error */
164 #define HECC_CANES_SE		BIT(20)	/* stuff bit error */
165 #define HECC_CANES_ACKE		BIT(19)	/* ack error */
166 #define HECC_CANES_BO		BIT(18)	/* Bus off status */
167 #define HECC_CANES_EP		BIT(17)	/* Error passive status */
168 #define HECC_CANES_EW		BIT(16)	/* Error warning status */
169 #define HECC_CANES_SMA		BIT(5)	/* suspend mode ack */
170 #define HECC_CANES_CCE		BIT(4)	/* Change config enabled */
171 #define HECC_CANES_PDA		BIT(3)	/* Power down mode ack */
172 
173 #define HECC_CANBTC_SAM		BIT(7)	/* sample points */
174 
175 #define HECC_BUS_ERROR		(HECC_CANES_FE | HECC_CANES_BE |\
176 				HECC_CANES_CRCE | HECC_CANES_SE |\
177 				HECC_CANES_ACKE)
178 
179 #define HECC_CANMCF_RTR		BIT(4)	/* Remote transmit request */
180 
181 #define HECC_CANGIF_MAIF	BIT(17)	/* Message alarm interrupt */
182 #define HECC_CANGIF_TCOIF	BIT(16) /* Timer counter overflow int */
183 #define HECC_CANGIF_GMIF	BIT(15)	/* Global mailbox interrupt */
184 #define HECC_CANGIF_AAIF	BIT(14)	/* Abort ack interrupt */
185 #define HECC_CANGIF_WDIF	BIT(13)	/* Write denied interrupt */
186 #define HECC_CANGIF_WUIF	BIT(12)	/* Wake up interrupt */
187 #define HECC_CANGIF_RMLIF	BIT(11)	/* Receive message lost interrupt */
188 #define HECC_CANGIF_BOIF	BIT(10)	/* Bus off interrupt */
189 #define HECC_CANGIF_EPIF	BIT(9)	/* Error passive interrupt */
190 #define HECC_CANGIF_WLIF	BIT(8)	/* Warning level interrupt */
191 #define HECC_CANGIF_MBOX_MASK	0x1F	/* Mailbox number mask */
192 #define HECC_CANGIM_I1EN	BIT(1)	/* Int line 1 enable */
193 #define HECC_CANGIM_I0EN	BIT(0)	/* Int line 0 enable */
194 #define HECC_CANGIM_DEF_MASK	0x700	/* only busoff/warning/passive */
195 #define HECC_CANGIM_SIL		BIT(2)	/* system interrupts to int line 1 */
196 
197 /* CAN Bittiming constants as per HECC specs */
198 static struct can_bittiming_const ti_hecc_bittiming_const = {
199 	.name = DRV_NAME,
200 	.tseg1_min = 1,
201 	.tseg1_max = 16,
202 	.tseg2_min = 1,
203 	.tseg2_max = 8,
204 	.sjw_max = 4,
205 	.brp_min = 1,
206 	.brp_max = 256,
207 	.brp_inc = 1,
208 };
209 
210 struct ti_hecc_priv {
211 	struct can_priv can;	/* MUST be first member/field */
212 	struct napi_struct napi;
213 	struct net_device *ndev;
214 	struct clk *clk;
215 	void __iomem *base;
216 	u32 scc_ram_offset;
217 	u32 hecc_ram_offset;
218 	u32 mbx_offset;
219 	u32 int_line;
220 	spinlock_t mbx_lock; /* CANME register needs protection */
221 	u32 tx_head;
222 	u32 tx_tail;
223 	u32 rx_next;
224 	void (*transceiver_switch)(int);
225 };
226 
227 static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
228 {
229 	return priv->tx_head & HECC_TX_MB_MASK;
230 }
231 
232 static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
233 {
234 	return priv->tx_tail & HECC_TX_MB_MASK;
235 }
236 
237 static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
238 {
239 	return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
240 }
241 
242 static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
243 {
244 	__raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4);
245 }
246 
247 static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
248 	u32 reg, u32 val)
249 {
250 	__raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 +
251 			reg);
252 }
253 
254 static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
255 {
256 	return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 +
257 			reg);
258 }
259 
260 static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
261 {
262 	__raw_writel(val, priv->base + reg);
263 }
264 
265 static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
266 {
267 	return __raw_readl(priv->base + reg);
268 }
269 
270 static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
271 	u32 bit_mask)
272 {
273 	hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
274 }
275 
276 static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
277 	u32 bit_mask)
278 {
279 	hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
280 }
281 
282 static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
283 {
284 	return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
285 }
286 
287 static int ti_hecc_get_state(const struct net_device *ndev,
288 	enum can_state *state)
289 {
290 	struct ti_hecc_priv *priv = netdev_priv(ndev);
291 
292 	*state = priv->can.state;
293 	return 0;
294 }
295 
296 static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
297 {
298 	struct can_bittiming *bit_timing = &priv->can.bittiming;
299 	u32 can_btc;
300 
301 	can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
302 	can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
303 			& 0xF) << 3;
304 	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
305 		if (bit_timing->brp > 4)
306 			can_btc |= HECC_CANBTC_SAM;
307 		else
308 			dev_warn(priv->ndev->dev.parent, "WARN: Triple" \
309 				"sampling not set due to h/w limitations");
310 	}
311 	can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
312 	can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
313 
314 	/* ERM being set to 0 by default meaning resync at falling edge */
315 
316 	hecc_write(priv, HECC_CANBTC, can_btc);
317 	dev_info(priv->ndev->dev.parent, "setting CANBTC=%#x\n", can_btc);
318 
319 	return 0;
320 }
321 
322 static void ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
323 					int on)
324 {
325 	if (priv->transceiver_switch)
326 		priv->transceiver_switch(on);
327 }
328 
329 static void ti_hecc_reset(struct net_device *ndev)
330 {
331 	u32 cnt;
332 	struct ti_hecc_priv *priv = netdev_priv(ndev);
333 
334 	dev_dbg(ndev->dev.parent, "resetting hecc ...\n");
335 	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
336 
337 	/* Set change control request and wait till enabled */
338 	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
339 
340 	/*
341 	 * INFO: It has been observed that at times CCE bit may not be
342 	 * set and hw seems to be ok even if this bit is not set so
343 	 * timing out with a timing of 1ms to respect the specs
344 	 */
345 	cnt = HECC_CCE_WAIT_COUNT;
346 	while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
347 		--cnt;
348 		udelay(10);
349 	}
350 
351 	/*
352 	 * Note: On HECC, BTC can be programmed only in initialization mode, so
353 	 * it is expected that the can bittiming parameters are set via ip
354 	 * utility before the device is opened
355 	 */
356 	ti_hecc_set_btc(priv);
357 
358 	/* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
359 	hecc_write(priv, HECC_CANMC, 0);
360 
361 	/*
362 	 * INFO: CAN net stack handles bus off and hence disabling auto-bus-on
363 	 * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
364 	 */
365 
366 	/*
367 	 * INFO: It has been observed that at times CCE bit may not be
368 	 * set and hw seems to be ok even if this bit is not set so
369 	 */
370 	cnt = HECC_CCE_WAIT_COUNT;
371 	while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
372 		--cnt;
373 		udelay(10);
374 	}
375 
376 	/* Enable TX and RX I/O Control pins */
377 	hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
378 	hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
379 
380 	/* Clear registers for clean operation */
381 	hecc_write(priv, HECC_CANTA, HECC_SET_REG);
382 	hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
383 	hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
384 	hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
385 	hecc_write(priv, HECC_CANME, 0);
386 	hecc_write(priv, HECC_CANMD, 0);
387 
388 	/* SCC compat mode NOT supported (and not needed too) */
389 	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
390 }
391 
392 static void ti_hecc_start(struct net_device *ndev)
393 {
394 	struct ti_hecc_priv *priv = netdev_priv(ndev);
395 	u32 cnt, mbxno, mbx_mask;
396 
397 	/* put HECC in initialization mode and set btc */
398 	ti_hecc_reset(ndev);
399 
400 	priv->tx_head = priv->tx_tail = HECC_TX_MASK;
401 	priv->rx_next = HECC_RX_FIRST_MBOX;
402 
403 	/* Enable local and global acceptance mask registers */
404 	hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
405 
406 	/* Prepare configured mailboxes to receive messages */
407 	for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
408 		mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
409 		mbx_mask = BIT(mbxno);
410 		hecc_clear_bit(priv, HECC_CANME, mbx_mask);
411 		hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
412 		hecc_write_lam(priv, mbxno, HECC_SET_REG);
413 		hecc_set_bit(priv, HECC_CANMD, mbx_mask);
414 		hecc_set_bit(priv, HECC_CANME, mbx_mask);
415 		hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
416 	}
417 
418 	/* Prevent message over-write & Enable interrupts */
419 	hecc_write(priv, HECC_CANOPC, HECC_SET_REG);
420 	if (priv->int_line) {
421 		hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
422 		hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
423 			HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
424 	} else {
425 		hecc_write(priv, HECC_CANMIL, 0);
426 		hecc_write(priv, HECC_CANGIM,
427 			HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
428 	}
429 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
430 }
431 
432 static void ti_hecc_stop(struct net_device *ndev)
433 {
434 	struct ti_hecc_priv *priv = netdev_priv(ndev);
435 
436 	/* Disable interrupts and disable mailboxes */
437 	hecc_write(priv, HECC_CANGIM, 0);
438 	hecc_write(priv, HECC_CANMIM, 0);
439 	hecc_write(priv, HECC_CANME, 0);
440 	priv->can.state = CAN_STATE_STOPPED;
441 }
442 
443 static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
444 {
445 	int ret = 0;
446 
447 	switch (mode) {
448 	case CAN_MODE_START:
449 		ti_hecc_start(ndev);
450 		netif_wake_queue(ndev);
451 		break;
452 	default:
453 		ret = -EOPNOTSUPP;
454 		break;
455 	}
456 
457 	return ret;
458 }
459 
460 /*
461  * ti_hecc_xmit: HECC Transmit
462  *
463  * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
464  * priority of the mailbox for tranmission is dependent upon priority setting
465  * field in mailbox registers. The mailbox with highest value in priority field
466  * is transmitted first. Only when two mailboxes have the same value in
467  * priority field the highest numbered mailbox is transmitted first.
468  *
469  * To utilize the HECC priority feature as described above we start with the
470  * highest numbered mailbox with highest priority level and move on to the next
471  * mailbox with the same priority level and so on. Once we loop through all the
472  * transmit mailboxes we choose the next priority level (lower) and so on
473  * until we reach the lowest priority level on the lowest numbered mailbox
474  * when we stop transmission until all mailboxes are transmitted and then
475  * restart at highest numbered mailbox with highest priority.
476  *
477  * Two counters (head and tail) are used to track the next mailbox to transmit
478  * and to track the echo buffer for already transmitted mailbox. The queue
479  * is stopped when all the mailboxes are busy or when there is a priority
480  * value roll-over happens.
481  */
482 static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
483 {
484 	struct ti_hecc_priv *priv = netdev_priv(ndev);
485 	struct can_frame *cf = (struct can_frame *)skb->data;
486 	u32 mbxno, mbx_mask, data;
487 	unsigned long flags;
488 
489 	if (can_dropped_invalid_skb(ndev, skb))
490 		return NETDEV_TX_OK;
491 
492 	mbxno = get_tx_head_mb(priv);
493 	mbx_mask = BIT(mbxno);
494 	spin_lock_irqsave(&priv->mbx_lock, flags);
495 	if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
496 		spin_unlock_irqrestore(&priv->mbx_lock, flags);
497 		netif_stop_queue(ndev);
498 		dev_err(priv->ndev->dev.parent,
499 			"BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
500 			priv->tx_head, priv->tx_tail);
501 		return NETDEV_TX_BUSY;
502 	}
503 	spin_unlock_irqrestore(&priv->mbx_lock, flags);
504 
505 	/* Prepare mailbox for transmission */
506 	if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
507 		data |= HECC_CANMCF_RTR;
508 	data |= get_tx_head_prio(priv) << 8;
509 	hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
510 
511 	if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
512 		data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
513 	else /* Standard frame format */
514 		data = (cf->can_id & CAN_SFF_MASK) << 18;
515 	hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
516 	hecc_write_mbx(priv, mbxno, HECC_CANMDL,
517 		be32_to_cpu(*(u32 *)(cf->data)));
518 	if (cf->can_dlc > 4)
519 		hecc_write_mbx(priv, mbxno, HECC_CANMDH,
520 			be32_to_cpu(*(u32 *)(cf->data + 4)));
521 	else
522 		*(u32 *)(cf->data + 4) = 0;
523 	can_put_echo_skb(skb, ndev, mbxno);
524 
525 	spin_lock_irqsave(&priv->mbx_lock, flags);
526 	--priv->tx_head;
527 	if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
528 		(priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
529 		netif_stop_queue(ndev);
530 	}
531 	hecc_set_bit(priv, HECC_CANME, mbx_mask);
532 	spin_unlock_irqrestore(&priv->mbx_lock, flags);
533 
534 	hecc_clear_bit(priv, HECC_CANMD, mbx_mask);
535 	hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
536 	hecc_write(priv, HECC_CANTRS, mbx_mask);
537 
538 	return NETDEV_TX_OK;
539 }
540 
541 static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno)
542 {
543 	struct net_device_stats *stats = &priv->ndev->stats;
544 	struct can_frame *cf;
545 	struct sk_buff *skb;
546 	u32 data, mbx_mask;
547 	unsigned long flags;
548 
549 	skb = alloc_can_skb(priv->ndev, &cf);
550 	if (!skb) {
551 		if (printk_ratelimit())
552 			dev_err(priv->ndev->dev.parent,
553 				"ti_hecc_rx_pkt: alloc_can_skb() failed\n");
554 		return -ENOMEM;
555 	}
556 
557 	mbx_mask = BIT(mbxno);
558 	data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
559 	if (data & HECC_CANMID_IDE)
560 		cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
561 	else
562 		cf->can_id = (data >> 18) & CAN_SFF_MASK;
563 	data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
564 	if (data & HECC_CANMCF_RTR)
565 		cf->can_id |= CAN_RTR_FLAG;
566 	cf->can_dlc = get_can_dlc(data & 0xF);
567 	data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
568 	*(u32 *)(cf->data) = cpu_to_be32(data);
569 	if (cf->can_dlc > 4) {
570 		data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
571 		*(u32 *)(cf->data + 4) = cpu_to_be32(data);
572 	} else {
573 		*(u32 *)(cf->data + 4) = 0;
574 	}
575 	spin_lock_irqsave(&priv->mbx_lock, flags);
576 	hecc_clear_bit(priv, HECC_CANME, mbx_mask);
577 	hecc_write(priv, HECC_CANRMP, mbx_mask);
578 	/* enable mailbox only if it is part of rx buffer mailboxes */
579 	if (priv->rx_next < HECC_RX_BUFFER_MBOX)
580 		hecc_set_bit(priv, HECC_CANME, mbx_mask);
581 	spin_unlock_irqrestore(&priv->mbx_lock, flags);
582 
583 	stats->rx_bytes += cf->can_dlc;
584 	netif_receive_skb(skb);
585 	stats->rx_packets++;
586 
587 	return 0;
588 }
589 
590 /*
591  * ti_hecc_rx_poll - HECC receive pkts
592  *
593  * The receive mailboxes start from highest numbered mailbox till last xmit
594  * mailbox. On CAN frame reception the hardware places the data into highest
595  * numbered mailbox that matches the CAN ID filter. Since all receive mailboxes
596  * have same filtering (ALL CAN frames) packets will arrive in the highest
597  * available RX mailbox and we need to ensure in-order packet reception.
598  *
599  * To ensure the packets are received in the right order we logically divide
600  * the RX mailboxes into main and buffer mailboxes. Packets are received as per
601  * mailbox priotity (higher to lower) in the main bank and once it is full we
602  * disable further reception into main mailboxes. While the main mailboxes are
603  * processed in NAPI, further packets are received in buffer mailboxes.
604  *
605  * We maintain a RX next mailbox counter to process packets and once all main
606  * mailboxe packets are passed to the upper stack we enable all of them but
607  * continue to process packets received in buffer mailboxes. With each packet
608  * received from buffer mailbox we enable it immediately so as to handle the
609  * overflow from higher mailboxes.
610  */
611 static int ti_hecc_rx_poll(struct napi_struct *napi, int quota)
612 {
613 	struct net_device *ndev = napi->dev;
614 	struct ti_hecc_priv *priv = netdev_priv(ndev);
615 	u32 num_pkts = 0;
616 	u32 mbx_mask;
617 	unsigned long pending_pkts, flags;
618 
619 	if (!netif_running(ndev))
620 		return 0;
621 
622 	while ((pending_pkts = hecc_read(priv, HECC_CANRMP)) &&
623 		num_pkts < quota) {
624 		mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */
625 		if (mbx_mask & pending_pkts) {
626 			if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0)
627 				return num_pkts;
628 			++num_pkts;
629 		} else if (priv->rx_next > HECC_RX_BUFFER_MBOX) {
630 			break; /* pkt not received yet */
631 		}
632 		--priv->rx_next;
633 		if (priv->rx_next == HECC_RX_BUFFER_MBOX) {
634 			/* enable high bank mailboxes */
635 			spin_lock_irqsave(&priv->mbx_lock, flags);
636 			mbx_mask = hecc_read(priv, HECC_CANME);
637 			mbx_mask |= HECC_RX_HIGH_MBOX_MASK;
638 			hecc_write(priv, HECC_CANME, mbx_mask);
639 			spin_unlock_irqrestore(&priv->mbx_lock, flags);
640 		} else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) {
641 			priv->rx_next = HECC_RX_FIRST_MBOX;
642 			break;
643 		}
644 	}
645 
646 	/* Enable packet interrupt if all pkts are handled */
647 	if (hecc_read(priv, HECC_CANRMP) == 0) {
648 		napi_complete(napi);
649 		/* Re-enable RX mailbox interrupts */
650 		mbx_mask = hecc_read(priv, HECC_CANMIM);
651 		mbx_mask |= HECC_TX_MBOX_MASK;
652 		hecc_write(priv, HECC_CANMIM, mbx_mask);
653 	}
654 
655 	return num_pkts;
656 }
657 
658 static int ti_hecc_error(struct net_device *ndev, int int_status,
659 	int err_status)
660 {
661 	struct ti_hecc_priv *priv = netdev_priv(ndev);
662 	struct net_device_stats *stats = &ndev->stats;
663 	struct can_frame *cf;
664 	struct sk_buff *skb;
665 
666 	/* propogate the error condition to the can stack */
667 	skb = alloc_can_err_skb(ndev, &cf);
668 	if (!skb) {
669 		if (printk_ratelimit())
670 			dev_err(priv->ndev->dev.parent,
671 				"ti_hecc_error: alloc_can_err_skb() failed\n");
672 		return -ENOMEM;
673 	}
674 
675 	if (int_status & HECC_CANGIF_WLIF) { /* warning level int */
676 		if ((int_status & HECC_CANGIF_BOIF) == 0) {
677 			priv->can.state = CAN_STATE_ERROR_WARNING;
678 			++priv->can.can_stats.error_warning;
679 			cf->can_id |= CAN_ERR_CRTL;
680 			if (hecc_read(priv, HECC_CANTEC) > 96)
681 				cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
682 			if (hecc_read(priv, HECC_CANREC) > 96)
683 				cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
684 		}
685 		hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW);
686 		dev_dbg(priv->ndev->dev.parent, "Error Warning interrupt\n");
687 		hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
688 	}
689 
690 	if (int_status & HECC_CANGIF_EPIF) { /* error passive int */
691 		if ((int_status & HECC_CANGIF_BOIF) == 0) {
692 			priv->can.state = CAN_STATE_ERROR_PASSIVE;
693 			++priv->can.can_stats.error_passive;
694 			cf->can_id |= CAN_ERR_CRTL;
695 			if (hecc_read(priv, HECC_CANTEC) > 127)
696 				cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
697 			if (hecc_read(priv, HECC_CANREC) > 127)
698 				cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
699 		}
700 		hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP);
701 		dev_dbg(priv->ndev->dev.parent, "Error passive interrupt\n");
702 		hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
703 	}
704 
705 	/*
706 	 * Need to check busoff condition in error status register too to
707 	 * ensure warning interrupts don't hog the system
708 	 */
709 	if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) {
710 		priv->can.state = CAN_STATE_BUS_OFF;
711 		cf->can_id |= CAN_ERR_BUSOFF;
712 		hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO);
713 		hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
714 		/* Disable all interrupts in bus-off to avoid int hog */
715 		hecc_write(priv, HECC_CANGIM, 0);
716 		can_bus_off(ndev);
717 	}
718 
719 	if (err_status & HECC_BUS_ERROR) {
720 		++priv->can.can_stats.bus_error;
721 		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
722 		cf->data[2] |= CAN_ERR_PROT_UNSPEC;
723 		if (err_status & HECC_CANES_FE) {
724 			hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE);
725 			cf->data[2] |= CAN_ERR_PROT_FORM;
726 		}
727 		if (err_status & HECC_CANES_BE) {
728 			hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE);
729 			cf->data[2] |= CAN_ERR_PROT_BIT;
730 		}
731 		if (err_status & HECC_CANES_SE) {
732 			hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE);
733 			cf->data[2] |= CAN_ERR_PROT_STUFF;
734 		}
735 		if (err_status & HECC_CANES_CRCE) {
736 			hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE);
737 			cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
738 					CAN_ERR_PROT_LOC_CRC_DEL;
739 		}
740 		if (err_status & HECC_CANES_ACKE) {
741 			hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE);
742 			cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
743 					CAN_ERR_PROT_LOC_ACK_DEL;
744 		}
745 	}
746 
747 	netif_receive_skb(skb);
748 	stats->rx_packets++;
749 	stats->rx_bytes += cf->can_dlc;
750 	return 0;
751 }
752 
753 static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
754 {
755 	struct net_device *ndev = (struct net_device *)dev_id;
756 	struct ti_hecc_priv *priv = netdev_priv(ndev);
757 	struct net_device_stats *stats = &ndev->stats;
758 	u32 mbxno, mbx_mask, int_status, err_status;
759 	unsigned long ack, flags;
760 
761 	int_status = hecc_read(priv,
762 		(priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0);
763 
764 	if (!int_status)
765 		return IRQ_NONE;
766 
767 	err_status = hecc_read(priv, HECC_CANES);
768 	if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO |
769 		HECC_CANES_EP | HECC_CANES_EW))
770 			ti_hecc_error(ndev, int_status, err_status);
771 
772 	if (int_status & HECC_CANGIF_GMIF) {
773 		while (priv->tx_tail - priv->tx_head > 0) {
774 			mbxno = get_tx_tail_mb(priv);
775 			mbx_mask = BIT(mbxno);
776 			if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
777 				break;
778 			hecc_clear_bit(priv, HECC_CANMIM, mbx_mask);
779 			hecc_write(priv, HECC_CANTA, mbx_mask);
780 			spin_lock_irqsave(&priv->mbx_lock, flags);
781 			hecc_clear_bit(priv, HECC_CANME, mbx_mask);
782 			spin_unlock_irqrestore(&priv->mbx_lock, flags);
783 			stats->tx_bytes += hecc_read_mbx(priv, mbxno,
784 						HECC_CANMCF) & 0xF;
785 			stats->tx_packets++;
786 			can_get_echo_skb(ndev, mbxno);
787 			--priv->tx_tail;
788 		}
789 
790 		/* restart queue if wrap-up or if queue stalled on last pkt */
791 		if (((priv->tx_head == priv->tx_tail) &&
792 		((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
793 		(((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
794 		((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
795 			netif_wake_queue(ndev);
796 
797 		/* Disable RX mailbox interrupts and let NAPI reenable them */
798 		if (hecc_read(priv, HECC_CANRMP)) {
799 			ack = hecc_read(priv, HECC_CANMIM);
800 			ack &= BIT(HECC_MAX_TX_MBOX) - 1;
801 			hecc_write(priv, HECC_CANMIM, ack);
802 			napi_schedule(&priv->napi);
803 		}
804 	}
805 
806 	/* clear all interrupt conditions - read back to avoid spurious ints */
807 	if (priv->int_line) {
808 		hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
809 		int_status = hecc_read(priv, HECC_CANGIF1);
810 	} else {
811 		hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
812 		int_status = hecc_read(priv, HECC_CANGIF0);
813 	}
814 
815 	return IRQ_HANDLED;
816 }
817 
818 static int ti_hecc_open(struct net_device *ndev)
819 {
820 	struct ti_hecc_priv *priv = netdev_priv(ndev);
821 	int err;
822 
823 	err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
824 			ndev->name, ndev);
825 	if (err) {
826 		dev_err(ndev->dev.parent, "error requesting interrupt\n");
827 		return err;
828 	}
829 
830 	ti_hecc_transceiver_switch(priv, 1);
831 
832 	/* Open common can device */
833 	err = open_candev(ndev);
834 	if (err) {
835 		dev_err(ndev->dev.parent, "open_candev() failed %d\n", err);
836 		ti_hecc_transceiver_switch(priv, 0);
837 		free_irq(ndev->irq, ndev);
838 		return err;
839 	}
840 
841 	ti_hecc_start(ndev);
842 	napi_enable(&priv->napi);
843 	netif_start_queue(ndev);
844 
845 	return 0;
846 }
847 
848 static int ti_hecc_close(struct net_device *ndev)
849 {
850 	struct ti_hecc_priv *priv = netdev_priv(ndev);
851 
852 	netif_stop_queue(ndev);
853 	napi_disable(&priv->napi);
854 	ti_hecc_stop(ndev);
855 	free_irq(ndev->irq, ndev);
856 	close_candev(ndev);
857 	ti_hecc_transceiver_switch(priv, 0);
858 
859 	return 0;
860 }
861 
862 static const struct net_device_ops ti_hecc_netdev_ops = {
863 	.ndo_open		= ti_hecc_open,
864 	.ndo_stop		= ti_hecc_close,
865 	.ndo_start_xmit		= ti_hecc_xmit,
866 };
867 
868 static int ti_hecc_probe(struct platform_device *pdev)
869 {
870 	struct net_device *ndev = (struct net_device *)0;
871 	struct ti_hecc_priv *priv;
872 	struct ti_hecc_platform_data *pdata;
873 	struct resource *mem, *irq;
874 	void __iomem *addr;
875 	int err = -ENODEV;
876 
877 	pdata = pdev->dev.platform_data;
878 	if (!pdata) {
879 		dev_err(&pdev->dev, "No platform data\n");
880 		goto probe_exit;
881 	}
882 
883 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
884 	if (!mem) {
885 		dev_err(&pdev->dev, "No mem resources\n");
886 		goto probe_exit;
887 	}
888 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
889 	if (!irq) {
890 		dev_err(&pdev->dev, "No irq resource\n");
891 		goto probe_exit;
892 	}
893 	if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) {
894 		dev_err(&pdev->dev, "HECC region already claimed\n");
895 		err = -EBUSY;
896 		goto probe_exit;
897 	}
898 	addr = ioremap(mem->start, resource_size(mem));
899 	if (!addr) {
900 		dev_err(&pdev->dev, "ioremap failed\n");
901 		err = -ENOMEM;
902 		goto probe_exit_free_region;
903 	}
904 
905 	ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
906 	if (!ndev) {
907 		dev_err(&pdev->dev, "alloc_candev failed\n");
908 		err = -ENOMEM;
909 		goto probe_exit_iounmap;
910 	}
911 
912 	priv = netdev_priv(ndev);
913 	priv->ndev = ndev;
914 	priv->base = addr;
915 	priv->scc_ram_offset = pdata->scc_ram_offset;
916 	priv->hecc_ram_offset = pdata->hecc_ram_offset;
917 	priv->mbx_offset = pdata->mbx_offset;
918 	priv->int_line = pdata->int_line;
919 	priv->transceiver_switch = pdata->transceiver_switch;
920 
921 	priv->can.bittiming_const = &ti_hecc_bittiming_const;
922 	priv->can.do_set_mode = ti_hecc_do_set_mode;
923 	priv->can.do_get_state = ti_hecc_get_state;
924 	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
925 
926 	ndev->irq = irq->start;
927 	ndev->flags |= IFF_ECHO;
928 	platform_set_drvdata(pdev, ndev);
929 	SET_NETDEV_DEV(ndev, &pdev->dev);
930 	ndev->netdev_ops = &ti_hecc_netdev_ops;
931 
932 	priv->clk = clk_get(&pdev->dev, "hecc_ck");
933 	if (IS_ERR(priv->clk)) {
934 		dev_err(&pdev->dev, "No clock available\n");
935 		err = PTR_ERR(priv->clk);
936 		priv->clk = NULL;
937 		goto probe_exit_candev;
938 	}
939 	priv->can.clock.freq = clk_get_rate(priv->clk);
940 	netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll,
941 		HECC_DEF_NAPI_WEIGHT);
942 
943 	clk_enable(priv->clk);
944 	err = register_candev(ndev);
945 	if (err) {
946 		dev_err(&pdev->dev, "register_candev() failed\n");
947 		goto probe_exit_clk;
948 	}
949 	dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
950 		priv->base, (u32) ndev->irq);
951 
952 	return 0;
953 
954 probe_exit_clk:
955 	clk_put(priv->clk);
956 probe_exit_candev:
957 	free_candev(ndev);
958 probe_exit_iounmap:
959 	iounmap(addr);
960 probe_exit_free_region:
961 	release_mem_region(mem->start, resource_size(mem));
962 probe_exit:
963 	return err;
964 }
965 
966 static int __devexit ti_hecc_remove(struct platform_device *pdev)
967 {
968 	struct resource *res;
969 	struct net_device *ndev = platform_get_drvdata(pdev);
970 	struct ti_hecc_priv *priv = netdev_priv(ndev);
971 
972 	clk_disable(priv->clk);
973 	clk_put(priv->clk);
974 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
975 	iounmap(priv->base);
976 	release_mem_region(res->start, resource_size(res));
977 	unregister_candev(ndev);
978 	free_candev(ndev);
979 	platform_set_drvdata(pdev, NULL);
980 
981 	return 0;
982 }
983 
984 
985 #ifdef CONFIG_PM
986 static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
987 {
988 	struct net_device *dev = platform_get_drvdata(pdev);
989 	struct ti_hecc_priv *priv = netdev_priv(dev);
990 
991 	if (netif_running(dev)) {
992 		netif_stop_queue(dev);
993 		netif_device_detach(dev);
994 	}
995 
996 	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
997 	priv->can.state = CAN_STATE_SLEEPING;
998 
999 	clk_disable(priv->clk);
1000 
1001 	return 0;
1002 }
1003 
1004 static int ti_hecc_resume(struct platform_device *pdev)
1005 {
1006 	struct net_device *dev = platform_get_drvdata(pdev);
1007 	struct ti_hecc_priv *priv = netdev_priv(dev);
1008 
1009 	clk_enable(priv->clk);
1010 
1011 	hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
1012 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1013 
1014 	if (netif_running(dev)) {
1015 		netif_device_attach(dev);
1016 		netif_start_queue(dev);
1017 	}
1018 
1019 	return 0;
1020 }
1021 #else
1022 #define ti_hecc_suspend NULL
1023 #define ti_hecc_resume NULL
1024 #endif
1025 
1026 /* TI HECC netdevice driver: platform driver structure */
1027 static struct platform_driver ti_hecc_driver = {
1028 	.driver = {
1029 		.name    = DRV_NAME,
1030 		.owner   = THIS_MODULE,
1031 	},
1032 	.probe = ti_hecc_probe,
1033 	.remove = __devexit_p(ti_hecc_remove),
1034 	.suspend = ti_hecc_suspend,
1035 	.resume = ti_hecc_resume,
1036 };
1037 
1038 static int __init ti_hecc_init_driver(void)
1039 {
1040 	printk(KERN_INFO DRV_DESC "\n");
1041 	return platform_driver_register(&ti_hecc_driver);
1042 }
1043 
1044 static void __exit ti_hecc_exit_driver(void)
1045 {
1046 	printk(KERN_INFO DRV_DESC " unloaded\n");
1047 	platform_driver_unregister(&ti_hecc_driver);
1048 }
1049 
1050 module_exit(ti_hecc_exit_driver);
1051 module_init(ti_hecc_init_driver);
1052 
1053 MODULE_AUTHOR("Anant Gole <anantgole@ti.com>");
1054 MODULE_LICENSE("GPL v2");
1055 MODULE_DESCRIPTION(DRV_DESC);
1056