1 /* 2 * TI HECC (CAN) device driver 3 * 4 * This driver supports TI's HECC (High End CAN Controller module) and the 5 * specs for the same is available at <http://www.ti.com> 6 * 7 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 8 * Copyright (C) 2019 Jeroen Hofstee <jhofstee@victronenergy.com> 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation version 2. 13 * 14 * This program is distributed as is WITHOUT ANY WARRANTY of any 15 * kind, whether express or implied; without even the implied warranty 16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 */ 20 21 #include <linux/module.h> 22 #include <linux/kernel.h> 23 #include <linux/types.h> 24 #include <linux/interrupt.h> 25 #include <linux/errno.h> 26 #include <linux/netdevice.h> 27 #include <linux/skbuff.h> 28 #include <linux/platform_device.h> 29 #include <linux/clk.h> 30 #include <linux/io.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <linux/can/dev.h> 36 #include <linux/can/error.h> 37 #include <linux/can/rx-offload.h> 38 39 #define DRV_NAME "ti_hecc" 40 #define HECC_MODULE_VERSION "0.7" 41 MODULE_VERSION(HECC_MODULE_VERSION); 42 #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION 43 44 /* TX / RX Mailbox Configuration */ 45 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */ 46 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */ 47 48 /* Important Note: TX mailbox configuration 49 * TX mailboxes should be restricted to the number of SKB buffers to avoid 50 * maintaining SKB buffers separately. TX mailboxes should be a power of 2 51 * for the mailbox logic to work. Top mailbox numbers are reserved for RX 52 * and lower mailboxes for TX. 53 * 54 * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT 55 * 4 (default) 2 56 * 8 3 57 * 16 4 58 */ 59 #define HECC_MB_TX_SHIFT 2 /* as per table above */ 60 #define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT) 61 62 #define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT) 63 #define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT) 64 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1) 65 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK) 66 67 /* RX mailbox configuration 68 * 69 * The remaining mailboxes are used for reception and are delivered 70 * based on their timestamp, to avoid a hardware race when CANME is 71 * changed while CAN-bus traffic is being received. 72 */ 73 #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX) 74 #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1) 75 #define HECC_RX_LAST_MBOX (HECC_MAX_TX_MBOX) 76 77 /* TI HECC module registers */ 78 #define HECC_CANME 0x0 /* Mailbox enable */ 79 #define HECC_CANMD 0x4 /* Mailbox direction */ 80 #define HECC_CANTRS 0x8 /* Transmit request set */ 81 #define HECC_CANTRR 0xC /* Transmit request */ 82 #define HECC_CANTA 0x10 /* Transmission acknowledge */ 83 #define HECC_CANAA 0x14 /* Abort acknowledge */ 84 #define HECC_CANRMP 0x18 /* Receive message pending */ 85 #define HECC_CANRML 0x1C /* Receive message lost */ 86 #define HECC_CANRFP 0x20 /* Remote frame pending */ 87 #define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */ 88 #define HECC_CANMC 0x28 /* Master control */ 89 #define HECC_CANBTC 0x2C /* Bit timing configuration */ 90 #define HECC_CANES 0x30 /* Error and status */ 91 #define HECC_CANTEC 0x34 /* Transmit error counter */ 92 #define HECC_CANREC 0x38 /* Receive error counter */ 93 #define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */ 94 #define HECC_CANGIM 0x40 /* Global interrupt mask */ 95 #define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */ 96 #define HECC_CANMIM 0x48 /* Mailbox interrupt mask */ 97 #define HECC_CANMIL 0x4C /* Mailbox interrupt level */ 98 #define HECC_CANOPC 0x50 /* Overwrite protection control */ 99 #define HECC_CANTIOC 0x54 /* Transmit I/O control */ 100 #define HECC_CANRIOC 0x58 /* Receive I/O control */ 101 #define HECC_CANLNT 0x5C /* HECC only: Local network time */ 102 #define HECC_CANTOC 0x60 /* HECC only: Time-out control */ 103 #define HECC_CANTOS 0x64 /* HECC only: Time-out status */ 104 #define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */ 105 #define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */ 106 107 /* TI HECC RAM registers */ 108 #define HECC_CANMOTS 0x80 /* Message object time stamp */ 109 110 /* Mailbox registers */ 111 #define HECC_CANMID 0x0 112 #define HECC_CANMCF 0x4 113 #define HECC_CANMDL 0x8 114 #define HECC_CANMDH 0xC 115 116 #define HECC_SET_REG 0xFFFFFFFF 117 #define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */ 118 #define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */ 119 120 #define HECC_CANMC_SCM BIT(13) /* SCC compat mode */ 121 #define HECC_CANMC_CCR BIT(12) /* Change config request */ 122 #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */ 123 #define HECC_CANMC_ABO BIT(7) /* Auto Bus On */ 124 #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */ 125 #define HECC_CANMC_SRES BIT(5) /* Software reset */ 126 127 #define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */ 128 #define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */ 129 130 #define HECC_CANMID_IDE BIT(31) /* Extended frame format */ 131 #define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */ 132 #define HECC_CANMID_AAM BIT(29) /* Auto answer mode */ 133 134 #define HECC_CANES_FE BIT(24) /* form error */ 135 #define HECC_CANES_BE BIT(23) /* bit error */ 136 #define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */ 137 #define HECC_CANES_CRCE BIT(21) /* CRC error */ 138 #define HECC_CANES_SE BIT(20) /* stuff bit error */ 139 #define HECC_CANES_ACKE BIT(19) /* ack error */ 140 #define HECC_CANES_BO BIT(18) /* Bus off status */ 141 #define HECC_CANES_EP BIT(17) /* Error passive status */ 142 #define HECC_CANES_EW BIT(16) /* Error warning status */ 143 #define HECC_CANES_SMA BIT(5) /* suspend mode ack */ 144 #define HECC_CANES_CCE BIT(4) /* Change config enabled */ 145 #define HECC_CANES_PDA BIT(3) /* Power down mode ack */ 146 147 #define HECC_CANBTC_SAM BIT(7) /* sample points */ 148 149 #define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\ 150 HECC_CANES_CRCE | HECC_CANES_SE |\ 151 HECC_CANES_ACKE) 152 #define HECC_CANES_FLAGS (HECC_BUS_ERROR | HECC_CANES_BO |\ 153 HECC_CANES_EP | HECC_CANES_EW) 154 155 #define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */ 156 157 #define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */ 158 #define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */ 159 #define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */ 160 #define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */ 161 #define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */ 162 #define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */ 163 #define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */ 164 #define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */ 165 #define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */ 166 #define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */ 167 #define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */ 168 #define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */ 169 #define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */ 170 #define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */ 171 #define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */ 172 173 /* CAN Bittiming constants as per HECC specs */ 174 static const struct can_bittiming_const ti_hecc_bittiming_const = { 175 .name = DRV_NAME, 176 .tseg1_min = 1, 177 .tseg1_max = 16, 178 .tseg2_min = 1, 179 .tseg2_max = 8, 180 .sjw_max = 4, 181 .brp_min = 1, 182 .brp_max = 256, 183 .brp_inc = 1, 184 }; 185 186 struct ti_hecc_priv { 187 struct can_priv can; /* MUST be first member/field */ 188 struct can_rx_offload offload; 189 struct net_device *ndev; 190 struct clk *clk; 191 void __iomem *base; 192 void __iomem *hecc_ram; 193 void __iomem *mbx; 194 bool use_hecc1int; 195 spinlock_t mbx_lock; /* CANME register needs protection */ 196 u32 tx_head; 197 u32 tx_tail; 198 struct regulator *reg_xceiver; 199 }; 200 201 static inline int get_tx_head_mb(struct ti_hecc_priv *priv) 202 { 203 return priv->tx_head & HECC_TX_MB_MASK; 204 } 205 206 static inline int get_tx_tail_mb(struct ti_hecc_priv *priv) 207 { 208 return priv->tx_tail & HECC_TX_MB_MASK; 209 } 210 211 static inline int get_tx_head_prio(struct ti_hecc_priv *priv) 212 { 213 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; 214 } 215 216 static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val) 217 { 218 __raw_writel(val, priv->hecc_ram + mbxno * 4); 219 } 220 221 static inline u32 hecc_read_stamp(struct ti_hecc_priv *priv, u32 mbxno) 222 { 223 return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4); 224 } 225 226 static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno, 227 u32 reg, u32 val) 228 { 229 __raw_writel(val, priv->mbx + mbxno * 0x10 + reg); 230 } 231 232 static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg) 233 { 234 return __raw_readl(priv->mbx + mbxno * 0x10 + reg); 235 } 236 237 static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val) 238 { 239 __raw_writel(val, priv->base + reg); 240 } 241 242 static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg) 243 { 244 return __raw_readl(priv->base + reg); 245 } 246 247 static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg, 248 u32 bit_mask) 249 { 250 hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask); 251 } 252 253 static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg, 254 u32 bit_mask) 255 { 256 hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask); 257 } 258 259 static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask) 260 { 261 return (hecc_read(priv, reg) & bit_mask) ? 1 : 0; 262 } 263 264 static int ti_hecc_set_btc(struct ti_hecc_priv *priv) 265 { 266 struct can_bittiming *bit_timing = &priv->can.bittiming; 267 u32 can_btc; 268 269 can_btc = (bit_timing->phase_seg2 - 1) & 0x7; 270 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) 271 & 0xF) << 3; 272 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { 273 if (bit_timing->brp > 4) 274 can_btc |= HECC_CANBTC_SAM; 275 else 276 netdev_warn(priv->ndev, 277 "WARN: Triple sampling not set due to h/w limitations"); 278 } 279 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; 280 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; 281 282 /* ERM being set to 0 by default meaning resync at falling edge */ 283 284 hecc_write(priv, HECC_CANBTC, can_btc); 285 netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc); 286 287 return 0; 288 } 289 290 static int ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv, 291 int on) 292 { 293 if (!priv->reg_xceiver) 294 return 0; 295 296 if (on) 297 return regulator_enable(priv->reg_xceiver); 298 else 299 return regulator_disable(priv->reg_xceiver); 300 } 301 302 static void ti_hecc_reset(struct net_device *ndev) 303 { 304 u32 cnt; 305 struct ti_hecc_priv *priv = netdev_priv(ndev); 306 307 netdev_dbg(ndev, "resetting hecc ...\n"); 308 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES); 309 310 /* Set change control request and wait till enabled */ 311 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 312 313 /* INFO: It has been observed that at times CCE bit may not be 314 * set and hw seems to be ok even if this bit is not set so 315 * timing out with a timing of 1ms to respect the specs 316 */ 317 cnt = HECC_CCE_WAIT_COUNT; 318 while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { 319 --cnt; 320 udelay(10); 321 } 322 323 /* Note: On HECC, BTC can be programmed only in initialization mode, so 324 * it is expected that the can bittiming parameters are set via ip 325 * utility before the device is opened 326 */ 327 ti_hecc_set_btc(priv); 328 329 /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */ 330 hecc_write(priv, HECC_CANMC, 0); 331 332 /* INFO: CAN net stack handles bus off and hence disabling auto-bus-on 333 * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO); 334 */ 335 336 /* INFO: It has been observed that at times CCE bit may not be 337 * set and hw seems to be ok even if this bit is not set so 338 */ 339 cnt = HECC_CCE_WAIT_COUNT; 340 while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { 341 --cnt; 342 udelay(10); 343 } 344 345 /* Enable TX and RX I/O Control pins */ 346 hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN); 347 hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN); 348 349 /* Clear registers for clean operation */ 350 hecc_write(priv, HECC_CANTA, HECC_SET_REG); 351 hecc_write(priv, HECC_CANRMP, HECC_SET_REG); 352 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); 353 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); 354 hecc_write(priv, HECC_CANME, 0); 355 hecc_write(priv, HECC_CANMD, 0); 356 357 /* SCC compat mode NOT supported (and not needed too) */ 358 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM); 359 } 360 361 static void ti_hecc_start(struct net_device *ndev) 362 { 363 struct ti_hecc_priv *priv = netdev_priv(ndev); 364 u32 cnt, mbxno, mbx_mask; 365 366 /* put HECC in initialization mode and set btc */ 367 ti_hecc_reset(ndev); 368 369 priv->tx_head = HECC_TX_MASK; 370 priv->tx_tail = HECC_TX_MASK; 371 372 /* Enable local and global acceptance mask registers */ 373 hecc_write(priv, HECC_CANGAM, HECC_SET_REG); 374 375 /* Prepare configured mailboxes to receive messages */ 376 for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) { 377 mbxno = HECC_MAX_MAILBOXES - 1 - cnt; 378 mbx_mask = BIT(mbxno); 379 hecc_clear_bit(priv, HECC_CANME, mbx_mask); 380 hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME); 381 hecc_write_lam(priv, mbxno, HECC_SET_REG); 382 hecc_set_bit(priv, HECC_CANMD, mbx_mask); 383 hecc_set_bit(priv, HECC_CANME, mbx_mask); 384 hecc_set_bit(priv, HECC_CANMIM, mbx_mask); 385 } 386 387 /* Enable tx interrupts */ 388 hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1); 389 390 /* Prevent message over-write to create a rx fifo, but not for 391 * the lowest priority mailbox, since that allows detecting 392 * overflows instead of the hardware silently dropping the 393 * messages. 394 */ 395 mbx_mask = ~BIT(HECC_RX_LAST_MBOX); 396 hecc_write(priv, HECC_CANOPC, mbx_mask); 397 398 /* Enable interrupts */ 399 if (priv->use_hecc1int) { 400 hecc_write(priv, HECC_CANMIL, HECC_SET_REG); 401 hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK | 402 HECC_CANGIM_I1EN | HECC_CANGIM_SIL); 403 } else { 404 hecc_write(priv, HECC_CANMIL, 0); 405 hecc_write(priv, HECC_CANGIM, 406 HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN); 407 } 408 priv->can.state = CAN_STATE_ERROR_ACTIVE; 409 } 410 411 static void ti_hecc_stop(struct net_device *ndev) 412 { 413 struct ti_hecc_priv *priv = netdev_priv(ndev); 414 415 /* Disable the CPK; stop sending, erroring and acking */ 416 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR); 417 418 /* Disable interrupts and disable mailboxes */ 419 hecc_write(priv, HECC_CANGIM, 0); 420 hecc_write(priv, HECC_CANMIM, 0); 421 hecc_write(priv, HECC_CANME, 0); 422 priv->can.state = CAN_STATE_STOPPED; 423 } 424 425 static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode) 426 { 427 int ret = 0; 428 429 switch (mode) { 430 case CAN_MODE_START: 431 ti_hecc_start(ndev); 432 netif_wake_queue(ndev); 433 break; 434 default: 435 ret = -EOPNOTSUPP; 436 break; 437 } 438 439 return ret; 440 } 441 442 static int ti_hecc_get_berr_counter(const struct net_device *ndev, 443 struct can_berr_counter *bec) 444 { 445 struct ti_hecc_priv *priv = netdev_priv(ndev); 446 447 bec->txerr = hecc_read(priv, HECC_CANTEC); 448 bec->rxerr = hecc_read(priv, HECC_CANREC); 449 450 return 0; 451 } 452 453 /* ti_hecc_xmit: HECC Transmit 454 * 455 * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the 456 * priority of the mailbox for transmission is dependent upon priority setting 457 * field in mailbox registers. The mailbox with highest value in priority field 458 * is transmitted first. Only when two mailboxes have the same value in 459 * priority field the highest numbered mailbox is transmitted first. 460 * 461 * To utilize the HECC priority feature as described above we start with the 462 * highest numbered mailbox with highest priority level and move on to the next 463 * mailbox with the same priority level and so on. Once we loop through all the 464 * transmit mailboxes we choose the next priority level (lower) and so on 465 * until we reach the lowest priority level on the lowest numbered mailbox 466 * when we stop transmission until all mailboxes are transmitted and then 467 * restart at highest numbered mailbox with highest priority. 468 * 469 * Two counters (head and tail) are used to track the next mailbox to transmit 470 * and to track the echo buffer for already transmitted mailbox. The queue 471 * is stopped when all the mailboxes are busy or when there is a priority 472 * value roll-over happens. 473 */ 474 static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev) 475 { 476 struct ti_hecc_priv *priv = netdev_priv(ndev); 477 struct can_frame *cf = (struct can_frame *)skb->data; 478 u32 mbxno, mbx_mask, data; 479 unsigned long flags; 480 481 if (can_dropped_invalid_skb(ndev, skb)) 482 return NETDEV_TX_OK; 483 484 mbxno = get_tx_head_mb(priv); 485 mbx_mask = BIT(mbxno); 486 spin_lock_irqsave(&priv->mbx_lock, flags); 487 if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) { 488 spin_unlock_irqrestore(&priv->mbx_lock, flags); 489 netif_stop_queue(ndev); 490 netdev_err(priv->ndev, 491 "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n", 492 priv->tx_head, priv->tx_tail); 493 return NETDEV_TX_BUSY; 494 } 495 spin_unlock_irqrestore(&priv->mbx_lock, flags); 496 497 /* Prepare mailbox for transmission */ 498 data = cf->len | (get_tx_head_prio(priv) << 8); 499 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ 500 data |= HECC_CANMCF_RTR; 501 hecc_write_mbx(priv, mbxno, HECC_CANMCF, data); 502 503 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 504 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; 505 else /* Standard frame format */ 506 data = (cf->can_id & CAN_SFF_MASK) << 18; 507 hecc_write_mbx(priv, mbxno, HECC_CANMID, data); 508 hecc_write_mbx(priv, mbxno, HECC_CANMDL, 509 be32_to_cpu(*(__be32 *)(cf->data))); 510 if (cf->len > 4) 511 hecc_write_mbx(priv, mbxno, HECC_CANMDH, 512 be32_to_cpu(*(__be32 *)(cf->data + 4))); 513 else 514 *(u32 *)(cf->data + 4) = 0; 515 can_put_echo_skb(skb, ndev, mbxno, 0); 516 517 spin_lock_irqsave(&priv->mbx_lock, flags); 518 --priv->tx_head; 519 if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) || 520 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { 521 netif_stop_queue(ndev); 522 } 523 hecc_set_bit(priv, HECC_CANME, mbx_mask); 524 spin_unlock_irqrestore(&priv->mbx_lock, flags); 525 526 hecc_write(priv, HECC_CANTRS, mbx_mask); 527 528 return NETDEV_TX_OK; 529 } 530 531 static inline 532 struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload) 533 { 534 return container_of(offload, struct ti_hecc_priv, offload); 535 } 536 537 static struct sk_buff *ti_hecc_mailbox_read(struct can_rx_offload *offload, 538 unsigned int mbxno, u32 *timestamp, 539 bool drop) 540 { 541 struct ti_hecc_priv *priv = rx_offload_to_priv(offload); 542 struct sk_buff *skb; 543 struct can_frame *cf; 544 u32 data, mbx_mask; 545 546 mbx_mask = BIT(mbxno); 547 548 if (unlikely(drop)) { 549 skb = ERR_PTR(-ENOBUFS); 550 goto mark_as_read; 551 } 552 553 skb = alloc_can_skb(offload->dev, &cf); 554 if (unlikely(!skb)) { 555 skb = ERR_PTR(-ENOMEM); 556 goto mark_as_read; 557 } 558 559 data = hecc_read_mbx(priv, mbxno, HECC_CANMID); 560 if (data & HECC_CANMID_IDE) 561 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 562 else 563 cf->can_id = (data >> 18) & CAN_SFF_MASK; 564 565 data = hecc_read_mbx(priv, mbxno, HECC_CANMCF); 566 if (data & HECC_CANMCF_RTR) 567 cf->can_id |= CAN_RTR_FLAG; 568 cf->len = can_cc_dlc2len(data & 0xF); 569 570 data = hecc_read_mbx(priv, mbxno, HECC_CANMDL); 571 *(__be32 *)(cf->data) = cpu_to_be32(data); 572 if (cf->len > 4) { 573 data = hecc_read_mbx(priv, mbxno, HECC_CANMDH); 574 *(__be32 *)(cf->data + 4) = cpu_to_be32(data); 575 } 576 577 *timestamp = hecc_read_stamp(priv, mbxno); 578 579 /* Check for FIFO overrun. 580 * 581 * All but the last RX mailbox have activated overwrite 582 * protection. So skip check for overrun, if we're not 583 * handling the last RX mailbox. 584 * 585 * As the overwrite protection for the last RX mailbox is 586 * disabled, the CAN core might update while we're reading 587 * it. This means the skb might be inconsistent. 588 * 589 * Return an error to let rx-offload discard this CAN frame. 590 */ 591 if (unlikely(mbxno == HECC_RX_LAST_MBOX && 592 hecc_read(priv, HECC_CANRML) & mbx_mask)) 593 skb = ERR_PTR(-ENOBUFS); 594 595 mark_as_read: 596 hecc_write(priv, HECC_CANRMP, mbx_mask); 597 598 return skb; 599 } 600 601 static int ti_hecc_error(struct net_device *ndev, int int_status, 602 int err_status) 603 { 604 struct ti_hecc_priv *priv = netdev_priv(ndev); 605 struct can_frame *cf; 606 struct sk_buff *skb; 607 u32 timestamp; 608 int err; 609 610 if (err_status & HECC_BUS_ERROR) { 611 /* propagate the error condition to the can stack */ 612 skb = alloc_can_err_skb(ndev, &cf); 613 if (!skb) { 614 if (net_ratelimit()) 615 netdev_err(priv->ndev, 616 "%s: alloc_can_err_skb() failed\n", 617 __func__); 618 return -ENOMEM; 619 } 620 621 ++priv->can.can_stats.bus_error; 622 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 623 if (err_status & HECC_CANES_FE) 624 cf->data[2] |= CAN_ERR_PROT_FORM; 625 if (err_status & HECC_CANES_BE) 626 cf->data[2] |= CAN_ERR_PROT_BIT; 627 if (err_status & HECC_CANES_SE) 628 cf->data[2] |= CAN_ERR_PROT_STUFF; 629 if (err_status & HECC_CANES_CRCE) 630 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 631 if (err_status & HECC_CANES_ACKE) 632 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 633 634 timestamp = hecc_read(priv, HECC_CANLNT); 635 err = can_rx_offload_queue_timestamp(&priv->offload, skb, 636 timestamp); 637 if (err) 638 ndev->stats.rx_fifo_errors++; 639 } 640 641 hecc_write(priv, HECC_CANES, HECC_CANES_FLAGS); 642 643 return 0; 644 } 645 646 static void ti_hecc_change_state(struct net_device *ndev, 647 enum can_state rx_state, 648 enum can_state tx_state) 649 { 650 struct ti_hecc_priv *priv = netdev_priv(ndev); 651 struct can_frame *cf; 652 struct sk_buff *skb; 653 u32 timestamp; 654 int err; 655 656 skb = alloc_can_err_skb(priv->ndev, &cf); 657 if (unlikely(!skb)) { 658 priv->can.state = max(tx_state, rx_state); 659 return; 660 } 661 662 can_change_state(priv->ndev, cf, tx_state, rx_state); 663 664 if (max(tx_state, rx_state) != CAN_STATE_BUS_OFF) { 665 cf->data[6] = hecc_read(priv, HECC_CANTEC); 666 cf->data[7] = hecc_read(priv, HECC_CANREC); 667 } 668 669 timestamp = hecc_read(priv, HECC_CANLNT); 670 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 671 if (err) 672 ndev->stats.rx_fifo_errors++; 673 } 674 675 static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id) 676 { 677 struct net_device *ndev = (struct net_device *)dev_id; 678 struct ti_hecc_priv *priv = netdev_priv(ndev); 679 struct net_device_stats *stats = &ndev->stats; 680 u32 mbxno, mbx_mask, int_status, err_status, stamp; 681 unsigned long flags, rx_pending; 682 u32 handled = 0; 683 684 int_status = hecc_read(priv, 685 priv->use_hecc1int ? 686 HECC_CANGIF1 : HECC_CANGIF0); 687 688 if (!int_status) 689 return IRQ_NONE; 690 691 err_status = hecc_read(priv, HECC_CANES); 692 if (unlikely(err_status & HECC_CANES_FLAGS)) 693 ti_hecc_error(ndev, int_status, err_status); 694 695 if (unlikely(int_status & HECC_CANGIM_DEF_MASK)) { 696 enum can_state rx_state, tx_state; 697 u32 rec = hecc_read(priv, HECC_CANREC); 698 u32 tec = hecc_read(priv, HECC_CANTEC); 699 700 if (int_status & HECC_CANGIF_WLIF) { 701 handled |= HECC_CANGIF_WLIF; 702 rx_state = rec >= tec ? CAN_STATE_ERROR_WARNING : 0; 703 tx_state = rec <= tec ? CAN_STATE_ERROR_WARNING : 0; 704 netdev_dbg(priv->ndev, "Error Warning interrupt\n"); 705 ti_hecc_change_state(ndev, rx_state, tx_state); 706 } 707 708 if (int_status & HECC_CANGIF_EPIF) { 709 handled |= HECC_CANGIF_EPIF; 710 rx_state = rec >= tec ? CAN_STATE_ERROR_PASSIVE : 0; 711 tx_state = rec <= tec ? CAN_STATE_ERROR_PASSIVE : 0; 712 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 713 ti_hecc_change_state(ndev, rx_state, tx_state); 714 } 715 716 if (int_status & HECC_CANGIF_BOIF) { 717 handled |= HECC_CANGIF_BOIF; 718 rx_state = CAN_STATE_BUS_OFF; 719 tx_state = CAN_STATE_BUS_OFF; 720 netdev_dbg(priv->ndev, "Bus off interrupt\n"); 721 722 /* Disable all interrupts */ 723 hecc_write(priv, HECC_CANGIM, 0); 724 can_bus_off(ndev); 725 ti_hecc_change_state(ndev, rx_state, tx_state); 726 } 727 } else if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE)) { 728 enum can_state new_state, tx_state, rx_state; 729 u32 rec = hecc_read(priv, HECC_CANREC); 730 u32 tec = hecc_read(priv, HECC_CANTEC); 731 732 if (rec >= 128 || tec >= 128) 733 new_state = CAN_STATE_ERROR_PASSIVE; 734 else if (rec >= 96 || tec >= 96) 735 new_state = CAN_STATE_ERROR_WARNING; 736 else 737 new_state = CAN_STATE_ERROR_ACTIVE; 738 739 if (new_state < priv->can.state) { 740 rx_state = rec >= tec ? new_state : 0; 741 tx_state = rec <= tec ? new_state : 0; 742 ti_hecc_change_state(ndev, rx_state, tx_state); 743 } 744 } 745 746 if (int_status & HECC_CANGIF_GMIF) { 747 while (priv->tx_tail - priv->tx_head > 0) { 748 mbxno = get_tx_tail_mb(priv); 749 mbx_mask = BIT(mbxno); 750 if (!(mbx_mask & hecc_read(priv, HECC_CANTA))) 751 break; 752 hecc_write(priv, HECC_CANTA, mbx_mask); 753 spin_lock_irqsave(&priv->mbx_lock, flags); 754 hecc_clear_bit(priv, HECC_CANME, mbx_mask); 755 spin_unlock_irqrestore(&priv->mbx_lock, flags); 756 stamp = hecc_read_stamp(priv, mbxno); 757 stats->tx_bytes += 758 can_rx_offload_get_echo_skb(&priv->offload, 759 mbxno, stamp, NULL); 760 stats->tx_packets++; 761 --priv->tx_tail; 762 } 763 764 /* restart queue if wrap-up or if queue stalled on last pkt */ 765 if ((priv->tx_head == priv->tx_tail && 766 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || 767 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && 768 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) 769 netif_wake_queue(ndev); 770 771 /* offload RX mailboxes and let NAPI deliver them */ 772 while ((rx_pending = hecc_read(priv, HECC_CANRMP))) { 773 can_rx_offload_irq_offload_timestamp(&priv->offload, 774 rx_pending); 775 } 776 } 777 778 /* clear all interrupt conditions - read back to avoid spurious ints */ 779 if (priv->use_hecc1int) { 780 hecc_write(priv, HECC_CANGIF1, handled); 781 int_status = hecc_read(priv, HECC_CANGIF1); 782 } else { 783 hecc_write(priv, HECC_CANGIF0, handled); 784 int_status = hecc_read(priv, HECC_CANGIF0); 785 } 786 787 can_rx_offload_irq_finish(&priv->offload); 788 789 return IRQ_HANDLED; 790 } 791 792 static int ti_hecc_open(struct net_device *ndev) 793 { 794 struct ti_hecc_priv *priv = netdev_priv(ndev); 795 int err; 796 797 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, 798 ndev->name, ndev); 799 if (err) { 800 netdev_err(ndev, "error requesting interrupt\n"); 801 return err; 802 } 803 804 ti_hecc_transceiver_switch(priv, 1); 805 806 /* Open common can device */ 807 err = open_candev(ndev); 808 if (err) { 809 netdev_err(ndev, "open_candev() failed %d\n", err); 810 ti_hecc_transceiver_switch(priv, 0); 811 free_irq(ndev->irq, ndev); 812 return err; 813 } 814 815 ti_hecc_start(ndev); 816 can_rx_offload_enable(&priv->offload); 817 netif_start_queue(ndev); 818 819 return 0; 820 } 821 822 static int ti_hecc_close(struct net_device *ndev) 823 { 824 struct ti_hecc_priv *priv = netdev_priv(ndev); 825 826 netif_stop_queue(ndev); 827 can_rx_offload_disable(&priv->offload); 828 ti_hecc_stop(ndev); 829 free_irq(ndev->irq, ndev); 830 close_candev(ndev); 831 ti_hecc_transceiver_switch(priv, 0); 832 833 return 0; 834 } 835 836 static const struct net_device_ops ti_hecc_netdev_ops = { 837 .ndo_open = ti_hecc_open, 838 .ndo_stop = ti_hecc_close, 839 .ndo_start_xmit = ti_hecc_xmit, 840 .ndo_change_mtu = can_change_mtu, 841 }; 842 843 static const struct of_device_id ti_hecc_dt_ids[] = { 844 { 845 .compatible = "ti,am3517-hecc", 846 }, 847 { } 848 }; 849 MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids); 850 851 static int ti_hecc_probe(struct platform_device *pdev) 852 { 853 struct net_device *ndev = (struct net_device *)0; 854 struct ti_hecc_priv *priv; 855 struct device_node *np = pdev->dev.of_node; 856 struct regulator *reg_xceiver; 857 int err = -ENODEV; 858 859 if (!IS_ENABLED(CONFIG_OF) || !np) 860 return -EINVAL; 861 862 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); 863 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) 864 return -EPROBE_DEFER; 865 else if (IS_ERR(reg_xceiver)) 866 reg_xceiver = NULL; 867 868 ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX); 869 if (!ndev) { 870 dev_err(&pdev->dev, "alloc_candev failed\n"); 871 return -ENOMEM; 872 } 873 priv = netdev_priv(ndev); 874 875 /* handle hecc memory */ 876 priv->base = devm_platform_ioremap_resource_byname(pdev, "hecc"); 877 if (IS_ERR(priv->base)) { 878 dev_err(&pdev->dev, "hecc ioremap failed\n"); 879 err = PTR_ERR(priv->base); 880 goto probe_exit_candev; 881 } 882 883 /* handle hecc-ram memory */ 884 priv->hecc_ram = devm_platform_ioremap_resource_byname(pdev, 885 "hecc-ram"); 886 if (IS_ERR(priv->hecc_ram)) { 887 dev_err(&pdev->dev, "hecc-ram ioremap failed\n"); 888 err = PTR_ERR(priv->hecc_ram); 889 goto probe_exit_candev; 890 } 891 892 /* handle mbx memory */ 893 priv->mbx = devm_platform_ioremap_resource_byname(pdev, "mbx"); 894 if (IS_ERR(priv->mbx)) { 895 dev_err(&pdev->dev, "mbx ioremap failed\n"); 896 err = PTR_ERR(priv->mbx); 897 goto probe_exit_candev; 898 } 899 900 ndev->irq = platform_get_irq(pdev, 0); 901 if (ndev->irq < 0) { 902 err = ndev->irq; 903 goto probe_exit_candev; 904 } 905 906 priv->ndev = ndev; 907 priv->reg_xceiver = reg_xceiver; 908 priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int"); 909 910 priv->can.bittiming_const = &ti_hecc_bittiming_const; 911 priv->can.do_set_mode = ti_hecc_do_set_mode; 912 priv->can.do_get_berr_counter = ti_hecc_get_berr_counter; 913 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 914 915 spin_lock_init(&priv->mbx_lock); 916 ndev->flags |= IFF_ECHO; 917 platform_set_drvdata(pdev, ndev); 918 SET_NETDEV_DEV(ndev, &pdev->dev); 919 ndev->netdev_ops = &ti_hecc_netdev_ops; 920 921 priv->clk = clk_get(&pdev->dev, "hecc_ck"); 922 if (IS_ERR(priv->clk)) { 923 dev_err(&pdev->dev, "No clock available\n"); 924 err = PTR_ERR(priv->clk); 925 priv->clk = NULL; 926 goto probe_exit_candev; 927 } 928 priv->can.clock.freq = clk_get_rate(priv->clk); 929 930 err = clk_prepare_enable(priv->clk); 931 if (err) { 932 dev_err(&pdev->dev, "clk_prepare_enable() failed\n"); 933 goto probe_exit_release_clk; 934 } 935 936 priv->offload.mailbox_read = ti_hecc_mailbox_read; 937 priv->offload.mb_first = HECC_RX_FIRST_MBOX; 938 priv->offload.mb_last = HECC_RX_LAST_MBOX; 939 err = can_rx_offload_add_timestamp(ndev, &priv->offload); 940 if (err) { 941 dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n"); 942 goto probe_exit_disable_clk; 943 } 944 945 err = register_candev(ndev); 946 if (err) { 947 dev_err(&pdev->dev, "register_candev() failed\n"); 948 goto probe_exit_offload; 949 } 950 951 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", 952 priv->base, (u32)ndev->irq); 953 954 return 0; 955 956 probe_exit_offload: 957 can_rx_offload_del(&priv->offload); 958 probe_exit_disable_clk: 959 clk_disable_unprepare(priv->clk); 960 probe_exit_release_clk: 961 clk_put(priv->clk); 962 probe_exit_candev: 963 free_candev(ndev); 964 965 return err; 966 } 967 968 static int ti_hecc_remove(struct platform_device *pdev) 969 { 970 struct net_device *ndev = platform_get_drvdata(pdev); 971 struct ti_hecc_priv *priv = netdev_priv(ndev); 972 973 unregister_candev(ndev); 974 clk_disable_unprepare(priv->clk); 975 clk_put(priv->clk); 976 can_rx_offload_del(&priv->offload); 977 free_candev(ndev); 978 979 return 0; 980 } 981 982 #ifdef CONFIG_PM 983 static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state) 984 { 985 struct net_device *dev = platform_get_drvdata(pdev); 986 struct ti_hecc_priv *priv = netdev_priv(dev); 987 988 if (netif_running(dev)) { 989 netif_stop_queue(dev); 990 netif_device_detach(dev); 991 } 992 993 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR); 994 priv->can.state = CAN_STATE_SLEEPING; 995 996 clk_disable_unprepare(priv->clk); 997 998 return 0; 999 } 1000 1001 static int ti_hecc_resume(struct platform_device *pdev) 1002 { 1003 struct net_device *dev = platform_get_drvdata(pdev); 1004 struct ti_hecc_priv *priv = netdev_priv(dev); 1005 int err; 1006 1007 err = clk_prepare_enable(priv->clk); 1008 if (err) 1009 return err; 1010 1011 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR); 1012 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1013 1014 if (netif_running(dev)) { 1015 netif_device_attach(dev); 1016 netif_start_queue(dev); 1017 } 1018 1019 return 0; 1020 } 1021 #else 1022 #define ti_hecc_suspend NULL 1023 #define ti_hecc_resume NULL 1024 #endif 1025 1026 /* TI HECC netdevice driver: platform driver structure */ 1027 static struct platform_driver ti_hecc_driver = { 1028 .driver = { 1029 .name = DRV_NAME, 1030 .of_match_table = ti_hecc_dt_ids, 1031 }, 1032 .probe = ti_hecc_probe, 1033 .remove = ti_hecc_remove, 1034 .suspend = ti_hecc_suspend, 1035 .resume = ti_hecc_resume, 1036 }; 1037 1038 module_platform_driver(ti_hecc_driver); 1039 1040 MODULE_AUTHOR("Anant Gole <anantgole@ti.com>"); 1041 MODULE_LICENSE("GPL v2"); 1042 MODULE_DESCRIPTION(DRV_DESC); 1043 MODULE_ALIAS("platform:" DRV_NAME); 1044