1 /* 2 * sun4i_can.c - CAN bus controller driver for Allwinner SUN4I&SUN7I based SoCs 3 * 4 * Copyright (C) 2013 Peter Chen 5 * Copyright (C) 2015 Gerhard Bertelsmann 6 * All rights reserved. 7 * 8 * Parts of this software are based on (derived from) the SJA1000 code by: 9 * Copyright (C) 2014 Oliver Hartkopp <oliver.hartkopp@volkswagen.de> 10 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 11 * Copyright (C) 2002-2007 Volkswagen Group Electronic Research 12 * Copyright (C) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33, 13 * 38106 Braunschweig, GERMANY 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. Neither the name of Volkswagen nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * Alternatively, provided that this notice is retained in full, this 28 * software may be distributed under the terms of the GNU General 29 * Public License ("GPL") version 2, in which case the provisions of the 30 * GPL apply INSTEAD OF those given above. 31 * 32 * The provided data structures and external interfaces from this code 33 * are not restricted to be used by modules with a GPL compatible license. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 38 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 39 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 40 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 41 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 46 * DAMAGE. 47 * 48 */ 49 50 #include <linux/netdevice.h> 51 #include <linux/can.h> 52 #include <linux/can/dev.h> 53 #include <linux/can/error.h> 54 #include <linux/clk.h> 55 #include <linux/delay.h> 56 #include <linux/ethtool.h> 57 #include <linux/interrupt.h> 58 #include <linux/init.h> 59 #include <linux/io.h> 60 #include <linux/module.h> 61 #include <linux/of.h> 62 #include <linux/of_device.h> 63 #include <linux/platform_device.h> 64 #include <linux/reset.h> 65 66 #define DRV_NAME "sun4i_can" 67 68 /* Registers address (physical base address 0x01C2BC00) */ 69 #define SUN4I_REG_MSEL_ADDR 0x0000 /* CAN Mode Select */ 70 #define SUN4I_REG_CMD_ADDR 0x0004 /* CAN Command */ 71 #define SUN4I_REG_STA_ADDR 0x0008 /* CAN Status */ 72 #define SUN4I_REG_INT_ADDR 0x000c /* CAN Interrupt Flag */ 73 #define SUN4I_REG_INTEN_ADDR 0x0010 /* CAN Interrupt Enable */ 74 #define SUN4I_REG_BTIME_ADDR 0x0014 /* CAN Bus Timing 0 */ 75 #define SUN4I_REG_TEWL_ADDR 0x0018 /* CAN Tx Error Warning Limit */ 76 #define SUN4I_REG_ERRC_ADDR 0x001c /* CAN Error Counter */ 77 #define SUN4I_REG_RMCNT_ADDR 0x0020 /* CAN Receive Message Counter */ 78 #define SUN4I_REG_RBUFSA_ADDR 0x0024 /* CAN Receive Buffer Start Address */ 79 #define SUN4I_REG_BUF0_ADDR 0x0040 /* CAN Tx/Rx Buffer 0 */ 80 #define SUN4I_REG_BUF1_ADDR 0x0044 /* CAN Tx/Rx Buffer 1 */ 81 #define SUN4I_REG_BUF2_ADDR 0x0048 /* CAN Tx/Rx Buffer 2 */ 82 #define SUN4I_REG_BUF3_ADDR 0x004c /* CAN Tx/Rx Buffer 3 */ 83 #define SUN4I_REG_BUF4_ADDR 0x0050 /* CAN Tx/Rx Buffer 4 */ 84 #define SUN4I_REG_BUF5_ADDR 0x0054 /* CAN Tx/Rx Buffer 5 */ 85 #define SUN4I_REG_BUF6_ADDR 0x0058 /* CAN Tx/Rx Buffer 6 */ 86 #define SUN4I_REG_BUF7_ADDR 0x005c /* CAN Tx/Rx Buffer 7 */ 87 #define SUN4I_REG_BUF8_ADDR 0x0060 /* CAN Tx/Rx Buffer 8 */ 88 #define SUN4I_REG_BUF9_ADDR 0x0064 /* CAN Tx/Rx Buffer 9 */ 89 #define SUN4I_REG_BUF10_ADDR 0x0068 /* CAN Tx/Rx Buffer 10 */ 90 #define SUN4I_REG_BUF11_ADDR 0x006c /* CAN Tx/Rx Buffer 11 */ 91 #define SUN4I_REG_BUF12_ADDR 0x0070 /* CAN Tx/Rx Buffer 12 */ 92 #define SUN4I_REG_ACPC_ADDR 0x0040 /* CAN Acceptance Code 0 */ 93 #define SUN4I_REG_ACPM_ADDR 0x0044 /* CAN Acceptance Mask 0 */ 94 #define SUN4I_REG_RBUF_RBACK_START_ADDR 0x0180 /* CAN transmit buffer start */ 95 #define SUN4I_REG_RBUF_RBACK_END_ADDR 0x01b0 /* CAN transmit buffer end */ 96 97 /* Controller Register Description */ 98 99 /* mode select register (r/w) 100 * offset:0x0000 default:0x0000_0001 101 */ 102 #define SUN4I_MSEL_SLEEP_MODE (0x01 << 4) /* write in reset mode */ 103 #define SUN4I_MSEL_WAKE_UP (0x00 << 4) 104 #define SUN4I_MSEL_SINGLE_FILTER (0x01 << 3) /* write in reset mode */ 105 #define SUN4I_MSEL_DUAL_FILTERS (0x00 << 3) 106 #define SUN4I_MSEL_LOOPBACK_MODE BIT(2) 107 #define SUN4I_MSEL_LISTEN_ONLY_MODE BIT(1) 108 #define SUN4I_MSEL_RESET_MODE BIT(0) 109 110 /* command register (w) 111 * offset:0x0004 default:0x0000_0000 112 */ 113 #define SUN4I_CMD_BUS_OFF_REQ BIT(5) 114 #define SUN4I_CMD_SELF_RCV_REQ BIT(4) 115 #define SUN4I_CMD_CLEAR_OR_FLAG BIT(3) 116 #define SUN4I_CMD_RELEASE_RBUF BIT(2) 117 #define SUN4I_CMD_ABORT_REQ BIT(1) 118 #define SUN4I_CMD_TRANS_REQ BIT(0) 119 120 /* status register (r) 121 * offset:0x0008 default:0x0000_003c 122 */ 123 #define SUN4I_STA_BIT_ERR (0x00 << 22) 124 #define SUN4I_STA_FORM_ERR (0x01 << 22) 125 #define SUN4I_STA_STUFF_ERR (0x02 << 22) 126 #define SUN4I_STA_OTHER_ERR (0x03 << 22) 127 #define SUN4I_STA_MASK_ERR (0x03 << 22) 128 #define SUN4I_STA_ERR_DIR BIT(21) 129 #define SUN4I_STA_ERR_SEG_CODE (0x1f << 16) 130 #define SUN4I_STA_START (0x03 << 16) 131 #define SUN4I_STA_ID28_21 (0x02 << 16) 132 #define SUN4I_STA_ID20_18 (0x06 << 16) 133 #define SUN4I_STA_SRTR (0x04 << 16) 134 #define SUN4I_STA_IDE (0x05 << 16) 135 #define SUN4I_STA_ID17_13 (0x07 << 16) 136 #define SUN4I_STA_ID12_5 (0x0f << 16) 137 #define SUN4I_STA_ID4_0 (0x0e << 16) 138 #define SUN4I_STA_RTR (0x0c << 16) 139 #define SUN4I_STA_RB1 (0x0d << 16) 140 #define SUN4I_STA_RB0 (0x09 << 16) 141 #define SUN4I_STA_DLEN (0x0b << 16) 142 #define SUN4I_STA_DATA_FIELD (0x0a << 16) 143 #define SUN4I_STA_CRC_SEQUENCE (0x08 << 16) 144 #define SUN4I_STA_CRC_DELIMITER (0x18 << 16) 145 #define SUN4I_STA_ACK (0x19 << 16) 146 #define SUN4I_STA_ACK_DELIMITER (0x1b << 16) 147 #define SUN4I_STA_END (0x1a << 16) 148 #define SUN4I_STA_INTERMISSION (0x12 << 16) 149 #define SUN4I_STA_ACTIVE_ERROR (0x11 << 16) 150 #define SUN4I_STA_PASSIVE_ERROR (0x16 << 16) 151 #define SUN4I_STA_TOLERATE_DOMINANT_BITS (0x13 << 16) 152 #define SUN4I_STA_ERROR_DELIMITER (0x17 << 16) 153 #define SUN4I_STA_OVERLOAD (0x1c << 16) 154 #define SUN4I_STA_BUS_OFF BIT(7) 155 #define SUN4I_STA_ERR_STA BIT(6) 156 #define SUN4I_STA_TRANS_BUSY BIT(5) 157 #define SUN4I_STA_RCV_BUSY BIT(4) 158 #define SUN4I_STA_TRANS_OVER BIT(3) 159 #define SUN4I_STA_TBUF_RDY BIT(2) 160 #define SUN4I_STA_DATA_ORUN BIT(1) 161 #define SUN4I_STA_RBUF_RDY BIT(0) 162 163 /* interrupt register (r) 164 * offset:0x000c default:0x0000_0000 165 */ 166 #define SUN4I_INT_BUS_ERR BIT(7) 167 #define SUN4I_INT_ARB_LOST BIT(6) 168 #define SUN4I_INT_ERR_PASSIVE BIT(5) 169 #define SUN4I_INT_WAKEUP BIT(4) 170 #define SUN4I_INT_DATA_OR BIT(3) 171 #define SUN4I_INT_ERR_WRN BIT(2) 172 #define SUN4I_INT_TBUF_VLD BIT(1) 173 #define SUN4I_INT_RBUF_VLD BIT(0) 174 175 /* interrupt enable register (r/w) 176 * offset:0x0010 default:0x0000_0000 177 */ 178 #define SUN4I_INTEN_BERR BIT(7) 179 #define SUN4I_INTEN_ARB_LOST BIT(6) 180 #define SUN4I_INTEN_ERR_PASSIVE BIT(5) 181 #define SUN4I_INTEN_WAKEUP BIT(4) 182 #define SUN4I_INTEN_OR BIT(3) 183 #define SUN4I_INTEN_ERR_WRN BIT(2) 184 #define SUN4I_INTEN_TX BIT(1) 185 #define SUN4I_INTEN_RX BIT(0) 186 187 /* error code */ 188 #define SUN4I_ERR_INRCV (0x1 << 5) 189 #define SUN4I_ERR_INTRANS (0x0 << 5) 190 191 /* filter mode */ 192 #define SUN4I_FILTER_CLOSE 0 193 #define SUN4I_SINGLE_FLTER_MODE 1 194 #define SUN4I_DUAL_FILTER_MODE 2 195 196 /* message buffer flags */ 197 #define SUN4I_MSG_EFF_FLAG BIT(7) 198 #define SUN4I_MSG_RTR_FLAG BIT(6) 199 200 /* max. number of interrupts handled in ISR */ 201 #define SUN4I_CAN_MAX_IRQ 20 202 #define SUN4I_MODE_MAX_RETRIES 100 203 204 /** 205 * struct sun4ican_quirks - Differences between SoC variants. 206 * 207 * @has_reset: SoC needs reset deasserted. 208 */ 209 struct sun4ican_quirks { 210 bool has_reset; 211 }; 212 213 struct sun4ican_priv { 214 struct can_priv can; 215 void __iomem *base; 216 struct clk *clk; 217 struct reset_control *reset; 218 spinlock_t cmdreg_lock; /* lock for concurrent cmd register writes */ 219 }; 220 221 static const struct can_bittiming_const sun4ican_bittiming_const = { 222 .name = DRV_NAME, 223 .tseg1_min = 1, 224 .tseg1_max = 16, 225 .tseg2_min = 1, 226 .tseg2_max = 8, 227 .sjw_max = 4, 228 .brp_min = 1, 229 .brp_max = 64, 230 .brp_inc = 1, 231 }; 232 233 static void sun4i_can_write_cmdreg(struct sun4ican_priv *priv, u8 val) 234 { 235 unsigned long flags; 236 237 spin_lock_irqsave(&priv->cmdreg_lock, flags); 238 writel(val, priv->base + SUN4I_REG_CMD_ADDR); 239 spin_unlock_irqrestore(&priv->cmdreg_lock, flags); 240 } 241 242 static int set_normal_mode(struct net_device *dev) 243 { 244 struct sun4ican_priv *priv = netdev_priv(dev); 245 int retry = SUN4I_MODE_MAX_RETRIES; 246 u32 mod_reg_val = 0; 247 248 do { 249 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); 250 mod_reg_val &= ~SUN4I_MSEL_RESET_MODE; 251 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); 252 } while (retry-- && (mod_reg_val & SUN4I_MSEL_RESET_MODE)); 253 254 if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) { 255 netdev_err(dev, 256 "setting controller into normal mode failed!\n"); 257 return -ETIMEDOUT; 258 } 259 260 return 0; 261 } 262 263 static int set_reset_mode(struct net_device *dev) 264 { 265 struct sun4ican_priv *priv = netdev_priv(dev); 266 int retry = SUN4I_MODE_MAX_RETRIES; 267 u32 mod_reg_val = 0; 268 269 do { 270 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); 271 mod_reg_val |= SUN4I_MSEL_RESET_MODE; 272 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); 273 } while (retry-- && !(mod_reg_val & SUN4I_MSEL_RESET_MODE)); 274 275 if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) & 276 SUN4I_MSEL_RESET_MODE)) { 277 netdev_err(dev, "setting controller into reset mode failed!\n"); 278 return -ETIMEDOUT; 279 } 280 281 return 0; 282 } 283 284 /* bittiming is called in reset_mode only */ 285 static int sun4ican_set_bittiming(struct net_device *dev) 286 { 287 struct sun4ican_priv *priv = netdev_priv(dev); 288 struct can_bittiming *bt = &priv->can.bittiming; 289 u32 cfg; 290 291 cfg = ((bt->brp - 1) & 0x3FF) | 292 (((bt->sjw - 1) & 0x3) << 14) | 293 (((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) << 16) | 294 (((bt->phase_seg2 - 1) & 0x7) << 20); 295 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 296 cfg |= 0x800000; 297 298 netdev_dbg(dev, "setting BITTIMING=0x%08x\n", cfg); 299 writel(cfg, priv->base + SUN4I_REG_BTIME_ADDR); 300 301 return 0; 302 } 303 304 static int sun4ican_get_berr_counter(const struct net_device *dev, 305 struct can_berr_counter *bec) 306 { 307 struct sun4ican_priv *priv = netdev_priv(dev); 308 u32 errors; 309 int err; 310 311 err = clk_prepare_enable(priv->clk); 312 if (err) { 313 netdev_err(dev, "could not enable clock\n"); 314 return err; 315 } 316 317 errors = readl(priv->base + SUN4I_REG_ERRC_ADDR); 318 319 bec->txerr = errors & 0xFF; 320 bec->rxerr = (errors >> 16) & 0xFF; 321 322 clk_disable_unprepare(priv->clk); 323 324 return 0; 325 } 326 327 static int sun4i_can_start(struct net_device *dev) 328 { 329 struct sun4ican_priv *priv = netdev_priv(dev); 330 int err; 331 u32 mod_reg_val; 332 333 /* we need to enter the reset mode */ 334 err = set_reset_mode(dev); 335 if (err) { 336 netdev_err(dev, "could not enter reset mode\n"); 337 return err; 338 } 339 340 /* set filters - we accept all */ 341 writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR); 342 writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR); 343 344 /* clear error counters and error code capture */ 345 writel(0, priv->base + SUN4I_REG_ERRC_ADDR); 346 347 /* enable interrupts */ 348 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 349 writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR); 350 else 351 writel(0xFF & ~SUN4I_INTEN_BERR, 352 priv->base + SUN4I_REG_INTEN_ADDR); 353 354 /* enter the selected mode */ 355 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); 356 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 357 mod_reg_val |= SUN4I_MSEL_LOOPBACK_MODE; 358 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 359 mod_reg_val |= SUN4I_MSEL_LISTEN_ONLY_MODE; 360 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); 361 362 err = sun4ican_set_bittiming(dev); 363 if (err) 364 return err; 365 366 /* we are ready to enter the normal mode */ 367 err = set_normal_mode(dev); 368 if (err) { 369 netdev_err(dev, "could not enter normal mode\n"); 370 return err; 371 } 372 373 priv->can.state = CAN_STATE_ERROR_ACTIVE; 374 375 return 0; 376 } 377 378 static int sun4i_can_stop(struct net_device *dev) 379 { 380 struct sun4ican_priv *priv = netdev_priv(dev); 381 int err; 382 383 priv->can.state = CAN_STATE_STOPPED; 384 /* we need to enter reset mode */ 385 err = set_reset_mode(dev); 386 if (err) { 387 netdev_err(dev, "could not enter reset mode\n"); 388 return err; 389 } 390 391 /* disable all interrupts */ 392 writel(0, priv->base + SUN4I_REG_INTEN_ADDR); 393 394 return 0; 395 } 396 397 static int sun4ican_set_mode(struct net_device *dev, enum can_mode mode) 398 { 399 int err; 400 401 switch (mode) { 402 case CAN_MODE_START: 403 err = sun4i_can_start(dev); 404 if (err) { 405 netdev_err(dev, "starting CAN controller failed!\n"); 406 return err; 407 } 408 if (netif_queue_stopped(dev)) 409 netif_wake_queue(dev); 410 break; 411 412 default: 413 return -EOPNOTSUPP; 414 } 415 return 0; 416 } 417 418 /* transmit a CAN message 419 * message layout in the sk_buff should be like this: 420 * xx xx xx xx ff ll 00 11 22 33 44 55 66 77 421 * [ can_id ] [flags] [len] [can data (up to 8 bytes] 422 */ 423 static netdev_tx_t sun4ican_start_xmit(struct sk_buff *skb, struct net_device *dev) 424 { 425 struct sun4ican_priv *priv = netdev_priv(dev); 426 struct can_frame *cf = (struct can_frame *)skb->data; 427 u8 dlc; 428 u32 dreg, msg_flag_n; 429 canid_t id; 430 int i; 431 432 if (can_dev_dropped_skb(dev, skb)) 433 return NETDEV_TX_OK; 434 435 netif_stop_queue(dev); 436 437 id = cf->can_id; 438 dlc = cf->len; 439 msg_flag_n = dlc; 440 441 if (id & CAN_RTR_FLAG) 442 msg_flag_n |= SUN4I_MSG_RTR_FLAG; 443 444 if (id & CAN_EFF_FLAG) { 445 msg_flag_n |= SUN4I_MSG_EFF_FLAG; 446 dreg = SUN4I_REG_BUF5_ADDR; 447 writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR); 448 writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR); 449 writel((id >> 5) & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR); 450 writel((id << 3) & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR); 451 } else { 452 dreg = SUN4I_REG_BUF3_ADDR; 453 writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR); 454 writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR); 455 } 456 457 for (i = 0; i < dlc; i++) 458 writel(cf->data[i], priv->base + (dreg + i * 4)); 459 460 writel(msg_flag_n, priv->base + SUN4I_REG_BUF0_ADDR); 461 462 can_put_echo_skb(skb, dev, 0, 0); 463 464 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 465 sun4i_can_write_cmdreg(priv, SUN4I_CMD_SELF_RCV_REQ); 466 else 467 sun4i_can_write_cmdreg(priv, SUN4I_CMD_TRANS_REQ); 468 469 return NETDEV_TX_OK; 470 } 471 472 static void sun4i_can_rx(struct net_device *dev) 473 { 474 struct sun4ican_priv *priv = netdev_priv(dev); 475 struct net_device_stats *stats = &dev->stats; 476 struct can_frame *cf; 477 struct sk_buff *skb; 478 u8 fi; 479 u32 dreg; 480 canid_t id; 481 int i; 482 483 /* create zero'ed CAN frame buffer */ 484 skb = alloc_can_skb(dev, &cf); 485 if (!skb) 486 return; 487 488 fi = readl(priv->base + SUN4I_REG_BUF0_ADDR); 489 cf->len = can_cc_dlc2len(fi & 0x0F); 490 if (fi & SUN4I_MSG_EFF_FLAG) { 491 dreg = SUN4I_REG_BUF5_ADDR; 492 id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 21) | 493 (readl(priv->base + SUN4I_REG_BUF2_ADDR) << 13) | 494 (readl(priv->base + SUN4I_REG_BUF3_ADDR) << 5) | 495 ((readl(priv->base + SUN4I_REG_BUF4_ADDR) >> 3) & 0x1f); 496 id |= CAN_EFF_FLAG; 497 } else { 498 dreg = SUN4I_REG_BUF3_ADDR; 499 id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 3) | 500 ((readl(priv->base + SUN4I_REG_BUF2_ADDR) >> 5) & 0x7); 501 } 502 503 /* remote frame ? */ 504 if (fi & SUN4I_MSG_RTR_FLAG) { 505 id |= CAN_RTR_FLAG; 506 } else { 507 for (i = 0; i < cf->len; i++) 508 cf->data[i] = readl(priv->base + dreg + i * 4); 509 510 stats->rx_bytes += cf->len; 511 } 512 stats->rx_packets++; 513 514 cf->can_id = id; 515 516 sun4i_can_write_cmdreg(priv, SUN4I_CMD_RELEASE_RBUF); 517 518 netif_rx(skb); 519 } 520 521 static int sun4i_can_err(struct net_device *dev, u8 isrc, u8 status) 522 { 523 struct sun4ican_priv *priv = netdev_priv(dev); 524 struct net_device_stats *stats = &dev->stats; 525 struct can_frame *cf; 526 struct sk_buff *skb; 527 enum can_state state = priv->can.state; 528 enum can_state rx_state, tx_state; 529 unsigned int rxerr, txerr, errc; 530 u32 ecc, alc; 531 532 /* we don't skip if alloc fails because we want the stats anyhow */ 533 skb = alloc_can_err_skb(dev, &cf); 534 535 errc = readl(priv->base + SUN4I_REG_ERRC_ADDR); 536 rxerr = (errc >> 16) & 0xFF; 537 txerr = errc & 0xFF; 538 539 if (isrc & SUN4I_INT_DATA_OR) { 540 /* data overrun interrupt */ 541 netdev_dbg(dev, "data overrun interrupt\n"); 542 if (likely(skb)) { 543 cf->can_id |= CAN_ERR_CRTL; 544 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 545 } 546 stats->rx_over_errors++; 547 stats->rx_errors++; 548 549 /* reset the CAN IP by entering reset mode 550 * ignoring timeout error 551 */ 552 set_reset_mode(dev); 553 set_normal_mode(dev); 554 555 /* clear bit */ 556 sun4i_can_write_cmdreg(priv, SUN4I_CMD_CLEAR_OR_FLAG); 557 } 558 if (isrc & SUN4I_INT_ERR_WRN) { 559 /* error warning interrupt */ 560 netdev_dbg(dev, "error warning interrupt\n"); 561 562 if (status & SUN4I_STA_BUS_OFF) 563 state = CAN_STATE_BUS_OFF; 564 else if (status & SUN4I_STA_ERR_STA) 565 state = CAN_STATE_ERROR_WARNING; 566 else 567 state = CAN_STATE_ERROR_ACTIVE; 568 } 569 if (skb && state != CAN_STATE_BUS_OFF) { 570 cf->can_id |= CAN_ERR_CNT; 571 cf->data[6] = txerr; 572 cf->data[7] = rxerr; 573 } 574 if (isrc & SUN4I_INT_BUS_ERR) { 575 /* bus error interrupt */ 576 netdev_dbg(dev, "bus error interrupt\n"); 577 priv->can.can_stats.bus_error++; 578 stats->rx_errors++; 579 580 if (likely(skb)) { 581 ecc = readl(priv->base + SUN4I_REG_STA_ADDR); 582 583 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 584 585 switch (ecc & SUN4I_STA_MASK_ERR) { 586 case SUN4I_STA_BIT_ERR: 587 cf->data[2] |= CAN_ERR_PROT_BIT; 588 break; 589 case SUN4I_STA_FORM_ERR: 590 cf->data[2] |= CAN_ERR_PROT_FORM; 591 break; 592 case SUN4I_STA_STUFF_ERR: 593 cf->data[2] |= CAN_ERR_PROT_STUFF; 594 break; 595 default: 596 cf->data[3] = (ecc & SUN4I_STA_ERR_SEG_CODE) 597 >> 16; 598 break; 599 } 600 /* error occurred during transmission? */ 601 if ((ecc & SUN4I_STA_ERR_DIR) == 0) 602 cf->data[2] |= CAN_ERR_PROT_TX; 603 } 604 } 605 if (isrc & SUN4I_INT_ERR_PASSIVE) { 606 /* error passive interrupt */ 607 netdev_dbg(dev, "error passive interrupt\n"); 608 if (state == CAN_STATE_ERROR_PASSIVE) 609 state = CAN_STATE_ERROR_WARNING; 610 else 611 state = CAN_STATE_ERROR_PASSIVE; 612 } 613 if (isrc & SUN4I_INT_ARB_LOST) { 614 /* arbitration lost interrupt */ 615 netdev_dbg(dev, "arbitration lost interrupt\n"); 616 alc = readl(priv->base + SUN4I_REG_STA_ADDR); 617 priv->can.can_stats.arbitration_lost++; 618 if (likely(skb)) { 619 cf->can_id |= CAN_ERR_LOSTARB; 620 cf->data[0] = (alc >> 8) & 0x1f; 621 } 622 } 623 624 if (state != priv->can.state) { 625 tx_state = txerr >= rxerr ? state : 0; 626 rx_state = txerr <= rxerr ? state : 0; 627 628 if (likely(skb)) 629 can_change_state(dev, cf, tx_state, rx_state); 630 else 631 priv->can.state = state; 632 if (state == CAN_STATE_BUS_OFF) 633 can_bus_off(dev); 634 } 635 636 if (likely(skb)) 637 netif_rx(skb); 638 else 639 return -ENOMEM; 640 641 return 0; 642 } 643 644 static irqreturn_t sun4i_can_interrupt(int irq, void *dev_id) 645 { 646 struct net_device *dev = (struct net_device *)dev_id; 647 struct sun4ican_priv *priv = netdev_priv(dev); 648 struct net_device_stats *stats = &dev->stats; 649 u8 isrc, status; 650 int n = 0; 651 652 while ((isrc = readl(priv->base + SUN4I_REG_INT_ADDR)) && 653 (n < SUN4I_CAN_MAX_IRQ)) { 654 n++; 655 status = readl(priv->base + SUN4I_REG_STA_ADDR); 656 657 if (isrc & SUN4I_INT_WAKEUP) 658 netdev_warn(dev, "wakeup interrupt\n"); 659 660 if (isrc & SUN4I_INT_TBUF_VLD) { 661 /* transmission complete interrupt */ 662 stats->tx_bytes += can_get_echo_skb(dev, 0, NULL); 663 stats->tx_packets++; 664 netif_wake_queue(dev); 665 } 666 if ((isrc & SUN4I_INT_RBUF_VLD) && 667 !(isrc & SUN4I_INT_DATA_OR)) { 668 /* receive interrupt - don't read if overrun occurred */ 669 while (status & SUN4I_STA_RBUF_RDY) { 670 /* RX buffer is not empty */ 671 sun4i_can_rx(dev); 672 status = readl(priv->base + SUN4I_REG_STA_ADDR); 673 } 674 } 675 if (isrc & 676 (SUN4I_INT_DATA_OR | SUN4I_INT_ERR_WRN | SUN4I_INT_BUS_ERR | 677 SUN4I_INT_ERR_PASSIVE | SUN4I_INT_ARB_LOST)) { 678 /* error interrupt */ 679 if (sun4i_can_err(dev, isrc, status)) 680 netdev_err(dev, "can't allocate buffer - clearing pending interrupts\n"); 681 } 682 /* clear interrupts */ 683 writel(isrc, priv->base + SUN4I_REG_INT_ADDR); 684 readl(priv->base + SUN4I_REG_INT_ADDR); 685 } 686 if (n >= SUN4I_CAN_MAX_IRQ) 687 netdev_dbg(dev, "%d messages handled in ISR", n); 688 689 return (n) ? IRQ_HANDLED : IRQ_NONE; 690 } 691 692 static int sun4ican_open(struct net_device *dev) 693 { 694 struct sun4ican_priv *priv = netdev_priv(dev); 695 int err; 696 697 /* common open */ 698 err = open_candev(dev); 699 if (err) 700 return err; 701 702 /* register interrupt handler */ 703 err = request_irq(dev->irq, sun4i_can_interrupt, 0, dev->name, dev); 704 if (err) { 705 netdev_err(dev, "request_irq err: %d\n", err); 706 goto exit_irq; 707 } 708 709 /* software reset deassert */ 710 err = reset_control_deassert(priv->reset); 711 if (err) { 712 netdev_err(dev, "could not deassert CAN reset\n"); 713 goto exit_soft_reset; 714 } 715 716 /* turn on clocking for CAN peripheral block */ 717 err = clk_prepare_enable(priv->clk); 718 if (err) { 719 netdev_err(dev, "could not enable CAN peripheral clock\n"); 720 goto exit_clock; 721 } 722 723 err = sun4i_can_start(dev); 724 if (err) { 725 netdev_err(dev, "could not start CAN peripheral\n"); 726 goto exit_can_start; 727 } 728 729 netif_start_queue(dev); 730 731 return 0; 732 733 exit_can_start: 734 clk_disable_unprepare(priv->clk); 735 exit_clock: 736 reset_control_assert(priv->reset); 737 exit_soft_reset: 738 free_irq(dev->irq, dev); 739 exit_irq: 740 close_candev(dev); 741 return err; 742 } 743 744 static int sun4ican_close(struct net_device *dev) 745 { 746 struct sun4ican_priv *priv = netdev_priv(dev); 747 748 netif_stop_queue(dev); 749 sun4i_can_stop(dev); 750 clk_disable_unprepare(priv->clk); 751 reset_control_assert(priv->reset); 752 753 free_irq(dev->irq, dev); 754 close_candev(dev); 755 756 return 0; 757 } 758 759 static const struct net_device_ops sun4ican_netdev_ops = { 760 .ndo_open = sun4ican_open, 761 .ndo_stop = sun4ican_close, 762 .ndo_start_xmit = sun4ican_start_xmit, 763 }; 764 765 static const struct ethtool_ops sun4ican_ethtool_ops = { 766 .get_ts_info = ethtool_op_get_ts_info, 767 }; 768 769 static const struct sun4ican_quirks sun4ican_quirks_a10 = { 770 .has_reset = false, 771 }; 772 773 static const struct sun4ican_quirks sun4ican_quirks_r40 = { 774 .has_reset = true, 775 }; 776 777 static const struct of_device_id sun4ican_of_match[] = { 778 { 779 .compatible = "allwinner,sun4i-a10-can", 780 .data = &sun4ican_quirks_a10 781 }, { 782 .compatible = "allwinner,sun7i-a20-can", 783 .data = &sun4ican_quirks_a10 784 }, { 785 .compatible = "allwinner,sun8i-r40-can", 786 .data = &sun4ican_quirks_r40 787 }, { 788 /* sentinel */ 789 }, 790 }; 791 792 MODULE_DEVICE_TABLE(of, sun4ican_of_match); 793 794 static int sun4ican_remove(struct platform_device *pdev) 795 { 796 struct net_device *dev = platform_get_drvdata(pdev); 797 798 unregister_netdev(dev); 799 free_candev(dev); 800 801 return 0; 802 } 803 804 static int sun4ican_probe(struct platform_device *pdev) 805 { 806 struct device_node *np = pdev->dev.of_node; 807 struct clk *clk; 808 struct reset_control *reset = NULL; 809 void __iomem *addr; 810 int err, irq; 811 struct net_device *dev; 812 struct sun4ican_priv *priv; 813 const struct sun4ican_quirks *quirks; 814 815 quirks = of_device_get_match_data(&pdev->dev); 816 if (!quirks) { 817 dev_err(&pdev->dev, "failed to determine the quirks to use\n"); 818 err = -ENODEV; 819 goto exit; 820 } 821 822 if (quirks->has_reset) { 823 reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); 824 if (IS_ERR(reset)) { 825 dev_err(&pdev->dev, "unable to request reset\n"); 826 err = PTR_ERR(reset); 827 goto exit; 828 } 829 } 830 831 clk = of_clk_get(np, 0); 832 if (IS_ERR(clk)) { 833 dev_err(&pdev->dev, "unable to request clock\n"); 834 err = -ENODEV; 835 goto exit; 836 } 837 838 irq = platform_get_irq(pdev, 0); 839 if (irq < 0) { 840 err = -ENODEV; 841 goto exit; 842 } 843 844 addr = devm_platform_ioremap_resource(pdev, 0); 845 if (IS_ERR(addr)) { 846 err = PTR_ERR(addr); 847 goto exit; 848 } 849 850 dev = alloc_candev(sizeof(struct sun4ican_priv), 1); 851 if (!dev) { 852 dev_err(&pdev->dev, 853 "could not allocate memory for CAN device\n"); 854 err = -ENOMEM; 855 goto exit; 856 } 857 858 dev->netdev_ops = &sun4ican_netdev_ops; 859 dev->ethtool_ops = &sun4ican_ethtool_ops; 860 dev->irq = irq; 861 dev->flags |= IFF_ECHO; 862 863 priv = netdev_priv(dev); 864 priv->can.clock.freq = clk_get_rate(clk); 865 priv->can.bittiming_const = &sun4ican_bittiming_const; 866 priv->can.do_set_mode = sun4ican_set_mode; 867 priv->can.do_get_berr_counter = sun4ican_get_berr_counter; 868 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING | 869 CAN_CTRLMODE_LISTENONLY | 870 CAN_CTRLMODE_LOOPBACK | 871 CAN_CTRLMODE_3_SAMPLES; 872 priv->base = addr; 873 priv->clk = clk; 874 priv->reset = reset; 875 spin_lock_init(&priv->cmdreg_lock); 876 877 platform_set_drvdata(pdev, dev); 878 SET_NETDEV_DEV(dev, &pdev->dev); 879 880 err = register_candev(dev); 881 if (err) { 882 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 883 DRV_NAME, err); 884 goto exit_free; 885 } 886 887 dev_info(&pdev->dev, "device registered (base=%p, irq=%d)\n", 888 priv->base, dev->irq); 889 890 return 0; 891 892 exit_free: 893 free_candev(dev); 894 exit: 895 return err; 896 } 897 898 static struct platform_driver sun4i_can_driver = { 899 .driver = { 900 .name = DRV_NAME, 901 .of_match_table = sun4ican_of_match, 902 }, 903 .probe = sun4ican_probe, 904 .remove = sun4ican_remove, 905 }; 906 907 module_platform_driver(sun4i_can_driver); 908 909 MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>"); 910 MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>"); 911 MODULE_LICENSE("Dual BSD/GPL"); 912 MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20)"); 913