1 /* 2 * sun4i_can.c - CAN bus controller driver for Allwinner SUN4I&SUN7I based SoCs 3 * 4 * Copyright (C) 2013 Peter Chen 5 * Copyright (C) 2015 Gerhard Bertelsmann 6 * All rights reserved. 7 * 8 * Parts of this software are based on (derived from) the SJA1000 code by: 9 * Copyright (C) 2014 Oliver Hartkopp <oliver.hartkopp@volkswagen.de> 10 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 11 * Copyright (C) 2002-2007 Volkswagen Group Electronic Research 12 * Copyright (C) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33, 13 * 38106 Braunschweig, GERMANY 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. Neither the name of Volkswagen nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * Alternatively, provided that this notice is retained in full, this 28 * software may be distributed under the terms of the GNU General 29 * Public License ("GPL") version 2, in which case the provisions of the 30 * GPL apply INSTEAD OF those given above. 31 * 32 * The provided data structures and external interfaces from this code 33 * are not restricted to be used by modules with a GPL compatible license. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 38 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 39 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 40 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 41 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 46 * DAMAGE. 47 * 48 */ 49 50 #include <linux/netdevice.h> 51 #include <linux/can.h> 52 #include <linux/can/dev.h> 53 #include <linux/can/error.h> 54 #include <linux/can/led.h> 55 #include <linux/clk.h> 56 #include <linux/delay.h> 57 #include <linux/interrupt.h> 58 #include <linux/init.h> 59 #include <linux/io.h> 60 #include <linux/module.h> 61 #include <linux/of.h> 62 #include <linux/of_device.h> 63 #include <linux/platform_device.h> 64 65 #define DRV_NAME "sun4i_can" 66 67 /* Registers address (physical base address 0x01C2BC00) */ 68 #define SUN4I_REG_MSEL_ADDR 0x0000 /* CAN Mode Select */ 69 #define SUN4I_REG_CMD_ADDR 0x0004 /* CAN Command */ 70 #define SUN4I_REG_STA_ADDR 0x0008 /* CAN Status */ 71 #define SUN4I_REG_INT_ADDR 0x000c /* CAN Interrupt Flag */ 72 #define SUN4I_REG_INTEN_ADDR 0x0010 /* CAN Interrupt Enable */ 73 #define SUN4I_REG_BTIME_ADDR 0x0014 /* CAN Bus Timing 0 */ 74 #define SUN4I_REG_TEWL_ADDR 0x0018 /* CAN Tx Error Warning Limit */ 75 #define SUN4I_REG_ERRC_ADDR 0x001c /* CAN Error Counter */ 76 #define SUN4I_REG_RMCNT_ADDR 0x0020 /* CAN Receive Message Counter */ 77 #define SUN4I_REG_RBUFSA_ADDR 0x0024 /* CAN Receive Buffer Start Address */ 78 #define SUN4I_REG_BUF0_ADDR 0x0040 /* CAN Tx/Rx Buffer 0 */ 79 #define SUN4I_REG_BUF1_ADDR 0x0044 /* CAN Tx/Rx Buffer 1 */ 80 #define SUN4I_REG_BUF2_ADDR 0x0048 /* CAN Tx/Rx Buffer 2 */ 81 #define SUN4I_REG_BUF3_ADDR 0x004c /* CAN Tx/Rx Buffer 3 */ 82 #define SUN4I_REG_BUF4_ADDR 0x0050 /* CAN Tx/Rx Buffer 4 */ 83 #define SUN4I_REG_BUF5_ADDR 0x0054 /* CAN Tx/Rx Buffer 5 */ 84 #define SUN4I_REG_BUF6_ADDR 0x0058 /* CAN Tx/Rx Buffer 6 */ 85 #define SUN4I_REG_BUF7_ADDR 0x005c /* CAN Tx/Rx Buffer 7 */ 86 #define SUN4I_REG_BUF8_ADDR 0x0060 /* CAN Tx/Rx Buffer 8 */ 87 #define SUN4I_REG_BUF9_ADDR 0x0064 /* CAN Tx/Rx Buffer 9 */ 88 #define SUN4I_REG_BUF10_ADDR 0x0068 /* CAN Tx/Rx Buffer 10 */ 89 #define SUN4I_REG_BUF11_ADDR 0x006c /* CAN Tx/Rx Buffer 11 */ 90 #define SUN4I_REG_BUF12_ADDR 0x0070 /* CAN Tx/Rx Buffer 12 */ 91 #define SUN4I_REG_ACPC_ADDR 0x0040 /* CAN Acceptance Code 0 */ 92 #define SUN4I_REG_ACPM_ADDR 0x0044 /* CAN Acceptance Mask 0 */ 93 #define SUN4I_REG_RBUF_RBACK_START_ADDR 0x0180 /* CAN transmit buffer start */ 94 #define SUN4I_REG_RBUF_RBACK_END_ADDR 0x01b0 /* CAN transmit buffer end */ 95 96 /* Controller Register Description */ 97 98 /* mode select register (r/w) 99 * offset:0x0000 default:0x0000_0001 100 */ 101 #define SUN4I_MSEL_SLEEP_MODE (0x01 << 4) /* write in reset mode */ 102 #define SUN4I_MSEL_WAKE_UP (0x00 << 4) 103 #define SUN4I_MSEL_SINGLE_FILTER (0x01 << 3) /* write in reset mode */ 104 #define SUN4I_MSEL_DUAL_FILTERS (0x00 << 3) 105 #define SUN4I_MSEL_LOOPBACK_MODE BIT(2) 106 #define SUN4I_MSEL_LISTEN_ONLY_MODE BIT(1) 107 #define SUN4I_MSEL_RESET_MODE BIT(0) 108 109 /* command register (w) 110 * offset:0x0004 default:0x0000_0000 111 */ 112 #define SUN4I_CMD_BUS_OFF_REQ BIT(5) 113 #define SUN4I_CMD_SELF_RCV_REQ BIT(4) 114 #define SUN4I_CMD_CLEAR_OR_FLAG BIT(3) 115 #define SUN4I_CMD_RELEASE_RBUF BIT(2) 116 #define SUN4I_CMD_ABORT_REQ BIT(1) 117 #define SUN4I_CMD_TRANS_REQ BIT(0) 118 119 /* status register (r) 120 * offset:0x0008 default:0x0000_003c 121 */ 122 #define SUN4I_STA_BIT_ERR (0x00 << 22) 123 #define SUN4I_STA_FORM_ERR (0x01 << 22) 124 #define SUN4I_STA_STUFF_ERR (0x02 << 22) 125 #define SUN4I_STA_OTHER_ERR (0x03 << 22) 126 #define SUN4I_STA_MASK_ERR (0x03 << 22) 127 #define SUN4I_STA_ERR_DIR BIT(21) 128 #define SUN4I_STA_ERR_SEG_CODE (0x1f << 16) 129 #define SUN4I_STA_START (0x03 << 16) 130 #define SUN4I_STA_ID28_21 (0x02 << 16) 131 #define SUN4I_STA_ID20_18 (0x06 << 16) 132 #define SUN4I_STA_SRTR (0x04 << 16) 133 #define SUN4I_STA_IDE (0x05 << 16) 134 #define SUN4I_STA_ID17_13 (0x07 << 16) 135 #define SUN4I_STA_ID12_5 (0x0f << 16) 136 #define SUN4I_STA_ID4_0 (0x0e << 16) 137 #define SUN4I_STA_RTR (0x0c << 16) 138 #define SUN4I_STA_RB1 (0x0d << 16) 139 #define SUN4I_STA_RB0 (0x09 << 16) 140 #define SUN4I_STA_DLEN (0x0b << 16) 141 #define SUN4I_STA_DATA_FIELD (0x0a << 16) 142 #define SUN4I_STA_CRC_SEQUENCE (0x08 << 16) 143 #define SUN4I_STA_CRC_DELIMITER (0x18 << 16) 144 #define SUN4I_STA_ACK (0x19 << 16) 145 #define SUN4I_STA_ACK_DELIMITER (0x1b << 16) 146 #define SUN4I_STA_END (0x1a << 16) 147 #define SUN4I_STA_INTERMISSION (0x12 << 16) 148 #define SUN4I_STA_ACTIVE_ERROR (0x11 << 16) 149 #define SUN4I_STA_PASSIVE_ERROR (0x16 << 16) 150 #define SUN4I_STA_TOLERATE_DOMINANT_BITS (0x13 << 16) 151 #define SUN4I_STA_ERROR_DELIMITER (0x17 << 16) 152 #define SUN4I_STA_OVERLOAD (0x1c << 16) 153 #define SUN4I_STA_BUS_OFF BIT(7) 154 #define SUN4I_STA_ERR_STA BIT(6) 155 #define SUN4I_STA_TRANS_BUSY BIT(5) 156 #define SUN4I_STA_RCV_BUSY BIT(4) 157 #define SUN4I_STA_TRANS_OVER BIT(3) 158 #define SUN4I_STA_TBUF_RDY BIT(2) 159 #define SUN4I_STA_DATA_ORUN BIT(1) 160 #define SUN4I_STA_RBUF_RDY BIT(0) 161 162 /* interrupt register (r) 163 * offset:0x000c default:0x0000_0000 164 */ 165 #define SUN4I_INT_BUS_ERR BIT(7) 166 #define SUN4I_INT_ARB_LOST BIT(6) 167 #define SUN4I_INT_ERR_PASSIVE BIT(5) 168 #define SUN4I_INT_WAKEUP BIT(4) 169 #define SUN4I_INT_DATA_OR BIT(3) 170 #define SUN4I_INT_ERR_WRN BIT(2) 171 #define SUN4I_INT_TBUF_VLD BIT(1) 172 #define SUN4I_INT_RBUF_VLD BIT(0) 173 174 /* interrupt enable register (r/w) 175 * offset:0x0010 default:0x0000_0000 176 */ 177 #define SUN4I_INTEN_BERR BIT(7) 178 #define SUN4I_INTEN_ARB_LOST BIT(6) 179 #define SUN4I_INTEN_ERR_PASSIVE BIT(5) 180 #define SUN4I_INTEN_WAKEUP BIT(4) 181 #define SUN4I_INTEN_OR BIT(3) 182 #define SUN4I_INTEN_ERR_WRN BIT(2) 183 #define SUN4I_INTEN_TX BIT(1) 184 #define SUN4I_INTEN_RX BIT(0) 185 186 /* error code */ 187 #define SUN4I_ERR_INRCV (0x1 << 5) 188 #define SUN4I_ERR_INTRANS (0x0 << 5) 189 190 /* filter mode */ 191 #define SUN4I_FILTER_CLOSE 0 192 #define SUN4I_SINGLE_FLTER_MODE 1 193 #define SUN4I_DUAL_FILTER_MODE 2 194 195 /* message buffer flags */ 196 #define SUN4I_MSG_EFF_FLAG BIT(7) 197 #define SUN4I_MSG_RTR_FLAG BIT(6) 198 199 /* max. number of interrupts handled in ISR */ 200 #define SUN4I_CAN_MAX_IRQ 20 201 #define SUN4I_MODE_MAX_RETRIES 100 202 203 struct sun4ican_priv { 204 struct can_priv can; 205 void __iomem *base; 206 struct clk *clk; 207 spinlock_t cmdreg_lock; /* lock for concurrent cmd register writes */ 208 }; 209 210 static const struct can_bittiming_const sun4ican_bittiming_const = { 211 .name = DRV_NAME, 212 .tseg1_min = 1, 213 .tseg1_max = 16, 214 .tseg2_min = 1, 215 .tseg2_max = 8, 216 .sjw_max = 4, 217 .brp_min = 1, 218 .brp_max = 64, 219 .brp_inc = 1, 220 }; 221 222 static void sun4i_can_write_cmdreg(struct sun4ican_priv *priv, u8 val) 223 { 224 unsigned long flags; 225 226 spin_lock_irqsave(&priv->cmdreg_lock, flags); 227 writel(val, priv->base + SUN4I_REG_CMD_ADDR); 228 spin_unlock_irqrestore(&priv->cmdreg_lock, flags); 229 } 230 231 static int set_normal_mode(struct net_device *dev) 232 { 233 struct sun4ican_priv *priv = netdev_priv(dev); 234 int retry = SUN4I_MODE_MAX_RETRIES; 235 u32 mod_reg_val = 0; 236 237 do { 238 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); 239 mod_reg_val &= ~SUN4I_MSEL_RESET_MODE; 240 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); 241 } while (retry-- && (mod_reg_val & SUN4I_MSEL_RESET_MODE)); 242 243 if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) { 244 netdev_err(dev, 245 "setting controller into normal mode failed!\n"); 246 return -ETIMEDOUT; 247 } 248 249 return 0; 250 } 251 252 static int set_reset_mode(struct net_device *dev) 253 { 254 struct sun4ican_priv *priv = netdev_priv(dev); 255 int retry = SUN4I_MODE_MAX_RETRIES; 256 u32 mod_reg_val = 0; 257 258 do { 259 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); 260 mod_reg_val |= SUN4I_MSEL_RESET_MODE; 261 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); 262 } while (retry-- && !(mod_reg_val & SUN4I_MSEL_RESET_MODE)); 263 264 if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) & 265 SUN4I_MSEL_RESET_MODE)) { 266 netdev_err(dev, "setting controller into reset mode failed!\n"); 267 return -ETIMEDOUT; 268 } 269 270 return 0; 271 } 272 273 /* bittiming is called in reset_mode only */ 274 static int sun4ican_set_bittiming(struct net_device *dev) 275 { 276 struct sun4ican_priv *priv = netdev_priv(dev); 277 struct can_bittiming *bt = &priv->can.bittiming; 278 u32 cfg; 279 280 cfg = ((bt->brp - 1) & 0x3FF) | 281 (((bt->sjw - 1) & 0x3) << 14) | 282 (((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) << 16) | 283 (((bt->phase_seg2 - 1) & 0x7) << 20); 284 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 285 cfg |= 0x800000; 286 287 netdev_dbg(dev, "setting BITTIMING=0x%08x\n", cfg); 288 writel(cfg, priv->base + SUN4I_REG_BTIME_ADDR); 289 290 return 0; 291 } 292 293 static int sun4ican_get_berr_counter(const struct net_device *dev, 294 struct can_berr_counter *bec) 295 { 296 struct sun4ican_priv *priv = netdev_priv(dev); 297 u32 errors; 298 int err; 299 300 err = clk_prepare_enable(priv->clk); 301 if (err) { 302 netdev_err(dev, "could not enable clock\n"); 303 return err; 304 } 305 306 errors = readl(priv->base + SUN4I_REG_ERRC_ADDR); 307 308 bec->txerr = errors & 0xFF; 309 bec->rxerr = (errors >> 16) & 0xFF; 310 311 clk_disable_unprepare(priv->clk); 312 313 return 0; 314 } 315 316 static int sun4i_can_start(struct net_device *dev) 317 { 318 struct sun4ican_priv *priv = netdev_priv(dev); 319 int err; 320 u32 mod_reg_val; 321 322 /* we need to enter the reset mode */ 323 err = set_reset_mode(dev); 324 if (err) { 325 netdev_err(dev, "could not enter reset mode\n"); 326 return err; 327 } 328 329 /* set filters - we accept all */ 330 writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR); 331 writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR); 332 333 /* clear error counters and error code capture */ 334 writel(0, priv->base + SUN4I_REG_ERRC_ADDR); 335 336 /* enable interrupts */ 337 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 338 writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR); 339 else 340 writel(0xFF & ~SUN4I_INTEN_BERR, 341 priv->base + SUN4I_REG_INTEN_ADDR); 342 343 /* enter the selected mode */ 344 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); 345 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 346 mod_reg_val |= SUN4I_MSEL_LOOPBACK_MODE; 347 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 348 mod_reg_val |= SUN4I_MSEL_LISTEN_ONLY_MODE; 349 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); 350 351 err = sun4ican_set_bittiming(dev); 352 if (err) 353 return err; 354 355 /* we are ready to enter the normal mode */ 356 err = set_normal_mode(dev); 357 if (err) { 358 netdev_err(dev, "could not enter normal mode\n"); 359 return err; 360 } 361 362 priv->can.state = CAN_STATE_ERROR_ACTIVE; 363 364 return 0; 365 } 366 367 static int sun4i_can_stop(struct net_device *dev) 368 { 369 struct sun4ican_priv *priv = netdev_priv(dev); 370 int err; 371 372 priv->can.state = CAN_STATE_STOPPED; 373 /* we need to enter reset mode */ 374 err = set_reset_mode(dev); 375 if (err) { 376 netdev_err(dev, "could not enter reset mode\n"); 377 return err; 378 } 379 380 /* disable all interrupts */ 381 writel(0, priv->base + SUN4I_REG_INTEN_ADDR); 382 383 return 0; 384 } 385 386 static int sun4ican_set_mode(struct net_device *dev, enum can_mode mode) 387 { 388 int err; 389 390 switch (mode) { 391 case CAN_MODE_START: 392 err = sun4i_can_start(dev); 393 if (err) { 394 netdev_err(dev, "starting CAN controller failed!\n"); 395 return err; 396 } 397 if (netif_queue_stopped(dev)) 398 netif_wake_queue(dev); 399 break; 400 401 default: 402 return -EOPNOTSUPP; 403 } 404 return 0; 405 } 406 407 /* transmit a CAN message 408 * message layout in the sk_buff should be like this: 409 * xx xx xx xx ff ll 00 11 22 33 44 55 66 77 410 * [ can_id ] [flags] [len] [can data (up to 8 bytes] 411 */ 412 static netdev_tx_t sun4ican_start_xmit(struct sk_buff *skb, struct net_device *dev) 413 { 414 struct sun4ican_priv *priv = netdev_priv(dev); 415 struct can_frame *cf = (struct can_frame *)skb->data; 416 u8 dlc; 417 u32 dreg, msg_flag_n; 418 canid_t id; 419 int i; 420 421 if (can_dropped_invalid_skb(dev, skb)) 422 return NETDEV_TX_OK; 423 424 netif_stop_queue(dev); 425 426 id = cf->can_id; 427 dlc = cf->len; 428 msg_flag_n = dlc; 429 430 if (id & CAN_RTR_FLAG) 431 msg_flag_n |= SUN4I_MSG_RTR_FLAG; 432 433 if (id & CAN_EFF_FLAG) { 434 msg_flag_n |= SUN4I_MSG_EFF_FLAG; 435 dreg = SUN4I_REG_BUF5_ADDR; 436 writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR); 437 writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR); 438 writel((id >> 5) & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR); 439 writel((id << 3) & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR); 440 } else { 441 dreg = SUN4I_REG_BUF3_ADDR; 442 writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR); 443 writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR); 444 } 445 446 for (i = 0; i < dlc; i++) 447 writel(cf->data[i], priv->base + (dreg + i * 4)); 448 449 writel(msg_flag_n, priv->base + SUN4I_REG_BUF0_ADDR); 450 451 can_put_echo_skb(skb, dev, 0); 452 453 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 454 sun4i_can_write_cmdreg(priv, SUN4I_CMD_SELF_RCV_REQ); 455 else 456 sun4i_can_write_cmdreg(priv, SUN4I_CMD_TRANS_REQ); 457 458 return NETDEV_TX_OK; 459 } 460 461 static void sun4i_can_rx(struct net_device *dev) 462 { 463 struct sun4ican_priv *priv = netdev_priv(dev); 464 struct net_device_stats *stats = &dev->stats; 465 struct can_frame *cf; 466 struct sk_buff *skb; 467 u8 fi; 468 u32 dreg; 469 canid_t id; 470 int i; 471 472 /* create zero'ed CAN frame buffer */ 473 skb = alloc_can_skb(dev, &cf); 474 if (!skb) 475 return; 476 477 fi = readl(priv->base + SUN4I_REG_BUF0_ADDR); 478 cf->len = can_cc_dlc2len(fi & 0x0F); 479 if (fi & SUN4I_MSG_EFF_FLAG) { 480 dreg = SUN4I_REG_BUF5_ADDR; 481 id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 21) | 482 (readl(priv->base + SUN4I_REG_BUF2_ADDR) << 13) | 483 (readl(priv->base + SUN4I_REG_BUF3_ADDR) << 5) | 484 ((readl(priv->base + SUN4I_REG_BUF4_ADDR) >> 3) & 0x1f); 485 id |= CAN_EFF_FLAG; 486 } else { 487 dreg = SUN4I_REG_BUF3_ADDR; 488 id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 3) | 489 ((readl(priv->base + SUN4I_REG_BUF2_ADDR) >> 5) & 0x7); 490 } 491 492 /* remote frame ? */ 493 if (fi & SUN4I_MSG_RTR_FLAG) 494 id |= CAN_RTR_FLAG; 495 else 496 for (i = 0; i < cf->len; i++) 497 cf->data[i] = readl(priv->base + dreg + i * 4); 498 499 cf->can_id = id; 500 501 sun4i_can_write_cmdreg(priv, SUN4I_CMD_RELEASE_RBUF); 502 503 stats->rx_packets++; 504 stats->rx_bytes += cf->len; 505 netif_rx(skb); 506 507 can_led_event(dev, CAN_LED_EVENT_RX); 508 } 509 510 static int sun4i_can_err(struct net_device *dev, u8 isrc, u8 status) 511 { 512 struct sun4ican_priv *priv = netdev_priv(dev); 513 struct net_device_stats *stats = &dev->stats; 514 struct can_frame *cf; 515 struct sk_buff *skb; 516 enum can_state state = priv->can.state; 517 enum can_state rx_state, tx_state; 518 unsigned int rxerr, txerr, errc; 519 u32 ecc, alc; 520 521 /* we don't skip if alloc fails because we want the stats anyhow */ 522 skb = alloc_can_err_skb(dev, &cf); 523 524 errc = readl(priv->base + SUN4I_REG_ERRC_ADDR); 525 rxerr = (errc >> 16) & 0xFF; 526 txerr = errc & 0xFF; 527 528 if (skb) { 529 cf->data[6] = txerr; 530 cf->data[7] = rxerr; 531 } 532 533 if (isrc & SUN4I_INT_DATA_OR) { 534 /* data overrun interrupt */ 535 netdev_dbg(dev, "data overrun interrupt\n"); 536 if (likely(skb)) { 537 cf->can_id |= CAN_ERR_CRTL; 538 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 539 } 540 stats->rx_over_errors++; 541 stats->rx_errors++; 542 543 /* reset the CAN IP by entering reset mode 544 * ignoring timeout error 545 */ 546 set_reset_mode(dev); 547 set_normal_mode(dev); 548 549 /* clear bit */ 550 sun4i_can_write_cmdreg(priv, SUN4I_CMD_CLEAR_OR_FLAG); 551 } 552 if (isrc & SUN4I_INT_ERR_WRN) { 553 /* error warning interrupt */ 554 netdev_dbg(dev, "error warning interrupt\n"); 555 556 if (status & SUN4I_STA_BUS_OFF) 557 state = CAN_STATE_BUS_OFF; 558 else if (status & SUN4I_STA_ERR_STA) 559 state = CAN_STATE_ERROR_WARNING; 560 else 561 state = CAN_STATE_ERROR_ACTIVE; 562 } 563 if (isrc & SUN4I_INT_BUS_ERR) { 564 /* bus error interrupt */ 565 netdev_dbg(dev, "bus error interrupt\n"); 566 priv->can.can_stats.bus_error++; 567 stats->rx_errors++; 568 569 if (likely(skb)) { 570 ecc = readl(priv->base + SUN4I_REG_STA_ADDR); 571 572 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 573 574 switch (ecc & SUN4I_STA_MASK_ERR) { 575 case SUN4I_STA_BIT_ERR: 576 cf->data[2] |= CAN_ERR_PROT_BIT; 577 break; 578 case SUN4I_STA_FORM_ERR: 579 cf->data[2] |= CAN_ERR_PROT_FORM; 580 break; 581 case SUN4I_STA_STUFF_ERR: 582 cf->data[2] |= CAN_ERR_PROT_STUFF; 583 break; 584 default: 585 cf->data[3] = (ecc & SUN4I_STA_ERR_SEG_CODE) 586 >> 16; 587 break; 588 } 589 /* error occurred during transmission? */ 590 if ((ecc & SUN4I_STA_ERR_DIR) == 0) 591 cf->data[2] |= CAN_ERR_PROT_TX; 592 } 593 } 594 if (isrc & SUN4I_INT_ERR_PASSIVE) { 595 /* error passive interrupt */ 596 netdev_dbg(dev, "error passive interrupt\n"); 597 if (state == CAN_STATE_ERROR_PASSIVE) 598 state = CAN_STATE_ERROR_WARNING; 599 else 600 state = CAN_STATE_ERROR_PASSIVE; 601 } 602 if (isrc & SUN4I_INT_ARB_LOST) { 603 /* arbitration lost interrupt */ 604 netdev_dbg(dev, "arbitration lost interrupt\n"); 605 alc = readl(priv->base + SUN4I_REG_STA_ADDR); 606 priv->can.can_stats.arbitration_lost++; 607 if (likely(skb)) { 608 cf->can_id |= CAN_ERR_LOSTARB; 609 cf->data[0] = (alc >> 8) & 0x1f; 610 } 611 } 612 613 if (state != priv->can.state) { 614 tx_state = txerr >= rxerr ? state : 0; 615 rx_state = txerr <= rxerr ? state : 0; 616 617 if (likely(skb)) 618 can_change_state(dev, cf, tx_state, rx_state); 619 else 620 priv->can.state = state; 621 if (state == CAN_STATE_BUS_OFF) 622 can_bus_off(dev); 623 } 624 625 if (likely(skb)) { 626 stats->rx_packets++; 627 stats->rx_bytes += cf->len; 628 netif_rx(skb); 629 } else { 630 return -ENOMEM; 631 } 632 633 return 0; 634 } 635 636 static irqreturn_t sun4i_can_interrupt(int irq, void *dev_id) 637 { 638 struct net_device *dev = (struct net_device *)dev_id; 639 struct sun4ican_priv *priv = netdev_priv(dev); 640 struct net_device_stats *stats = &dev->stats; 641 u8 isrc, status; 642 int n = 0; 643 644 while ((isrc = readl(priv->base + SUN4I_REG_INT_ADDR)) && 645 (n < SUN4I_CAN_MAX_IRQ)) { 646 n++; 647 status = readl(priv->base + SUN4I_REG_STA_ADDR); 648 649 if (isrc & SUN4I_INT_WAKEUP) 650 netdev_warn(dev, "wakeup interrupt\n"); 651 652 if (isrc & SUN4I_INT_TBUF_VLD) { 653 /* transmission complete interrupt */ 654 stats->tx_bytes += 655 readl(priv->base + 656 SUN4I_REG_RBUF_RBACK_START_ADDR) & 0xf; 657 stats->tx_packets++; 658 can_get_echo_skb(dev, 0); 659 netif_wake_queue(dev); 660 can_led_event(dev, CAN_LED_EVENT_TX); 661 } 662 if ((isrc & SUN4I_INT_RBUF_VLD) && 663 !(isrc & SUN4I_INT_DATA_OR)) { 664 /* receive interrupt - don't read if overrun occurred */ 665 while (status & SUN4I_STA_RBUF_RDY) { 666 /* RX buffer is not empty */ 667 sun4i_can_rx(dev); 668 status = readl(priv->base + SUN4I_REG_STA_ADDR); 669 } 670 } 671 if (isrc & 672 (SUN4I_INT_DATA_OR | SUN4I_INT_ERR_WRN | SUN4I_INT_BUS_ERR | 673 SUN4I_INT_ERR_PASSIVE | SUN4I_INT_ARB_LOST)) { 674 /* error interrupt */ 675 if (sun4i_can_err(dev, isrc, status)) 676 netdev_err(dev, "can't allocate buffer - clearing pending interrupts\n"); 677 } 678 /* clear interrupts */ 679 writel(isrc, priv->base + SUN4I_REG_INT_ADDR); 680 readl(priv->base + SUN4I_REG_INT_ADDR); 681 } 682 if (n >= SUN4I_CAN_MAX_IRQ) 683 netdev_dbg(dev, "%d messages handled in ISR", n); 684 685 return (n) ? IRQ_HANDLED : IRQ_NONE; 686 } 687 688 static int sun4ican_open(struct net_device *dev) 689 { 690 struct sun4ican_priv *priv = netdev_priv(dev); 691 int err; 692 693 /* common open */ 694 err = open_candev(dev); 695 if (err) 696 return err; 697 698 /* register interrupt handler */ 699 err = request_irq(dev->irq, sun4i_can_interrupt, 0, dev->name, dev); 700 if (err) { 701 netdev_err(dev, "request_irq err: %d\n", err); 702 goto exit_irq; 703 } 704 705 /* turn on clocking for CAN peripheral block */ 706 err = clk_prepare_enable(priv->clk); 707 if (err) { 708 netdev_err(dev, "could not enable CAN peripheral clock\n"); 709 goto exit_clock; 710 } 711 712 err = sun4i_can_start(dev); 713 if (err) { 714 netdev_err(dev, "could not start CAN peripheral\n"); 715 goto exit_can_start; 716 } 717 718 can_led_event(dev, CAN_LED_EVENT_OPEN); 719 netif_start_queue(dev); 720 721 return 0; 722 723 exit_can_start: 724 clk_disable_unprepare(priv->clk); 725 exit_clock: 726 free_irq(dev->irq, dev); 727 exit_irq: 728 close_candev(dev); 729 return err; 730 } 731 732 static int sun4ican_close(struct net_device *dev) 733 { 734 struct sun4ican_priv *priv = netdev_priv(dev); 735 736 netif_stop_queue(dev); 737 sun4i_can_stop(dev); 738 clk_disable_unprepare(priv->clk); 739 740 free_irq(dev->irq, dev); 741 close_candev(dev); 742 can_led_event(dev, CAN_LED_EVENT_STOP); 743 744 return 0; 745 } 746 747 static const struct net_device_ops sun4ican_netdev_ops = { 748 .ndo_open = sun4ican_open, 749 .ndo_stop = sun4ican_close, 750 .ndo_start_xmit = sun4ican_start_xmit, 751 }; 752 753 static const struct of_device_id sun4ican_of_match[] = { 754 {.compatible = "allwinner,sun4i-a10-can"}, 755 {}, 756 }; 757 758 MODULE_DEVICE_TABLE(of, sun4ican_of_match); 759 760 static int sun4ican_remove(struct platform_device *pdev) 761 { 762 struct net_device *dev = platform_get_drvdata(pdev); 763 764 unregister_netdev(dev); 765 free_candev(dev); 766 767 return 0; 768 } 769 770 static int sun4ican_probe(struct platform_device *pdev) 771 { 772 struct device_node *np = pdev->dev.of_node; 773 struct clk *clk; 774 void __iomem *addr; 775 int err, irq; 776 struct net_device *dev; 777 struct sun4ican_priv *priv; 778 779 clk = of_clk_get(np, 0); 780 if (IS_ERR(clk)) { 781 dev_err(&pdev->dev, "unable to request clock\n"); 782 err = -ENODEV; 783 goto exit; 784 } 785 786 irq = platform_get_irq(pdev, 0); 787 if (irq < 0) { 788 err = -ENODEV; 789 goto exit; 790 } 791 792 addr = devm_platform_ioremap_resource(pdev, 0); 793 if (IS_ERR(addr)) { 794 err = PTR_ERR(addr); 795 goto exit; 796 } 797 798 dev = alloc_candev(sizeof(struct sun4ican_priv), 1); 799 if (!dev) { 800 dev_err(&pdev->dev, 801 "could not allocate memory for CAN device\n"); 802 err = -ENOMEM; 803 goto exit; 804 } 805 806 dev->netdev_ops = &sun4ican_netdev_ops; 807 dev->irq = irq; 808 dev->flags |= IFF_ECHO; 809 810 priv = netdev_priv(dev); 811 priv->can.clock.freq = clk_get_rate(clk); 812 priv->can.bittiming_const = &sun4ican_bittiming_const; 813 priv->can.do_set_mode = sun4ican_set_mode; 814 priv->can.do_get_berr_counter = sun4ican_get_berr_counter; 815 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING | 816 CAN_CTRLMODE_LISTENONLY | 817 CAN_CTRLMODE_LOOPBACK | 818 CAN_CTRLMODE_3_SAMPLES; 819 priv->base = addr; 820 priv->clk = clk; 821 spin_lock_init(&priv->cmdreg_lock); 822 823 platform_set_drvdata(pdev, dev); 824 SET_NETDEV_DEV(dev, &pdev->dev); 825 826 err = register_candev(dev); 827 if (err) { 828 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 829 DRV_NAME, err); 830 goto exit_free; 831 } 832 devm_can_led_init(dev); 833 834 dev_info(&pdev->dev, "device registered (base=%p, irq=%d)\n", 835 priv->base, dev->irq); 836 837 return 0; 838 839 exit_free: 840 free_candev(dev); 841 exit: 842 return err; 843 } 844 845 static struct platform_driver sun4i_can_driver = { 846 .driver = { 847 .name = DRV_NAME, 848 .of_match_table = sun4ican_of_match, 849 }, 850 .probe = sun4ican_probe, 851 .remove = sun4ican_remove, 852 }; 853 854 module_platform_driver(sun4i_can_driver); 855 856 MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>"); 857 MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>"); 858 MODULE_LICENSE("Dual BSD/GPL"); 859 MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20)"); 860