1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver 4 // 5 // Copyright (c) 2019, 2020 Pengutronix, 6 // Marc Kleine-Budde <kernel@pengutronix.de> 7 // 8 9 #include "mcp251xfd.h" 10 11 #include <asm/unaligned.h> 12 13 static const struct regmap_config mcp251xfd_regmap_crc; 14 15 static int 16 mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count) 17 { 18 struct spi_device *spi = context; 19 20 return spi_write(spi, data, count); 21 } 22 23 static int 24 mcp251xfd_regmap_nocrc_gather_write(void *context, 25 const void *reg, size_t reg_len, 26 const void *val, size_t val_len) 27 { 28 struct spi_device *spi = context; 29 struct mcp251xfd_priv *priv = spi_get_drvdata(spi); 30 struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx; 31 struct spi_transfer xfer[] = { 32 { 33 .tx_buf = buf_tx, 34 .len = sizeof(buf_tx->cmd) + val_len, 35 }, 36 }; 37 38 BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16)); 39 40 if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) && 41 reg_len != sizeof(buf_tx->cmd.cmd)) 42 return -EINVAL; 43 44 memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd)); 45 memcpy(buf_tx->data, val, val_len); 46 47 return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); 48 } 49 50 static inline bool mcp251xfd_update_bits_read_reg(unsigned int reg) 51 { 52 switch (reg) { 53 case MCP251XFD_REG_INT: 54 case MCP251XFD_REG_TEFCON: 55 case MCP251XFD_REG_FIFOCON(MCP251XFD_RX_FIFO(0)): 56 case MCP251XFD_REG_FLTCON(0): 57 case MCP251XFD_REG_ECCSTAT: 58 case MCP251XFD_REG_CRC: 59 return false; 60 case MCP251XFD_REG_CON: 61 case MCP251XFD_REG_FIFOSTA(MCP251XFD_RX_FIFO(0)): 62 case MCP251XFD_REG_OSC: 63 case MCP251XFD_REG_ECCCON: 64 return true; 65 default: 66 WARN(1, "Status of reg 0x%04x unknown.\n", reg); 67 } 68 69 return true; 70 } 71 72 static int 73 mcp251xfd_regmap_nocrc_update_bits(void *context, unsigned int reg, 74 unsigned int mask, unsigned int val) 75 { 76 struct spi_device *spi = context; 77 struct mcp251xfd_priv *priv = spi_get_drvdata(spi); 78 struct mcp251xfd_map_buf_nocrc *buf_rx = priv->map_buf_nocrc_rx; 79 struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx; 80 __le32 orig_le32 = 0, mask_le32, val_le32, tmp_le32; 81 u8 first_byte, last_byte, len; 82 int err; 83 84 BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16)); 85 BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16)); 86 87 if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) && 88 mask == 0) 89 return -EINVAL; 90 91 first_byte = mcp251xfd_first_byte_set(mask); 92 last_byte = mcp251xfd_last_byte_set(mask); 93 len = last_byte - first_byte + 1; 94 95 if (mcp251xfd_update_bits_read_reg(reg)) { 96 struct spi_transfer xfer[2] = { }; 97 struct spi_message msg; 98 99 spi_message_init(&msg); 100 spi_message_add_tail(&xfer[0], &msg); 101 102 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) { 103 xfer[0].tx_buf = buf_tx; 104 xfer[0].len = sizeof(buf_tx->cmd); 105 106 xfer[1].rx_buf = buf_rx->data; 107 xfer[1].len = len; 108 spi_message_add_tail(&xfer[1], &msg); 109 } else { 110 xfer[0].tx_buf = buf_tx; 111 xfer[0].rx_buf = buf_rx; 112 xfer[0].len = sizeof(buf_tx->cmd) + len; 113 114 if (MCP251XFD_SANITIZE_SPI) 115 memset(buf_tx->data, 0x0, len); 116 } 117 118 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, reg + first_byte); 119 err = spi_sync(spi, &msg); 120 if (err) 121 return err; 122 123 memcpy(&orig_le32, buf_rx->data, len); 124 } 125 126 mask_le32 = cpu_to_le32(mask >> BITS_PER_BYTE * first_byte); 127 val_le32 = cpu_to_le32(val >> BITS_PER_BYTE * first_byte); 128 129 tmp_le32 = orig_le32 & ~mask_le32; 130 tmp_le32 |= val_le32 & mask_le32; 131 132 mcp251xfd_spi_cmd_write_nocrc(&buf_tx->cmd, reg + first_byte); 133 memcpy(buf_tx->data, &tmp_le32, len); 134 135 return spi_write(spi, buf_tx, sizeof(buf_tx->cmd) + len); 136 } 137 138 static int 139 mcp251xfd_regmap_nocrc_read(void *context, 140 const void *reg, size_t reg_len, 141 void *val_buf, size_t val_len) 142 { 143 struct spi_device *spi = context; 144 struct mcp251xfd_priv *priv = spi_get_drvdata(spi); 145 struct mcp251xfd_map_buf_nocrc *buf_rx = priv->map_buf_nocrc_rx; 146 struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx; 147 struct spi_transfer xfer[2] = { }; 148 struct spi_message msg; 149 int err; 150 151 BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16)); 152 BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16)); 153 154 if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) && 155 reg_len != sizeof(buf_tx->cmd.cmd)) 156 return -EINVAL; 157 158 spi_message_init(&msg); 159 spi_message_add_tail(&xfer[0], &msg); 160 161 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) { 162 xfer[0].tx_buf = reg; 163 xfer[0].len = sizeof(buf_tx->cmd); 164 165 xfer[1].rx_buf = val_buf; 166 xfer[1].len = val_len; 167 spi_message_add_tail(&xfer[1], &msg); 168 } else { 169 xfer[0].tx_buf = buf_tx; 170 xfer[0].rx_buf = buf_rx; 171 xfer[0].len = sizeof(buf_tx->cmd) + val_len; 172 173 memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd)); 174 if (MCP251XFD_SANITIZE_SPI) 175 memset(buf_tx->data, 0x0, val_len); 176 } 177 178 err = spi_sync(spi, &msg); 179 if (err) 180 return err; 181 182 if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX)) 183 memcpy(val_buf, buf_rx->data, val_len); 184 185 return 0; 186 } 187 188 static int 189 mcp251xfd_regmap_crc_gather_write(void *context, 190 const void *reg_p, size_t reg_len, 191 const void *val, size_t val_len) 192 { 193 struct spi_device *spi = context; 194 struct mcp251xfd_priv *priv = spi_get_drvdata(spi); 195 struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx; 196 struct spi_transfer xfer[] = { 197 { 198 .tx_buf = buf_tx, 199 .len = sizeof(buf_tx->cmd) + val_len + 200 sizeof(buf_tx->crc), 201 }, 202 }; 203 u16 reg = *(u16 *)reg_p; 204 u16 crc; 205 206 BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8)); 207 208 if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) && 209 reg_len != sizeof(buf_tx->cmd.cmd) + 210 mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE) 211 return -EINVAL; 212 213 mcp251xfd_spi_cmd_write_crc(&buf_tx->cmd, reg, val_len); 214 memcpy(buf_tx->data, val, val_len); 215 216 crc = mcp251xfd_crc16_compute(buf_tx, sizeof(buf_tx->cmd) + val_len); 217 put_unaligned_be16(crc, buf_tx->data + val_len); 218 219 return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); 220 } 221 222 static int 223 mcp251xfd_regmap_crc_write(void *context, 224 const void *data, size_t count) 225 { 226 const size_t data_offset = sizeof(__be16) + 227 mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE; 228 229 return mcp251xfd_regmap_crc_gather_write(context, 230 data, data_offset, 231 data + data_offset, 232 count - data_offset); 233 } 234 235 static int 236 mcp251xfd_regmap_crc_read_check_crc(const struct mcp251xfd_map_buf_crc * const buf_rx, 237 const struct mcp251xfd_map_buf_crc * const buf_tx, 238 unsigned int data_len) 239 { 240 u16 crc_received, crc_calculated; 241 242 crc_received = get_unaligned_be16(buf_rx->data + data_len); 243 crc_calculated = mcp251xfd_crc16_compute2(&buf_tx->cmd, 244 sizeof(buf_tx->cmd), 245 buf_rx->data, 246 data_len); 247 if (crc_received != crc_calculated) 248 return -EBADMSG; 249 250 return 0; 251 } 252 253 static int 254 mcp251xfd_regmap_crc_read_one(struct mcp251xfd_priv *priv, 255 struct spi_message *msg, unsigned int data_len) 256 { 257 const struct mcp251xfd_map_buf_crc *buf_rx = priv->map_buf_crc_rx; 258 const struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx; 259 int err; 260 261 BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16) + sizeof(u8)); 262 BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8)); 263 264 err = spi_sync(priv->spi, msg); 265 if (err) 266 return err; 267 268 return mcp251xfd_regmap_crc_read_check_crc(buf_rx, buf_tx, data_len); 269 } 270 271 static int 272 mcp251xfd_regmap_crc_read(void *context, 273 const void *reg_p, size_t reg_len, 274 void *val_buf, size_t val_len) 275 { 276 struct spi_device *spi = context; 277 struct mcp251xfd_priv *priv = spi_get_drvdata(spi); 278 struct mcp251xfd_map_buf_crc *buf_rx = priv->map_buf_crc_rx; 279 struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx; 280 struct spi_transfer xfer[2] = { }; 281 struct spi_message msg; 282 u16 reg = *(u16 *)reg_p; 283 int i, err; 284 285 BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16) + sizeof(u8)); 286 BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8)); 287 288 if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) && 289 reg_len != sizeof(buf_tx->cmd.cmd) + 290 mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE) 291 return -EINVAL; 292 293 spi_message_init(&msg); 294 spi_message_add_tail(&xfer[0], &msg); 295 296 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) { 297 xfer[0].tx_buf = buf_tx; 298 xfer[0].len = sizeof(buf_tx->cmd); 299 300 xfer[1].rx_buf = buf_rx->data; 301 xfer[1].len = val_len + sizeof(buf_tx->crc); 302 spi_message_add_tail(&xfer[1], &msg); 303 } else { 304 xfer[0].tx_buf = buf_tx; 305 xfer[0].rx_buf = buf_rx; 306 xfer[0].len = sizeof(buf_tx->cmd) + val_len + 307 sizeof(buf_tx->crc); 308 309 if (MCP251XFD_SANITIZE_SPI) 310 memset(buf_tx->data, 0x0, val_len + 311 sizeof(buf_tx->crc)); 312 } 313 314 mcp251xfd_spi_cmd_read_crc(&buf_tx->cmd, reg, val_len); 315 316 for (i = 0; i < MCP251XFD_READ_CRC_RETRIES_MAX; i++) { 317 err = mcp251xfd_regmap_crc_read_one(priv, &msg, val_len); 318 if (!err) 319 goto out; 320 if (err != -EBADMSG) 321 return err; 322 323 /* MCP251XFD_REG_TBC is the time base counter 324 * register. It increments once per SYS clock tick, 325 * which is 20 or 40 MHz. 326 * 327 * Observation shows that if the lowest byte (which is 328 * transferred first on the SPI bus) of that register 329 * is 0x00 or 0x80 the calculated CRC doesn't always 330 * match the transferred one. 331 * 332 * If the highest bit in the lowest byte is flipped 333 * the transferred CRC matches the calculated one. We 334 * assume for now the CRC calculation in the chip 335 * works on wrong data and the transferred data is 336 * correct. 337 */ 338 if (reg == MCP251XFD_REG_TBC && 339 (buf_rx->data[0] == 0x0 || buf_rx->data[0] == 0x80)) { 340 /* Flip highest bit in lowest byte of le32 */ 341 buf_rx->data[0] ^= 0x80; 342 343 /* re-check CRC */ 344 err = mcp251xfd_regmap_crc_read_check_crc(buf_rx, 345 buf_tx, 346 val_len); 347 if (!err) { 348 /* If CRC is now correct, assume 349 * transferred data was OK, flip bit 350 * back to original value. 351 */ 352 buf_rx->data[0] ^= 0x80; 353 goto out; 354 } 355 } 356 357 /* MCP251XFD_REG_OSC is the first ever reg we read from. 358 * 359 * The chip may be in deep sleep and this SPI transfer 360 * (i.e. the assertion of the CS) will wake the chip 361 * up. This takes about 3ms. The CRC of this transfer 362 * is wrong. 363 * 364 * Or there isn't a chip at all, in this case the CRC 365 * will be wrong, too. 366 * 367 * In both cases ignore the CRC and copy the read data 368 * to the caller. It will take care of both cases. 369 * 370 */ 371 if (reg == MCP251XFD_REG_OSC) { 372 err = 0; 373 goto out; 374 } 375 376 netdev_info(priv->ndev, 377 "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x) retrying.\n", 378 reg, val_len, (int)val_len, buf_rx->data, 379 get_unaligned_be16(buf_rx->data + val_len)); 380 } 381 382 if (err) { 383 netdev_err(priv->ndev, 384 "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x).\n", 385 reg, val_len, (int)val_len, buf_rx->data, 386 get_unaligned_be16(buf_rx->data + val_len)); 387 388 return err; 389 } 390 out: 391 memcpy(val_buf, buf_rx->data, val_len); 392 393 return 0; 394 } 395 396 static const struct regmap_range mcp251xfd_reg_table_yes_range[] = { 397 regmap_reg_range(0x000, 0x2ec), /* CAN FD Controller Module SFR */ 398 regmap_reg_range(0x400, 0xbfc), /* RAM */ 399 regmap_reg_range(0xe00, 0xe14), /* MCP2517/18FD SFR */ 400 }; 401 402 static const struct regmap_access_table mcp251xfd_reg_table = { 403 .yes_ranges = mcp251xfd_reg_table_yes_range, 404 .n_yes_ranges = ARRAY_SIZE(mcp251xfd_reg_table_yes_range), 405 }; 406 407 static const struct regmap_config mcp251xfd_regmap_nocrc = { 408 .name = "nocrc", 409 .reg_bits = 16, 410 .reg_stride = 4, 411 .pad_bits = 0, 412 .val_bits = 32, 413 .max_register = 0xffc, 414 .wr_table = &mcp251xfd_reg_table, 415 .rd_table = &mcp251xfd_reg_table, 416 .cache_type = REGCACHE_NONE, 417 .read_flag_mask = (__force unsigned long) 418 cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_READ), 419 .write_flag_mask = (__force unsigned long) 420 cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE), 421 }; 422 423 static const struct regmap_bus mcp251xfd_bus_nocrc = { 424 .write = mcp251xfd_regmap_nocrc_write, 425 .gather_write = mcp251xfd_regmap_nocrc_gather_write, 426 .reg_update_bits = mcp251xfd_regmap_nocrc_update_bits, 427 .read = mcp251xfd_regmap_nocrc_read, 428 .reg_format_endian_default = REGMAP_ENDIAN_BIG, 429 .val_format_endian_default = REGMAP_ENDIAN_LITTLE, 430 .max_raw_read = sizeof_field(struct mcp251xfd_map_buf_nocrc, data), 431 .max_raw_write = sizeof_field(struct mcp251xfd_map_buf_nocrc, data), 432 }; 433 434 static const struct regmap_config mcp251xfd_regmap_crc = { 435 .name = "crc", 436 .reg_bits = 16, 437 .reg_stride = 4, 438 .pad_bits = 16, /* keep data bits aligned */ 439 .val_bits = 32, 440 .max_register = 0xffc, 441 .wr_table = &mcp251xfd_reg_table, 442 .rd_table = &mcp251xfd_reg_table, 443 .cache_type = REGCACHE_NONE, 444 }; 445 446 static const struct regmap_bus mcp251xfd_bus_crc = { 447 .write = mcp251xfd_regmap_crc_write, 448 .gather_write = mcp251xfd_regmap_crc_gather_write, 449 .read = mcp251xfd_regmap_crc_read, 450 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, 451 .val_format_endian_default = REGMAP_ENDIAN_LITTLE, 452 .max_raw_read = sizeof_field(struct mcp251xfd_map_buf_crc, data), 453 .max_raw_write = sizeof_field(struct mcp251xfd_map_buf_crc, data), 454 }; 455 456 static inline bool 457 mcp251xfd_regmap_use_nocrc(struct mcp251xfd_priv *priv) 458 { 459 return (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)) || 460 (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX)); 461 } 462 463 static inline bool 464 mcp251xfd_regmap_use_crc(struct mcp251xfd_priv *priv) 465 { 466 return (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) || 467 (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX); 468 } 469 470 static int 471 mcp251xfd_regmap_init_nocrc(struct mcp251xfd_priv *priv) 472 { 473 if (!priv->map_nocrc) { 474 struct regmap *map; 475 476 map = devm_regmap_init(&priv->spi->dev, &mcp251xfd_bus_nocrc, 477 priv->spi, &mcp251xfd_regmap_nocrc); 478 if (IS_ERR(map)) 479 return PTR_ERR(map); 480 481 priv->map_nocrc = map; 482 } 483 484 if (!priv->map_buf_nocrc_rx) { 485 priv->map_buf_nocrc_rx = 486 devm_kzalloc(&priv->spi->dev, 487 sizeof(*priv->map_buf_nocrc_rx), 488 GFP_KERNEL); 489 if (!priv->map_buf_nocrc_rx) 490 return -ENOMEM; 491 } 492 493 if (!priv->map_buf_nocrc_tx) { 494 priv->map_buf_nocrc_tx = 495 devm_kzalloc(&priv->spi->dev, 496 sizeof(*priv->map_buf_nocrc_tx), 497 GFP_KERNEL); 498 if (!priv->map_buf_nocrc_tx) 499 return -ENOMEM; 500 } 501 502 if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)) 503 priv->map_reg = priv->map_nocrc; 504 505 if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX)) 506 priv->map_rx = priv->map_nocrc; 507 508 return 0; 509 } 510 511 static void mcp251xfd_regmap_destroy_nocrc(struct mcp251xfd_priv *priv) 512 { 513 if (priv->map_buf_nocrc_rx) { 514 devm_kfree(&priv->spi->dev, priv->map_buf_nocrc_rx); 515 priv->map_buf_nocrc_rx = NULL; 516 } 517 if (priv->map_buf_nocrc_tx) { 518 devm_kfree(&priv->spi->dev, priv->map_buf_nocrc_tx); 519 priv->map_buf_nocrc_tx = NULL; 520 } 521 } 522 523 static int 524 mcp251xfd_regmap_init_crc(struct mcp251xfd_priv *priv) 525 { 526 if (!priv->map_crc) { 527 struct regmap *map; 528 529 map = devm_regmap_init(&priv->spi->dev, &mcp251xfd_bus_crc, 530 priv->spi, &mcp251xfd_regmap_crc); 531 if (IS_ERR(map)) 532 return PTR_ERR(map); 533 534 priv->map_crc = map; 535 } 536 537 if (!priv->map_buf_crc_rx) { 538 priv->map_buf_crc_rx = 539 devm_kzalloc(&priv->spi->dev, 540 sizeof(*priv->map_buf_crc_rx), 541 GFP_KERNEL); 542 if (!priv->map_buf_crc_rx) 543 return -ENOMEM; 544 } 545 546 if (!priv->map_buf_crc_tx) { 547 priv->map_buf_crc_tx = 548 devm_kzalloc(&priv->spi->dev, 549 sizeof(*priv->map_buf_crc_tx), 550 GFP_KERNEL); 551 if (!priv->map_buf_crc_tx) 552 return -ENOMEM; 553 } 554 555 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) 556 priv->map_reg = priv->map_crc; 557 558 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX) 559 priv->map_rx = priv->map_crc; 560 561 return 0; 562 } 563 564 static void mcp251xfd_regmap_destroy_crc(struct mcp251xfd_priv *priv) 565 { 566 if (priv->map_buf_crc_rx) { 567 devm_kfree(&priv->spi->dev, priv->map_buf_crc_rx); 568 priv->map_buf_crc_rx = NULL; 569 } 570 if (priv->map_buf_crc_tx) { 571 devm_kfree(&priv->spi->dev, priv->map_buf_crc_tx); 572 priv->map_buf_crc_tx = NULL; 573 } 574 } 575 576 int mcp251xfd_regmap_init(struct mcp251xfd_priv *priv) 577 { 578 int err; 579 580 if (mcp251xfd_regmap_use_nocrc(priv)) { 581 err = mcp251xfd_regmap_init_nocrc(priv); 582 583 if (err) 584 return err; 585 } else { 586 mcp251xfd_regmap_destroy_nocrc(priv); 587 } 588 589 if (mcp251xfd_regmap_use_crc(priv)) { 590 err = mcp251xfd_regmap_init_crc(priv); 591 592 if (err) 593 return err; 594 } else { 595 mcp251xfd_regmap_destroy_crc(priv); 596 } 597 598 return 0; 599 } 600