1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
4 //
5 // Copyright (c) 2019, 2020 Pengutronix,
6 //                          Marc Kleine-Budde <kernel@pengutronix.de>
7 //
8 
9 #include "mcp251xfd.h"
10 
11 #include <asm/unaligned.h>
12 
13 static const struct regmap_config mcp251xfd_regmap_crc;
14 
15 static int
16 mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count)
17 {
18 	struct spi_device *spi = context;
19 
20 	return spi_write(spi, data, count);
21 }
22 
23 static int
24 mcp251xfd_regmap_nocrc_gather_write(void *context,
25 				    const void *reg, size_t reg_len,
26 				    const void *val, size_t val_len)
27 {
28 	struct spi_device *spi = context;
29 	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
30 	struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
31 	struct spi_transfer xfer[] = {
32 		{
33 			.tx_buf = buf_tx,
34 			.len = sizeof(buf_tx->cmd) + val_len,
35 		},
36 	};
37 
38 	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
39 
40 	if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
41 	    reg_len != sizeof(buf_tx->cmd.cmd))
42 		return -EINVAL;
43 
44 	memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd));
45 	memcpy(buf_tx->data, val, val_len);
46 
47 	return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
48 }
49 
50 static inline bool mcp251xfd_update_bits_read_reg(unsigned int reg)
51 {
52 	switch (reg) {
53 	case MCP251XFD_REG_INT:
54 	case MCP251XFD_REG_TEFCON:
55 	case MCP251XFD_REG_FIFOCON(MCP251XFD_RX_FIFO(0)):
56 	case MCP251XFD_REG_FLTCON(0):
57 	case MCP251XFD_REG_ECCSTAT:
58 	case MCP251XFD_REG_CRC:
59 		return false;
60 	case MCP251XFD_REG_CON:
61 	case MCP251XFD_REG_FIFOSTA(MCP251XFD_RX_FIFO(0)):
62 	case MCP251XFD_REG_OSC:
63 	case MCP251XFD_REG_ECCCON:
64 		return true;
65 	default:
66 		WARN(1, "Status of reg 0x%04x unknown.\n", reg);
67 	}
68 
69 	return true;
70 }
71 
72 static int
73 mcp251xfd_regmap_nocrc_update_bits(void *context, unsigned int reg,
74 				   unsigned int mask, unsigned int val)
75 {
76 	struct spi_device *spi = context;
77 	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
78 	struct mcp251xfd_map_buf_nocrc *buf_rx = priv->map_buf_nocrc_rx;
79 	struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
80 	__le32 orig_le32 = 0, mask_le32, val_le32, tmp_le32;
81 	u8 first_byte, last_byte, len;
82 	int err;
83 
84 	BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16));
85 	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
86 
87 	if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
88 	    mask == 0)
89 		return -EINVAL;
90 
91 	first_byte = mcp251xfd_first_byte_set(mask);
92 	last_byte = mcp251xfd_last_byte_set(mask);
93 	len = last_byte - first_byte + 1;
94 
95 	if (mcp251xfd_update_bits_read_reg(reg)) {
96 		struct spi_transfer xfer[2] = { };
97 		struct spi_message msg;
98 
99 		spi_message_init(&msg);
100 		spi_message_add_tail(&xfer[0], &msg);
101 
102 		if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
103 			xfer[0].tx_buf = buf_tx;
104 			xfer[0].len = sizeof(buf_tx->cmd);
105 
106 			xfer[1].rx_buf = buf_rx->data;
107 			xfer[1].len = len;
108 			spi_message_add_tail(&xfer[1], &msg);
109 		} else {
110 			xfer[0].tx_buf = buf_tx;
111 			xfer[0].rx_buf = buf_rx;
112 			xfer[0].len = sizeof(buf_tx->cmd) + len;
113 
114 			if (MCP251XFD_SANITIZE_SPI)
115 				memset(buf_tx->data, 0x0, len);
116 		}
117 
118 		mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, reg + first_byte);
119 		err = spi_sync(spi, &msg);
120 		if (err)
121 			return err;
122 
123 		memcpy(&orig_le32, buf_rx->data, len);
124 	}
125 
126 	mask_le32 = cpu_to_le32(mask >> BITS_PER_BYTE * first_byte);
127 	val_le32 = cpu_to_le32(val >> BITS_PER_BYTE * first_byte);
128 
129 	tmp_le32 = orig_le32 & ~mask_le32;
130 	tmp_le32 |= val_le32 & mask_le32;
131 
132 	mcp251xfd_spi_cmd_write_nocrc(&buf_tx->cmd, reg + first_byte);
133 	memcpy(buf_tx->data, &tmp_le32, len);
134 
135 	return spi_write(spi, buf_tx, sizeof(buf_tx->cmd) + len);
136 }
137 
138 static int
139 mcp251xfd_regmap_nocrc_read(void *context,
140 			    const void *reg, size_t reg_len,
141 			    void *val_buf, size_t val_len)
142 {
143 	struct spi_device *spi = context;
144 	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
145 	struct mcp251xfd_map_buf_nocrc *buf_rx = priv->map_buf_nocrc_rx;
146 	struct mcp251xfd_map_buf_nocrc *buf_tx = priv->map_buf_nocrc_tx;
147 	struct spi_transfer xfer[2] = { };
148 	struct spi_message msg;
149 	int err;
150 
151 	BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16));
152 	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16));
153 
154 	if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
155 	    reg_len != sizeof(buf_tx->cmd.cmd))
156 		return -EINVAL;
157 
158 	spi_message_init(&msg);
159 	spi_message_add_tail(&xfer[0], &msg);
160 
161 	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
162 		xfer[0].tx_buf = reg;
163 		xfer[0].len = sizeof(buf_tx->cmd);
164 
165 		xfer[1].rx_buf = val_buf;
166 		xfer[1].len = val_len;
167 		spi_message_add_tail(&xfer[1], &msg);
168 	} else {
169 		xfer[0].tx_buf = buf_tx;
170 		xfer[0].rx_buf = buf_rx;
171 		xfer[0].len = sizeof(buf_tx->cmd) + val_len;
172 
173 		memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd));
174 		if (MCP251XFD_SANITIZE_SPI)
175 			memset(buf_tx->data, 0x0, val_len);
176 	};
177 
178 	err = spi_sync(spi, &msg);
179 	if (err)
180 		return err;
181 
182 	if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX))
183 		memcpy(val_buf, buf_rx->data, val_len);
184 
185 	return 0;
186 }
187 
188 static int
189 mcp251xfd_regmap_crc_gather_write(void *context,
190 				  const void *reg_p, size_t reg_len,
191 				  const void *val, size_t val_len)
192 {
193 	struct spi_device *spi = context;
194 	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
195 	struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
196 	struct spi_transfer xfer[] = {
197 		{
198 			.tx_buf = buf_tx,
199 			.len = sizeof(buf_tx->cmd) + val_len +
200 				sizeof(buf_tx->crc),
201 		},
202 	};
203 	u16 reg = *(u16 *)reg_p;
204 	u16 crc;
205 
206 	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
207 
208 	if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
209 	    reg_len != sizeof(buf_tx->cmd.cmd) +
210 	    mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE)
211 		return -EINVAL;
212 
213 	mcp251xfd_spi_cmd_write_crc(&buf_tx->cmd, reg, val_len);
214 	memcpy(buf_tx->data, val, val_len);
215 
216 	crc = mcp251xfd_crc16_compute(buf_tx, sizeof(buf_tx->cmd) + val_len);
217 	put_unaligned_be16(crc, buf_tx->data + val_len);
218 
219 	return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
220 }
221 
222 static int
223 mcp251xfd_regmap_crc_write(void *context,
224 			   const void *data, size_t count)
225 {
226 	const size_t data_offset = sizeof(__be16) +
227 		mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE;
228 
229 	return mcp251xfd_regmap_crc_gather_write(context,
230 						 data, data_offset,
231 						 data + data_offset,
232 						 count - data_offset);
233 }
234 
235 static int
236 mcp251xfd_regmap_crc_read_one(struct mcp251xfd_priv *priv,
237 			      struct spi_message *msg, unsigned int data_len)
238 {
239 	const struct mcp251xfd_map_buf_crc *buf_rx = priv->map_buf_crc_rx;
240 	const struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
241 	u16 crc_received, crc_calculated;
242 	int err;
243 
244 	BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16) + sizeof(u8));
245 	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
246 
247 	err = spi_sync(priv->spi, msg);
248 	if (err)
249 		return err;
250 
251 	crc_received = get_unaligned_be16(buf_rx->data + data_len);
252 	crc_calculated = mcp251xfd_crc16_compute2(&buf_tx->cmd,
253 						  sizeof(buf_tx->cmd),
254 						  buf_rx->data,
255 						  data_len);
256 	if (crc_received != crc_calculated)
257 		return -EBADMSG;
258 
259 	return 0;
260 }
261 
262 static int
263 mcp251xfd_regmap_crc_read(void *context,
264 			  const void *reg_p, size_t reg_len,
265 			  void *val_buf, size_t val_len)
266 {
267 	struct spi_device *spi = context;
268 	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
269 	struct mcp251xfd_map_buf_crc *buf_rx = priv->map_buf_crc_rx;
270 	struct mcp251xfd_map_buf_crc *buf_tx = priv->map_buf_crc_tx;
271 	struct spi_transfer xfer[2] = { };
272 	struct spi_message msg;
273 	u16 reg = *(u16 *)reg_p;
274 	int i, err;
275 
276 	BUILD_BUG_ON(sizeof(buf_rx->cmd) != sizeof(__be16) + sizeof(u8));
277 	BUILD_BUG_ON(sizeof(buf_tx->cmd) != sizeof(__be16) + sizeof(u8));
278 
279 	if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) &&
280 	    reg_len != sizeof(buf_tx->cmd.cmd) +
281 	    mcp251xfd_regmap_crc.pad_bits / BITS_PER_BYTE)
282 		return -EINVAL;
283 
284 	spi_message_init(&msg);
285 	spi_message_add_tail(&xfer[0], &msg);
286 
287 	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_HALF_DUPLEX) {
288 		xfer[0].tx_buf = buf_tx;
289 		xfer[0].len = sizeof(buf_tx->cmd);
290 
291 		xfer[1].rx_buf = buf_rx->data;
292 		xfer[1].len = val_len + sizeof(buf_tx->crc);
293 		spi_message_add_tail(&xfer[1], &msg);
294 	} else {
295 		xfer[0].tx_buf = buf_tx;
296 		xfer[0].rx_buf = buf_rx;
297 		xfer[0].len = sizeof(buf_tx->cmd) + val_len +
298 			sizeof(buf_tx->crc);
299 
300 		if (MCP251XFD_SANITIZE_SPI)
301 			memset(buf_tx->data, 0x0, val_len +
302 			       sizeof(buf_tx->crc));
303 	}
304 
305 	mcp251xfd_spi_cmd_read_crc(&buf_tx->cmd, reg, val_len);
306 
307 	for (i = 0; i < MCP251XFD_READ_CRC_RETRIES_MAX; i++) {
308 		err = mcp251xfd_regmap_crc_read_one(priv, &msg, val_len);
309 		if (!err)
310 			goto out;
311 		if (err != -EBADMSG)
312 			return err;
313 
314 		/* MCP251XFD_REG_OSC is the first ever reg we read from.
315 		 *
316 		 * The chip may be in deep sleep and this SPI transfer
317 		 * (i.e. the assertion of the CS) will wake the chip
318 		 * up. This takes about 3ms. The CRC of this transfer
319 		 * is wrong.
320 		 *
321 		 * Or there isn't a chip at all, in this case the CRC
322 		 * will be wrong, too.
323 		 *
324 		 * In both cases ignore the CRC and copy the read data
325 		 * to the caller. It will take care of both cases.
326 		 *
327 		 */
328 		if (reg == MCP251XFD_REG_OSC) {
329 			err = 0;
330 			goto out;
331 		}
332 
333 		netdev_dbg(priv->ndev,
334 			   "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x) retrying.\n",
335 			   reg, val_len, (int)val_len, buf_rx->data,
336 			   get_unaligned_be16(buf_rx->data + val_len));
337 	}
338 
339 	if (err) {
340 		netdev_info(priv->ndev,
341 			    "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x).\n",
342 			    reg, val_len, (int)val_len, buf_rx->data,
343 			    get_unaligned_be16(buf_rx->data + val_len));
344 
345 		return err;
346 	}
347  out:
348 	memcpy(val_buf, buf_rx->data, val_len);
349 
350 	return 0;
351 }
352 
353 static const struct regmap_range mcp251xfd_reg_table_yes_range[] = {
354 	regmap_reg_range(0x000, 0x2ec),	/* CAN FD Controller Module SFR */
355 	regmap_reg_range(0x400, 0xbfc),	/* RAM */
356 	regmap_reg_range(0xe00, 0xe14),	/* MCP2517/18FD SFR */
357 };
358 
359 static const struct regmap_access_table mcp251xfd_reg_table = {
360 	.yes_ranges = mcp251xfd_reg_table_yes_range,
361 	.n_yes_ranges = ARRAY_SIZE(mcp251xfd_reg_table_yes_range),
362 };
363 
364 static const struct regmap_config mcp251xfd_regmap_nocrc = {
365 	.name = "nocrc",
366 	.reg_bits = 16,
367 	.reg_stride = 4,
368 	.pad_bits = 0,
369 	.val_bits = 32,
370 	.max_register = 0xffc,
371 	.wr_table = &mcp251xfd_reg_table,
372 	.rd_table = &mcp251xfd_reg_table,
373 	.cache_type = REGCACHE_NONE,
374 	.read_flag_mask = (__force unsigned long)
375 		cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_READ),
376 	.write_flag_mask = (__force unsigned long)
377 		cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE),
378 };
379 
380 static const struct regmap_bus mcp251xfd_bus_nocrc = {
381 	.write = mcp251xfd_regmap_nocrc_write,
382 	.gather_write = mcp251xfd_regmap_nocrc_gather_write,
383 	.reg_update_bits = mcp251xfd_regmap_nocrc_update_bits,
384 	.read = mcp251xfd_regmap_nocrc_read,
385 	.reg_format_endian_default = REGMAP_ENDIAN_BIG,
386 	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
387 	.max_raw_read = sizeof_field(struct mcp251xfd_map_buf_nocrc, data),
388 	.max_raw_write = sizeof_field(struct mcp251xfd_map_buf_nocrc, data),
389 };
390 
391 static const struct regmap_config mcp251xfd_regmap_crc = {
392 	.name = "crc",
393 	.reg_bits = 16,
394 	.reg_stride = 4,
395 	.pad_bits = 16,		/* keep data bits aligned */
396 	.val_bits = 32,
397 	.max_register = 0xffc,
398 	.wr_table = &mcp251xfd_reg_table,
399 	.rd_table = &mcp251xfd_reg_table,
400 	.cache_type = REGCACHE_NONE,
401 };
402 
403 static const struct regmap_bus mcp251xfd_bus_crc = {
404 	.write = mcp251xfd_regmap_crc_write,
405 	.gather_write = mcp251xfd_regmap_crc_gather_write,
406 	.read = mcp251xfd_regmap_crc_read,
407 	.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
408 	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
409 	.max_raw_read = sizeof_field(struct mcp251xfd_map_buf_crc, data),
410 	.max_raw_write = sizeof_field(struct mcp251xfd_map_buf_crc, data),
411 };
412 
413 static inline bool
414 mcp251xfd_regmap_use_nocrc(struct mcp251xfd_priv *priv)
415 {
416 	return (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)) ||
417 		(!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX));
418 }
419 
420 static inline bool
421 mcp251xfd_regmap_use_crc(struct mcp251xfd_priv *priv)
422 {
423 	return (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) ||
424 		(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX);
425 }
426 
427 static int
428 mcp251xfd_regmap_init_nocrc(struct mcp251xfd_priv *priv)
429 {
430 	if (!priv->map_nocrc) {
431 		struct regmap *map;
432 
433 		map = devm_regmap_init(&priv->spi->dev, &mcp251xfd_bus_nocrc,
434 				       priv->spi, &mcp251xfd_regmap_nocrc);
435 		if (IS_ERR(map))
436 			return PTR_ERR(map);
437 
438 		priv->map_nocrc = map;
439 	}
440 
441 	if (!priv->map_buf_nocrc_rx) {
442 		priv->map_buf_nocrc_rx =
443 			devm_kzalloc(&priv->spi->dev,
444 				     sizeof(*priv->map_buf_nocrc_rx),
445 				     GFP_KERNEL);
446 		if (!priv->map_buf_nocrc_rx)
447 			return -ENOMEM;
448 	}
449 
450 	if (!priv->map_buf_nocrc_tx) {
451 		priv->map_buf_nocrc_tx =
452 			devm_kzalloc(&priv->spi->dev,
453 				     sizeof(*priv->map_buf_nocrc_tx),
454 				     GFP_KERNEL);
455 		if (!priv->map_buf_nocrc_tx)
456 			return -ENOMEM;
457 	}
458 
459 	if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG))
460 		priv->map_reg = priv->map_nocrc;
461 
462 	if (!(priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX))
463 		priv->map_rx = priv->map_nocrc;
464 
465 	return 0;
466 }
467 
468 static void mcp251xfd_regmap_destroy_nocrc(struct mcp251xfd_priv *priv)
469 {
470 	if (priv->map_buf_nocrc_rx) {
471 		devm_kfree(&priv->spi->dev, priv->map_buf_nocrc_rx);
472 		priv->map_buf_nocrc_rx = NULL;
473 	}
474 	if (priv->map_buf_nocrc_tx) {
475 		devm_kfree(&priv->spi->dev, priv->map_buf_nocrc_tx);
476 		priv->map_buf_nocrc_tx = NULL;
477 	}
478 }
479 
480 static int
481 mcp251xfd_regmap_init_crc(struct mcp251xfd_priv *priv)
482 {
483 	if (!priv->map_crc) {
484 		struct regmap *map;
485 
486 		map = devm_regmap_init(&priv->spi->dev, &mcp251xfd_bus_crc,
487 				       priv->spi, &mcp251xfd_regmap_crc);
488 		if (IS_ERR(map))
489 			return PTR_ERR(map);
490 
491 		priv->map_crc = map;
492 	}
493 
494 	if (!priv->map_buf_crc_rx) {
495 		priv->map_buf_crc_rx =
496 			devm_kzalloc(&priv->spi->dev,
497 				     sizeof(*priv->map_buf_crc_rx),
498 				     GFP_KERNEL);
499 		if (!priv->map_buf_crc_rx)
500 			return -ENOMEM;
501 	}
502 
503 	if (!priv->map_buf_crc_tx) {
504 		priv->map_buf_crc_tx =
505 			devm_kzalloc(&priv->spi->dev,
506 				     sizeof(*priv->map_buf_crc_tx),
507 				     GFP_KERNEL);
508 		if (!priv->map_buf_crc_tx)
509 			return -ENOMEM;
510 	}
511 
512 	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG)
513 		priv->map_reg = priv->map_crc;
514 
515 	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_RX)
516 		priv->map_rx = priv->map_crc;
517 
518 	return 0;
519 }
520 
521 static void mcp251xfd_regmap_destroy_crc(struct mcp251xfd_priv *priv)
522 {
523 	if (priv->map_buf_crc_rx) {
524 		devm_kfree(&priv->spi->dev, priv->map_buf_crc_rx);
525 		priv->map_buf_crc_rx = NULL;
526 	}
527 	if (priv->map_buf_crc_tx) {
528 		devm_kfree(&priv->spi->dev, priv->map_buf_crc_tx);
529 		priv->map_buf_crc_tx = NULL;
530 	}
531 }
532 
533 int mcp251xfd_regmap_init(struct mcp251xfd_priv *priv)
534 {
535 	int err;
536 
537 	if (mcp251xfd_regmap_use_nocrc(priv)) {
538 		err = mcp251xfd_regmap_init_nocrc(priv);
539 
540 		if (err)
541 			return err;
542 	} else {
543 		mcp251xfd_regmap_destroy_nocrc(priv);
544 	}
545 
546 	if (mcp251xfd_regmap_use_crc(priv)) {
547 		err = mcp251xfd_regmap_init_crc(priv);
548 
549 		if (err)
550 			return err;
551 	} else {
552 		mcp251xfd_regmap_destroy_crc(priv);
553 	}
554 
555 	return 0;
556 }
557