1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver 4 // 5 // Copyright (c) 2019, 2020, 2021 Pengutronix, 6 // Marc Kleine-Budde <kernel@pengutronix.de> 7 // 8 // Based on: 9 // 10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface 11 // 12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org> 13 // 14 15 #include <linux/bitfield.h> 16 #include <linux/clk.h> 17 #include <linux/device.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/property.h> 22 23 #include "mcp251xfd.h" 24 25 #define DEVICE_NAME "mcp251xfd" 26 27 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = { 28 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG | 29 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX | 30 MCP251XFD_QUIRK_ECC, 31 .model = MCP251XFD_MODEL_MCP2517FD, 32 }; 33 34 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = { 35 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 36 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 37 .model = MCP251XFD_MODEL_MCP2518FD, 38 }; 39 40 /* Autodetect model, start with CRC enabled. */ 41 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = { 42 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 43 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 44 .model = MCP251XFD_MODEL_MCP251XFD, 45 }; 46 47 static const struct can_bittiming_const mcp251xfd_bittiming_const = { 48 .name = DEVICE_NAME, 49 .tseg1_min = 2, 50 .tseg1_max = 256, 51 .tseg2_min = 1, 52 .tseg2_max = 128, 53 .sjw_max = 128, 54 .brp_min = 1, 55 .brp_max = 256, 56 .brp_inc = 1, 57 }; 58 59 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = { 60 .name = DEVICE_NAME, 61 .tseg1_min = 1, 62 .tseg1_max = 32, 63 .tseg2_min = 1, 64 .tseg2_max = 16, 65 .sjw_max = 16, 66 .brp_min = 1, 67 .brp_max = 256, 68 .brp_inc = 1, 69 }; 70 71 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model) 72 { 73 switch (model) { 74 case MCP251XFD_MODEL_MCP2517FD: 75 return "MCP2517FD"; 76 case MCP251XFD_MODEL_MCP2518FD: 77 return "MCP2518FD"; 78 case MCP251XFD_MODEL_MCP251XFD: 79 return "MCP251xFD"; 80 } 81 82 return "<unknown>"; 83 } 84 85 static inline const char * 86 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv) 87 { 88 return __mcp251xfd_get_model_str(priv->devtype_data.model); 89 } 90 91 static const char *mcp251xfd_get_mode_str(const u8 mode) 92 { 93 switch (mode) { 94 case MCP251XFD_REG_CON_MODE_MIXED: 95 return "Mixed (CAN FD/CAN 2.0)"; 96 case MCP251XFD_REG_CON_MODE_SLEEP: 97 return "Sleep"; 98 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK: 99 return "Internal Loopback"; 100 case MCP251XFD_REG_CON_MODE_LISTENONLY: 101 return "Listen Only"; 102 case MCP251XFD_REG_CON_MODE_CONFIG: 103 return "Configuration"; 104 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK: 105 return "External Loopback"; 106 case MCP251XFD_REG_CON_MODE_CAN2_0: 107 return "CAN 2.0"; 108 case MCP251XFD_REG_CON_MODE_RESTRICTED: 109 return "Restricted Operation"; 110 } 111 112 return "<unknown>"; 113 } 114 115 static const char * 116 mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference) 117 { 118 switch (~osc & osc_reference & 119 (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) { 120 case MCP251XFD_REG_OSC_PLLRDY: 121 return "PLL"; 122 case MCP251XFD_REG_OSC_OSCRDY: 123 return "Oscillator"; 124 case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY: 125 return "Oscillator/PLL"; 126 } 127 128 return "<unknown>"; 129 } 130 131 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv) 132 { 133 if (!priv->reg_vdd) 134 return 0; 135 136 return regulator_enable(priv->reg_vdd); 137 } 138 139 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv) 140 { 141 if (!priv->reg_vdd) 142 return 0; 143 144 return regulator_disable(priv->reg_vdd); 145 } 146 147 static inline int 148 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv) 149 { 150 if (!priv->reg_xceiver) 151 return 0; 152 153 return regulator_enable(priv->reg_xceiver); 154 } 155 156 static inline int 157 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv) 158 { 159 if (!priv->reg_xceiver) 160 return 0; 161 162 return regulator_disable(priv->reg_xceiver); 163 } 164 165 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv) 166 { 167 int err; 168 169 err = clk_prepare_enable(priv->clk); 170 if (err) 171 return err; 172 173 err = mcp251xfd_vdd_enable(priv); 174 if (err) 175 clk_disable_unprepare(priv->clk); 176 177 /* Wait for oscillator stabilisation time after power up */ 178 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US, 179 2 * MCP251XFD_OSC_STAB_SLEEP_US); 180 181 return err; 182 } 183 184 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv) 185 { 186 int err; 187 188 err = mcp251xfd_vdd_disable(priv); 189 if (err) 190 return err; 191 192 clk_disable_unprepare(priv->clk); 193 194 return 0; 195 } 196 197 static inline bool mcp251xfd_reg_invalid(u32 reg) 198 { 199 return reg == 0x0 || reg == 0xffffffff; 200 } 201 202 static inline int 203 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode) 204 { 205 u32 val; 206 int err; 207 208 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val); 209 if (err) 210 return err; 211 212 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val); 213 214 return 0; 215 } 216 217 static int 218 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, 219 const u8 mode_req, bool nowait) 220 { 221 u32 con = 0, con_reqop, osc = 0; 222 u8 mode; 223 int err; 224 225 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req); 226 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON, 227 MCP251XFD_REG_CON_REQOP_MASK, con_reqop); 228 if (err == -EBADMSG) { 229 netdev_err(priv->ndev, 230 "Failed to set Requested Operation Mode.\n"); 231 232 return -ENODEV; 233 } else if (err) { 234 return err; 235 } 236 237 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait) 238 return 0; 239 240 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con, 241 !mcp251xfd_reg_invalid(con) && 242 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, 243 con) == mode_req, 244 MCP251XFD_POLL_SLEEP_US, 245 MCP251XFD_POLL_TIMEOUT_US); 246 if (err != -ETIMEDOUT && err != -EBADMSG) 247 return err; 248 249 /* Ignore return value. 250 * Print below error messages, even if this fails. 251 */ 252 regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); 253 254 if (mcp251xfd_reg_invalid(con)) { 255 netdev_err(priv->ndev, 256 "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n", 257 con, osc); 258 259 return -ENODEV; 260 } 261 262 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con); 263 netdev_err(priv->ndev, 264 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n", 265 mcp251xfd_get_mode_str(mode_req), mode_req, 266 mcp251xfd_get_mode_str(mode), mode, 267 con, osc); 268 269 return -ETIMEDOUT; 270 } 271 272 static inline int 273 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, 274 const u8 mode_req) 275 { 276 return __mcp251xfd_chip_set_mode(priv, mode_req, false); 277 } 278 279 static inline int __maybe_unused 280 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv, 281 const u8 mode_req) 282 { 283 return __mcp251xfd_chip_set_mode(priv, mode_req, true); 284 } 285 286 static int 287 mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv, 288 u32 osc_reference, u32 osc_mask) 289 { 290 u32 osc; 291 int err; 292 293 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc, 294 !mcp251xfd_reg_invalid(osc) && 295 (osc & osc_mask) == osc_reference, 296 MCP251XFD_OSC_STAB_SLEEP_US, 297 MCP251XFD_OSC_STAB_TIMEOUT_US); 298 if (err != -ETIMEDOUT) 299 return err; 300 301 if (mcp251xfd_reg_invalid(osc)) { 302 netdev_err(priv->ndev, 303 "Failed to read Oscillator Configuration Register (osc=0x%08x).\n", 304 osc); 305 return -ENODEV; 306 } 307 308 netdev_err(priv->ndev, 309 "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n", 310 mcp251xfd_get_osc_str(osc, osc_reference), 311 osc, osc_reference, osc_mask); 312 313 return -ETIMEDOUT; 314 } 315 316 static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv) 317 { 318 u32 osc, osc_reference, osc_mask; 319 int err; 320 321 /* For normal sleep on MCP2517FD and MCP2518FD, clearing 322 * "Oscillator Disable" will wake the chip. For low power mode 323 * on MCP2518FD, asserting the chip select will wake the 324 * chip. Writing to the Oscillator register will wake it in 325 * both cases. 326 */ 327 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 328 MCP251XFD_REG_OSC_CLKODIV_10); 329 330 /* We cannot check for the PLL ready bit (either set or 331 * unset), as the PLL might be enabled. This can happen if the 332 * system reboots, while the mcp251xfd stays powered. 333 */ 334 osc_reference = MCP251XFD_REG_OSC_OSCRDY; 335 osc_mask = MCP251XFD_REG_OSC_OSCRDY; 336 337 /* If the controller is in Sleep Mode the following write only 338 * removes the "Oscillator Disable" bit and powers it up. All 339 * other bits are unaffected. 340 */ 341 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 342 if (err) 343 return err; 344 345 /* Sometimes the PLL is stuck enabled, the controller never 346 * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our 347 * caller takes care of retry. 348 */ 349 return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); 350 } 351 352 static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv) 353 { 354 if (priv->pll_enable) { 355 u32 osc; 356 int err; 357 358 /* Turn off PLL */ 359 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 360 MCP251XFD_REG_OSC_CLKODIV_10); 361 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 362 if (err) 363 netdev_err(priv->ndev, 364 "Failed to disable PLL.\n"); 365 366 priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow; 367 } 368 369 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); 370 } 371 372 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv) 373 { 374 const __be16 cmd = mcp251xfd_cmd_reset(); 375 int err; 376 377 /* The Set Mode and SPI Reset command only works if the 378 * controller is not in Sleep Mode. 379 */ 380 err = mcp251xfd_chip_wake(priv); 381 if (err) 382 return err; 383 384 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG); 385 if (err) 386 return err; 387 388 /* spi_write_then_read() works with non DMA-safe buffers */ 389 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0); 390 } 391 392 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv) 393 { 394 u32 osc_reference, osc_mask; 395 u8 mode; 396 int err; 397 398 /* Check for reset defaults of OSC reg. 399 * This will take care of stabilization period. 400 */ 401 osc_reference = MCP251XFD_REG_OSC_OSCRDY | 402 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 403 MCP251XFD_REG_OSC_CLKODIV_10); 404 osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY; 405 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); 406 if (err) 407 return err; 408 409 err = mcp251xfd_chip_get_mode(priv, &mode); 410 if (err) 411 return err; 412 413 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) { 414 netdev_info(priv->ndev, 415 "Controller not in Config Mode after reset, but in %s Mode (%u).\n", 416 mcp251xfd_get_mode_str(mode), mode); 417 return -ETIMEDOUT; 418 } 419 420 return 0; 421 } 422 423 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv) 424 { 425 int err, i; 426 427 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) { 428 if (i) 429 netdev_info(priv->ndev, 430 "Retrying to reset controller.\n"); 431 432 err = mcp251xfd_chip_softreset_do(priv); 433 if (err == -ETIMEDOUT) 434 continue; 435 if (err) 436 return err; 437 438 err = mcp251xfd_chip_softreset_check(priv); 439 if (err == -ETIMEDOUT) 440 continue; 441 if (err) 442 return err; 443 444 return 0; 445 } 446 447 return err; 448 } 449 450 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv) 451 { 452 u32 osc, osc_reference, osc_mask; 453 int err; 454 455 /* Activate Low Power Mode on Oscillator Disable. This only 456 * works on the MCP2518FD. The MCP2517FD will go into normal 457 * Sleep Mode instead. 458 */ 459 osc = MCP251XFD_REG_OSC_LPMEN | 460 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 461 MCP251XFD_REG_OSC_CLKODIV_10); 462 osc_reference = MCP251XFD_REG_OSC_OSCRDY; 463 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY; 464 465 if (priv->pll_enable) { 466 osc |= MCP251XFD_REG_OSC_PLLEN; 467 osc_reference |= MCP251XFD_REG_OSC_PLLRDY; 468 } 469 470 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 471 if (err) 472 return err; 473 474 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); 475 if (err) 476 return err; 477 478 priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast; 479 480 return 0; 481 } 482 483 static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv) 484 { 485 /* Set Time Base Counter Prescaler to 1. 486 * 487 * This means an overflow of the 32 bit Time Base Counter 488 * register at 40 MHz every 107 seconds. 489 */ 490 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON, 491 MCP251XFD_REG_TSCON_TBCEN); 492 } 493 494 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv) 495 { 496 const struct can_bittiming *bt = &priv->can.bittiming; 497 const struct can_bittiming *dbt = &priv->can.data_bittiming; 498 u32 val = 0; 499 s8 tdco; 500 int err; 501 502 /* CAN Control Register 503 * 504 * - no transmit bandwidth sharing 505 * - config mode 506 * - disable transmit queue 507 * - store in transmit FIFO event 508 * - transition to restricted operation mode on system error 509 * - ESI is transmitted recessive when ESI of message is high or 510 * CAN controller error passive 511 * - restricted retransmission attempts, 512 * use TQXCON_TXAT and FIFOCON_TXAT 513 * - wake-up filter bits T11FILTER 514 * - use CAN bus line filter for wakeup 515 * - protocol exception is treated as a form error 516 * - Do not compare data bytes 517 */ 518 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, 519 MCP251XFD_REG_CON_MODE_CONFIG) | 520 MCP251XFD_REG_CON_STEF | 521 MCP251XFD_REG_CON_ESIGM | 522 MCP251XFD_REG_CON_RTXAT | 523 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK, 524 MCP251XFD_REG_CON_WFT_T11FILTER) | 525 MCP251XFD_REG_CON_WAKFIL | 526 MCP251XFD_REG_CON_PXEDIS; 527 528 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) 529 val |= MCP251XFD_REG_CON_ISOCRCEN; 530 531 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val); 532 if (err) 533 return err; 534 535 /* Nominal Bit Time */ 536 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) | 537 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK, 538 bt->prop_seg + bt->phase_seg1 - 1) | 539 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK, 540 bt->phase_seg2 - 1) | 541 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1); 542 543 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val); 544 if (err) 545 return err; 546 547 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) 548 return 0; 549 550 /* Data Bit Time */ 551 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) | 552 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK, 553 dbt->prop_seg + dbt->phase_seg1 - 1) | 554 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK, 555 dbt->phase_seg2 - 1) | 556 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1); 557 558 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val); 559 if (err) 560 return err; 561 562 /* Transmitter Delay Compensation */ 563 tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1), 564 -64, 63); 565 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, 566 MCP251XFD_REG_TDC_TDCMOD_AUTO) | 567 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco); 568 569 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val); 570 } 571 572 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv) 573 { 574 u32 val; 575 576 if (!priv->rx_int) 577 return 0; 578 579 /* Configure GPIOs: 580 * - PIN0: GPIO Input 581 * - PIN1: GPIO Input/RX Interrupt 582 * 583 * PIN1 must be Input, otherwise there is a glitch on the 584 * rx-INT line. It happens between setting the PIN as output 585 * (in the first byte of the SPI transfer) and configuring the 586 * PIN as interrupt (in the last byte of the SPI transfer). 587 */ 588 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 | 589 MCP251XFD_REG_IOCON_TRIS0; 590 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); 591 } 592 593 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv) 594 { 595 u32 val; 596 597 if (!priv->rx_int) 598 return 0; 599 600 /* Configure GPIOs: 601 * - PIN0: GPIO Input 602 * - PIN1: GPIO Input 603 */ 604 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 | 605 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0; 606 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); 607 } 608 609 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv) 610 { 611 struct mcp251xfd_ecc *ecc = &priv->ecc; 612 void *ram; 613 u32 val = 0; 614 int err; 615 616 ecc->ecc_stat = 0; 617 618 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC) 619 val = MCP251XFD_REG_ECCCON_ECCEN; 620 621 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, 622 MCP251XFD_REG_ECCCON_ECCEN, val); 623 if (err) 624 return err; 625 626 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL); 627 if (!ram) 628 return -ENOMEM; 629 630 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram, 631 MCP251XFD_RAM_SIZE); 632 kfree(ram); 633 634 return err; 635 } 636 637 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv) 638 { 639 u8 mode; 640 641 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 642 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK; 643 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 644 mode = MCP251XFD_REG_CON_MODE_LISTENONLY; 645 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 646 mode = MCP251XFD_REG_CON_MODE_MIXED; 647 else 648 mode = MCP251XFD_REG_CON_MODE_CAN2_0; 649 650 return mode; 651 } 652 653 static int 654 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv, 655 bool nowait) 656 { 657 u8 mode; 658 659 mode = mcp251xfd_get_normal_mode(priv); 660 661 return __mcp251xfd_chip_set_mode(priv, mode, nowait); 662 } 663 664 static inline int 665 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv) 666 { 667 return __mcp251xfd_chip_set_normal_mode(priv, false); 668 } 669 670 static inline int 671 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv) 672 { 673 return __mcp251xfd_chip_set_normal_mode(priv, true); 674 } 675 676 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv) 677 { 678 u32 val; 679 int err; 680 681 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE; 682 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val); 683 if (err) 684 return err; 685 686 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; 687 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val); 688 if (err) 689 return err; 690 691 val = MCP251XFD_REG_INT_CERRIE | 692 MCP251XFD_REG_INT_SERRIE | 693 MCP251XFD_REG_INT_RXOVIE | 694 MCP251XFD_REG_INT_TXATIE | 695 MCP251XFD_REG_INT_SPICRCIE | 696 MCP251XFD_REG_INT_ECCIE | 697 MCP251XFD_REG_INT_TEFIE | 698 MCP251XFD_REG_INT_MODIE | 699 MCP251XFD_REG_INT_RXIE; 700 701 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 702 val |= MCP251XFD_REG_INT_IVMIE; 703 704 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val); 705 } 706 707 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv) 708 { 709 int err; 710 u32 mask; 711 712 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0); 713 if (err) 714 return err; 715 716 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; 717 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, 718 mask, 0x0); 719 if (err) 720 return err; 721 722 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0); 723 } 724 725 static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv, 726 const enum can_state state) 727 { 728 priv->can.state = state; 729 730 mcp251xfd_chip_interrupts_disable(priv); 731 mcp251xfd_chip_rx_int_disable(priv); 732 mcp251xfd_chip_sleep(priv); 733 } 734 735 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv) 736 { 737 int err; 738 739 err = mcp251xfd_chip_softreset(priv); 740 if (err) 741 goto out_chip_stop; 742 743 err = mcp251xfd_chip_clock_init(priv); 744 if (err) 745 goto out_chip_stop; 746 747 err = mcp251xfd_chip_timestamp_init(priv); 748 if (err) 749 goto out_chip_stop; 750 751 err = mcp251xfd_set_bittiming(priv); 752 if (err) 753 goto out_chip_stop; 754 755 err = mcp251xfd_chip_rx_int_enable(priv); 756 if (err) 757 goto out_chip_stop; 758 759 err = mcp251xfd_chip_ecc_init(priv); 760 if (err) 761 goto out_chip_stop; 762 763 err = mcp251xfd_ring_init(priv); 764 if (err) 765 goto out_chip_stop; 766 767 err = mcp251xfd_chip_fifo_init(priv); 768 if (err) 769 goto out_chip_stop; 770 771 priv->can.state = CAN_STATE_ERROR_ACTIVE; 772 773 err = mcp251xfd_chip_set_normal_mode(priv); 774 if (err) 775 goto out_chip_stop; 776 777 return 0; 778 779 out_chip_stop: 780 mcp251xfd_dump(priv); 781 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 782 783 return err; 784 } 785 786 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode) 787 { 788 struct mcp251xfd_priv *priv = netdev_priv(ndev); 789 int err; 790 791 switch (mode) { 792 case CAN_MODE_START: 793 err = mcp251xfd_chip_start(priv); 794 if (err) 795 return err; 796 797 err = mcp251xfd_chip_interrupts_enable(priv); 798 if (err) { 799 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 800 return err; 801 } 802 803 netif_wake_queue(ndev); 804 break; 805 806 default: 807 return -EOPNOTSUPP; 808 } 809 810 return 0; 811 } 812 813 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev, 814 struct can_berr_counter *bec) 815 { 816 const struct mcp251xfd_priv *priv = netdev_priv(ndev); 817 u32 trec; 818 int err; 819 820 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); 821 if (err) 822 return err; 823 824 if (trec & MCP251XFD_REG_TREC_TXBO) 825 bec->txerr = 256; 826 else 827 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec); 828 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec); 829 830 return 0; 831 } 832 833 static int mcp251xfd_get_berr_counter(const struct net_device *ndev, 834 struct can_berr_counter *bec) 835 { 836 const struct mcp251xfd_priv *priv = netdev_priv(ndev); 837 838 /* Avoid waking up the controller if the interface is down */ 839 if (!(ndev->flags & IFF_UP)) 840 return 0; 841 842 /* The controller is powered down during Bus Off, use saved 843 * bec values. 844 */ 845 if (priv->can.state == CAN_STATE_BUS_OFF) { 846 *bec = priv->bec; 847 return 0; 848 } 849 850 return __mcp251xfd_get_berr_counter(ndev, bec); 851 } 852 853 static struct sk_buff * 854 mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv, 855 struct can_frame **cf, u32 *timestamp) 856 { 857 struct sk_buff *skb; 858 int err; 859 860 err = mcp251xfd_get_timestamp(priv, timestamp); 861 if (err) 862 return NULL; 863 864 skb = alloc_can_err_skb(priv->ndev, cf); 865 if (skb) 866 mcp251xfd_skb_set_timestamp(priv, skb, *timestamp); 867 868 return skb; 869 } 870 871 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv) 872 { 873 struct net_device_stats *stats = &priv->ndev->stats; 874 struct mcp251xfd_rx_ring *ring; 875 struct sk_buff *skb; 876 struct can_frame *cf; 877 u32 timestamp, rxovif; 878 int err, i; 879 880 stats->rx_over_errors++; 881 stats->rx_errors++; 882 883 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif); 884 if (err) 885 return err; 886 887 mcp251xfd_for_each_rx_ring(priv, ring, i) { 888 if (!(rxovif & BIT(ring->fifo_nr))) 889 continue; 890 891 /* If SERRIF is active, there was a RX MAB overflow. */ 892 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) { 893 if (net_ratelimit()) 894 netdev_dbg(priv->ndev, 895 "RX-%d: MAB overflow detected.\n", 896 ring->nr); 897 } else { 898 if (net_ratelimit()) 899 netdev_dbg(priv->ndev, 900 "RX-%d: FIFO overflow.\n", 901 ring->nr); 902 } 903 904 err = regmap_update_bits(priv->map_reg, 905 MCP251XFD_REG_FIFOSTA(ring->fifo_nr), 906 MCP251XFD_REG_FIFOSTA_RXOVIF, 907 0x0); 908 if (err) 909 return err; 910 } 911 912 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); 913 if (!skb) 914 return 0; 915 916 cf->can_id |= CAN_ERR_CRTL; 917 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 918 919 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); 920 if (err) 921 stats->rx_fifo_errors++; 922 923 return 0; 924 } 925 926 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv) 927 { 928 netdev_info(priv->ndev, "%s\n", __func__); 929 930 return 0; 931 } 932 933 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv) 934 { 935 struct net_device_stats *stats = &priv->ndev->stats; 936 u32 bdiag1, timestamp; 937 struct sk_buff *skb; 938 struct can_frame *cf = NULL; 939 int err; 940 941 err = mcp251xfd_get_timestamp(priv, ×tamp); 942 if (err) 943 return err; 944 945 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1); 946 if (err) 947 return err; 948 949 /* Write 0s to clear error bits, don't write 1s to non active 950 * bits, as they will be set. 951 */ 952 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0); 953 if (err) 954 return err; 955 956 priv->can.can_stats.bus_error++; 957 958 skb = alloc_can_err_skb(priv->ndev, &cf); 959 if (cf) 960 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 961 962 /* Controller misconfiguration */ 963 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM)) 964 netdev_err(priv->ndev, 965 "recv'd DLC is larger than PLSIZE of FIFO element."); 966 967 /* RX errors */ 968 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR | 969 MCP251XFD_REG_BDIAG1_NCRCERR)) { 970 netdev_dbg(priv->ndev, "CRC error\n"); 971 972 stats->rx_errors++; 973 if (cf) 974 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 975 } 976 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR | 977 MCP251XFD_REG_BDIAG1_NSTUFERR)) { 978 netdev_dbg(priv->ndev, "Stuff error\n"); 979 980 stats->rx_errors++; 981 if (cf) 982 cf->data[2] |= CAN_ERR_PROT_STUFF; 983 } 984 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR | 985 MCP251XFD_REG_BDIAG1_NFORMERR)) { 986 netdev_dbg(priv->ndev, "Format error\n"); 987 988 stats->rx_errors++; 989 if (cf) 990 cf->data[2] |= CAN_ERR_PROT_FORM; 991 } 992 993 /* TX errors */ 994 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) { 995 netdev_dbg(priv->ndev, "NACK error\n"); 996 997 stats->tx_errors++; 998 if (cf) { 999 cf->can_id |= CAN_ERR_ACK; 1000 cf->data[2] |= CAN_ERR_PROT_TX; 1001 } 1002 } 1003 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR | 1004 MCP251XFD_REG_BDIAG1_NBIT1ERR)) { 1005 netdev_dbg(priv->ndev, "Bit1 error\n"); 1006 1007 stats->tx_errors++; 1008 if (cf) 1009 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1; 1010 } 1011 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR | 1012 MCP251XFD_REG_BDIAG1_NBIT0ERR)) { 1013 netdev_dbg(priv->ndev, "Bit0 error\n"); 1014 1015 stats->tx_errors++; 1016 if (cf) 1017 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0; 1018 } 1019 1020 if (!cf) 1021 return 0; 1022 1023 mcp251xfd_skb_set_timestamp(priv, skb, timestamp); 1024 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); 1025 if (err) 1026 stats->rx_fifo_errors++; 1027 1028 return 0; 1029 } 1030 1031 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv) 1032 { 1033 struct net_device_stats *stats = &priv->ndev->stats; 1034 struct sk_buff *skb; 1035 struct can_frame *cf = NULL; 1036 enum can_state new_state, rx_state, tx_state; 1037 u32 trec, timestamp; 1038 int err; 1039 1040 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); 1041 if (err) 1042 return err; 1043 1044 if (trec & MCP251XFD_REG_TREC_TXBO) 1045 tx_state = CAN_STATE_BUS_OFF; 1046 else if (trec & MCP251XFD_REG_TREC_TXBP) 1047 tx_state = CAN_STATE_ERROR_PASSIVE; 1048 else if (trec & MCP251XFD_REG_TREC_TXWARN) 1049 tx_state = CAN_STATE_ERROR_WARNING; 1050 else 1051 tx_state = CAN_STATE_ERROR_ACTIVE; 1052 1053 if (trec & MCP251XFD_REG_TREC_RXBP) 1054 rx_state = CAN_STATE_ERROR_PASSIVE; 1055 else if (trec & MCP251XFD_REG_TREC_RXWARN) 1056 rx_state = CAN_STATE_ERROR_WARNING; 1057 else 1058 rx_state = CAN_STATE_ERROR_ACTIVE; 1059 1060 new_state = max(tx_state, rx_state); 1061 if (new_state == priv->can.state) 1062 return 0; 1063 1064 /* The skb allocation might fail, but can_change_state() 1065 * handles cf == NULL. 1066 */ 1067 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); 1068 can_change_state(priv->ndev, cf, tx_state, rx_state); 1069 1070 if (new_state == CAN_STATE_BUS_OFF) { 1071 /* As we're going to switch off the chip now, let's 1072 * save the error counters and return them to 1073 * userspace, if do_get_berr_counter() is called while 1074 * the chip is in Bus Off. 1075 */ 1076 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec); 1077 if (err) 1078 return err; 1079 1080 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF); 1081 can_bus_off(priv->ndev); 1082 } 1083 1084 if (!skb) 1085 return 0; 1086 1087 if (new_state != CAN_STATE_BUS_OFF) { 1088 struct can_berr_counter bec; 1089 1090 err = mcp251xfd_get_berr_counter(priv->ndev, &bec); 1091 if (err) 1092 return err; 1093 cf->data[6] = bec.txerr; 1094 cf->data[7] = bec.rxerr; 1095 } 1096 1097 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); 1098 if (err) 1099 stats->rx_fifo_errors++; 1100 1101 return 0; 1102 } 1103 1104 static int 1105 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode) 1106 { 1107 const u8 mode_reference = mcp251xfd_get_normal_mode(priv); 1108 u8 mode; 1109 int err; 1110 1111 err = mcp251xfd_chip_get_mode(priv, &mode); 1112 if (err) 1113 return err; 1114 1115 if (mode == mode_reference) { 1116 netdev_dbg(priv->ndev, 1117 "Controller changed into %s Mode (%u).\n", 1118 mcp251xfd_get_mode_str(mode), mode); 1119 return 0; 1120 } 1121 1122 /* According to MCP2517FD errata DS80000792B 1., during a TX 1123 * MAB underflow, the controller will transition to Restricted 1124 * Operation Mode or Listen Only Mode (depending on SERR2LOM). 1125 * 1126 * However this is not always the case. If SERR2LOM is 1127 * configured for Restricted Operation Mode (SERR2LOM not set) 1128 * the MCP2517FD will sometimes transition to Listen Only Mode 1129 * first. When polling this bit we see that it will transition 1130 * to Restricted Operation Mode shortly after. 1131 */ 1132 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) && 1133 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED || 1134 mode == MCP251XFD_REG_CON_MODE_LISTENONLY)) 1135 netdev_dbg(priv->ndev, 1136 "Controller changed into %s Mode (%u).\n", 1137 mcp251xfd_get_mode_str(mode), mode); 1138 else 1139 netdev_err(priv->ndev, 1140 "Controller changed into %s Mode (%u).\n", 1141 mcp251xfd_get_mode_str(mode), mode); 1142 1143 /* After the application requests Normal mode, the controller 1144 * will automatically attempt to retransmit the message that 1145 * caused the TX MAB underflow. 1146 * 1147 * However, if there is an ECC error in the TX-RAM, we first 1148 * have to reload the tx-object before requesting Normal 1149 * mode. This is done later in mcp251xfd_handle_eccif(). 1150 */ 1151 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) { 1152 *set_normal_mode = true; 1153 return 0; 1154 } 1155 1156 return mcp251xfd_chip_set_normal_mode_nowait(priv); 1157 } 1158 1159 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv) 1160 { 1161 struct mcp251xfd_ecc *ecc = &priv->ecc; 1162 struct net_device_stats *stats = &priv->ndev->stats; 1163 bool handled = false; 1164 1165 /* TX MAB underflow 1166 * 1167 * According to MCP2517FD Errata DS80000792B 1. a TX MAB 1168 * underflow is indicated by SERRIF and MODIF. 1169 * 1170 * In addition to the effects mentioned in the Errata, there 1171 * are Bus Errors due to the aborted CAN frame, so a IVMIF 1172 * will be seen as well. 1173 * 1174 * Sometimes there is an ECC error in the TX-RAM, which leads 1175 * to a TX MAB underflow. 1176 * 1177 * However, probably due to a race condition, there is no 1178 * associated MODIF pending. 1179 * 1180 * Further, there are situations, where the SERRIF is caused 1181 * by an ECC error in the TX-RAM, but not even the ECCIF is 1182 * set. This only seems to happen _after_ the first occurrence 1183 * of a ECCIF (which is tracked in ecc->cnt). 1184 * 1185 * Treat all as a known system errors.. 1186 */ 1187 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF && 1188 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) || 1189 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || 1190 ecc->cnt) { 1191 const char *msg; 1192 1193 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || 1194 ecc->cnt) 1195 msg = "TX MAB underflow due to ECC error detected."; 1196 else 1197 msg = "TX MAB underflow detected."; 1198 1199 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) 1200 netdev_dbg(priv->ndev, "%s\n", msg); 1201 else 1202 netdev_info(priv->ndev, "%s\n", msg); 1203 1204 stats->tx_aborted_errors++; 1205 stats->tx_errors++; 1206 handled = true; 1207 } 1208 1209 /* RX MAB overflow 1210 * 1211 * According to MCP2517FD Errata DS80000792B 1. a RX MAB 1212 * overflow is indicated by SERRIF. 1213 * 1214 * In addition to the effects mentioned in the Errata, (most 1215 * of the times) a RXOVIF is raised, if the FIFO that is being 1216 * received into has the RXOVIE activated (and we have enabled 1217 * RXOVIE on all FIFOs). 1218 * 1219 * Sometimes there is no RXOVIF just a RXIF is pending. 1220 * 1221 * Treat all as a known system errors.. 1222 */ 1223 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF || 1224 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) { 1225 stats->rx_dropped++; 1226 handled = true; 1227 } 1228 1229 if (!handled) 1230 netdev_err(priv->ndev, 1231 "Unhandled System Error Interrupt (intf=0x%08x)!\n", 1232 priv->regs_status.intf); 1233 1234 return 0; 1235 } 1236 1237 static int 1238 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr) 1239 { 1240 struct mcp251xfd_tx_ring *tx_ring = priv->tx; 1241 struct mcp251xfd_ecc *ecc = &priv->ecc; 1242 struct mcp251xfd_tx_obj *tx_obj; 1243 u8 chip_tx_tail, tx_tail, offset; 1244 u16 addr; 1245 int err; 1246 1247 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat); 1248 1249 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail); 1250 if (err) 1251 return err; 1252 1253 tx_tail = mcp251xfd_get_tx_tail(tx_ring); 1254 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1); 1255 1256 /* Bail out if one of the following is met: 1257 * - tx_tail information is inconsistent 1258 * - for mcp2517fd: offset not 0 1259 * - for mcp2518fd: offset not 0 or 1 1260 */ 1261 if (chip_tx_tail != tx_tail || 1262 !(offset == 0 || (offset == 1 && mcp251xfd_is_2518(priv)))) { 1263 netdev_err(priv->ndev, 1264 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n", 1265 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail, 1266 offset); 1267 return -EINVAL; 1268 } 1269 1270 netdev_info(priv->ndev, 1271 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n", 1272 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ? 1273 "Single" : "Double", 1274 addr, nr, tx_ring->tail, tx_tail, offset); 1275 1276 /* reload tx_obj into controller RAM ... */ 1277 tx_obj = &tx_ring->obj[nr]; 1278 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1); 1279 if (err) 1280 return err; 1281 1282 /* ... and trigger retransmit */ 1283 return mcp251xfd_chip_set_normal_mode(priv); 1284 } 1285 1286 static int 1287 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode) 1288 { 1289 struct mcp251xfd_ecc *ecc = &priv->ecc; 1290 const char *msg; 1291 bool in_tx_ram; 1292 u32 ecc_stat; 1293 u16 addr; 1294 u8 nr; 1295 int err; 1296 1297 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat); 1298 if (err) 1299 return err; 1300 1301 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT, 1302 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat); 1303 if (err) 1304 return err; 1305 1306 /* Check if ECC error occurred in TX-RAM */ 1307 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat); 1308 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr); 1309 if (!err) 1310 in_tx_ram = true; 1311 else if (err == -ENOENT) 1312 in_tx_ram = false; 1313 else 1314 return err; 1315 1316 /* Errata Reference: 1317 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2. 1318 * 1319 * ECC single error correction does not work in all cases: 1320 * 1321 * Fix/Work Around: 1322 * Enable single error correction and double error detection 1323 * interrupts by setting SECIE and DEDIE. Handle SECIF as a 1324 * detection interrupt and do not rely on the error 1325 * correction. Instead, handle both interrupts as a 1326 * notification that the RAM word at ERRADDR was corrupted. 1327 */ 1328 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF) 1329 msg = "Single ECC Error detected at address"; 1330 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF) 1331 msg = "Double ECC Error detected at address"; 1332 else 1333 return -EINVAL; 1334 1335 if (!in_tx_ram) { 1336 ecc->ecc_stat = 0; 1337 1338 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr); 1339 } else { 1340 /* Re-occurring error? */ 1341 if (ecc->ecc_stat == ecc_stat) { 1342 ecc->cnt++; 1343 } else { 1344 ecc->ecc_stat = ecc_stat; 1345 ecc->cnt = 1; 1346 } 1347 1348 netdev_info(priv->ndev, 1349 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n", 1350 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : ""); 1351 1352 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX) 1353 return mcp251xfd_handle_eccif_recover(priv, nr); 1354 } 1355 1356 if (set_normal_mode) 1357 return mcp251xfd_chip_set_normal_mode_nowait(priv); 1358 1359 return 0; 1360 } 1361 1362 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv) 1363 { 1364 int err; 1365 u32 crc; 1366 1367 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc); 1368 if (err) 1369 return err; 1370 1371 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC, 1372 MCP251XFD_REG_CRC_IF_MASK, 1373 ~crc); 1374 if (err) 1375 return err; 1376 1377 if (crc & MCP251XFD_REG_CRC_FERRIF) 1378 netdev_notice(priv->ndev, "CRC write command format error.\n"); 1379 else if (crc & MCP251XFD_REG_CRC_CRCERRIF) 1380 netdev_notice(priv->ndev, 1381 "CRC write error detected. CRC=0x%04lx.\n", 1382 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc)); 1383 1384 return 0; 1385 } 1386 1387 static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv) 1388 { 1389 const int val_bytes = regmap_get_val_bytes(priv->map_reg); 1390 size_t len; 1391 1392 if (priv->rx_ring_num == 1) 1393 len = sizeof(priv->regs_status.intf); 1394 else 1395 len = sizeof(priv->regs_status); 1396 1397 return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT, 1398 &priv->regs_status, len / val_bytes); 1399 } 1400 1401 #define mcp251xfd_handle(priv, irq, ...) \ 1402 ({ \ 1403 struct mcp251xfd_priv *_priv = (priv); \ 1404 int err; \ 1405 \ 1406 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \ 1407 if (err) \ 1408 netdev_err(_priv->ndev, \ 1409 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \ 1410 __stringify(irq), err); \ 1411 err; \ 1412 }) 1413 1414 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id) 1415 { 1416 struct mcp251xfd_priv *priv = dev_id; 1417 irqreturn_t handled = IRQ_NONE; 1418 int err; 1419 1420 if (priv->rx_int) 1421 do { 1422 int rx_pending; 1423 1424 rx_pending = gpiod_get_value_cansleep(priv->rx_int); 1425 if (!rx_pending) 1426 break; 1427 1428 /* Assume 1st RX-FIFO pending, if other FIFOs 1429 * are pending the main IRQ handler will take 1430 * care. 1431 */ 1432 priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr); 1433 err = mcp251xfd_handle(priv, rxif); 1434 if (err) 1435 goto out_fail; 1436 1437 handled = IRQ_HANDLED; 1438 1439 /* We don't know which RX-FIFO is pending, but only 1440 * handle the 1st RX-FIFO. Leave loop here if we have 1441 * more than 1 RX-FIFO to avoid starvation. 1442 */ 1443 } while (priv->rx_ring_num == 1); 1444 1445 do { 1446 u32 intf_pending, intf_pending_clearable; 1447 bool set_normal_mode = false; 1448 1449 err = mcp251xfd_read_regs_status(priv); 1450 if (err) 1451 goto out_fail; 1452 1453 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK, 1454 priv->regs_status.intf) & 1455 FIELD_GET(MCP251XFD_REG_INT_IE_MASK, 1456 priv->regs_status.intf); 1457 1458 if (!(intf_pending)) { 1459 can_rx_offload_threaded_irq_finish(&priv->offload); 1460 return handled; 1461 } 1462 1463 /* Some interrupts must be ACKed in the 1464 * MCP251XFD_REG_INT register. 1465 * - First ACK then handle, to avoid lost-IRQ race 1466 * condition on fast re-occurring interrupts. 1467 * - Write "0" to clear active IRQs, "1" to all other, 1468 * to avoid r/m/w race condition on the 1469 * MCP251XFD_REG_INT register. 1470 */ 1471 intf_pending_clearable = intf_pending & 1472 MCP251XFD_REG_INT_IF_CLEARABLE_MASK; 1473 if (intf_pending_clearable) { 1474 err = regmap_update_bits(priv->map_reg, 1475 MCP251XFD_REG_INT, 1476 MCP251XFD_REG_INT_IF_MASK, 1477 ~intf_pending_clearable); 1478 if (err) 1479 goto out_fail; 1480 } 1481 1482 if (intf_pending & MCP251XFD_REG_INT_MODIF) { 1483 err = mcp251xfd_handle(priv, modif, &set_normal_mode); 1484 if (err) 1485 goto out_fail; 1486 } 1487 1488 if (intf_pending & MCP251XFD_REG_INT_RXIF) { 1489 err = mcp251xfd_handle(priv, rxif); 1490 if (err) 1491 goto out_fail; 1492 } 1493 1494 if (intf_pending & MCP251XFD_REG_INT_TEFIF) { 1495 err = mcp251xfd_handle(priv, tefif); 1496 if (err) 1497 goto out_fail; 1498 } 1499 1500 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) { 1501 err = mcp251xfd_handle(priv, rxovif); 1502 if (err) 1503 goto out_fail; 1504 } 1505 1506 if (intf_pending & MCP251XFD_REG_INT_TXATIF) { 1507 err = mcp251xfd_handle(priv, txatif); 1508 if (err) 1509 goto out_fail; 1510 } 1511 1512 if (intf_pending & MCP251XFD_REG_INT_IVMIF) { 1513 err = mcp251xfd_handle(priv, ivmif); 1514 if (err) 1515 goto out_fail; 1516 } 1517 1518 if (intf_pending & MCP251XFD_REG_INT_SERRIF) { 1519 err = mcp251xfd_handle(priv, serrif); 1520 if (err) 1521 goto out_fail; 1522 } 1523 1524 if (intf_pending & MCP251XFD_REG_INT_ECCIF) { 1525 err = mcp251xfd_handle(priv, eccif, set_normal_mode); 1526 if (err) 1527 goto out_fail; 1528 } 1529 1530 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) { 1531 err = mcp251xfd_handle(priv, spicrcif); 1532 if (err) 1533 goto out_fail; 1534 } 1535 1536 /* On the MCP2527FD and MCP2518FD, we don't get a 1537 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX 1538 * ERROR_ACTIVE. 1539 */ 1540 if (intf_pending & MCP251XFD_REG_INT_CERRIF || 1541 priv->can.state > CAN_STATE_ERROR_ACTIVE) { 1542 err = mcp251xfd_handle(priv, cerrif); 1543 if (err) 1544 goto out_fail; 1545 1546 /* In Bus Off we completely shut down the 1547 * controller. Every subsequent register read 1548 * will read bogus data, and if 1549 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC 1550 * check will fail, too. So leave IRQ handler 1551 * directly. 1552 */ 1553 if (priv->can.state == CAN_STATE_BUS_OFF) { 1554 can_rx_offload_threaded_irq_finish(&priv->offload); 1555 return IRQ_HANDLED; 1556 } 1557 } 1558 1559 handled = IRQ_HANDLED; 1560 } while (1); 1561 1562 out_fail: 1563 can_rx_offload_threaded_irq_finish(&priv->offload); 1564 1565 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n", 1566 err, priv->regs_status.intf); 1567 mcp251xfd_dump(priv); 1568 mcp251xfd_chip_interrupts_disable(priv); 1569 mcp251xfd_timestamp_stop(priv); 1570 1571 return handled; 1572 } 1573 1574 static int mcp251xfd_open(struct net_device *ndev) 1575 { 1576 struct mcp251xfd_priv *priv = netdev_priv(ndev); 1577 const struct spi_device *spi = priv->spi; 1578 int err; 1579 1580 err = open_candev(ndev); 1581 if (err) 1582 return err; 1583 1584 err = pm_runtime_resume_and_get(ndev->dev.parent); 1585 if (err) 1586 goto out_close_candev; 1587 1588 err = mcp251xfd_ring_alloc(priv); 1589 if (err) 1590 goto out_pm_runtime_put; 1591 1592 err = mcp251xfd_transceiver_enable(priv); 1593 if (err) 1594 goto out_mcp251xfd_ring_free; 1595 1596 err = mcp251xfd_chip_start(priv); 1597 if (err) 1598 goto out_transceiver_disable; 1599 1600 mcp251xfd_timestamp_init(priv); 1601 clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 1602 can_rx_offload_enable(&priv->offload); 1603 1604 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq, 1605 IRQF_SHARED | IRQF_ONESHOT, 1606 dev_name(&spi->dev), priv); 1607 if (err) 1608 goto out_can_rx_offload_disable; 1609 1610 err = mcp251xfd_chip_interrupts_enable(priv); 1611 if (err) 1612 goto out_free_irq; 1613 1614 netif_start_queue(ndev); 1615 1616 return 0; 1617 1618 out_free_irq: 1619 free_irq(spi->irq, priv); 1620 out_can_rx_offload_disable: 1621 can_rx_offload_disable(&priv->offload); 1622 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 1623 mcp251xfd_timestamp_stop(priv); 1624 out_transceiver_disable: 1625 mcp251xfd_transceiver_disable(priv); 1626 out_mcp251xfd_ring_free: 1627 mcp251xfd_ring_free(priv); 1628 out_pm_runtime_put: 1629 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 1630 pm_runtime_put(ndev->dev.parent); 1631 out_close_candev: 1632 close_candev(ndev); 1633 1634 return err; 1635 } 1636 1637 static int mcp251xfd_stop(struct net_device *ndev) 1638 { 1639 struct mcp251xfd_priv *priv = netdev_priv(ndev); 1640 1641 netif_stop_queue(ndev); 1642 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 1643 hrtimer_cancel(&priv->rx_irq_timer); 1644 mcp251xfd_chip_interrupts_disable(priv); 1645 free_irq(ndev->irq, priv); 1646 can_rx_offload_disable(&priv->offload); 1647 mcp251xfd_timestamp_stop(priv); 1648 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 1649 mcp251xfd_transceiver_disable(priv); 1650 mcp251xfd_ring_free(priv); 1651 close_candev(ndev); 1652 1653 pm_runtime_put(ndev->dev.parent); 1654 1655 return 0; 1656 } 1657 1658 static const struct net_device_ops mcp251xfd_netdev_ops = { 1659 .ndo_open = mcp251xfd_open, 1660 .ndo_stop = mcp251xfd_stop, 1661 .ndo_start_xmit = mcp251xfd_start_xmit, 1662 .ndo_change_mtu = can_change_mtu, 1663 }; 1664 1665 static void 1666 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv) 1667 { 1668 const struct spi_device *spi = priv->spi; 1669 const struct spi_controller *ctlr = spi->controller; 1670 1671 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX) 1672 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX; 1673 } 1674 1675 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv) 1676 { 1677 const struct net_device *ndev = priv->ndev; 1678 const struct mcp251xfd_devtype_data *devtype_data; 1679 u32 osc; 1680 int err; 1681 1682 /* The OSC_LPMEN is only supported on MCP2518FD, so use it to 1683 * autodetect the model. 1684 */ 1685 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC, 1686 MCP251XFD_REG_OSC_LPMEN, 1687 MCP251XFD_REG_OSC_LPMEN); 1688 if (err) 1689 return err; 1690 1691 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); 1692 if (err) 1693 return err; 1694 1695 if (osc & MCP251XFD_REG_OSC_LPMEN) 1696 devtype_data = &mcp251xfd_devtype_data_mcp2518fd; 1697 else 1698 devtype_data = &mcp251xfd_devtype_data_mcp2517fd; 1699 1700 if (!mcp251xfd_is_251X(priv) && 1701 priv->devtype_data.model != devtype_data->model) { 1702 netdev_info(ndev, 1703 "Detected %s, but firmware specifies a %s. Fixing up.\n", 1704 __mcp251xfd_get_model_str(devtype_data->model), 1705 mcp251xfd_get_model_str(priv)); 1706 } 1707 priv->devtype_data = *devtype_data; 1708 1709 /* We need to preserve the Half Duplex Quirk. */ 1710 mcp251xfd_register_quirks(priv); 1711 1712 /* Re-init regmap with quirks of detected model. */ 1713 return mcp251xfd_regmap_init(priv); 1714 } 1715 1716 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv) 1717 { 1718 int err, rx_pending; 1719 1720 if (!priv->rx_int) 1721 return 0; 1722 1723 err = mcp251xfd_chip_rx_int_enable(priv); 1724 if (err) 1725 return err; 1726 1727 /* Check if RX_INT is properly working. The RX_INT should not 1728 * be active after a softreset. 1729 */ 1730 rx_pending = gpiod_get_value_cansleep(priv->rx_int); 1731 1732 err = mcp251xfd_chip_rx_int_disable(priv); 1733 if (err) 1734 return err; 1735 1736 if (!rx_pending) 1737 return 0; 1738 1739 netdev_info(priv->ndev, 1740 "RX_INT active after softreset, disabling RX_INT support.\n"); 1741 devm_gpiod_put(&priv->spi->dev, priv->rx_int); 1742 priv->rx_int = NULL; 1743 1744 return 0; 1745 } 1746 1747 static int 1748 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id, 1749 u32 *effective_speed_hz_slow, 1750 u32 *effective_speed_hz_fast) 1751 { 1752 struct mcp251xfd_map_buf_nocrc *buf_rx; 1753 struct mcp251xfd_map_buf_nocrc *buf_tx; 1754 struct spi_transfer xfer[2] = { }; 1755 int err; 1756 1757 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL); 1758 if (!buf_rx) 1759 return -ENOMEM; 1760 1761 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL); 1762 if (!buf_tx) { 1763 err = -ENOMEM; 1764 goto out_kfree_buf_rx; 1765 } 1766 1767 xfer[0].tx_buf = buf_tx; 1768 xfer[0].len = sizeof(buf_tx->cmd); 1769 xfer[0].speed_hz = priv->spi_max_speed_hz_slow; 1770 xfer[1].rx_buf = buf_rx->data; 1771 xfer[1].len = sizeof(dev_id); 1772 xfer[1].speed_hz = priv->spi_max_speed_hz_fast; 1773 1774 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID); 1775 1776 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer)); 1777 if (err) 1778 goto out_kfree_buf_tx; 1779 1780 *dev_id = be32_to_cpup((__be32 *)buf_rx->data); 1781 *effective_speed_hz_slow = xfer[0].effective_speed_hz; 1782 *effective_speed_hz_fast = xfer[1].effective_speed_hz; 1783 1784 out_kfree_buf_tx: 1785 kfree(buf_tx); 1786 out_kfree_buf_rx: 1787 kfree(buf_rx); 1788 1789 return err; 1790 } 1791 1792 #define MCP251XFD_QUIRK_ACTIVE(quirk) \ 1793 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-') 1794 1795 static int 1796 mcp251xfd_register_done(const struct mcp251xfd_priv *priv) 1797 { 1798 u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast; 1799 unsigned long clk_rate; 1800 int err; 1801 1802 err = mcp251xfd_register_get_dev_id(priv, &dev_id, 1803 &effective_speed_hz_slow, 1804 &effective_speed_hz_fast); 1805 if (err) 1806 return err; 1807 1808 clk_rate = clk_get_rate(priv->clk); 1809 1810 netdev_info(priv->ndev, 1811 "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n", 1812 mcp251xfd_get_model_str(priv), 1813 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id), 1814 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id), 1815 priv->rx_int ? '+' : '-', 1816 priv->pll_enable ? '+' : '-', 1817 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN), 1818 MCP251XFD_QUIRK_ACTIVE(CRC_REG), 1819 MCP251XFD_QUIRK_ACTIVE(CRC_RX), 1820 MCP251XFD_QUIRK_ACTIVE(CRC_TX), 1821 MCP251XFD_QUIRK_ACTIVE(ECC), 1822 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX), 1823 clk_rate / 1000000, 1824 clk_rate % 1000000 / 1000 / 10, 1825 priv->can.clock.freq / 1000000, 1826 priv->can.clock.freq % 1000000 / 1000 / 10, 1827 priv->spi_max_speed_hz_orig / 1000000, 1828 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10, 1829 priv->spi_max_speed_hz_slow / 1000000, 1830 priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10, 1831 effective_speed_hz_slow / 1000000, 1832 effective_speed_hz_slow % 1000000 / 1000 / 10, 1833 priv->spi_max_speed_hz_fast / 1000000, 1834 priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10, 1835 effective_speed_hz_fast / 1000000, 1836 effective_speed_hz_fast % 1000000 / 1000 / 10); 1837 1838 return 0; 1839 } 1840 1841 static int mcp251xfd_register(struct mcp251xfd_priv *priv) 1842 { 1843 struct net_device *ndev = priv->ndev; 1844 int err; 1845 1846 err = mcp251xfd_clks_and_vdd_enable(priv); 1847 if (err) 1848 return err; 1849 1850 pm_runtime_get_noresume(ndev->dev.parent); 1851 err = pm_runtime_set_active(ndev->dev.parent); 1852 if (err) 1853 goto out_runtime_put_noidle; 1854 pm_runtime_enable(ndev->dev.parent); 1855 1856 mcp251xfd_register_quirks(priv); 1857 1858 err = mcp251xfd_chip_softreset(priv); 1859 if (err == -ENODEV) 1860 goto out_runtime_disable; 1861 if (err) 1862 goto out_chip_sleep; 1863 1864 err = mcp251xfd_chip_clock_init(priv); 1865 if (err == -ENODEV) 1866 goto out_runtime_disable; 1867 if (err) 1868 goto out_chip_sleep; 1869 1870 err = mcp251xfd_register_chip_detect(priv); 1871 if (err) 1872 goto out_chip_sleep; 1873 1874 err = mcp251xfd_register_check_rx_int(priv); 1875 if (err) 1876 goto out_chip_sleep; 1877 1878 mcp251xfd_ethtool_init(priv); 1879 1880 err = register_candev(ndev); 1881 if (err) 1882 goto out_chip_sleep; 1883 1884 err = mcp251xfd_register_done(priv); 1885 if (err) 1886 goto out_unregister_candev; 1887 1888 /* Put controller into sleep mode and let pm_runtime_put() 1889 * disable the clocks and vdd. If CONFIG_PM is not enabled, 1890 * the clocks and vdd will stay powered. 1891 */ 1892 err = mcp251xfd_chip_sleep(priv); 1893 if (err) 1894 goto out_unregister_candev; 1895 1896 pm_runtime_put(ndev->dev.parent); 1897 1898 return 0; 1899 1900 out_unregister_candev: 1901 unregister_candev(ndev); 1902 out_chip_sleep: 1903 mcp251xfd_chip_sleep(priv); 1904 out_runtime_disable: 1905 pm_runtime_disable(ndev->dev.parent); 1906 out_runtime_put_noidle: 1907 pm_runtime_put_noidle(ndev->dev.parent); 1908 mcp251xfd_clks_and_vdd_disable(priv); 1909 1910 return err; 1911 } 1912 1913 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv) 1914 { 1915 struct net_device *ndev = priv->ndev; 1916 1917 unregister_candev(ndev); 1918 1919 if (pm_runtime_enabled(ndev->dev.parent)) 1920 pm_runtime_disable(ndev->dev.parent); 1921 else 1922 mcp251xfd_clks_and_vdd_disable(priv); 1923 } 1924 1925 static const struct of_device_id mcp251xfd_of_match[] = { 1926 { 1927 .compatible = "microchip,mcp2517fd", 1928 .data = &mcp251xfd_devtype_data_mcp2517fd, 1929 }, { 1930 .compatible = "microchip,mcp2518fd", 1931 .data = &mcp251xfd_devtype_data_mcp2518fd, 1932 }, { 1933 .compatible = "microchip,mcp251xfd", 1934 .data = &mcp251xfd_devtype_data_mcp251xfd, 1935 }, { 1936 /* sentinel */ 1937 }, 1938 }; 1939 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match); 1940 1941 static const struct spi_device_id mcp251xfd_id_table[] = { 1942 { 1943 .name = "mcp2517fd", 1944 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd, 1945 }, { 1946 .name = "mcp2518fd", 1947 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd, 1948 }, { 1949 .name = "mcp251xfd", 1950 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd, 1951 }, { 1952 /* sentinel */ 1953 }, 1954 }; 1955 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table); 1956 1957 static int mcp251xfd_probe(struct spi_device *spi) 1958 { 1959 const void *match; 1960 struct net_device *ndev; 1961 struct mcp251xfd_priv *priv; 1962 struct gpio_desc *rx_int; 1963 struct regulator *reg_vdd, *reg_xceiver; 1964 struct clk *clk; 1965 bool pll_enable = false; 1966 u32 freq = 0; 1967 int err; 1968 1969 if (!spi->irq) 1970 return dev_err_probe(&spi->dev, -ENXIO, 1971 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n"); 1972 1973 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int", 1974 GPIOD_IN); 1975 if (IS_ERR(rx_int)) 1976 return dev_err_probe(&spi->dev, PTR_ERR(rx_int), 1977 "Failed to get RX-INT!\n"); 1978 1979 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd"); 1980 if (PTR_ERR(reg_vdd) == -ENODEV) 1981 reg_vdd = NULL; 1982 else if (IS_ERR(reg_vdd)) 1983 return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd), 1984 "Failed to get VDD regulator!\n"); 1985 1986 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 1987 if (PTR_ERR(reg_xceiver) == -ENODEV) 1988 reg_xceiver = NULL; 1989 else if (IS_ERR(reg_xceiver)) 1990 return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver), 1991 "Failed to get Transceiver regulator!\n"); 1992 1993 clk = devm_clk_get_optional(&spi->dev, NULL); 1994 if (IS_ERR(clk)) 1995 return dev_err_probe(&spi->dev, PTR_ERR(clk), 1996 "Failed to get Oscillator (clock)!\n"); 1997 if (clk) { 1998 freq = clk_get_rate(clk); 1999 } else { 2000 err = device_property_read_u32(&spi->dev, "clock-frequency", 2001 &freq); 2002 if (err) 2003 return dev_err_probe(&spi->dev, err, 2004 "Failed to get clock-frequency!\n"); 2005 } 2006 2007 /* Sanity check */ 2008 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN || 2009 freq > MCP251XFD_SYSCLOCK_HZ_MAX) { 2010 dev_err(&spi->dev, 2011 "Oscillator frequency (%u Hz) is too low or high.\n", 2012 freq); 2013 return -ERANGE; 2014 } 2015 2016 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER) 2017 pll_enable = true; 2018 2019 ndev = alloc_candev(sizeof(struct mcp251xfd_priv), 2020 MCP251XFD_TX_OBJ_NUM_MAX); 2021 if (!ndev) 2022 return -ENOMEM; 2023 2024 SET_NETDEV_DEV(ndev, &spi->dev); 2025 2026 ndev->netdev_ops = &mcp251xfd_netdev_ops; 2027 ndev->irq = spi->irq; 2028 ndev->flags |= IFF_ECHO; 2029 2030 priv = netdev_priv(ndev); 2031 spi_set_drvdata(spi, priv); 2032 priv->can.clock.freq = freq; 2033 if (pll_enable) 2034 priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER; 2035 priv->can.do_set_mode = mcp251xfd_set_mode; 2036 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter; 2037 priv->can.bittiming_const = &mcp251xfd_bittiming_const; 2038 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const; 2039 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 2040 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING | 2041 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO | 2042 CAN_CTRLMODE_CC_LEN8_DLC; 2043 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 2044 priv->ndev = ndev; 2045 priv->spi = spi; 2046 priv->rx_int = rx_int; 2047 priv->clk = clk; 2048 priv->pll_enable = pll_enable; 2049 priv->reg_vdd = reg_vdd; 2050 priv->reg_xceiver = reg_xceiver; 2051 2052 match = device_get_match_data(&spi->dev); 2053 if (match) 2054 priv->devtype_data = *(struct mcp251xfd_devtype_data *)match; 2055 else 2056 priv->devtype_data = *(struct mcp251xfd_devtype_data *) 2057 spi_get_device_id(spi)->driver_data; 2058 2059 /* Errata Reference: 2060 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789C 4. 2061 * 2062 * The SPI can write corrupted data to the RAM at fast SPI 2063 * speeds: 2064 * 2065 * Simultaneous activity on the CAN bus while writing data to 2066 * RAM via the SPI interface, with high SCK frequency, can 2067 * lead to corrupted data being written to RAM. 2068 * 2069 * Fix/Work Around: 2070 * Ensure that FSCK is less than or equal to 0.85 * 2071 * (FSYSCLK/2). 2072 * 2073 * Known good combinations are: 2074 * 2075 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config 2076 * 2077 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx> 2078 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx> 2079 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default 2080 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default 2081 * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default 2082 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT> 2083 * 2084 */ 2085 priv->spi_max_speed_hz_orig = spi->max_speed_hz; 2086 priv->spi_max_speed_hz_slow = min(spi->max_speed_hz, 2087 freq / 2 / 1000 * 850); 2088 if (priv->pll_enable) 2089 priv->spi_max_speed_hz_fast = min(spi->max_speed_hz, 2090 freq * 2091 MCP251XFD_OSC_PLL_MULTIPLIER / 2092 2 / 1000 * 850); 2093 else 2094 priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow; 2095 spi->max_speed_hz = priv->spi_max_speed_hz_slow; 2096 spi->bits_per_word = 8; 2097 spi->rt = true; 2098 err = spi_setup(spi); 2099 if (err) 2100 goto out_free_candev; 2101 2102 err = mcp251xfd_regmap_init(priv); 2103 if (err) 2104 goto out_free_candev; 2105 2106 err = can_rx_offload_add_manual(ndev, &priv->offload, 2107 MCP251XFD_NAPI_WEIGHT); 2108 if (err) 2109 goto out_free_candev; 2110 2111 err = mcp251xfd_register(priv); 2112 if (err) { 2113 dev_err_probe(&spi->dev, err, "Failed to detect %s.\n", 2114 mcp251xfd_get_model_str(priv)); 2115 goto out_can_rx_offload_del; 2116 } 2117 2118 return 0; 2119 2120 out_can_rx_offload_del: 2121 can_rx_offload_del(&priv->offload); 2122 out_free_candev: 2123 spi->max_speed_hz = priv->spi_max_speed_hz_orig; 2124 2125 free_candev(ndev); 2126 2127 return err; 2128 } 2129 2130 static void mcp251xfd_remove(struct spi_device *spi) 2131 { 2132 struct mcp251xfd_priv *priv = spi_get_drvdata(spi); 2133 struct net_device *ndev = priv->ndev; 2134 2135 can_rx_offload_del(&priv->offload); 2136 mcp251xfd_unregister(priv); 2137 spi->max_speed_hz = priv->spi_max_speed_hz_orig; 2138 free_candev(ndev); 2139 } 2140 2141 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device) 2142 { 2143 const struct mcp251xfd_priv *priv = dev_get_drvdata(device); 2144 2145 return mcp251xfd_clks_and_vdd_disable(priv); 2146 } 2147 2148 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device) 2149 { 2150 const struct mcp251xfd_priv *priv = dev_get_drvdata(device); 2151 2152 return mcp251xfd_clks_and_vdd_enable(priv); 2153 } 2154 2155 static const struct dev_pm_ops mcp251xfd_pm_ops = { 2156 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend, 2157 mcp251xfd_runtime_resume, NULL) 2158 }; 2159 2160 static struct spi_driver mcp251xfd_driver = { 2161 .driver = { 2162 .name = DEVICE_NAME, 2163 .pm = &mcp251xfd_pm_ops, 2164 .of_match_table = mcp251xfd_of_match, 2165 }, 2166 .probe = mcp251xfd_probe, 2167 .remove = mcp251xfd_remove, 2168 .id_table = mcp251xfd_id_table, 2169 }; 2170 module_spi_driver(mcp251xfd_driver); 2171 2172 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 2173 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver"); 2174 MODULE_LICENSE("GPL v2"); 2175