1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface 4 * 5 * MCP2510 support and bug fixes by Christian Pellegrin 6 * <chripell@evolware.org> 7 * 8 * Copyright 2009 Christian Pellegrin EVOL S.r.l. 9 * 10 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. 11 * Written under contract by: 12 * Chris Elston, Katalix Systems, Ltd. 13 * 14 * Based on Microchip MCP251x CAN controller driver written by 15 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. 16 * 17 * Based on CAN bus driver for the CCAN controller written by 18 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix 19 * - Simon Kallweit, intefo AG 20 * Copyright 2007 21 * 22 * Your platform definition file should specify something like: 23 * 24 * static struct mcp251x_platform_data mcp251x_info = { 25 * .oscillator_frequency = 8000000, 26 * }; 27 * 28 * static struct spi_board_info spi_board_info[] = { 29 * { 30 * .modalias = "mcp2510", 31 * // "mcp2515" or "mcp25625" depending on your controller 32 * .platform_data = &mcp251x_info, 33 * .irq = IRQ_EINT13, 34 * .max_speed_hz = 2*1000*1000, 35 * .chip_select = 2, 36 * }, 37 * }; 38 * 39 * Please see mcp251x.h for a description of the fields in 40 * struct mcp251x_platform_data. 41 */ 42 43 #include <linux/can/core.h> 44 #include <linux/can/dev.h> 45 #include <linux/can/led.h> 46 #include <linux/can/platform/mcp251x.h> 47 #include <linux/clk.h> 48 #include <linux/completion.h> 49 #include <linux/delay.h> 50 #include <linux/device.h> 51 #include <linux/dma-mapping.h> 52 #include <linux/freezer.h> 53 #include <linux/interrupt.h> 54 #include <linux/io.h> 55 #include <linux/kernel.h> 56 #include <linux/module.h> 57 #include <linux/netdevice.h> 58 #include <linux/of.h> 59 #include <linux/of_device.h> 60 #include <linux/platform_device.h> 61 #include <linux/slab.h> 62 #include <linux/spi/spi.h> 63 #include <linux/uaccess.h> 64 #include <linux/regulator/consumer.h> 65 66 /* SPI interface instruction set */ 67 #define INSTRUCTION_WRITE 0x02 68 #define INSTRUCTION_READ 0x03 69 #define INSTRUCTION_BIT_MODIFY 0x05 70 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n)) 71 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94) 72 #define INSTRUCTION_RESET 0xC0 73 #define RTS_TXB0 0x01 74 #define RTS_TXB1 0x02 75 #define RTS_TXB2 0x04 76 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07)) 77 78 79 /* MPC251x registers */ 80 #define CANSTAT 0x0e 81 #define CANCTRL 0x0f 82 # define CANCTRL_REQOP_MASK 0xe0 83 # define CANCTRL_REQOP_CONF 0x80 84 # define CANCTRL_REQOP_LISTEN_ONLY 0x60 85 # define CANCTRL_REQOP_LOOPBACK 0x40 86 # define CANCTRL_REQOP_SLEEP 0x20 87 # define CANCTRL_REQOP_NORMAL 0x00 88 # define CANCTRL_OSM 0x08 89 # define CANCTRL_ABAT 0x10 90 #define TEC 0x1c 91 #define REC 0x1d 92 #define CNF1 0x2a 93 # define CNF1_SJW_SHIFT 6 94 #define CNF2 0x29 95 # define CNF2_BTLMODE 0x80 96 # define CNF2_SAM 0x40 97 # define CNF2_PS1_SHIFT 3 98 #define CNF3 0x28 99 # define CNF3_SOF 0x08 100 # define CNF3_WAKFIL 0x04 101 # define CNF3_PHSEG2_MASK 0x07 102 #define CANINTE 0x2b 103 # define CANINTE_MERRE 0x80 104 # define CANINTE_WAKIE 0x40 105 # define CANINTE_ERRIE 0x20 106 # define CANINTE_TX2IE 0x10 107 # define CANINTE_TX1IE 0x08 108 # define CANINTE_TX0IE 0x04 109 # define CANINTE_RX1IE 0x02 110 # define CANINTE_RX0IE 0x01 111 #define CANINTF 0x2c 112 # define CANINTF_MERRF 0x80 113 # define CANINTF_WAKIF 0x40 114 # define CANINTF_ERRIF 0x20 115 # define CANINTF_TX2IF 0x10 116 # define CANINTF_TX1IF 0x08 117 # define CANINTF_TX0IF 0x04 118 # define CANINTF_RX1IF 0x02 119 # define CANINTF_RX0IF 0x01 120 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF) 121 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF) 122 # define CANINTF_ERR (CANINTF_ERRIF) 123 #define EFLG 0x2d 124 # define EFLG_EWARN 0x01 125 # define EFLG_RXWAR 0x02 126 # define EFLG_TXWAR 0x04 127 # define EFLG_RXEP 0x08 128 # define EFLG_TXEP 0x10 129 # define EFLG_TXBO 0x20 130 # define EFLG_RX0OVR 0x40 131 # define EFLG_RX1OVR 0x80 132 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF) 133 # define TXBCTRL_ABTF 0x40 134 # define TXBCTRL_MLOA 0x20 135 # define TXBCTRL_TXERR 0x10 136 # define TXBCTRL_TXREQ 0x08 137 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF) 138 # define SIDH_SHIFT 3 139 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF) 140 # define SIDL_SID_MASK 7 141 # define SIDL_SID_SHIFT 5 142 # define SIDL_EXIDE_SHIFT 3 143 # define SIDL_EID_SHIFT 16 144 # define SIDL_EID_MASK 3 145 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF) 146 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF) 147 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF) 148 # define DLC_RTR_SHIFT 6 149 #define TXBCTRL_OFF 0 150 #define TXBSIDH_OFF 1 151 #define TXBSIDL_OFF 2 152 #define TXBEID8_OFF 3 153 #define TXBEID0_OFF 4 154 #define TXBDLC_OFF 5 155 #define TXBDAT_OFF 6 156 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF) 157 # define RXBCTRL_BUKT 0x04 158 # define RXBCTRL_RXM0 0x20 159 # define RXBCTRL_RXM1 0x40 160 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF) 161 # define RXBSIDH_SHIFT 3 162 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF) 163 # define RXBSIDL_IDE 0x08 164 # define RXBSIDL_SRR 0x10 165 # define RXBSIDL_EID 3 166 # define RXBSIDL_SHIFT 5 167 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF) 168 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF) 169 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF) 170 # define RXBDLC_LEN_MASK 0x0f 171 # define RXBDLC_RTR 0x40 172 #define RXBCTRL_OFF 0 173 #define RXBSIDH_OFF 1 174 #define RXBSIDL_OFF 2 175 #define RXBEID8_OFF 3 176 #define RXBEID0_OFF 4 177 #define RXBDLC_OFF 5 178 #define RXBDAT_OFF 6 179 #define RXFSID(n) ((n < 3) ? 0 : 4) 180 #define RXFSIDH(n) ((n) * 4 + RXFSID(n)) 181 #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n)) 182 #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n)) 183 #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n)) 184 #define RXMSIDH(n) ((n) * 4 + 0x20) 185 #define RXMSIDL(n) ((n) * 4 + 0x21) 186 #define RXMEID8(n) ((n) * 4 + 0x22) 187 #define RXMEID0(n) ((n) * 4 + 0x23) 188 189 #define GET_BYTE(val, byte) \ 190 (((val) >> ((byte) * 8)) & 0xff) 191 #define SET_BYTE(val, byte) \ 192 (((val) & 0xff) << ((byte) * 8)) 193 194 /* 195 * Buffer size required for the largest SPI transfer (i.e., reading a 196 * frame) 197 */ 198 #define CAN_FRAME_MAX_DATA_LEN 8 199 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN) 200 #define CAN_FRAME_MAX_BITS 128 201 202 #define TX_ECHO_SKB_MAX 1 203 204 #define MCP251X_OST_DELAY_MS (5) 205 206 #define DEVICE_NAME "mcp251x" 207 208 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */ 209 module_param(mcp251x_enable_dma, int, 0444); 210 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)"); 211 212 static const struct can_bittiming_const mcp251x_bittiming_const = { 213 .name = DEVICE_NAME, 214 .tseg1_min = 3, 215 .tseg1_max = 16, 216 .tseg2_min = 2, 217 .tseg2_max = 8, 218 .sjw_max = 4, 219 .brp_min = 1, 220 .brp_max = 64, 221 .brp_inc = 1, 222 }; 223 224 enum mcp251x_model { 225 CAN_MCP251X_MCP2510 = 0x2510, 226 CAN_MCP251X_MCP2515 = 0x2515, 227 CAN_MCP251X_MCP25625 = 0x25625, 228 }; 229 230 struct mcp251x_priv { 231 struct can_priv can; 232 struct net_device *net; 233 struct spi_device *spi; 234 enum mcp251x_model model; 235 236 struct mutex mcp_lock; /* SPI device lock */ 237 238 u8 *spi_tx_buf; 239 u8 *spi_rx_buf; 240 dma_addr_t spi_tx_dma; 241 dma_addr_t spi_rx_dma; 242 243 struct sk_buff *tx_skb; 244 int tx_len; 245 246 struct workqueue_struct *wq; 247 struct work_struct tx_work; 248 struct work_struct restart_work; 249 250 int force_quit; 251 int after_suspend; 252 #define AFTER_SUSPEND_UP 1 253 #define AFTER_SUSPEND_DOWN 2 254 #define AFTER_SUSPEND_POWER 4 255 #define AFTER_SUSPEND_RESTART 8 256 int restart_tx; 257 struct regulator *power; 258 struct regulator *transceiver; 259 struct clk *clk; 260 }; 261 262 #define MCP251X_IS(_model) \ 263 static inline int mcp251x_is_##_model(struct spi_device *spi) \ 264 { \ 265 struct mcp251x_priv *priv = spi_get_drvdata(spi); \ 266 return priv->model == CAN_MCP251X_MCP##_model; \ 267 } 268 269 MCP251X_IS(2510); 270 271 static void mcp251x_clean(struct net_device *net) 272 { 273 struct mcp251x_priv *priv = netdev_priv(net); 274 275 if (priv->tx_skb || priv->tx_len) 276 net->stats.tx_errors++; 277 if (priv->tx_skb) 278 dev_kfree_skb(priv->tx_skb); 279 if (priv->tx_len) 280 can_free_echo_skb(priv->net, 0); 281 priv->tx_skb = NULL; 282 priv->tx_len = 0; 283 } 284 285 /* 286 * Note about handling of error return of mcp251x_spi_trans: accessing 287 * registers via SPI is not really different conceptually than using 288 * normal I/O assembler instructions, although it's much more 289 * complicated from a practical POV. So it's not advisable to always 290 * check the return value of this function. Imagine that every 291 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) 292 * error();", it would be a great mess (well there are some situation 293 * when exception handling C++ like could be useful after all). So we 294 * just check that transfers are OK at the beginning of our 295 * conversation with the chip and to avoid doing really nasty things 296 * (like injecting bogus packets in the network stack). 297 */ 298 static int mcp251x_spi_trans(struct spi_device *spi, int len) 299 { 300 struct mcp251x_priv *priv = spi_get_drvdata(spi); 301 struct spi_transfer t = { 302 .tx_buf = priv->spi_tx_buf, 303 .rx_buf = priv->spi_rx_buf, 304 .len = len, 305 .cs_change = 0, 306 }; 307 struct spi_message m; 308 int ret; 309 310 spi_message_init(&m); 311 312 if (mcp251x_enable_dma) { 313 t.tx_dma = priv->spi_tx_dma; 314 t.rx_dma = priv->spi_rx_dma; 315 m.is_dma_mapped = 1; 316 } 317 318 spi_message_add_tail(&t, &m); 319 320 ret = spi_sync(spi, &m); 321 if (ret) 322 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); 323 return ret; 324 } 325 326 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) 327 { 328 struct mcp251x_priv *priv = spi_get_drvdata(spi); 329 u8 val = 0; 330 331 priv->spi_tx_buf[0] = INSTRUCTION_READ; 332 priv->spi_tx_buf[1] = reg; 333 334 mcp251x_spi_trans(spi, 3); 335 val = priv->spi_rx_buf[2]; 336 337 return val; 338 } 339 340 static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg, 341 uint8_t *v1, uint8_t *v2) 342 { 343 struct mcp251x_priv *priv = spi_get_drvdata(spi); 344 345 priv->spi_tx_buf[0] = INSTRUCTION_READ; 346 priv->spi_tx_buf[1] = reg; 347 348 mcp251x_spi_trans(spi, 4); 349 350 *v1 = priv->spi_rx_buf[2]; 351 *v2 = priv->spi_rx_buf[3]; 352 } 353 354 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val) 355 { 356 struct mcp251x_priv *priv = spi_get_drvdata(spi); 357 358 priv->spi_tx_buf[0] = INSTRUCTION_WRITE; 359 priv->spi_tx_buf[1] = reg; 360 priv->spi_tx_buf[2] = val; 361 362 mcp251x_spi_trans(spi, 3); 363 } 364 365 static void mcp251x_write_bits(struct spi_device *spi, u8 reg, 366 u8 mask, uint8_t val) 367 { 368 struct mcp251x_priv *priv = spi_get_drvdata(spi); 369 370 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY; 371 priv->spi_tx_buf[1] = reg; 372 priv->spi_tx_buf[2] = mask; 373 priv->spi_tx_buf[3] = val; 374 375 mcp251x_spi_trans(spi, 4); 376 } 377 378 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, 379 int len, int tx_buf_idx) 380 { 381 struct mcp251x_priv *priv = spi_get_drvdata(spi); 382 383 if (mcp251x_is_2510(spi)) { 384 int i; 385 386 for (i = 1; i < TXBDAT_OFF + len; i++) 387 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i, 388 buf[i]); 389 } else { 390 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len); 391 mcp251x_spi_trans(spi, TXBDAT_OFF + len); 392 } 393 } 394 395 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, 396 int tx_buf_idx) 397 { 398 struct mcp251x_priv *priv = spi_get_drvdata(spi); 399 u32 sid, eid, exide, rtr; 400 u8 buf[SPI_TRANSFER_BUF_LEN]; 401 402 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */ 403 if (exide) 404 sid = (frame->can_id & CAN_EFF_MASK) >> 18; 405 else 406 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */ 407 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */ 408 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */ 409 410 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx); 411 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT; 412 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) | 413 (exide << SIDL_EXIDE_SHIFT) | 414 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK); 415 buf[TXBEID8_OFF] = GET_BYTE(eid, 1); 416 buf[TXBEID0_OFF] = GET_BYTE(eid, 0); 417 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc; 418 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc); 419 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx); 420 421 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */ 422 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx); 423 mcp251x_spi_trans(priv->spi, 1); 424 } 425 426 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, 427 int buf_idx) 428 { 429 struct mcp251x_priv *priv = spi_get_drvdata(spi); 430 431 if (mcp251x_is_2510(spi)) { 432 int i, len; 433 434 for (i = 1; i < RXBDAT_OFF; i++) 435 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); 436 437 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); 438 for (; i < (RXBDAT_OFF + len); i++) 439 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); 440 } else { 441 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx); 442 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN); 443 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN); 444 } 445 } 446 447 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx) 448 { 449 struct mcp251x_priv *priv = spi_get_drvdata(spi); 450 struct sk_buff *skb; 451 struct can_frame *frame; 452 u8 buf[SPI_TRANSFER_BUF_LEN]; 453 454 skb = alloc_can_skb(priv->net, &frame); 455 if (!skb) { 456 dev_err(&spi->dev, "cannot allocate RX skb\n"); 457 priv->net->stats.rx_dropped++; 458 return; 459 } 460 461 mcp251x_hw_rx_frame(spi, buf, buf_idx); 462 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) { 463 /* Extended ID format */ 464 frame->can_id = CAN_EFF_FLAG; 465 frame->can_id |= 466 /* Extended ID part */ 467 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) | 468 SET_BYTE(buf[RXBEID8_OFF], 1) | 469 SET_BYTE(buf[RXBEID0_OFF], 0) | 470 /* Standard ID part */ 471 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | 472 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18); 473 /* Remote transmission request */ 474 if (buf[RXBDLC_OFF] & RXBDLC_RTR) 475 frame->can_id |= CAN_RTR_FLAG; 476 } else { 477 /* Standard ID format */ 478 frame->can_id = 479 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | 480 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT); 481 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR) 482 frame->can_id |= CAN_RTR_FLAG; 483 } 484 /* Data length */ 485 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); 486 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc); 487 488 priv->net->stats.rx_packets++; 489 priv->net->stats.rx_bytes += frame->can_dlc; 490 491 can_led_event(priv->net, CAN_LED_EVENT_RX); 492 493 netif_rx_ni(skb); 494 } 495 496 static void mcp251x_hw_sleep(struct spi_device *spi) 497 { 498 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP); 499 } 500 501 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb, 502 struct net_device *net) 503 { 504 struct mcp251x_priv *priv = netdev_priv(net); 505 struct spi_device *spi = priv->spi; 506 507 if (priv->tx_skb || priv->tx_len) { 508 dev_warn(&spi->dev, "hard_xmit called while tx busy\n"); 509 return NETDEV_TX_BUSY; 510 } 511 512 if (can_dropped_invalid_skb(net, skb)) 513 return NETDEV_TX_OK; 514 515 netif_stop_queue(net); 516 priv->tx_skb = skb; 517 queue_work(priv->wq, &priv->tx_work); 518 519 return NETDEV_TX_OK; 520 } 521 522 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode) 523 { 524 struct mcp251x_priv *priv = netdev_priv(net); 525 526 switch (mode) { 527 case CAN_MODE_START: 528 mcp251x_clean(net); 529 /* We have to delay work since SPI I/O may sleep */ 530 priv->can.state = CAN_STATE_ERROR_ACTIVE; 531 priv->restart_tx = 1; 532 if (priv->can.restart_ms == 0) 533 priv->after_suspend = AFTER_SUSPEND_RESTART; 534 queue_work(priv->wq, &priv->restart_work); 535 break; 536 default: 537 return -EOPNOTSUPP; 538 } 539 540 return 0; 541 } 542 543 static int mcp251x_set_normal_mode(struct spi_device *spi) 544 { 545 struct mcp251x_priv *priv = spi_get_drvdata(spi); 546 unsigned long timeout; 547 548 /* Enable interrupts */ 549 mcp251x_write_reg(spi, CANINTE, 550 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE | 551 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE); 552 553 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 554 /* Put device into loopback mode */ 555 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK); 556 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 557 /* Put device into listen-only mode */ 558 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY); 559 } else { 560 /* Put device into normal mode */ 561 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL); 562 563 /* Wait for the device to enter normal mode */ 564 timeout = jiffies + HZ; 565 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) { 566 schedule(); 567 if (time_after(jiffies, timeout)) { 568 dev_err(&spi->dev, "MCP251x didn't" 569 " enter in normal mode\n"); 570 return -EBUSY; 571 } 572 } 573 } 574 priv->can.state = CAN_STATE_ERROR_ACTIVE; 575 return 0; 576 } 577 578 static int mcp251x_do_set_bittiming(struct net_device *net) 579 { 580 struct mcp251x_priv *priv = netdev_priv(net); 581 struct can_bittiming *bt = &priv->can.bittiming; 582 struct spi_device *spi = priv->spi; 583 584 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) | 585 (bt->brp - 1)); 586 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE | 587 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ? 588 CNF2_SAM : 0) | 589 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) | 590 (bt->prop_seg - 1)); 591 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK, 592 (bt->phase_seg2 - 1)); 593 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n", 594 mcp251x_read_reg(spi, CNF1), 595 mcp251x_read_reg(spi, CNF2), 596 mcp251x_read_reg(spi, CNF3)); 597 598 return 0; 599 } 600 601 static int mcp251x_setup(struct net_device *net, struct spi_device *spi) 602 { 603 mcp251x_do_set_bittiming(net); 604 605 mcp251x_write_reg(spi, RXBCTRL(0), 606 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1); 607 mcp251x_write_reg(spi, RXBCTRL(1), 608 RXBCTRL_RXM0 | RXBCTRL_RXM1); 609 return 0; 610 } 611 612 static int mcp251x_hw_reset(struct spi_device *spi) 613 { 614 struct mcp251x_priv *priv = spi_get_drvdata(spi); 615 u8 reg; 616 int ret; 617 618 /* Wait for oscillator startup timer after power up */ 619 mdelay(MCP251X_OST_DELAY_MS); 620 621 priv->spi_tx_buf[0] = INSTRUCTION_RESET; 622 ret = mcp251x_spi_trans(spi, 1); 623 if (ret) 624 return ret; 625 626 /* Wait for oscillator startup timer after reset */ 627 mdelay(MCP251X_OST_DELAY_MS); 628 629 reg = mcp251x_read_reg(spi, CANSTAT); 630 if ((reg & CANCTRL_REQOP_MASK) != CANCTRL_REQOP_CONF) 631 return -ENODEV; 632 633 return 0; 634 } 635 636 static int mcp251x_hw_probe(struct spi_device *spi) 637 { 638 u8 ctrl; 639 int ret; 640 641 ret = mcp251x_hw_reset(spi); 642 if (ret) 643 return ret; 644 645 ctrl = mcp251x_read_reg(spi, CANCTRL); 646 647 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl); 648 649 /* Check for power up default value */ 650 if ((ctrl & 0x17) != 0x07) 651 return -ENODEV; 652 653 return 0; 654 } 655 656 static int mcp251x_power_enable(struct regulator *reg, int enable) 657 { 658 if (IS_ERR_OR_NULL(reg)) 659 return 0; 660 661 if (enable) 662 return regulator_enable(reg); 663 else 664 return regulator_disable(reg); 665 } 666 667 static void mcp251x_open_clean(struct net_device *net) 668 { 669 struct mcp251x_priv *priv = netdev_priv(net); 670 struct spi_device *spi = priv->spi; 671 672 free_irq(spi->irq, priv); 673 mcp251x_hw_sleep(spi); 674 mcp251x_power_enable(priv->transceiver, 0); 675 close_candev(net); 676 } 677 678 static int mcp251x_stop(struct net_device *net) 679 { 680 struct mcp251x_priv *priv = netdev_priv(net); 681 struct spi_device *spi = priv->spi; 682 683 close_candev(net); 684 685 priv->force_quit = 1; 686 free_irq(spi->irq, priv); 687 destroy_workqueue(priv->wq); 688 priv->wq = NULL; 689 690 mutex_lock(&priv->mcp_lock); 691 692 /* Disable and clear pending interrupts */ 693 mcp251x_write_reg(spi, CANINTE, 0x00); 694 mcp251x_write_reg(spi, CANINTF, 0x00); 695 696 mcp251x_write_reg(spi, TXBCTRL(0), 0); 697 mcp251x_clean(net); 698 699 mcp251x_hw_sleep(spi); 700 701 mcp251x_power_enable(priv->transceiver, 0); 702 703 priv->can.state = CAN_STATE_STOPPED; 704 705 mutex_unlock(&priv->mcp_lock); 706 707 can_led_event(net, CAN_LED_EVENT_STOP); 708 709 return 0; 710 } 711 712 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1) 713 { 714 struct sk_buff *skb; 715 struct can_frame *frame; 716 717 skb = alloc_can_err_skb(net, &frame); 718 if (skb) { 719 frame->can_id |= can_id; 720 frame->data[1] = data1; 721 netif_rx_ni(skb); 722 } else { 723 netdev_err(net, "cannot allocate error skb\n"); 724 } 725 } 726 727 static void mcp251x_tx_work_handler(struct work_struct *ws) 728 { 729 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, 730 tx_work); 731 struct spi_device *spi = priv->spi; 732 struct net_device *net = priv->net; 733 struct can_frame *frame; 734 735 mutex_lock(&priv->mcp_lock); 736 if (priv->tx_skb) { 737 if (priv->can.state == CAN_STATE_BUS_OFF) { 738 mcp251x_clean(net); 739 } else { 740 frame = (struct can_frame *)priv->tx_skb->data; 741 742 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN) 743 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN; 744 mcp251x_hw_tx(spi, frame, 0); 745 priv->tx_len = 1 + frame->can_dlc; 746 can_put_echo_skb(priv->tx_skb, net, 0); 747 priv->tx_skb = NULL; 748 } 749 } 750 mutex_unlock(&priv->mcp_lock); 751 } 752 753 static void mcp251x_restart_work_handler(struct work_struct *ws) 754 { 755 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, 756 restart_work); 757 struct spi_device *spi = priv->spi; 758 struct net_device *net = priv->net; 759 760 mutex_lock(&priv->mcp_lock); 761 if (priv->after_suspend) { 762 mcp251x_hw_reset(spi); 763 mcp251x_setup(net, spi); 764 if (priv->after_suspend & AFTER_SUSPEND_RESTART) { 765 mcp251x_set_normal_mode(spi); 766 } else if (priv->after_suspend & AFTER_SUSPEND_UP) { 767 netif_device_attach(net); 768 mcp251x_clean(net); 769 mcp251x_set_normal_mode(spi); 770 netif_wake_queue(net); 771 } else { 772 mcp251x_hw_sleep(spi); 773 } 774 priv->after_suspend = 0; 775 priv->force_quit = 0; 776 } 777 778 if (priv->restart_tx) { 779 priv->restart_tx = 0; 780 mcp251x_write_reg(spi, TXBCTRL(0), 0); 781 mcp251x_clean(net); 782 netif_wake_queue(net); 783 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0); 784 } 785 mutex_unlock(&priv->mcp_lock); 786 } 787 788 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id) 789 { 790 struct mcp251x_priv *priv = dev_id; 791 struct spi_device *spi = priv->spi; 792 struct net_device *net = priv->net; 793 794 mutex_lock(&priv->mcp_lock); 795 while (!priv->force_quit) { 796 enum can_state new_state; 797 u8 intf, eflag; 798 u8 clear_intf = 0; 799 int can_id = 0, data1 = 0; 800 801 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag); 802 803 /* mask out flags we don't care about */ 804 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR; 805 806 /* receive buffer 0 */ 807 if (intf & CANINTF_RX0IF) { 808 mcp251x_hw_rx(spi, 0); 809 /* Free one buffer ASAP 810 * (The MCP2515/25625 does this automatically.) 811 */ 812 if (mcp251x_is_2510(spi)) 813 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00); 814 } 815 816 /* receive buffer 1 */ 817 if (intf & CANINTF_RX1IF) { 818 mcp251x_hw_rx(spi, 1); 819 /* The MCP2515/25625 does this automatically. */ 820 if (mcp251x_is_2510(spi)) 821 clear_intf |= CANINTF_RX1IF; 822 } 823 824 /* any error or tx interrupt we need to clear? */ 825 if (intf & (CANINTF_ERR | CANINTF_TX)) 826 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX); 827 if (clear_intf) 828 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00); 829 830 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) 831 mcp251x_write_bits(spi, EFLG, eflag, 0x00); 832 833 /* Update can state */ 834 if (eflag & EFLG_TXBO) { 835 new_state = CAN_STATE_BUS_OFF; 836 can_id |= CAN_ERR_BUSOFF; 837 } else if (eflag & EFLG_TXEP) { 838 new_state = CAN_STATE_ERROR_PASSIVE; 839 can_id |= CAN_ERR_CRTL; 840 data1 |= CAN_ERR_CRTL_TX_PASSIVE; 841 } else if (eflag & EFLG_RXEP) { 842 new_state = CAN_STATE_ERROR_PASSIVE; 843 can_id |= CAN_ERR_CRTL; 844 data1 |= CAN_ERR_CRTL_RX_PASSIVE; 845 } else if (eflag & EFLG_TXWAR) { 846 new_state = CAN_STATE_ERROR_WARNING; 847 can_id |= CAN_ERR_CRTL; 848 data1 |= CAN_ERR_CRTL_TX_WARNING; 849 } else if (eflag & EFLG_RXWAR) { 850 new_state = CAN_STATE_ERROR_WARNING; 851 can_id |= CAN_ERR_CRTL; 852 data1 |= CAN_ERR_CRTL_RX_WARNING; 853 } else { 854 new_state = CAN_STATE_ERROR_ACTIVE; 855 } 856 857 /* Update can state statistics */ 858 switch (priv->can.state) { 859 case CAN_STATE_ERROR_ACTIVE: 860 if (new_state >= CAN_STATE_ERROR_WARNING && 861 new_state <= CAN_STATE_BUS_OFF) 862 priv->can.can_stats.error_warning++; 863 /* fall through */ 864 case CAN_STATE_ERROR_WARNING: 865 if (new_state >= CAN_STATE_ERROR_PASSIVE && 866 new_state <= CAN_STATE_BUS_OFF) 867 priv->can.can_stats.error_passive++; 868 break; 869 default: 870 break; 871 } 872 priv->can.state = new_state; 873 874 if (intf & CANINTF_ERRIF) { 875 /* Handle overflow counters */ 876 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) { 877 if (eflag & EFLG_RX0OVR) { 878 net->stats.rx_over_errors++; 879 net->stats.rx_errors++; 880 } 881 if (eflag & EFLG_RX1OVR) { 882 net->stats.rx_over_errors++; 883 net->stats.rx_errors++; 884 } 885 can_id |= CAN_ERR_CRTL; 886 data1 |= CAN_ERR_CRTL_RX_OVERFLOW; 887 } 888 mcp251x_error_skb(net, can_id, data1); 889 } 890 891 if (priv->can.state == CAN_STATE_BUS_OFF) { 892 if (priv->can.restart_ms == 0) { 893 priv->force_quit = 1; 894 priv->can.can_stats.bus_off++; 895 can_bus_off(net); 896 mcp251x_hw_sleep(spi); 897 break; 898 } 899 } 900 901 if (intf == 0) 902 break; 903 904 if (intf & CANINTF_TX) { 905 net->stats.tx_packets++; 906 net->stats.tx_bytes += priv->tx_len - 1; 907 can_led_event(net, CAN_LED_EVENT_TX); 908 if (priv->tx_len) { 909 can_get_echo_skb(net, 0); 910 priv->tx_len = 0; 911 } 912 netif_wake_queue(net); 913 } 914 915 } 916 mutex_unlock(&priv->mcp_lock); 917 return IRQ_HANDLED; 918 } 919 920 static int mcp251x_open(struct net_device *net) 921 { 922 struct mcp251x_priv *priv = netdev_priv(net); 923 struct spi_device *spi = priv->spi; 924 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING; 925 int ret; 926 927 ret = open_candev(net); 928 if (ret) { 929 dev_err(&spi->dev, "unable to set initial baudrate!\n"); 930 return ret; 931 } 932 933 mutex_lock(&priv->mcp_lock); 934 mcp251x_power_enable(priv->transceiver, 1); 935 936 priv->force_quit = 0; 937 priv->tx_skb = NULL; 938 priv->tx_len = 0; 939 940 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist, 941 flags | IRQF_ONESHOT, DEVICE_NAME, priv); 942 if (ret) { 943 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 944 mcp251x_power_enable(priv->transceiver, 0); 945 close_candev(net); 946 goto open_unlock; 947 } 948 949 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, 950 0); 951 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler); 952 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler); 953 954 ret = mcp251x_hw_reset(spi); 955 if (ret) { 956 mcp251x_open_clean(net); 957 goto open_unlock; 958 } 959 ret = mcp251x_setup(net, spi); 960 if (ret) { 961 mcp251x_open_clean(net); 962 goto open_unlock; 963 } 964 ret = mcp251x_set_normal_mode(spi); 965 if (ret) { 966 mcp251x_open_clean(net); 967 goto open_unlock; 968 } 969 970 can_led_event(net, CAN_LED_EVENT_OPEN); 971 972 netif_wake_queue(net); 973 974 open_unlock: 975 mutex_unlock(&priv->mcp_lock); 976 return ret; 977 } 978 979 static const struct net_device_ops mcp251x_netdev_ops = { 980 .ndo_open = mcp251x_open, 981 .ndo_stop = mcp251x_stop, 982 .ndo_start_xmit = mcp251x_hard_start_xmit, 983 .ndo_change_mtu = can_change_mtu, 984 }; 985 986 static const struct of_device_id mcp251x_of_match[] = { 987 { 988 .compatible = "microchip,mcp2510", 989 .data = (void *)CAN_MCP251X_MCP2510, 990 }, 991 { 992 .compatible = "microchip,mcp2515", 993 .data = (void *)CAN_MCP251X_MCP2515, 994 }, 995 { 996 .compatible = "microchip,mcp25625", 997 .data = (void *)CAN_MCP251X_MCP25625, 998 }, 999 { } 1000 }; 1001 MODULE_DEVICE_TABLE(of, mcp251x_of_match); 1002 1003 static const struct spi_device_id mcp251x_id_table[] = { 1004 { 1005 .name = "mcp2510", 1006 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510, 1007 }, 1008 { 1009 .name = "mcp2515", 1010 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515, 1011 }, 1012 { 1013 .name = "mcp25625", 1014 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625, 1015 }, 1016 { } 1017 }; 1018 MODULE_DEVICE_TABLE(spi, mcp251x_id_table); 1019 1020 static int mcp251x_can_probe(struct spi_device *spi) 1021 { 1022 const struct of_device_id *of_id = of_match_device(mcp251x_of_match, 1023 &spi->dev); 1024 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev); 1025 struct net_device *net; 1026 struct mcp251x_priv *priv; 1027 struct clk *clk; 1028 int freq, ret; 1029 1030 clk = devm_clk_get(&spi->dev, NULL); 1031 if (IS_ERR(clk)) { 1032 if (pdata) 1033 freq = pdata->oscillator_frequency; 1034 else 1035 return PTR_ERR(clk); 1036 } else { 1037 freq = clk_get_rate(clk); 1038 } 1039 1040 /* Sanity check */ 1041 if (freq < 1000000 || freq > 25000000) 1042 return -ERANGE; 1043 1044 /* Allocate can/net device */ 1045 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX); 1046 if (!net) 1047 return -ENOMEM; 1048 1049 if (!IS_ERR(clk)) { 1050 ret = clk_prepare_enable(clk); 1051 if (ret) 1052 goto out_free; 1053 } 1054 1055 net->netdev_ops = &mcp251x_netdev_ops; 1056 net->flags |= IFF_ECHO; 1057 1058 priv = netdev_priv(net); 1059 priv->can.bittiming_const = &mcp251x_bittiming_const; 1060 priv->can.do_set_mode = mcp251x_do_set_mode; 1061 priv->can.clock.freq = freq / 2; 1062 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 1063 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; 1064 if (of_id) 1065 priv->model = (enum mcp251x_model)of_id->data; 1066 else 1067 priv->model = spi_get_device_id(spi)->driver_data; 1068 priv->net = net; 1069 priv->clk = clk; 1070 1071 spi_set_drvdata(spi, priv); 1072 1073 /* Configure the SPI bus */ 1074 spi->bits_per_word = 8; 1075 if (mcp251x_is_2510(spi)) 1076 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000; 1077 else 1078 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000; 1079 ret = spi_setup(spi); 1080 if (ret) 1081 goto out_clk; 1082 1083 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); 1084 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 1085 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 1086 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { 1087 ret = -EPROBE_DEFER; 1088 goto out_clk; 1089 } 1090 1091 ret = mcp251x_power_enable(priv->power, 1); 1092 if (ret) 1093 goto out_clk; 1094 1095 priv->spi = spi; 1096 mutex_init(&priv->mcp_lock); 1097 1098 /* If requested, allocate DMA buffers */ 1099 if (mcp251x_enable_dma) { 1100 spi->dev.coherent_dma_mask = ~0; 1101 1102 /* 1103 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate 1104 * that much and share it between Tx and Rx DMA buffers. 1105 */ 1106 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev, 1107 PAGE_SIZE, 1108 &priv->spi_tx_dma, 1109 GFP_DMA); 1110 1111 if (priv->spi_tx_buf) { 1112 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2)); 1113 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma + 1114 (PAGE_SIZE / 2)); 1115 } else { 1116 /* Fall back to non-DMA */ 1117 mcp251x_enable_dma = 0; 1118 } 1119 } 1120 1121 /* Allocate non-DMA buffers */ 1122 if (!mcp251x_enable_dma) { 1123 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN, 1124 GFP_KERNEL); 1125 if (!priv->spi_tx_buf) { 1126 ret = -ENOMEM; 1127 goto error_probe; 1128 } 1129 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN, 1130 GFP_KERNEL); 1131 if (!priv->spi_rx_buf) { 1132 ret = -ENOMEM; 1133 goto error_probe; 1134 } 1135 } 1136 1137 SET_NETDEV_DEV(net, &spi->dev); 1138 1139 /* Here is OK to not lock the MCP, no one knows about it yet */ 1140 ret = mcp251x_hw_probe(spi); 1141 if (ret) { 1142 if (ret == -ENODEV) 1143 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n", priv->model); 1144 goto error_probe; 1145 } 1146 1147 mcp251x_hw_sleep(spi); 1148 1149 ret = register_candev(net); 1150 if (ret) 1151 goto error_probe; 1152 1153 devm_can_led_init(net); 1154 1155 netdev_info(net, "MCP%x successfully initialized.\n", priv->model); 1156 return 0; 1157 1158 error_probe: 1159 mcp251x_power_enable(priv->power, 0); 1160 1161 out_clk: 1162 if (!IS_ERR(clk)) 1163 clk_disable_unprepare(clk); 1164 1165 out_free: 1166 free_candev(net); 1167 1168 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret); 1169 return ret; 1170 } 1171 1172 static int mcp251x_can_remove(struct spi_device *spi) 1173 { 1174 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1175 struct net_device *net = priv->net; 1176 1177 unregister_candev(net); 1178 1179 mcp251x_power_enable(priv->power, 0); 1180 1181 if (!IS_ERR(priv->clk)) 1182 clk_disable_unprepare(priv->clk); 1183 1184 free_candev(net); 1185 1186 return 0; 1187 } 1188 1189 static int __maybe_unused mcp251x_can_suspend(struct device *dev) 1190 { 1191 struct spi_device *spi = to_spi_device(dev); 1192 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1193 struct net_device *net = priv->net; 1194 1195 priv->force_quit = 1; 1196 disable_irq(spi->irq); 1197 /* 1198 * Note: at this point neither IST nor workqueues are running. 1199 * open/stop cannot be called anyway so locking is not needed 1200 */ 1201 if (netif_running(net)) { 1202 netif_device_detach(net); 1203 1204 mcp251x_hw_sleep(spi); 1205 mcp251x_power_enable(priv->transceiver, 0); 1206 priv->after_suspend = AFTER_SUSPEND_UP; 1207 } else { 1208 priv->after_suspend = AFTER_SUSPEND_DOWN; 1209 } 1210 1211 if (!IS_ERR_OR_NULL(priv->power)) { 1212 regulator_disable(priv->power); 1213 priv->after_suspend |= AFTER_SUSPEND_POWER; 1214 } 1215 1216 return 0; 1217 } 1218 1219 static int __maybe_unused mcp251x_can_resume(struct device *dev) 1220 { 1221 struct spi_device *spi = to_spi_device(dev); 1222 struct mcp251x_priv *priv = spi_get_drvdata(spi); 1223 1224 if (priv->after_suspend & AFTER_SUSPEND_POWER) 1225 mcp251x_power_enable(priv->power, 1); 1226 1227 if (priv->after_suspend & AFTER_SUSPEND_UP) { 1228 mcp251x_power_enable(priv->transceiver, 1); 1229 queue_work(priv->wq, &priv->restart_work); 1230 } else { 1231 priv->after_suspend = 0; 1232 } 1233 1234 priv->force_quit = 0; 1235 enable_irq(spi->irq); 1236 return 0; 1237 } 1238 1239 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend, 1240 mcp251x_can_resume); 1241 1242 static struct spi_driver mcp251x_can_driver = { 1243 .driver = { 1244 .name = DEVICE_NAME, 1245 .of_match_table = mcp251x_of_match, 1246 .pm = &mcp251x_can_pm_ops, 1247 }, 1248 .id_table = mcp251x_id_table, 1249 .probe = mcp251x_can_probe, 1250 .remove = mcp251x_can_remove, 1251 }; 1252 module_spi_driver(mcp251x_can_driver); 1253 1254 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, " 1255 "Christian Pellegrin <chripell@evolware.org>"); 1256 MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver"); 1257 MODULE_LICENSE("GPL v2"); 1258