1 /* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface 2 * 3 * Copyright(C) Timesys Corporation 2016 4 * 5 * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver 6 * Copyright 2009 Christian Pellegrin EVOL S.r.l. 7 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. 8 * Copyright 2006 Arcom Control Systems Ltd. 9 * 10 * Based on CAN bus driver for the CCAN controller written by 11 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix 12 * - Simon Kallweit, intefo AG 13 * Copyright 2007 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 20 #include <linux/can/core.h> 21 #include <linux/can/dev.h> 22 #include <linux/can/led.h> 23 #include <linux/clk.h> 24 #include <linux/completion.h> 25 #include <linux/delay.h> 26 #include <linux/device.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/freezer.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/netdevice.h> 34 #include <linux/of.h> 35 #include <linux/of_device.h> 36 #include <linux/platform_device.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/slab.h> 39 #include <linux/spi/spi.h> 40 #include <linux/uaccess.h> 41 42 #define HI3110_MASTER_RESET 0x56 43 #define HI3110_READ_CTRL0 0xD2 44 #define HI3110_READ_CTRL1 0xD4 45 #define HI3110_READ_STATF 0xE2 46 #define HI3110_WRITE_CTRL0 0x14 47 #define HI3110_WRITE_CTRL1 0x16 48 #define HI3110_WRITE_INTE 0x1C 49 #define HI3110_WRITE_BTR0 0x18 50 #define HI3110_WRITE_BTR1 0x1A 51 #define HI3110_READ_BTR0 0xD6 52 #define HI3110_READ_BTR1 0xD8 53 #define HI3110_READ_INTF 0xDE 54 #define HI3110_READ_ERR 0xDC 55 #define HI3110_READ_FIFO_WOTIME 0x48 56 #define HI3110_WRITE_FIFO 0x12 57 #define HI3110_READ_MESSTAT 0xDA 58 #define HI3110_READ_REC 0xEA 59 #define HI3110_READ_TEC 0xEC 60 61 #define HI3110_CTRL0_MODE_MASK (7 << 5) 62 #define HI3110_CTRL0_NORMAL_MODE (0 << 5) 63 #define HI3110_CTRL0_LOOPBACK_MODE (1 << 5) 64 #define HI3110_CTRL0_MONITOR_MODE (2 << 5) 65 #define HI3110_CTRL0_SLEEP_MODE (3 << 5) 66 #define HI3110_CTRL0_INIT_MODE (4 << 5) 67 68 #define HI3110_CTRL1_TXEN BIT(7) 69 70 #define HI3110_INT_RXTMP BIT(7) 71 #define HI3110_INT_RXFIFO BIT(6) 72 #define HI3110_INT_TXCPLT BIT(5) 73 #define HI3110_INT_BUSERR BIT(4) 74 #define HI3110_INT_MCHG BIT(3) 75 #define HI3110_INT_WAKEUP BIT(2) 76 #define HI3110_INT_F1MESS BIT(1) 77 #define HI3110_INT_F0MESS BIT(0) 78 79 #define HI3110_ERR_BUSOFF BIT(7) 80 #define HI3110_ERR_TXERRP BIT(6) 81 #define HI3110_ERR_RXERRP BIT(5) 82 #define HI3110_ERR_BITERR BIT(4) 83 #define HI3110_ERR_FRMERR BIT(3) 84 #define HI3110_ERR_CRCERR BIT(2) 85 #define HI3110_ERR_ACKERR BIT(1) 86 #define HI3110_ERR_STUFERR BIT(0) 87 #define HI3110_ERR_PROTOCOL_MASK (0x1F) 88 #define HI3110_ERR_PASSIVE_MASK (0x60) 89 90 #define HI3110_STAT_RXFMTY BIT(1) 91 #define HI3110_STAT_BUSOFF BIT(2) 92 #define HI3110_STAT_ERRP BIT(3) 93 #define HI3110_STAT_ERRW BIT(4) 94 #define HI3110_STAT_TXMTY BIT(7) 95 96 #define HI3110_BTR0_SJW_SHIFT 6 97 #define HI3110_BTR0_BRP_SHIFT 0 98 99 #define HI3110_BTR1_SAMP_3PERBIT (1 << 7) 100 #define HI3110_BTR1_SAMP_1PERBIT (0 << 7) 101 #define HI3110_BTR1_TSEG2_SHIFT 4 102 #define HI3110_BTR1_TSEG1_SHIFT 0 103 104 #define HI3110_FIFO_WOTIME_TAG_OFF 0 105 #define HI3110_FIFO_WOTIME_ID_OFF 1 106 #define HI3110_FIFO_WOTIME_DLC_OFF 5 107 #define HI3110_FIFO_WOTIME_DAT_OFF 6 108 109 #define HI3110_FIFO_WOTIME_TAG_IDE BIT(7) 110 #define HI3110_FIFO_WOTIME_ID_RTR BIT(0) 111 112 #define HI3110_FIFO_TAG_OFF 0 113 #define HI3110_FIFO_ID_OFF 1 114 #define HI3110_FIFO_STD_DLC_OFF 3 115 #define HI3110_FIFO_STD_DATA_OFF 4 116 #define HI3110_FIFO_EXT_DLC_OFF 5 117 #define HI3110_FIFO_EXT_DATA_OFF 6 118 119 #define HI3110_CAN_MAX_DATA_LEN 8 120 #define HI3110_RX_BUF_LEN 15 121 #define HI3110_TX_STD_BUF_LEN 12 122 #define HI3110_TX_EXT_BUF_LEN 14 123 #define HI3110_CAN_FRAME_MAX_BITS 128 124 #define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */ 125 126 #define HI3110_TX_ECHO_SKB_MAX 1 127 128 #define HI3110_OST_DELAY_MS (10) 129 130 #define DEVICE_NAME "hi3110" 131 132 static int hi3110_enable_dma = 1; /* Enable SPI DMA. Default: 1 (On) */ 133 module_param(hi3110_enable_dma, int, 0444); 134 MODULE_PARM_DESC(hi3110_enable_dma, "Enable SPI DMA. Default: 1 (On)"); 135 136 static const struct can_bittiming_const hi3110_bittiming_const = { 137 .name = DEVICE_NAME, 138 .tseg1_min = 2, 139 .tseg1_max = 16, 140 .tseg2_min = 2, 141 .tseg2_max = 8, 142 .sjw_max = 4, 143 .brp_min = 1, 144 .brp_max = 64, 145 .brp_inc = 1, 146 }; 147 148 enum hi3110_model { 149 CAN_HI3110_HI3110 = 0x3110, 150 }; 151 152 struct hi3110_priv { 153 struct can_priv can; 154 struct net_device *net; 155 struct spi_device *spi; 156 enum hi3110_model model; 157 158 struct mutex hi3110_lock; /* SPI device lock */ 159 160 u8 *spi_tx_buf; 161 u8 *spi_rx_buf; 162 dma_addr_t spi_tx_dma; 163 dma_addr_t spi_rx_dma; 164 165 struct sk_buff *tx_skb; 166 int tx_len; 167 168 struct workqueue_struct *wq; 169 struct work_struct tx_work; 170 struct work_struct restart_work; 171 172 int force_quit; 173 int after_suspend; 174 #define HI3110_AFTER_SUSPEND_UP 1 175 #define HI3110_AFTER_SUSPEND_DOWN 2 176 #define HI3110_AFTER_SUSPEND_POWER 4 177 #define HI3110_AFTER_SUSPEND_RESTART 8 178 int restart_tx; 179 struct regulator *power; 180 struct regulator *transceiver; 181 struct clk *clk; 182 }; 183 184 static void hi3110_clean(struct net_device *net) 185 { 186 struct hi3110_priv *priv = netdev_priv(net); 187 188 if (priv->tx_skb || priv->tx_len) 189 net->stats.tx_errors++; 190 if (priv->tx_skb) 191 dev_kfree_skb(priv->tx_skb); 192 if (priv->tx_len) 193 can_free_echo_skb(priv->net, 0); 194 priv->tx_skb = NULL; 195 priv->tx_len = 0; 196 } 197 198 /* Note about handling of error return of hi3110_spi_trans: accessing 199 * registers via SPI is not really different conceptually than using 200 * normal I/O assembler instructions, although it's much more 201 * complicated from a practical POV. So it's not advisable to always 202 * check the return value of this function. Imagine that every 203 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) 204 * error();", it would be a great mess (well there are some situation 205 * when exception handling C++ like could be useful after all). So we 206 * just check that transfers are OK at the beginning of our 207 * conversation with the chip and to avoid doing really nasty things 208 * (like injecting bogus packets in the network stack). 209 */ 210 static int hi3110_spi_trans(struct spi_device *spi, int len) 211 { 212 struct hi3110_priv *priv = spi_get_drvdata(spi); 213 struct spi_transfer t = { 214 .tx_buf = priv->spi_tx_buf, 215 .rx_buf = priv->spi_rx_buf, 216 .len = len, 217 .cs_change = 0, 218 }; 219 struct spi_message m; 220 int ret; 221 222 spi_message_init(&m); 223 224 if (hi3110_enable_dma) { 225 t.tx_dma = priv->spi_tx_dma; 226 t.rx_dma = priv->spi_rx_dma; 227 m.is_dma_mapped = 1; 228 } 229 230 spi_message_add_tail(&t, &m); 231 232 ret = spi_sync(spi, &m); 233 234 if (ret) 235 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); 236 return ret; 237 } 238 239 static u8 hi3110_cmd(struct spi_device *spi, u8 command) 240 { 241 struct hi3110_priv *priv = spi_get_drvdata(spi); 242 243 priv->spi_tx_buf[0] = command; 244 dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command); 245 246 return hi3110_spi_trans(spi, 1); 247 } 248 249 static u8 hi3110_read(struct spi_device *spi, u8 command) 250 { 251 struct hi3110_priv *priv = spi_get_drvdata(spi); 252 u8 val = 0; 253 254 priv->spi_tx_buf[0] = command; 255 hi3110_spi_trans(spi, 2); 256 val = priv->spi_rx_buf[1]; 257 258 return val; 259 } 260 261 static void hi3110_write(struct spi_device *spi, u8 reg, u8 val) 262 { 263 struct hi3110_priv *priv = spi_get_drvdata(spi); 264 265 priv->spi_tx_buf[0] = reg; 266 priv->spi_tx_buf[1] = val; 267 hi3110_spi_trans(spi, 2); 268 } 269 270 static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len) 271 { 272 struct hi3110_priv *priv = spi_get_drvdata(spi); 273 274 priv->spi_tx_buf[0] = HI3110_WRITE_FIFO; 275 memcpy(priv->spi_tx_buf + 1, buf, len); 276 hi3110_spi_trans(spi, len + 1); 277 } 278 279 static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame) 280 { 281 u8 buf[HI3110_TX_EXT_BUF_LEN]; 282 283 buf[HI3110_FIFO_TAG_OFF] = 0; 284 285 if (frame->can_id & CAN_EFF_FLAG) { 286 /* Extended frame */ 287 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21; 288 buf[HI3110_FIFO_ID_OFF + 1] = 289 (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) | 290 HI3110_EFF_FLAGS | 291 (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07); 292 buf[HI3110_FIFO_ID_OFF + 2] = 293 (frame->can_id & CAN_EFF_MASK) >> 7; 294 buf[HI3110_FIFO_ID_OFF + 3] = 295 ((frame->can_id & CAN_EFF_MASK) << 1) | 296 ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0); 297 298 buf[HI3110_FIFO_EXT_DLC_OFF] = frame->can_dlc; 299 300 memcpy(buf + HI3110_FIFO_EXT_DATA_OFF, 301 frame->data, frame->can_dlc); 302 303 hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN - 304 (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc)); 305 } else { 306 /* Standard frame */ 307 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3; 308 buf[HI3110_FIFO_ID_OFF + 1] = 309 ((frame->can_id & CAN_SFF_MASK) << 5) | 310 ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0); 311 312 buf[HI3110_FIFO_STD_DLC_OFF] = frame->can_dlc; 313 314 memcpy(buf + HI3110_FIFO_STD_DATA_OFF, 315 frame->data, frame->can_dlc); 316 317 hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN - 318 (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc)); 319 } 320 } 321 322 static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf) 323 { 324 struct hi3110_priv *priv = spi_get_drvdata(spi); 325 326 priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME; 327 hi3110_spi_trans(spi, HI3110_RX_BUF_LEN); 328 memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1); 329 } 330 331 static void hi3110_hw_rx(struct spi_device *spi) 332 { 333 struct hi3110_priv *priv = spi_get_drvdata(spi); 334 struct sk_buff *skb; 335 struct can_frame *frame; 336 u8 buf[HI3110_RX_BUF_LEN - 1]; 337 338 skb = alloc_can_skb(priv->net, &frame); 339 if (!skb) { 340 priv->net->stats.rx_dropped++; 341 return; 342 } 343 344 hi3110_hw_rx_frame(spi, buf); 345 if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) { 346 /* IDE is recessive (1), indicating extended 29-bit frame */ 347 frame->can_id = CAN_EFF_FLAG; 348 frame->can_id |= 349 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) | 350 (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) | 351 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) | 352 (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) | 353 (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1); 354 } else { 355 /* IDE is dominant (0), frame indicating standard 11-bit */ 356 frame->can_id = 357 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) | 358 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5); 359 } 360 361 /* Data length */ 362 frame->can_dlc = get_can_dlc(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F); 363 364 if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR) 365 frame->can_id |= CAN_RTR_FLAG; 366 else 367 memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF, 368 frame->can_dlc); 369 370 priv->net->stats.rx_packets++; 371 priv->net->stats.rx_bytes += frame->can_dlc; 372 373 can_led_event(priv->net, CAN_LED_EVENT_RX); 374 375 netif_rx_ni(skb); 376 } 377 378 static void hi3110_hw_sleep(struct spi_device *spi) 379 { 380 hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE); 381 } 382 383 static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb, 384 struct net_device *net) 385 { 386 struct hi3110_priv *priv = netdev_priv(net); 387 struct spi_device *spi = priv->spi; 388 389 if (priv->tx_skb || priv->tx_len) { 390 dev_err(&spi->dev, "hard_xmit called while tx busy\n"); 391 return NETDEV_TX_BUSY; 392 } 393 394 if (can_dropped_invalid_skb(net, skb)) 395 return NETDEV_TX_OK; 396 397 netif_stop_queue(net); 398 priv->tx_skb = skb; 399 queue_work(priv->wq, &priv->tx_work); 400 401 return NETDEV_TX_OK; 402 } 403 404 static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode) 405 { 406 struct hi3110_priv *priv = netdev_priv(net); 407 408 switch (mode) { 409 case CAN_MODE_START: 410 hi3110_clean(net); 411 /* We have to delay work since SPI I/O may sleep */ 412 priv->can.state = CAN_STATE_ERROR_ACTIVE; 413 priv->restart_tx = 1; 414 if (priv->can.restart_ms == 0) 415 priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART; 416 queue_work(priv->wq, &priv->restart_work); 417 break; 418 default: 419 return -EOPNOTSUPP; 420 } 421 422 return 0; 423 } 424 425 static int hi3110_get_berr_counter(const struct net_device *net, 426 struct can_berr_counter *bec) 427 { 428 struct hi3110_priv *priv = netdev_priv(net); 429 struct spi_device *spi = priv->spi; 430 431 mutex_lock(&priv->hi3110_lock); 432 bec->txerr = hi3110_read(spi, HI3110_READ_TEC); 433 bec->rxerr = hi3110_read(spi, HI3110_READ_REC); 434 mutex_unlock(&priv->hi3110_lock); 435 436 return 0; 437 } 438 439 static int hi3110_set_normal_mode(struct spi_device *spi) 440 { 441 struct hi3110_priv *priv = spi_get_drvdata(spi); 442 u8 reg = 0; 443 444 hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR | 445 HI3110_INT_RXFIFO | HI3110_INT_TXCPLT); 446 447 /* Enable TX */ 448 hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN); 449 450 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 451 reg = HI3110_CTRL0_LOOPBACK_MODE; 452 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 453 reg = HI3110_CTRL0_MONITOR_MODE; 454 else 455 reg = HI3110_CTRL0_NORMAL_MODE; 456 457 hi3110_write(spi, HI3110_WRITE_CTRL0, reg); 458 459 /* Wait for the device to enter the mode */ 460 mdelay(HI3110_OST_DELAY_MS); 461 reg = hi3110_read(spi, HI3110_READ_CTRL0); 462 if ((reg & HI3110_CTRL0_MODE_MASK) != reg) 463 return -EBUSY; 464 465 priv->can.state = CAN_STATE_ERROR_ACTIVE; 466 return 0; 467 } 468 469 static int hi3110_do_set_bittiming(struct net_device *net) 470 { 471 struct hi3110_priv *priv = netdev_priv(net); 472 struct can_bittiming *bt = &priv->can.bittiming; 473 struct spi_device *spi = priv->spi; 474 475 hi3110_write(spi, HI3110_WRITE_BTR0, 476 ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) | 477 ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT)); 478 479 hi3110_write(spi, HI3110_WRITE_BTR1, 480 (priv->can.ctrlmode & 481 CAN_CTRLMODE_3_SAMPLES ? 482 HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) | 483 ((bt->phase_seg1 + bt->prop_seg - 1) 484 << HI3110_BTR1_TSEG1_SHIFT) | 485 ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT)); 486 487 dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n", 488 hi3110_read(spi, HI3110_READ_BTR0), 489 hi3110_read(spi, HI3110_READ_BTR1)); 490 491 return 0; 492 } 493 494 static int hi3110_setup(struct net_device *net) 495 { 496 hi3110_do_set_bittiming(net); 497 return 0; 498 } 499 500 static int hi3110_hw_reset(struct spi_device *spi) 501 { 502 u8 reg; 503 int ret; 504 505 /* Wait for oscillator startup timer after power up */ 506 mdelay(HI3110_OST_DELAY_MS); 507 508 ret = hi3110_cmd(spi, HI3110_MASTER_RESET); 509 if (ret) 510 return ret; 511 512 /* Wait for oscillator startup timer after reset */ 513 mdelay(HI3110_OST_DELAY_MS); 514 515 reg = hi3110_read(spi, HI3110_READ_CTRL0); 516 if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE) 517 return -ENODEV; 518 519 /* As per the datasheet it appears the error flags are 520 * not cleared on reset. Explicitly clear them by performing a read 521 */ 522 hi3110_read(spi, HI3110_READ_ERR); 523 524 return 0; 525 } 526 527 static int hi3110_hw_probe(struct spi_device *spi) 528 { 529 u8 statf; 530 531 hi3110_hw_reset(spi); 532 533 /* Confirm correct operation by checking against reset values 534 * in datasheet 535 */ 536 statf = hi3110_read(spi, HI3110_READ_STATF); 537 538 dev_dbg(&spi->dev, "statf: %02X\n", statf); 539 540 if (statf != 0x82) 541 return -ENODEV; 542 543 return 0; 544 } 545 546 static int hi3110_power_enable(struct regulator *reg, int enable) 547 { 548 if (IS_ERR_OR_NULL(reg)) 549 return 0; 550 551 if (enable) 552 return regulator_enable(reg); 553 else 554 return regulator_disable(reg); 555 } 556 557 static int hi3110_stop(struct net_device *net) 558 { 559 struct hi3110_priv *priv = netdev_priv(net); 560 struct spi_device *spi = priv->spi; 561 562 close_candev(net); 563 564 priv->force_quit = 1; 565 free_irq(spi->irq, priv); 566 destroy_workqueue(priv->wq); 567 priv->wq = NULL; 568 569 mutex_lock(&priv->hi3110_lock); 570 571 /* Disable transmit, interrupts and clear flags */ 572 hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0); 573 hi3110_write(spi, HI3110_WRITE_INTE, 0x0); 574 hi3110_read(spi, HI3110_READ_INTF); 575 576 hi3110_clean(net); 577 578 hi3110_hw_sleep(spi); 579 580 hi3110_power_enable(priv->transceiver, 0); 581 582 priv->can.state = CAN_STATE_STOPPED; 583 584 mutex_unlock(&priv->hi3110_lock); 585 586 can_led_event(net, CAN_LED_EVENT_STOP); 587 588 return 0; 589 } 590 591 static void hi3110_tx_work_handler(struct work_struct *ws) 592 { 593 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 594 tx_work); 595 struct spi_device *spi = priv->spi; 596 struct net_device *net = priv->net; 597 struct can_frame *frame; 598 599 mutex_lock(&priv->hi3110_lock); 600 if (priv->tx_skb) { 601 if (priv->can.state == CAN_STATE_BUS_OFF) { 602 hi3110_clean(net); 603 } else { 604 frame = (struct can_frame *)priv->tx_skb->data; 605 hi3110_hw_tx(spi, frame); 606 priv->tx_len = 1 + frame->can_dlc; 607 can_put_echo_skb(priv->tx_skb, net, 0); 608 priv->tx_skb = NULL; 609 } 610 } 611 mutex_unlock(&priv->hi3110_lock); 612 } 613 614 static void hi3110_restart_work_handler(struct work_struct *ws) 615 { 616 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 617 restart_work); 618 struct spi_device *spi = priv->spi; 619 struct net_device *net = priv->net; 620 621 mutex_lock(&priv->hi3110_lock); 622 if (priv->after_suspend) { 623 hi3110_hw_reset(spi); 624 hi3110_setup(net); 625 if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) { 626 hi3110_set_normal_mode(spi); 627 } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 628 netif_device_attach(net); 629 hi3110_clean(net); 630 hi3110_set_normal_mode(spi); 631 netif_wake_queue(net); 632 } else { 633 hi3110_hw_sleep(spi); 634 } 635 priv->after_suspend = 0; 636 priv->force_quit = 0; 637 } 638 639 if (priv->restart_tx) { 640 priv->restart_tx = 0; 641 hi3110_hw_reset(spi); 642 hi3110_setup(net); 643 hi3110_clean(net); 644 hi3110_set_normal_mode(spi); 645 netif_wake_queue(net); 646 } 647 mutex_unlock(&priv->hi3110_lock); 648 } 649 650 static irqreturn_t hi3110_can_ist(int irq, void *dev_id) 651 { 652 struct hi3110_priv *priv = dev_id; 653 struct spi_device *spi = priv->spi; 654 struct net_device *net = priv->net; 655 656 mutex_lock(&priv->hi3110_lock); 657 658 while (!priv->force_quit) { 659 enum can_state new_state; 660 u8 intf, eflag, statf; 661 662 while (!(HI3110_STAT_RXFMTY & 663 (statf = hi3110_read(spi, HI3110_READ_STATF)))) { 664 hi3110_hw_rx(spi); 665 } 666 667 intf = hi3110_read(spi, HI3110_READ_INTF); 668 eflag = hi3110_read(spi, HI3110_READ_ERR); 669 /* Update can state */ 670 if (eflag & HI3110_ERR_BUSOFF) 671 new_state = CAN_STATE_BUS_OFF; 672 else if (eflag & HI3110_ERR_PASSIVE_MASK) 673 new_state = CAN_STATE_ERROR_PASSIVE; 674 else if (statf & HI3110_STAT_ERRW) 675 new_state = CAN_STATE_ERROR_WARNING; 676 else 677 new_state = CAN_STATE_ERROR_ACTIVE; 678 679 if (new_state != priv->can.state) { 680 struct can_frame *cf; 681 struct sk_buff *skb; 682 enum can_state rx_state, tx_state; 683 u8 rxerr, txerr; 684 685 skb = alloc_can_err_skb(net, &cf); 686 if (!skb) 687 break; 688 689 txerr = hi3110_read(spi, HI3110_READ_TEC); 690 rxerr = hi3110_read(spi, HI3110_READ_REC); 691 cf->data[6] = txerr; 692 cf->data[7] = rxerr; 693 tx_state = txerr >= rxerr ? new_state : 0; 694 rx_state = txerr <= rxerr ? new_state : 0; 695 can_change_state(net, cf, tx_state, rx_state); 696 netif_rx_ni(skb); 697 698 if (new_state == CAN_STATE_BUS_OFF) { 699 can_bus_off(net); 700 if (priv->can.restart_ms == 0) { 701 priv->force_quit = 1; 702 hi3110_hw_sleep(spi); 703 break; 704 } 705 } 706 } 707 708 /* Update bus errors */ 709 if ((intf & HI3110_INT_BUSERR) && 710 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 711 struct can_frame *cf; 712 struct sk_buff *skb; 713 714 /* Check for protocol errors */ 715 if (eflag & HI3110_ERR_PROTOCOL_MASK) { 716 skb = alloc_can_err_skb(net, &cf); 717 if (!skb) 718 break; 719 720 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 721 priv->can.can_stats.bus_error++; 722 priv->net->stats.rx_errors++; 723 if (eflag & HI3110_ERR_BITERR) 724 cf->data[2] |= CAN_ERR_PROT_BIT; 725 else if (eflag & HI3110_ERR_FRMERR) 726 cf->data[2] |= CAN_ERR_PROT_FORM; 727 else if (eflag & HI3110_ERR_STUFERR) 728 cf->data[2] |= CAN_ERR_PROT_STUFF; 729 else if (eflag & HI3110_ERR_CRCERR) 730 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 731 else if (eflag & HI3110_ERR_ACKERR) 732 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 733 734 cf->data[6] = hi3110_read(spi, HI3110_READ_TEC); 735 cf->data[7] = hi3110_read(spi, HI3110_READ_REC); 736 netdev_dbg(priv->net, "Bus Error\n"); 737 netif_rx_ni(skb); 738 } 739 } 740 741 if (priv->tx_len && statf & HI3110_STAT_TXMTY) { 742 net->stats.tx_packets++; 743 net->stats.tx_bytes += priv->tx_len - 1; 744 can_led_event(net, CAN_LED_EVENT_TX); 745 if (priv->tx_len) { 746 can_get_echo_skb(net, 0); 747 priv->tx_len = 0; 748 } 749 netif_wake_queue(net); 750 } 751 752 if (intf == 0) 753 break; 754 } 755 mutex_unlock(&priv->hi3110_lock); 756 return IRQ_HANDLED; 757 } 758 759 static int hi3110_open(struct net_device *net) 760 { 761 struct hi3110_priv *priv = netdev_priv(net); 762 struct spi_device *spi = priv->spi; 763 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_RISING; 764 int ret; 765 766 ret = open_candev(net); 767 if (ret) 768 return ret; 769 770 mutex_lock(&priv->hi3110_lock); 771 hi3110_power_enable(priv->transceiver, 1); 772 773 priv->force_quit = 0; 774 priv->tx_skb = NULL; 775 priv->tx_len = 0; 776 777 ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist, 778 flags, DEVICE_NAME, priv); 779 if (ret) { 780 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 781 goto out_close; 782 } 783 784 priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, 785 0); 786 if (!priv->wq) { 787 ret = -ENOMEM; 788 goto out_free_irq; 789 } 790 INIT_WORK(&priv->tx_work, hi3110_tx_work_handler); 791 INIT_WORK(&priv->restart_work, hi3110_restart_work_handler); 792 793 ret = hi3110_hw_reset(spi); 794 if (ret) 795 goto out_free_wq; 796 797 ret = hi3110_setup(net); 798 if (ret) 799 goto out_free_wq; 800 801 ret = hi3110_set_normal_mode(spi); 802 if (ret) 803 goto out_free_wq; 804 805 can_led_event(net, CAN_LED_EVENT_OPEN); 806 netif_wake_queue(net); 807 mutex_unlock(&priv->hi3110_lock); 808 809 return 0; 810 811 out_free_wq: 812 destroy_workqueue(priv->wq); 813 out_free_irq: 814 free_irq(spi->irq, priv); 815 hi3110_hw_sleep(spi); 816 out_close: 817 hi3110_power_enable(priv->transceiver, 0); 818 close_candev(net); 819 mutex_unlock(&priv->hi3110_lock); 820 return ret; 821 } 822 823 static const struct net_device_ops hi3110_netdev_ops = { 824 .ndo_open = hi3110_open, 825 .ndo_stop = hi3110_stop, 826 .ndo_start_xmit = hi3110_hard_start_xmit, 827 }; 828 829 static const struct of_device_id hi3110_of_match[] = { 830 { 831 .compatible = "holt,hi3110", 832 .data = (void *)CAN_HI3110_HI3110, 833 }, 834 { } 835 }; 836 MODULE_DEVICE_TABLE(of, hi3110_of_match); 837 838 static const struct spi_device_id hi3110_id_table[] = { 839 { 840 .name = "hi3110", 841 .driver_data = (kernel_ulong_t)CAN_HI3110_HI3110, 842 }, 843 { } 844 }; 845 MODULE_DEVICE_TABLE(spi, hi3110_id_table); 846 847 static int hi3110_can_probe(struct spi_device *spi) 848 { 849 const struct of_device_id *of_id = of_match_device(hi3110_of_match, 850 &spi->dev); 851 struct net_device *net; 852 struct hi3110_priv *priv; 853 struct clk *clk; 854 int freq, ret; 855 856 clk = devm_clk_get(&spi->dev, NULL); 857 if (IS_ERR(clk)) { 858 dev_err(&spi->dev, "no CAN clock source defined\n"); 859 return PTR_ERR(clk); 860 } 861 freq = clk_get_rate(clk); 862 863 /* Sanity check */ 864 if (freq > 40000000) 865 return -ERANGE; 866 867 /* Allocate can/net device */ 868 net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX); 869 if (!net) 870 return -ENOMEM; 871 872 if (!IS_ERR(clk)) { 873 ret = clk_prepare_enable(clk); 874 if (ret) 875 goto out_free; 876 } 877 878 net->netdev_ops = &hi3110_netdev_ops; 879 net->flags |= IFF_ECHO; 880 881 priv = netdev_priv(net); 882 priv->can.bittiming_const = &hi3110_bittiming_const; 883 priv->can.do_set_mode = hi3110_do_set_mode; 884 priv->can.do_get_berr_counter = hi3110_get_berr_counter; 885 priv->can.clock.freq = freq / 2; 886 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 887 CAN_CTRLMODE_LOOPBACK | 888 CAN_CTRLMODE_LISTENONLY | 889 CAN_CTRLMODE_BERR_REPORTING; 890 891 if (of_id) 892 priv->model = (enum hi3110_model)of_id->data; 893 else 894 priv->model = spi_get_device_id(spi)->driver_data; 895 priv->net = net; 896 priv->clk = clk; 897 898 spi_set_drvdata(spi, priv); 899 900 /* Configure the SPI bus */ 901 spi->bits_per_word = 8; 902 ret = spi_setup(spi); 903 if (ret) 904 goto out_clk; 905 906 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); 907 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 908 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 909 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { 910 ret = -EPROBE_DEFER; 911 goto out_clk; 912 } 913 914 ret = hi3110_power_enable(priv->power, 1); 915 if (ret) 916 goto out_clk; 917 918 priv->spi = spi; 919 mutex_init(&priv->hi3110_lock); 920 921 /* If requested, allocate DMA buffers */ 922 if (hi3110_enable_dma) { 923 spi->dev.coherent_dma_mask = ~0; 924 925 /* Minimum coherent DMA allocation is PAGE_SIZE, so allocate 926 * that much and share it between Tx and Rx DMA buffers. 927 */ 928 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev, 929 PAGE_SIZE, 930 &priv->spi_tx_dma, 931 GFP_DMA); 932 933 if (priv->spi_tx_buf) { 934 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2)); 935 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma + 936 (PAGE_SIZE / 2)); 937 } else { 938 /* Fall back to non-DMA */ 939 hi3110_enable_dma = 0; 940 } 941 } 942 943 /* Allocate non-DMA buffers */ 944 if (!hi3110_enable_dma) { 945 priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 946 GFP_KERNEL); 947 if (!priv->spi_tx_buf) { 948 ret = -ENOMEM; 949 goto error_probe; 950 } 951 priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 952 GFP_KERNEL); 953 954 if (!priv->spi_rx_buf) { 955 ret = -ENOMEM; 956 goto error_probe; 957 } 958 } 959 960 SET_NETDEV_DEV(net, &spi->dev); 961 962 ret = hi3110_hw_probe(spi); 963 if (ret) { 964 if (ret == -ENODEV) 965 dev_err(&spi->dev, "Cannot initialize %x. Wrong wiring?\n", 966 priv->model); 967 goto error_probe; 968 } 969 hi3110_hw_sleep(spi); 970 971 ret = register_candev(net); 972 if (ret) 973 goto error_probe; 974 975 devm_can_led_init(net); 976 netdev_info(net, "%x successfully initialized.\n", priv->model); 977 978 return 0; 979 980 error_probe: 981 hi3110_power_enable(priv->power, 0); 982 983 out_clk: 984 if (!IS_ERR(clk)) 985 clk_disable_unprepare(clk); 986 987 out_free: 988 free_candev(net); 989 990 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret); 991 return ret; 992 } 993 994 static int hi3110_can_remove(struct spi_device *spi) 995 { 996 struct hi3110_priv *priv = spi_get_drvdata(spi); 997 struct net_device *net = priv->net; 998 999 unregister_candev(net); 1000 1001 hi3110_power_enable(priv->power, 0); 1002 1003 if (!IS_ERR(priv->clk)) 1004 clk_disable_unprepare(priv->clk); 1005 1006 free_candev(net); 1007 1008 return 0; 1009 } 1010 1011 static int __maybe_unused hi3110_can_suspend(struct device *dev) 1012 { 1013 struct spi_device *spi = to_spi_device(dev); 1014 struct hi3110_priv *priv = spi_get_drvdata(spi); 1015 struct net_device *net = priv->net; 1016 1017 priv->force_quit = 1; 1018 disable_irq(spi->irq); 1019 1020 /* Note: at this point neither IST nor workqueues are running. 1021 * open/stop cannot be called anyway so locking is not needed 1022 */ 1023 if (netif_running(net)) { 1024 netif_device_detach(net); 1025 1026 hi3110_hw_sleep(spi); 1027 hi3110_power_enable(priv->transceiver, 0); 1028 priv->after_suspend = HI3110_AFTER_SUSPEND_UP; 1029 } else { 1030 priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN; 1031 } 1032 1033 if (!IS_ERR_OR_NULL(priv->power)) { 1034 regulator_disable(priv->power); 1035 priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER; 1036 } 1037 1038 return 0; 1039 } 1040 1041 static int __maybe_unused hi3110_can_resume(struct device *dev) 1042 { 1043 struct spi_device *spi = to_spi_device(dev); 1044 struct hi3110_priv *priv = spi_get_drvdata(spi); 1045 1046 if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER) 1047 hi3110_power_enable(priv->power, 1); 1048 1049 if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 1050 hi3110_power_enable(priv->transceiver, 1); 1051 queue_work(priv->wq, &priv->restart_work); 1052 } else { 1053 priv->after_suspend = 0; 1054 } 1055 1056 priv->force_quit = 0; 1057 enable_irq(spi->irq); 1058 return 0; 1059 } 1060 1061 static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume); 1062 1063 static struct spi_driver hi3110_can_driver = { 1064 .driver = { 1065 .name = DEVICE_NAME, 1066 .of_match_table = hi3110_of_match, 1067 .pm = &hi3110_can_pm_ops, 1068 }, 1069 .id_table = hi3110_id_table, 1070 .probe = hi3110_can_probe, 1071 .remove = hi3110_can_remove, 1072 }; 1073 1074 module_spi_driver(hi3110_can_driver); 1075 1076 MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>"); 1077 MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>"); 1078 MODULE_DESCRIPTION("Holt HI-3110 CAN driver"); 1079 MODULE_LICENSE("GPL v2"); 1080