1 // SPDX-License-Identifier: GPL-2.0-only 2 /* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface 3 * 4 * Copyright(C) Timesys Corporation 2016 5 * 6 * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver 7 * Copyright 2009 Christian Pellegrin EVOL S.r.l. 8 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. 9 * Copyright 2006 Arcom Control Systems Ltd. 10 * 11 * Based on CAN bus driver for the CCAN controller written by 12 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix 13 * - Simon Kallweit, intefo AG 14 * Copyright 2007 15 */ 16 17 #include <linux/can/core.h> 18 #include <linux/can/dev.h> 19 #include <linux/can/led.h> 20 #include <linux/clk.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/device.h> 24 #include <linux/freezer.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/mod_devicetable.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/platform_device.h> 32 #include <linux/property.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/slab.h> 35 #include <linux/spi/spi.h> 36 #include <linux/uaccess.h> 37 38 #define HI3110_MASTER_RESET 0x56 39 #define HI3110_READ_CTRL0 0xD2 40 #define HI3110_READ_CTRL1 0xD4 41 #define HI3110_READ_STATF 0xE2 42 #define HI3110_WRITE_CTRL0 0x14 43 #define HI3110_WRITE_CTRL1 0x16 44 #define HI3110_WRITE_INTE 0x1C 45 #define HI3110_WRITE_BTR0 0x18 46 #define HI3110_WRITE_BTR1 0x1A 47 #define HI3110_READ_BTR0 0xD6 48 #define HI3110_READ_BTR1 0xD8 49 #define HI3110_READ_INTF 0xDE 50 #define HI3110_READ_ERR 0xDC 51 #define HI3110_READ_FIFO_WOTIME 0x48 52 #define HI3110_WRITE_FIFO 0x12 53 #define HI3110_READ_MESSTAT 0xDA 54 #define HI3110_READ_REC 0xEA 55 #define HI3110_READ_TEC 0xEC 56 57 #define HI3110_CTRL0_MODE_MASK (7 << 5) 58 #define HI3110_CTRL0_NORMAL_MODE (0 << 5) 59 #define HI3110_CTRL0_LOOPBACK_MODE (1 << 5) 60 #define HI3110_CTRL0_MONITOR_MODE (2 << 5) 61 #define HI3110_CTRL0_SLEEP_MODE (3 << 5) 62 #define HI3110_CTRL0_INIT_MODE (4 << 5) 63 64 #define HI3110_CTRL1_TXEN BIT(7) 65 66 #define HI3110_INT_RXTMP BIT(7) 67 #define HI3110_INT_RXFIFO BIT(6) 68 #define HI3110_INT_TXCPLT BIT(5) 69 #define HI3110_INT_BUSERR BIT(4) 70 #define HI3110_INT_MCHG BIT(3) 71 #define HI3110_INT_WAKEUP BIT(2) 72 #define HI3110_INT_F1MESS BIT(1) 73 #define HI3110_INT_F0MESS BIT(0) 74 75 #define HI3110_ERR_BUSOFF BIT(7) 76 #define HI3110_ERR_TXERRP BIT(6) 77 #define HI3110_ERR_RXERRP BIT(5) 78 #define HI3110_ERR_BITERR BIT(4) 79 #define HI3110_ERR_FRMERR BIT(3) 80 #define HI3110_ERR_CRCERR BIT(2) 81 #define HI3110_ERR_ACKERR BIT(1) 82 #define HI3110_ERR_STUFERR BIT(0) 83 #define HI3110_ERR_PROTOCOL_MASK (0x1F) 84 #define HI3110_ERR_PASSIVE_MASK (0x60) 85 86 #define HI3110_STAT_RXFMTY BIT(1) 87 #define HI3110_STAT_BUSOFF BIT(2) 88 #define HI3110_STAT_ERRP BIT(3) 89 #define HI3110_STAT_ERRW BIT(4) 90 #define HI3110_STAT_TXMTY BIT(7) 91 92 #define HI3110_BTR0_SJW_SHIFT 6 93 #define HI3110_BTR0_BRP_SHIFT 0 94 95 #define HI3110_BTR1_SAMP_3PERBIT (1 << 7) 96 #define HI3110_BTR1_SAMP_1PERBIT (0 << 7) 97 #define HI3110_BTR1_TSEG2_SHIFT 4 98 #define HI3110_BTR1_TSEG1_SHIFT 0 99 100 #define HI3110_FIFO_WOTIME_TAG_OFF 0 101 #define HI3110_FIFO_WOTIME_ID_OFF 1 102 #define HI3110_FIFO_WOTIME_DLC_OFF 5 103 #define HI3110_FIFO_WOTIME_DAT_OFF 6 104 105 #define HI3110_FIFO_WOTIME_TAG_IDE BIT(7) 106 #define HI3110_FIFO_WOTIME_ID_RTR BIT(0) 107 108 #define HI3110_FIFO_TAG_OFF 0 109 #define HI3110_FIFO_ID_OFF 1 110 #define HI3110_FIFO_STD_DLC_OFF 3 111 #define HI3110_FIFO_STD_DATA_OFF 4 112 #define HI3110_FIFO_EXT_DLC_OFF 5 113 #define HI3110_FIFO_EXT_DATA_OFF 6 114 115 #define HI3110_CAN_MAX_DATA_LEN 8 116 #define HI3110_RX_BUF_LEN 15 117 #define HI3110_TX_STD_BUF_LEN 12 118 #define HI3110_TX_EXT_BUF_LEN 14 119 #define HI3110_CAN_FRAME_MAX_BITS 128 120 #define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */ 121 122 #define HI3110_TX_ECHO_SKB_MAX 1 123 124 #define HI3110_OST_DELAY_MS (10) 125 126 #define DEVICE_NAME "hi3110" 127 128 static const struct can_bittiming_const hi3110_bittiming_const = { 129 .name = DEVICE_NAME, 130 .tseg1_min = 2, 131 .tseg1_max = 16, 132 .tseg2_min = 2, 133 .tseg2_max = 8, 134 .sjw_max = 4, 135 .brp_min = 1, 136 .brp_max = 64, 137 .brp_inc = 1, 138 }; 139 140 enum hi3110_model { 141 CAN_HI3110_HI3110 = 0x3110, 142 }; 143 144 struct hi3110_priv { 145 struct can_priv can; 146 struct net_device *net; 147 struct spi_device *spi; 148 enum hi3110_model model; 149 150 struct mutex hi3110_lock; /* SPI device lock */ 151 152 u8 *spi_tx_buf; 153 u8 *spi_rx_buf; 154 155 struct sk_buff *tx_skb; 156 157 struct workqueue_struct *wq; 158 struct work_struct tx_work; 159 struct work_struct restart_work; 160 161 int force_quit; 162 int after_suspend; 163 #define HI3110_AFTER_SUSPEND_UP 1 164 #define HI3110_AFTER_SUSPEND_DOWN 2 165 #define HI3110_AFTER_SUSPEND_POWER 4 166 #define HI3110_AFTER_SUSPEND_RESTART 8 167 int restart_tx; 168 bool tx_busy; 169 170 struct regulator *power; 171 struct regulator *transceiver; 172 struct clk *clk; 173 }; 174 175 static void hi3110_clean(struct net_device *net) 176 { 177 struct hi3110_priv *priv = netdev_priv(net); 178 179 if (priv->tx_skb || priv->tx_busy) 180 net->stats.tx_errors++; 181 dev_kfree_skb(priv->tx_skb); 182 if (priv->tx_busy) 183 can_free_echo_skb(priv->net, 0, NULL); 184 priv->tx_skb = NULL; 185 priv->tx_busy = false; 186 } 187 188 /* Note about handling of error return of hi3110_spi_trans: accessing 189 * registers via SPI is not really different conceptually than using 190 * normal I/O assembler instructions, although it's much more 191 * complicated from a practical POV. So it's not advisable to always 192 * check the return value of this function. Imagine that every 193 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) 194 * error();", it would be a great mess (well there are some situation 195 * when exception handling C++ like could be useful after all). So we 196 * just check that transfers are OK at the beginning of our 197 * conversation with the chip and to avoid doing really nasty things 198 * (like injecting bogus packets in the network stack). 199 */ 200 static int hi3110_spi_trans(struct spi_device *spi, int len) 201 { 202 struct hi3110_priv *priv = spi_get_drvdata(spi); 203 struct spi_transfer t = { 204 .tx_buf = priv->spi_tx_buf, 205 .rx_buf = priv->spi_rx_buf, 206 .len = len, 207 .cs_change = 0, 208 }; 209 struct spi_message m; 210 int ret; 211 212 spi_message_init(&m); 213 spi_message_add_tail(&t, &m); 214 215 ret = spi_sync(spi, &m); 216 217 if (ret) 218 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); 219 return ret; 220 } 221 222 static int hi3110_cmd(struct spi_device *spi, u8 command) 223 { 224 struct hi3110_priv *priv = spi_get_drvdata(spi); 225 226 priv->spi_tx_buf[0] = command; 227 dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command); 228 229 return hi3110_spi_trans(spi, 1); 230 } 231 232 static u8 hi3110_read(struct spi_device *spi, u8 command) 233 { 234 struct hi3110_priv *priv = spi_get_drvdata(spi); 235 u8 val = 0; 236 237 priv->spi_tx_buf[0] = command; 238 hi3110_spi_trans(spi, 2); 239 val = priv->spi_rx_buf[1]; 240 241 return val; 242 } 243 244 static void hi3110_write(struct spi_device *spi, u8 reg, u8 val) 245 { 246 struct hi3110_priv *priv = spi_get_drvdata(spi); 247 248 priv->spi_tx_buf[0] = reg; 249 priv->spi_tx_buf[1] = val; 250 hi3110_spi_trans(spi, 2); 251 } 252 253 static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len) 254 { 255 struct hi3110_priv *priv = spi_get_drvdata(spi); 256 257 priv->spi_tx_buf[0] = HI3110_WRITE_FIFO; 258 memcpy(priv->spi_tx_buf + 1, buf, len); 259 hi3110_spi_trans(spi, len + 1); 260 } 261 262 static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame) 263 { 264 u8 buf[HI3110_TX_EXT_BUF_LEN]; 265 266 buf[HI3110_FIFO_TAG_OFF] = 0; 267 268 if (frame->can_id & CAN_EFF_FLAG) { 269 /* Extended frame */ 270 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21; 271 buf[HI3110_FIFO_ID_OFF + 1] = 272 (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) | 273 HI3110_EFF_FLAGS | 274 (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07); 275 buf[HI3110_FIFO_ID_OFF + 2] = 276 (frame->can_id & CAN_EFF_MASK) >> 7; 277 buf[HI3110_FIFO_ID_OFF + 3] = 278 ((frame->can_id & CAN_EFF_MASK) << 1) | 279 ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0); 280 281 buf[HI3110_FIFO_EXT_DLC_OFF] = frame->len; 282 283 memcpy(buf + HI3110_FIFO_EXT_DATA_OFF, 284 frame->data, frame->len); 285 286 hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN - 287 (HI3110_CAN_MAX_DATA_LEN - frame->len)); 288 } else { 289 /* Standard frame */ 290 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3; 291 buf[HI3110_FIFO_ID_OFF + 1] = 292 ((frame->can_id & CAN_SFF_MASK) << 5) | 293 ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0); 294 295 buf[HI3110_FIFO_STD_DLC_OFF] = frame->len; 296 297 memcpy(buf + HI3110_FIFO_STD_DATA_OFF, 298 frame->data, frame->len); 299 300 hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN - 301 (HI3110_CAN_MAX_DATA_LEN - frame->len)); 302 } 303 } 304 305 static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf) 306 { 307 struct hi3110_priv *priv = spi_get_drvdata(spi); 308 309 priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME; 310 hi3110_spi_trans(spi, HI3110_RX_BUF_LEN); 311 memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1); 312 } 313 314 static void hi3110_hw_rx(struct spi_device *spi) 315 { 316 struct hi3110_priv *priv = spi_get_drvdata(spi); 317 struct sk_buff *skb; 318 struct can_frame *frame; 319 u8 buf[HI3110_RX_BUF_LEN - 1]; 320 321 skb = alloc_can_skb(priv->net, &frame); 322 if (!skb) { 323 priv->net->stats.rx_dropped++; 324 return; 325 } 326 327 hi3110_hw_rx_frame(spi, buf); 328 if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) { 329 /* IDE is recessive (1), indicating extended 29-bit frame */ 330 frame->can_id = CAN_EFF_FLAG; 331 frame->can_id |= 332 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) | 333 (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) | 334 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) | 335 (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) | 336 (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1); 337 } else { 338 /* IDE is dominant (0), frame indicating standard 11-bit */ 339 frame->can_id = 340 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) | 341 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5); 342 } 343 344 /* Data length */ 345 frame->len = can_cc_dlc2len(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F); 346 347 if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR) { 348 frame->can_id |= CAN_RTR_FLAG; 349 } else { 350 memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF, 351 frame->len); 352 353 priv->net->stats.rx_bytes += frame->len; 354 } 355 priv->net->stats.rx_packets++; 356 357 can_led_event(priv->net, CAN_LED_EVENT_RX); 358 359 netif_rx(skb); 360 } 361 362 static void hi3110_hw_sleep(struct spi_device *spi) 363 { 364 hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE); 365 } 366 367 static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb, 368 struct net_device *net) 369 { 370 struct hi3110_priv *priv = netdev_priv(net); 371 struct spi_device *spi = priv->spi; 372 373 if (priv->tx_skb || priv->tx_busy) { 374 dev_err(&spi->dev, "hard_xmit called while tx busy\n"); 375 return NETDEV_TX_BUSY; 376 } 377 378 if (can_dropped_invalid_skb(net, skb)) 379 return NETDEV_TX_OK; 380 381 netif_stop_queue(net); 382 priv->tx_skb = skb; 383 queue_work(priv->wq, &priv->tx_work); 384 385 return NETDEV_TX_OK; 386 } 387 388 static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode) 389 { 390 struct hi3110_priv *priv = netdev_priv(net); 391 392 switch (mode) { 393 case CAN_MODE_START: 394 hi3110_clean(net); 395 /* We have to delay work since SPI I/O may sleep */ 396 priv->can.state = CAN_STATE_ERROR_ACTIVE; 397 priv->restart_tx = 1; 398 if (priv->can.restart_ms == 0) 399 priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART; 400 queue_work(priv->wq, &priv->restart_work); 401 break; 402 default: 403 return -EOPNOTSUPP; 404 } 405 406 return 0; 407 } 408 409 static int hi3110_get_berr_counter(const struct net_device *net, 410 struct can_berr_counter *bec) 411 { 412 struct hi3110_priv *priv = netdev_priv(net); 413 struct spi_device *spi = priv->spi; 414 415 mutex_lock(&priv->hi3110_lock); 416 bec->txerr = hi3110_read(spi, HI3110_READ_TEC); 417 bec->rxerr = hi3110_read(spi, HI3110_READ_REC); 418 mutex_unlock(&priv->hi3110_lock); 419 420 return 0; 421 } 422 423 static int hi3110_set_normal_mode(struct spi_device *spi) 424 { 425 struct hi3110_priv *priv = spi_get_drvdata(spi); 426 u8 reg = 0; 427 428 hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR | 429 HI3110_INT_RXFIFO | HI3110_INT_TXCPLT); 430 431 /* Enable TX */ 432 hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN); 433 434 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 435 reg = HI3110_CTRL0_LOOPBACK_MODE; 436 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 437 reg = HI3110_CTRL0_MONITOR_MODE; 438 else 439 reg = HI3110_CTRL0_NORMAL_MODE; 440 441 hi3110_write(spi, HI3110_WRITE_CTRL0, reg); 442 443 /* Wait for the device to enter the mode */ 444 mdelay(HI3110_OST_DELAY_MS); 445 reg = hi3110_read(spi, HI3110_READ_CTRL0); 446 if ((reg & HI3110_CTRL0_MODE_MASK) != reg) 447 return -EBUSY; 448 449 priv->can.state = CAN_STATE_ERROR_ACTIVE; 450 return 0; 451 } 452 453 static int hi3110_do_set_bittiming(struct net_device *net) 454 { 455 struct hi3110_priv *priv = netdev_priv(net); 456 struct can_bittiming *bt = &priv->can.bittiming; 457 struct spi_device *spi = priv->spi; 458 459 hi3110_write(spi, HI3110_WRITE_BTR0, 460 ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) | 461 ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT)); 462 463 hi3110_write(spi, HI3110_WRITE_BTR1, 464 (priv->can.ctrlmode & 465 CAN_CTRLMODE_3_SAMPLES ? 466 HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) | 467 ((bt->phase_seg1 + bt->prop_seg - 1) 468 << HI3110_BTR1_TSEG1_SHIFT) | 469 ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT)); 470 471 dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n", 472 hi3110_read(spi, HI3110_READ_BTR0), 473 hi3110_read(spi, HI3110_READ_BTR1)); 474 475 return 0; 476 } 477 478 static int hi3110_setup(struct net_device *net) 479 { 480 hi3110_do_set_bittiming(net); 481 return 0; 482 } 483 484 static int hi3110_hw_reset(struct spi_device *spi) 485 { 486 u8 reg; 487 int ret; 488 489 /* Wait for oscillator startup timer after power up */ 490 mdelay(HI3110_OST_DELAY_MS); 491 492 ret = hi3110_cmd(spi, HI3110_MASTER_RESET); 493 if (ret) 494 return ret; 495 496 /* Wait for oscillator startup timer after reset */ 497 mdelay(HI3110_OST_DELAY_MS); 498 499 reg = hi3110_read(spi, HI3110_READ_CTRL0); 500 if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE) 501 return -ENODEV; 502 503 /* As per the datasheet it appears the error flags are 504 * not cleared on reset. Explicitly clear them by performing a read 505 */ 506 hi3110_read(spi, HI3110_READ_ERR); 507 508 return 0; 509 } 510 511 static int hi3110_hw_probe(struct spi_device *spi) 512 { 513 u8 statf; 514 515 hi3110_hw_reset(spi); 516 517 /* Confirm correct operation by checking against reset values 518 * in datasheet 519 */ 520 statf = hi3110_read(spi, HI3110_READ_STATF); 521 522 dev_dbg(&spi->dev, "statf: %02X\n", statf); 523 524 if (statf != 0x82) 525 return -ENODEV; 526 527 return 0; 528 } 529 530 static int hi3110_power_enable(struct regulator *reg, int enable) 531 { 532 if (IS_ERR_OR_NULL(reg)) 533 return 0; 534 535 if (enable) 536 return regulator_enable(reg); 537 else 538 return regulator_disable(reg); 539 } 540 541 static int hi3110_stop(struct net_device *net) 542 { 543 struct hi3110_priv *priv = netdev_priv(net); 544 struct spi_device *spi = priv->spi; 545 546 close_candev(net); 547 548 priv->force_quit = 1; 549 free_irq(spi->irq, priv); 550 destroy_workqueue(priv->wq); 551 priv->wq = NULL; 552 553 mutex_lock(&priv->hi3110_lock); 554 555 /* Disable transmit, interrupts and clear flags */ 556 hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0); 557 hi3110_write(spi, HI3110_WRITE_INTE, 0x0); 558 hi3110_read(spi, HI3110_READ_INTF); 559 560 hi3110_clean(net); 561 562 hi3110_hw_sleep(spi); 563 564 hi3110_power_enable(priv->transceiver, 0); 565 566 priv->can.state = CAN_STATE_STOPPED; 567 568 mutex_unlock(&priv->hi3110_lock); 569 570 can_led_event(net, CAN_LED_EVENT_STOP); 571 572 return 0; 573 } 574 575 static void hi3110_tx_work_handler(struct work_struct *ws) 576 { 577 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 578 tx_work); 579 struct spi_device *spi = priv->spi; 580 struct net_device *net = priv->net; 581 struct can_frame *frame; 582 583 mutex_lock(&priv->hi3110_lock); 584 if (priv->tx_skb) { 585 if (priv->can.state == CAN_STATE_BUS_OFF) { 586 hi3110_clean(net); 587 } else { 588 frame = (struct can_frame *)priv->tx_skb->data; 589 hi3110_hw_tx(spi, frame); 590 priv->tx_busy = true; 591 can_put_echo_skb(priv->tx_skb, net, 0, 0); 592 priv->tx_skb = NULL; 593 } 594 } 595 mutex_unlock(&priv->hi3110_lock); 596 } 597 598 static void hi3110_restart_work_handler(struct work_struct *ws) 599 { 600 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 601 restart_work); 602 struct spi_device *spi = priv->spi; 603 struct net_device *net = priv->net; 604 605 mutex_lock(&priv->hi3110_lock); 606 if (priv->after_suspend) { 607 hi3110_hw_reset(spi); 608 hi3110_setup(net); 609 if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) { 610 hi3110_set_normal_mode(spi); 611 } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 612 netif_device_attach(net); 613 hi3110_clean(net); 614 hi3110_set_normal_mode(spi); 615 netif_wake_queue(net); 616 } else { 617 hi3110_hw_sleep(spi); 618 } 619 priv->after_suspend = 0; 620 priv->force_quit = 0; 621 } 622 623 if (priv->restart_tx) { 624 priv->restart_tx = 0; 625 hi3110_hw_reset(spi); 626 hi3110_setup(net); 627 hi3110_clean(net); 628 hi3110_set_normal_mode(spi); 629 netif_wake_queue(net); 630 } 631 mutex_unlock(&priv->hi3110_lock); 632 } 633 634 static irqreturn_t hi3110_can_ist(int irq, void *dev_id) 635 { 636 struct hi3110_priv *priv = dev_id; 637 struct spi_device *spi = priv->spi; 638 struct net_device *net = priv->net; 639 640 mutex_lock(&priv->hi3110_lock); 641 642 while (!priv->force_quit) { 643 enum can_state new_state; 644 u8 intf, eflag, statf; 645 646 while (!(HI3110_STAT_RXFMTY & 647 (statf = hi3110_read(spi, HI3110_READ_STATF)))) { 648 hi3110_hw_rx(spi); 649 } 650 651 intf = hi3110_read(spi, HI3110_READ_INTF); 652 eflag = hi3110_read(spi, HI3110_READ_ERR); 653 /* Update can state */ 654 if (eflag & HI3110_ERR_BUSOFF) 655 new_state = CAN_STATE_BUS_OFF; 656 else if (eflag & HI3110_ERR_PASSIVE_MASK) 657 new_state = CAN_STATE_ERROR_PASSIVE; 658 else if (statf & HI3110_STAT_ERRW) 659 new_state = CAN_STATE_ERROR_WARNING; 660 else 661 new_state = CAN_STATE_ERROR_ACTIVE; 662 663 if (new_state != priv->can.state) { 664 struct can_frame *cf; 665 struct sk_buff *skb; 666 enum can_state rx_state, tx_state; 667 u8 rxerr, txerr; 668 669 skb = alloc_can_err_skb(net, &cf); 670 if (!skb) 671 break; 672 673 txerr = hi3110_read(spi, HI3110_READ_TEC); 674 rxerr = hi3110_read(spi, HI3110_READ_REC); 675 cf->data[6] = txerr; 676 cf->data[7] = rxerr; 677 tx_state = txerr >= rxerr ? new_state : 0; 678 rx_state = txerr <= rxerr ? new_state : 0; 679 can_change_state(net, cf, tx_state, rx_state); 680 netif_rx(skb); 681 682 if (new_state == CAN_STATE_BUS_OFF) { 683 can_bus_off(net); 684 if (priv->can.restart_ms == 0) { 685 priv->force_quit = 1; 686 hi3110_hw_sleep(spi); 687 break; 688 } 689 } 690 } 691 692 /* Update bus errors */ 693 if ((intf & HI3110_INT_BUSERR) && 694 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 695 struct can_frame *cf; 696 struct sk_buff *skb; 697 698 /* Check for protocol errors */ 699 if (eflag & HI3110_ERR_PROTOCOL_MASK) { 700 skb = alloc_can_err_skb(net, &cf); 701 if (!skb) 702 break; 703 704 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 705 priv->can.can_stats.bus_error++; 706 priv->net->stats.rx_errors++; 707 if (eflag & HI3110_ERR_BITERR) 708 cf->data[2] |= CAN_ERR_PROT_BIT; 709 else if (eflag & HI3110_ERR_FRMERR) 710 cf->data[2] |= CAN_ERR_PROT_FORM; 711 else if (eflag & HI3110_ERR_STUFERR) 712 cf->data[2] |= CAN_ERR_PROT_STUFF; 713 else if (eflag & HI3110_ERR_CRCERR) 714 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 715 else if (eflag & HI3110_ERR_ACKERR) 716 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 717 718 cf->data[6] = hi3110_read(spi, HI3110_READ_TEC); 719 cf->data[7] = hi3110_read(spi, HI3110_READ_REC); 720 netdev_dbg(priv->net, "Bus Error\n"); 721 netif_rx(skb); 722 } 723 } 724 725 if (priv->tx_busy && statf & HI3110_STAT_TXMTY) { 726 net->stats.tx_packets++; 727 net->stats.tx_bytes += can_get_echo_skb(net, 0, NULL); 728 can_led_event(net, CAN_LED_EVENT_TX); 729 priv->tx_busy = false; 730 netif_wake_queue(net); 731 } 732 733 if (intf == 0) 734 break; 735 } 736 mutex_unlock(&priv->hi3110_lock); 737 return IRQ_HANDLED; 738 } 739 740 static int hi3110_open(struct net_device *net) 741 { 742 struct hi3110_priv *priv = netdev_priv(net); 743 struct spi_device *spi = priv->spi; 744 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH; 745 int ret; 746 747 ret = open_candev(net); 748 if (ret) 749 return ret; 750 751 mutex_lock(&priv->hi3110_lock); 752 hi3110_power_enable(priv->transceiver, 1); 753 754 priv->force_quit = 0; 755 priv->tx_skb = NULL; 756 priv->tx_busy = false; 757 758 ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist, 759 flags, DEVICE_NAME, priv); 760 if (ret) { 761 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 762 goto out_close; 763 } 764 765 priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, 766 0); 767 if (!priv->wq) { 768 ret = -ENOMEM; 769 goto out_free_irq; 770 } 771 INIT_WORK(&priv->tx_work, hi3110_tx_work_handler); 772 INIT_WORK(&priv->restart_work, hi3110_restart_work_handler); 773 774 ret = hi3110_hw_reset(spi); 775 if (ret) 776 goto out_free_wq; 777 778 ret = hi3110_setup(net); 779 if (ret) 780 goto out_free_wq; 781 782 ret = hi3110_set_normal_mode(spi); 783 if (ret) 784 goto out_free_wq; 785 786 can_led_event(net, CAN_LED_EVENT_OPEN); 787 netif_wake_queue(net); 788 mutex_unlock(&priv->hi3110_lock); 789 790 return 0; 791 792 out_free_wq: 793 destroy_workqueue(priv->wq); 794 out_free_irq: 795 free_irq(spi->irq, priv); 796 hi3110_hw_sleep(spi); 797 out_close: 798 hi3110_power_enable(priv->transceiver, 0); 799 close_candev(net); 800 mutex_unlock(&priv->hi3110_lock); 801 return ret; 802 } 803 804 static const struct net_device_ops hi3110_netdev_ops = { 805 .ndo_open = hi3110_open, 806 .ndo_stop = hi3110_stop, 807 .ndo_start_xmit = hi3110_hard_start_xmit, 808 }; 809 810 static const struct of_device_id hi3110_of_match[] = { 811 { 812 .compatible = "holt,hi3110", 813 .data = (void *)CAN_HI3110_HI3110, 814 }, 815 { } 816 }; 817 MODULE_DEVICE_TABLE(of, hi3110_of_match); 818 819 static const struct spi_device_id hi3110_id_table[] = { 820 { 821 .name = "hi3110", 822 .driver_data = (kernel_ulong_t)CAN_HI3110_HI3110, 823 }, 824 { } 825 }; 826 MODULE_DEVICE_TABLE(spi, hi3110_id_table); 827 828 static int hi3110_can_probe(struct spi_device *spi) 829 { 830 struct device *dev = &spi->dev; 831 struct net_device *net; 832 struct hi3110_priv *priv; 833 const void *match; 834 struct clk *clk; 835 u32 freq; 836 int ret; 837 838 clk = devm_clk_get_optional(&spi->dev, NULL); 839 if (IS_ERR(clk)) 840 return dev_err_probe(dev, PTR_ERR(clk), "no CAN clock source defined\n"); 841 842 if (clk) { 843 freq = clk_get_rate(clk); 844 } else { 845 ret = device_property_read_u32(dev, "clock-frequency", &freq); 846 if (ret) 847 return dev_err_probe(dev, ret, "Failed to get clock-frequency!\n"); 848 } 849 850 /* Sanity check */ 851 if (freq > 40000000) 852 return -ERANGE; 853 854 /* Allocate can/net device */ 855 net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX); 856 if (!net) 857 return -ENOMEM; 858 859 ret = clk_prepare_enable(clk); 860 if (ret) 861 goto out_free; 862 863 net->netdev_ops = &hi3110_netdev_ops; 864 net->flags |= IFF_ECHO; 865 866 priv = netdev_priv(net); 867 priv->can.bittiming_const = &hi3110_bittiming_const; 868 priv->can.do_set_mode = hi3110_do_set_mode; 869 priv->can.do_get_berr_counter = hi3110_get_berr_counter; 870 priv->can.clock.freq = freq / 2; 871 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 872 CAN_CTRLMODE_LOOPBACK | 873 CAN_CTRLMODE_LISTENONLY | 874 CAN_CTRLMODE_BERR_REPORTING; 875 876 match = device_get_match_data(dev); 877 if (match) 878 priv->model = (enum hi3110_model)(uintptr_t)match; 879 else 880 priv->model = spi_get_device_id(spi)->driver_data; 881 priv->net = net; 882 priv->clk = clk; 883 884 spi_set_drvdata(spi, priv); 885 886 /* Configure the SPI bus */ 887 spi->bits_per_word = 8; 888 ret = spi_setup(spi); 889 if (ret) 890 goto out_clk; 891 892 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); 893 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 894 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 895 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { 896 ret = -EPROBE_DEFER; 897 goto out_clk; 898 } 899 900 ret = hi3110_power_enable(priv->power, 1); 901 if (ret) 902 goto out_clk; 903 904 priv->spi = spi; 905 mutex_init(&priv->hi3110_lock); 906 907 priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 908 GFP_KERNEL); 909 if (!priv->spi_tx_buf) { 910 ret = -ENOMEM; 911 goto error_probe; 912 } 913 priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 914 GFP_KERNEL); 915 916 if (!priv->spi_rx_buf) { 917 ret = -ENOMEM; 918 goto error_probe; 919 } 920 921 SET_NETDEV_DEV(net, &spi->dev); 922 923 ret = hi3110_hw_probe(spi); 924 if (ret) { 925 dev_err_probe(dev, ret, "Cannot initialize %x. Wrong wiring?\n", priv->model); 926 goto error_probe; 927 } 928 hi3110_hw_sleep(spi); 929 930 ret = register_candev(net); 931 if (ret) 932 goto error_probe; 933 934 devm_can_led_init(net); 935 netdev_info(net, "%x successfully initialized.\n", priv->model); 936 937 return 0; 938 939 error_probe: 940 hi3110_power_enable(priv->power, 0); 941 942 out_clk: 943 clk_disable_unprepare(clk); 944 945 out_free: 946 free_candev(net); 947 948 return dev_err_probe(dev, ret, "Probe failed\n"); 949 } 950 951 static void hi3110_can_remove(struct spi_device *spi) 952 { 953 struct hi3110_priv *priv = spi_get_drvdata(spi); 954 struct net_device *net = priv->net; 955 956 unregister_candev(net); 957 958 hi3110_power_enable(priv->power, 0); 959 960 clk_disable_unprepare(priv->clk); 961 962 free_candev(net); 963 } 964 965 static int __maybe_unused hi3110_can_suspend(struct device *dev) 966 { 967 struct spi_device *spi = to_spi_device(dev); 968 struct hi3110_priv *priv = spi_get_drvdata(spi); 969 struct net_device *net = priv->net; 970 971 priv->force_quit = 1; 972 disable_irq(spi->irq); 973 974 /* Note: at this point neither IST nor workqueues are running. 975 * open/stop cannot be called anyway so locking is not needed 976 */ 977 if (netif_running(net)) { 978 netif_device_detach(net); 979 980 hi3110_hw_sleep(spi); 981 hi3110_power_enable(priv->transceiver, 0); 982 priv->after_suspend = HI3110_AFTER_SUSPEND_UP; 983 } else { 984 priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN; 985 } 986 987 if (!IS_ERR_OR_NULL(priv->power)) { 988 regulator_disable(priv->power); 989 priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER; 990 } 991 992 return 0; 993 } 994 995 static int __maybe_unused hi3110_can_resume(struct device *dev) 996 { 997 struct spi_device *spi = to_spi_device(dev); 998 struct hi3110_priv *priv = spi_get_drvdata(spi); 999 1000 if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER) 1001 hi3110_power_enable(priv->power, 1); 1002 1003 if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 1004 hi3110_power_enable(priv->transceiver, 1); 1005 queue_work(priv->wq, &priv->restart_work); 1006 } else { 1007 priv->after_suspend = 0; 1008 } 1009 1010 priv->force_quit = 0; 1011 enable_irq(spi->irq); 1012 return 0; 1013 } 1014 1015 static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume); 1016 1017 static struct spi_driver hi3110_can_driver = { 1018 .driver = { 1019 .name = DEVICE_NAME, 1020 .of_match_table = hi3110_of_match, 1021 .pm = &hi3110_can_pm_ops, 1022 }, 1023 .id_table = hi3110_id_table, 1024 .probe = hi3110_can_probe, 1025 .remove = hi3110_can_remove, 1026 }; 1027 1028 module_spi_driver(hi3110_can_driver); 1029 1030 MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>"); 1031 MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>"); 1032 MODULE_DESCRIPTION("Holt HI-3110 CAN driver"); 1033 MODULE_LICENSE("GPL v2"); 1034