1 // SPDX-License-Identifier: GPL-2.0-only 2 /* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface 3 * 4 * Copyright(C) Timesys Corporation 2016 5 * 6 * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver 7 * Copyright 2009 Christian Pellegrin EVOL S.r.l. 8 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. 9 * Copyright 2006 Arcom Control Systems Ltd. 10 * 11 * Based on CAN bus driver for the CCAN controller written by 12 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix 13 * - Simon Kallweit, intefo AG 14 * Copyright 2007 15 */ 16 17 #include <linux/can/core.h> 18 #include <linux/can/dev.h> 19 #include <linux/can/led.h> 20 #include <linux/clk.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/device.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/freezer.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/platform_device.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/slab.h> 36 #include <linux/spi/spi.h> 37 #include <linux/uaccess.h> 38 39 #define HI3110_MASTER_RESET 0x56 40 #define HI3110_READ_CTRL0 0xD2 41 #define HI3110_READ_CTRL1 0xD4 42 #define HI3110_READ_STATF 0xE2 43 #define HI3110_WRITE_CTRL0 0x14 44 #define HI3110_WRITE_CTRL1 0x16 45 #define HI3110_WRITE_INTE 0x1C 46 #define HI3110_WRITE_BTR0 0x18 47 #define HI3110_WRITE_BTR1 0x1A 48 #define HI3110_READ_BTR0 0xD6 49 #define HI3110_READ_BTR1 0xD8 50 #define HI3110_READ_INTF 0xDE 51 #define HI3110_READ_ERR 0xDC 52 #define HI3110_READ_FIFO_WOTIME 0x48 53 #define HI3110_WRITE_FIFO 0x12 54 #define HI3110_READ_MESSTAT 0xDA 55 #define HI3110_READ_REC 0xEA 56 #define HI3110_READ_TEC 0xEC 57 58 #define HI3110_CTRL0_MODE_MASK (7 << 5) 59 #define HI3110_CTRL0_NORMAL_MODE (0 << 5) 60 #define HI3110_CTRL0_LOOPBACK_MODE (1 << 5) 61 #define HI3110_CTRL0_MONITOR_MODE (2 << 5) 62 #define HI3110_CTRL0_SLEEP_MODE (3 << 5) 63 #define HI3110_CTRL0_INIT_MODE (4 << 5) 64 65 #define HI3110_CTRL1_TXEN BIT(7) 66 67 #define HI3110_INT_RXTMP BIT(7) 68 #define HI3110_INT_RXFIFO BIT(6) 69 #define HI3110_INT_TXCPLT BIT(5) 70 #define HI3110_INT_BUSERR BIT(4) 71 #define HI3110_INT_MCHG BIT(3) 72 #define HI3110_INT_WAKEUP BIT(2) 73 #define HI3110_INT_F1MESS BIT(1) 74 #define HI3110_INT_F0MESS BIT(0) 75 76 #define HI3110_ERR_BUSOFF BIT(7) 77 #define HI3110_ERR_TXERRP BIT(6) 78 #define HI3110_ERR_RXERRP BIT(5) 79 #define HI3110_ERR_BITERR BIT(4) 80 #define HI3110_ERR_FRMERR BIT(3) 81 #define HI3110_ERR_CRCERR BIT(2) 82 #define HI3110_ERR_ACKERR BIT(1) 83 #define HI3110_ERR_STUFERR BIT(0) 84 #define HI3110_ERR_PROTOCOL_MASK (0x1F) 85 #define HI3110_ERR_PASSIVE_MASK (0x60) 86 87 #define HI3110_STAT_RXFMTY BIT(1) 88 #define HI3110_STAT_BUSOFF BIT(2) 89 #define HI3110_STAT_ERRP BIT(3) 90 #define HI3110_STAT_ERRW BIT(4) 91 #define HI3110_STAT_TXMTY BIT(7) 92 93 #define HI3110_BTR0_SJW_SHIFT 6 94 #define HI3110_BTR0_BRP_SHIFT 0 95 96 #define HI3110_BTR1_SAMP_3PERBIT (1 << 7) 97 #define HI3110_BTR1_SAMP_1PERBIT (0 << 7) 98 #define HI3110_BTR1_TSEG2_SHIFT 4 99 #define HI3110_BTR1_TSEG1_SHIFT 0 100 101 #define HI3110_FIFO_WOTIME_TAG_OFF 0 102 #define HI3110_FIFO_WOTIME_ID_OFF 1 103 #define HI3110_FIFO_WOTIME_DLC_OFF 5 104 #define HI3110_FIFO_WOTIME_DAT_OFF 6 105 106 #define HI3110_FIFO_WOTIME_TAG_IDE BIT(7) 107 #define HI3110_FIFO_WOTIME_ID_RTR BIT(0) 108 109 #define HI3110_FIFO_TAG_OFF 0 110 #define HI3110_FIFO_ID_OFF 1 111 #define HI3110_FIFO_STD_DLC_OFF 3 112 #define HI3110_FIFO_STD_DATA_OFF 4 113 #define HI3110_FIFO_EXT_DLC_OFF 5 114 #define HI3110_FIFO_EXT_DATA_OFF 6 115 116 #define HI3110_CAN_MAX_DATA_LEN 8 117 #define HI3110_RX_BUF_LEN 15 118 #define HI3110_TX_STD_BUF_LEN 12 119 #define HI3110_TX_EXT_BUF_LEN 14 120 #define HI3110_CAN_FRAME_MAX_BITS 128 121 #define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */ 122 123 #define HI3110_TX_ECHO_SKB_MAX 1 124 125 #define HI3110_OST_DELAY_MS (10) 126 127 #define DEVICE_NAME "hi3110" 128 129 static int hi3110_enable_dma = 1; /* Enable SPI DMA. Default: 1 (On) */ 130 module_param(hi3110_enable_dma, int, 0444); 131 MODULE_PARM_DESC(hi3110_enable_dma, "Enable SPI DMA. Default: 1 (On)"); 132 133 static const struct can_bittiming_const hi3110_bittiming_const = { 134 .name = DEVICE_NAME, 135 .tseg1_min = 2, 136 .tseg1_max = 16, 137 .tseg2_min = 2, 138 .tseg2_max = 8, 139 .sjw_max = 4, 140 .brp_min = 1, 141 .brp_max = 64, 142 .brp_inc = 1, 143 }; 144 145 enum hi3110_model { 146 CAN_HI3110_HI3110 = 0x3110, 147 }; 148 149 struct hi3110_priv { 150 struct can_priv can; 151 struct net_device *net; 152 struct spi_device *spi; 153 enum hi3110_model model; 154 155 struct mutex hi3110_lock; /* SPI device lock */ 156 157 u8 *spi_tx_buf; 158 u8 *spi_rx_buf; 159 dma_addr_t spi_tx_dma; 160 dma_addr_t spi_rx_dma; 161 162 struct sk_buff *tx_skb; 163 int tx_len; 164 165 struct workqueue_struct *wq; 166 struct work_struct tx_work; 167 struct work_struct restart_work; 168 169 int force_quit; 170 int after_suspend; 171 #define HI3110_AFTER_SUSPEND_UP 1 172 #define HI3110_AFTER_SUSPEND_DOWN 2 173 #define HI3110_AFTER_SUSPEND_POWER 4 174 #define HI3110_AFTER_SUSPEND_RESTART 8 175 int restart_tx; 176 struct regulator *power; 177 struct regulator *transceiver; 178 struct clk *clk; 179 }; 180 181 static void hi3110_clean(struct net_device *net) 182 { 183 struct hi3110_priv *priv = netdev_priv(net); 184 185 if (priv->tx_skb || priv->tx_len) 186 net->stats.tx_errors++; 187 if (priv->tx_skb) 188 dev_kfree_skb(priv->tx_skb); 189 if (priv->tx_len) 190 can_free_echo_skb(priv->net, 0); 191 priv->tx_skb = NULL; 192 priv->tx_len = 0; 193 } 194 195 /* Note about handling of error return of hi3110_spi_trans: accessing 196 * registers via SPI is not really different conceptually than using 197 * normal I/O assembler instructions, although it's much more 198 * complicated from a practical POV. So it's not advisable to always 199 * check the return value of this function. Imagine that every 200 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) 201 * error();", it would be a great mess (well there are some situation 202 * when exception handling C++ like could be useful after all). So we 203 * just check that transfers are OK at the beginning of our 204 * conversation with the chip and to avoid doing really nasty things 205 * (like injecting bogus packets in the network stack). 206 */ 207 static int hi3110_spi_trans(struct spi_device *spi, int len) 208 { 209 struct hi3110_priv *priv = spi_get_drvdata(spi); 210 struct spi_transfer t = { 211 .tx_buf = priv->spi_tx_buf, 212 .rx_buf = priv->spi_rx_buf, 213 .len = len, 214 .cs_change = 0, 215 }; 216 struct spi_message m; 217 int ret; 218 219 spi_message_init(&m); 220 221 if (hi3110_enable_dma) { 222 t.tx_dma = priv->spi_tx_dma; 223 t.rx_dma = priv->spi_rx_dma; 224 m.is_dma_mapped = 1; 225 } 226 227 spi_message_add_tail(&t, &m); 228 229 ret = spi_sync(spi, &m); 230 231 if (ret) 232 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); 233 return ret; 234 } 235 236 static u8 hi3110_cmd(struct spi_device *spi, u8 command) 237 { 238 struct hi3110_priv *priv = spi_get_drvdata(spi); 239 240 priv->spi_tx_buf[0] = command; 241 dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command); 242 243 return hi3110_spi_trans(spi, 1); 244 } 245 246 static u8 hi3110_read(struct spi_device *spi, u8 command) 247 { 248 struct hi3110_priv *priv = spi_get_drvdata(spi); 249 u8 val = 0; 250 251 priv->spi_tx_buf[0] = command; 252 hi3110_spi_trans(spi, 2); 253 val = priv->spi_rx_buf[1]; 254 255 return val; 256 } 257 258 static void hi3110_write(struct spi_device *spi, u8 reg, u8 val) 259 { 260 struct hi3110_priv *priv = spi_get_drvdata(spi); 261 262 priv->spi_tx_buf[0] = reg; 263 priv->spi_tx_buf[1] = val; 264 hi3110_spi_trans(spi, 2); 265 } 266 267 static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len) 268 { 269 struct hi3110_priv *priv = spi_get_drvdata(spi); 270 271 priv->spi_tx_buf[0] = HI3110_WRITE_FIFO; 272 memcpy(priv->spi_tx_buf + 1, buf, len); 273 hi3110_spi_trans(spi, len + 1); 274 } 275 276 static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame) 277 { 278 u8 buf[HI3110_TX_EXT_BUF_LEN]; 279 280 buf[HI3110_FIFO_TAG_OFF] = 0; 281 282 if (frame->can_id & CAN_EFF_FLAG) { 283 /* Extended frame */ 284 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21; 285 buf[HI3110_FIFO_ID_OFF + 1] = 286 (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) | 287 HI3110_EFF_FLAGS | 288 (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07); 289 buf[HI3110_FIFO_ID_OFF + 2] = 290 (frame->can_id & CAN_EFF_MASK) >> 7; 291 buf[HI3110_FIFO_ID_OFF + 3] = 292 ((frame->can_id & CAN_EFF_MASK) << 1) | 293 ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0); 294 295 buf[HI3110_FIFO_EXT_DLC_OFF] = frame->can_dlc; 296 297 memcpy(buf + HI3110_FIFO_EXT_DATA_OFF, 298 frame->data, frame->can_dlc); 299 300 hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN - 301 (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc)); 302 } else { 303 /* Standard frame */ 304 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3; 305 buf[HI3110_FIFO_ID_OFF + 1] = 306 ((frame->can_id & CAN_SFF_MASK) << 5) | 307 ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0); 308 309 buf[HI3110_FIFO_STD_DLC_OFF] = frame->can_dlc; 310 311 memcpy(buf + HI3110_FIFO_STD_DATA_OFF, 312 frame->data, frame->can_dlc); 313 314 hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN - 315 (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc)); 316 } 317 } 318 319 static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf) 320 { 321 struct hi3110_priv *priv = spi_get_drvdata(spi); 322 323 priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME; 324 hi3110_spi_trans(spi, HI3110_RX_BUF_LEN); 325 memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1); 326 } 327 328 static void hi3110_hw_rx(struct spi_device *spi) 329 { 330 struct hi3110_priv *priv = spi_get_drvdata(spi); 331 struct sk_buff *skb; 332 struct can_frame *frame; 333 u8 buf[HI3110_RX_BUF_LEN - 1]; 334 335 skb = alloc_can_skb(priv->net, &frame); 336 if (!skb) { 337 priv->net->stats.rx_dropped++; 338 return; 339 } 340 341 hi3110_hw_rx_frame(spi, buf); 342 if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) { 343 /* IDE is recessive (1), indicating extended 29-bit frame */ 344 frame->can_id = CAN_EFF_FLAG; 345 frame->can_id |= 346 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) | 347 (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) | 348 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) | 349 (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) | 350 (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1); 351 } else { 352 /* IDE is dominant (0), frame indicating standard 11-bit */ 353 frame->can_id = 354 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) | 355 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5); 356 } 357 358 /* Data length */ 359 frame->can_dlc = get_can_dlc(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F); 360 361 if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR) 362 frame->can_id |= CAN_RTR_FLAG; 363 else 364 memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF, 365 frame->can_dlc); 366 367 priv->net->stats.rx_packets++; 368 priv->net->stats.rx_bytes += frame->can_dlc; 369 370 can_led_event(priv->net, CAN_LED_EVENT_RX); 371 372 netif_rx_ni(skb); 373 } 374 375 static void hi3110_hw_sleep(struct spi_device *spi) 376 { 377 hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE); 378 } 379 380 static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb, 381 struct net_device *net) 382 { 383 struct hi3110_priv *priv = netdev_priv(net); 384 struct spi_device *spi = priv->spi; 385 386 if (priv->tx_skb || priv->tx_len) { 387 dev_err(&spi->dev, "hard_xmit called while tx busy\n"); 388 return NETDEV_TX_BUSY; 389 } 390 391 if (can_dropped_invalid_skb(net, skb)) 392 return NETDEV_TX_OK; 393 394 netif_stop_queue(net); 395 priv->tx_skb = skb; 396 queue_work(priv->wq, &priv->tx_work); 397 398 return NETDEV_TX_OK; 399 } 400 401 static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode) 402 { 403 struct hi3110_priv *priv = netdev_priv(net); 404 405 switch (mode) { 406 case CAN_MODE_START: 407 hi3110_clean(net); 408 /* We have to delay work since SPI I/O may sleep */ 409 priv->can.state = CAN_STATE_ERROR_ACTIVE; 410 priv->restart_tx = 1; 411 if (priv->can.restart_ms == 0) 412 priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART; 413 queue_work(priv->wq, &priv->restart_work); 414 break; 415 default: 416 return -EOPNOTSUPP; 417 } 418 419 return 0; 420 } 421 422 static int hi3110_get_berr_counter(const struct net_device *net, 423 struct can_berr_counter *bec) 424 { 425 struct hi3110_priv *priv = netdev_priv(net); 426 struct spi_device *spi = priv->spi; 427 428 mutex_lock(&priv->hi3110_lock); 429 bec->txerr = hi3110_read(spi, HI3110_READ_TEC); 430 bec->rxerr = hi3110_read(spi, HI3110_READ_REC); 431 mutex_unlock(&priv->hi3110_lock); 432 433 return 0; 434 } 435 436 static int hi3110_set_normal_mode(struct spi_device *spi) 437 { 438 struct hi3110_priv *priv = spi_get_drvdata(spi); 439 u8 reg = 0; 440 441 hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR | 442 HI3110_INT_RXFIFO | HI3110_INT_TXCPLT); 443 444 /* Enable TX */ 445 hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN); 446 447 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 448 reg = HI3110_CTRL0_LOOPBACK_MODE; 449 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 450 reg = HI3110_CTRL0_MONITOR_MODE; 451 else 452 reg = HI3110_CTRL0_NORMAL_MODE; 453 454 hi3110_write(spi, HI3110_WRITE_CTRL0, reg); 455 456 /* Wait for the device to enter the mode */ 457 mdelay(HI3110_OST_DELAY_MS); 458 reg = hi3110_read(spi, HI3110_READ_CTRL0); 459 if ((reg & HI3110_CTRL0_MODE_MASK) != reg) 460 return -EBUSY; 461 462 priv->can.state = CAN_STATE_ERROR_ACTIVE; 463 return 0; 464 } 465 466 static int hi3110_do_set_bittiming(struct net_device *net) 467 { 468 struct hi3110_priv *priv = netdev_priv(net); 469 struct can_bittiming *bt = &priv->can.bittiming; 470 struct spi_device *spi = priv->spi; 471 472 hi3110_write(spi, HI3110_WRITE_BTR0, 473 ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) | 474 ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT)); 475 476 hi3110_write(spi, HI3110_WRITE_BTR1, 477 (priv->can.ctrlmode & 478 CAN_CTRLMODE_3_SAMPLES ? 479 HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) | 480 ((bt->phase_seg1 + bt->prop_seg - 1) 481 << HI3110_BTR1_TSEG1_SHIFT) | 482 ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT)); 483 484 dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n", 485 hi3110_read(spi, HI3110_READ_BTR0), 486 hi3110_read(spi, HI3110_READ_BTR1)); 487 488 return 0; 489 } 490 491 static int hi3110_setup(struct net_device *net) 492 { 493 hi3110_do_set_bittiming(net); 494 return 0; 495 } 496 497 static int hi3110_hw_reset(struct spi_device *spi) 498 { 499 u8 reg; 500 int ret; 501 502 /* Wait for oscillator startup timer after power up */ 503 mdelay(HI3110_OST_DELAY_MS); 504 505 ret = hi3110_cmd(spi, HI3110_MASTER_RESET); 506 if (ret) 507 return ret; 508 509 /* Wait for oscillator startup timer after reset */ 510 mdelay(HI3110_OST_DELAY_MS); 511 512 reg = hi3110_read(spi, HI3110_READ_CTRL0); 513 if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE) 514 return -ENODEV; 515 516 /* As per the datasheet it appears the error flags are 517 * not cleared on reset. Explicitly clear them by performing a read 518 */ 519 hi3110_read(spi, HI3110_READ_ERR); 520 521 return 0; 522 } 523 524 static int hi3110_hw_probe(struct spi_device *spi) 525 { 526 u8 statf; 527 528 hi3110_hw_reset(spi); 529 530 /* Confirm correct operation by checking against reset values 531 * in datasheet 532 */ 533 statf = hi3110_read(spi, HI3110_READ_STATF); 534 535 dev_dbg(&spi->dev, "statf: %02X\n", statf); 536 537 if (statf != 0x82) 538 return -ENODEV; 539 540 return 0; 541 } 542 543 static int hi3110_power_enable(struct regulator *reg, int enable) 544 { 545 if (IS_ERR_OR_NULL(reg)) 546 return 0; 547 548 if (enable) 549 return regulator_enable(reg); 550 else 551 return regulator_disable(reg); 552 } 553 554 static int hi3110_stop(struct net_device *net) 555 { 556 struct hi3110_priv *priv = netdev_priv(net); 557 struct spi_device *spi = priv->spi; 558 559 close_candev(net); 560 561 priv->force_quit = 1; 562 free_irq(spi->irq, priv); 563 destroy_workqueue(priv->wq); 564 priv->wq = NULL; 565 566 mutex_lock(&priv->hi3110_lock); 567 568 /* Disable transmit, interrupts and clear flags */ 569 hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0); 570 hi3110_write(spi, HI3110_WRITE_INTE, 0x0); 571 hi3110_read(spi, HI3110_READ_INTF); 572 573 hi3110_clean(net); 574 575 hi3110_hw_sleep(spi); 576 577 hi3110_power_enable(priv->transceiver, 0); 578 579 priv->can.state = CAN_STATE_STOPPED; 580 581 mutex_unlock(&priv->hi3110_lock); 582 583 can_led_event(net, CAN_LED_EVENT_STOP); 584 585 return 0; 586 } 587 588 static void hi3110_tx_work_handler(struct work_struct *ws) 589 { 590 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 591 tx_work); 592 struct spi_device *spi = priv->spi; 593 struct net_device *net = priv->net; 594 struct can_frame *frame; 595 596 mutex_lock(&priv->hi3110_lock); 597 if (priv->tx_skb) { 598 if (priv->can.state == CAN_STATE_BUS_OFF) { 599 hi3110_clean(net); 600 } else { 601 frame = (struct can_frame *)priv->tx_skb->data; 602 hi3110_hw_tx(spi, frame); 603 priv->tx_len = 1 + frame->can_dlc; 604 can_put_echo_skb(priv->tx_skb, net, 0); 605 priv->tx_skb = NULL; 606 } 607 } 608 mutex_unlock(&priv->hi3110_lock); 609 } 610 611 static void hi3110_restart_work_handler(struct work_struct *ws) 612 { 613 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 614 restart_work); 615 struct spi_device *spi = priv->spi; 616 struct net_device *net = priv->net; 617 618 mutex_lock(&priv->hi3110_lock); 619 if (priv->after_suspend) { 620 hi3110_hw_reset(spi); 621 hi3110_setup(net); 622 if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) { 623 hi3110_set_normal_mode(spi); 624 } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 625 netif_device_attach(net); 626 hi3110_clean(net); 627 hi3110_set_normal_mode(spi); 628 netif_wake_queue(net); 629 } else { 630 hi3110_hw_sleep(spi); 631 } 632 priv->after_suspend = 0; 633 priv->force_quit = 0; 634 } 635 636 if (priv->restart_tx) { 637 priv->restart_tx = 0; 638 hi3110_hw_reset(spi); 639 hi3110_setup(net); 640 hi3110_clean(net); 641 hi3110_set_normal_mode(spi); 642 netif_wake_queue(net); 643 } 644 mutex_unlock(&priv->hi3110_lock); 645 } 646 647 static irqreturn_t hi3110_can_ist(int irq, void *dev_id) 648 { 649 struct hi3110_priv *priv = dev_id; 650 struct spi_device *spi = priv->spi; 651 struct net_device *net = priv->net; 652 653 mutex_lock(&priv->hi3110_lock); 654 655 while (!priv->force_quit) { 656 enum can_state new_state; 657 u8 intf, eflag, statf; 658 659 while (!(HI3110_STAT_RXFMTY & 660 (statf = hi3110_read(spi, HI3110_READ_STATF)))) { 661 hi3110_hw_rx(spi); 662 } 663 664 intf = hi3110_read(spi, HI3110_READ_INTF); 665 eflag = hi3110_read(spi, HI3110_READ_ERR); 666 /* Update can state */ 667 if (eflag & HI3110_ERR_BUSOFF) 668 new_state = CAN_STATE_BUS_OFF; 669 else if (eflag & HI3110_ERR_PASSIVE_MASK) 670 new_state = CAN_STATE_ERROR_PASSIVE; 671 else if (statf & HI3110_STAT_ERRW) 672 new_state = CAN_STATE_ERROR_WARNING; 673 else 674 new_state = CAN_STATE_ERROR_ACTIVE; 675 676 if (new_state != priv->can.state) { 677 struct can_frame *cf; 678 struct sk_buff *skb; 679 enum can_state rx_state, tx_state; 680 u8 rxerr, txerr; 681 682 skb = alloc_can_err_skb(net, &cf); 683 if (!skb) 684 break; 685 686 txerr = hi3110_read(spi, HI3110_READ_TEC); 687 rxerr = hi3110_read(spi, HI3110_READ_REC); 688 cf->data[6] = txerr; 689 cf->data[7] = rxerr; 690 tx_state = txerr >= rxerr ? new_state : 0; 691 rx_state = txerr <= rxerr ? new_state : 0; 692 can_change_state(net, cf, tx_state, rx_state); 693 netif_rx_ni(skb); 694 695 if (new_state == CAN_STATE_BUS_OFF) { 696 can_bus_off(net); 697 if (priv->can.restart_ms == 0) { 698 priv->force_quit = 1; 699 hi3110_hw_sleep(spi); 700 break; 701 } 702 } 703 } 704 705 /* Update bus errors */ 706 if ((intf & HI3110_INT_BUSERR) && 707 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 708 struct can_frame *cf; 709 struct sk_buff *skb; 710 711 /* Check for protocol errors */ 712 if (eflag & HI3110_ERR_PROTOCOL_MASK) { 713 skb = alloc_can_err_skb(net, &cf); 714 if (!skb) 715 break; 716 717 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 718 priv->can.can_stats.bus_error++; 719 priv->net->stats.rx_errors++; 720 if (eflag & HI3110_ERR_BITERR) 721 cf->data[2] |= CAN_ERR_PROT_BIT; 722 else if (eflag & HI3110_ERR_FRMERR) 723 cf->data[2] |= CAN_ERR_PROT_FORM; 724 else if (eflag & HI3110_ERR_STUFERR) 725 cf->data[2] |= CAN_ERR_PROT_STUFF; 726 else if (eflag & HI3110_ERR_CRCERR) 727 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 728 else if (eflag & HI3110_ERR_ACKERR) 729 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 730 731 cf->data[6] = hi3110_read(spi, HI3110_READ_TEC); 732 cf->data[7] = hi3110_read(spi, HI3110_READ_REC); 733 netdev_dbg(priv->net, "Bus Error\n"); 734 netif_rx_ni(skb); 735 } 736 } 737 738 if (priv->tx_len && statf & HI3110_STAT_TXMTY) { 739 net->stats.tx_packets++; 740 net->stats.tx_bytes += priv->tx_len - 1; 741 can_led_event(net, CAN_LED_EVENT_TX); 742 if (priv->tx_len) { 743 can_get_echo_skb(net, 0); 744 priv->tx_len = 0; 745 } 746 netif_wake_queue(net); 747 } 748 749 if (intf == 0) 750 break; 751 } 752 mutex_unlock(&priv->hi3110_lock); 753 return IRQ_HANDLED; 754 } 755 756 static int hi3110_open(struct net_device *net) 757 { 758 struct hi3110_priv *priv = netdev_priv(net); 759 struct spi_device *spi = priv->spi; 760 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH; 761 int ret; 762 763 ret = open_candev(net); 764 if (ret) 765 return ret; 766 767 mutex_lock(&priv->hi3110_lock); 768 hi3110_power_enable(priv->transceiver, 1); 769 770 priv->force_quit = 0; 771 priv->tx_skb = NULL; 772 priv->tx_len = 0; 773 774 ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist, 775 flags, DEVICE_NAME, priv); 776 if (ret) { 777 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 778 goto out_close; 779 } 780 781 priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, 782 0); 783 if (!priv->wq) { 784 ret = -ENOMEM; 785 goto out_free_irq; 786 } 787 INIT_WORK(&priv->tx_work, hi3110_tx_work_handler); 788 INIT_WORK(&priv->restart_work, hi3110_restart_work_handler); 789 790 ret = hi3110_hw_reset(spi); 791 if (ret) 792 goto out_free_wq; 793 794 ret = hi3110_setup(net); 795 if (ret) 796 goto out_free_wq; 797 798 ret = hi3110_set_normal_mode(spi); 799 if (ret) 800 goto out_free_wq; 801 802 can_led_event(net, CAN_LED_EVENT_OPEN); 803 netif_wake_queue(net); 804 mutex_unlock(&priv->hi3110_lock); 805 806 return 0; 807 808 out_free_wq: 809 destroy_workqueue(priv->wq); 810 out_free_irq: 811 free_irq(spi->irq, priv); 812 hi3110_hw_sleep(spi); 813 out_close: 814 hi3110_power_enable(priv->transceiver, 0); 815 close_candev(net); 816 mutex_unlock(&priv->hi3110_lock); 817 return ret; 818 } 819 820 static const struct net_device_ops hi3110_netdev_ops = { 821 .ndo_open = hi3110_open, 822 .ndo_stop = hi3110_stop, 823 .ndo_start_xmit = hi3110_hard_start_xmit, 824 }; 825 826 static const struct of_device_id hi3110_of_match[] = { 827 { 828 .compatible = "holt,hi3110", 829 .data = (void *)CAN_HI3110_HI3110, 830 }, 831 { } 832 }; 833 MODULE_DEVICE_TABLE(of, hi3110_of_match); 834 835 static const struct spi_device_id hi3110_id_table[] = { 836 { 837 .name = "hi3110", 838 .driver_data = (kernel_ulong_t)CAN_HI3110_HI3110, 839 }, 840 { } 841 }; 842 MODULE_DEVICE_TABLE(spi, hi3110_id_table); 843 844 static int hi3110_can_probe(struct spi_device *spi) 845 { 846 const struct of_device_id *of_id = of_match_device(hi3110_of_match, 847 &spi->dev); 848 struct net_device *net; 849 struct hi3110_priv *priv; 850 struct clk *clk; 851 int freq, ret; 852 853 clk = devm_clk_get(&spi->dev, NULL); 854 if (IS_ERR(clk)) { 855 dev_err(&spi->dev, "no CAN clock source defined\n"); 856 return PTR_ERR(clk); 857 } 858 freq = clk_get_rate(clk); 859 860 /* Sanity check */ 861 if (freq > 40000000) 862 return -ERANGE; 863 864 /* Allocate can/net device */ 865 net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX); 866 if (!net) 867 return -ENOMEM; 868 869 if (!IS_ERR(clk)) { 870 ret = clk_prepare_enable(clk); 871 if (ret) 872 goto out_free; 873 } 874 875 net->netdev_ops = &hi3110_netdev_ops; 876 net->flags |= IFF_ECHO; 877 878 priv = netdev_priv(net); 879 priv->can.bittiming_const = &hi3110_bittiming_const; 880 priv->can.do_set_mode = hi3110_do_set_mode; 881 priv->can.do_get_berr_counter = hi3110_get_berr_counter; 882 priv->can.clock.freq = freq / 2; 883 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 884 CAN_CTRLMODE_LOOPBACK | 885 CAN_CTRLMODE_LISTENONLY | 886 CAN_CTRLMODE_BERR_REPORTING; 887 888 if (of_id) 889 priv->model = (enum hi3110_model)of_id->data; 890 else 891 priv->model = spi_get_device_id(spi)->driver_data; 892 priv->net = net; 893 priv->clk = clk; 894 895 spi_set_drvdata(spi, priv); 896 897 /* Configure the SPI bus */ 898 spi->bits_per_word = 8; 899 ret = spi_setup(spi); 900 if (ret) 901 goto out_clk; 902 903 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); 904 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 905 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 906 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { 907 ret = -EPROBE_DEFER; 908 goto out_clk; 909 } 910 911 ret = hi3110_power_enable(priv->power, 1); 912 if (ret) 913 goto out_clk; 914 915 priv->spi = spi; 916 mutex_init(&priv->hi3110_lock); 917 918 /* If requested, allocate DMA buffers */ 919 if (hi3110_enable_dma) { 920 spi->dev.coherent_dma_mask = ~0; 921 922 /* Minimum coherent DMA allocation is PAGE_SIZE, so allocate 923 * that much and share it between Tx and Rx DMA buffers. 924 */ 925 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev, 926 PAGE_SIZE, 927 &priv->spi_tx_dma, 928 GFP_DMA); 929 930 if (priv->spi_tx_buf) { 931 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2)); 932 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma + 933 (PAGE_SIZE / 2)); 934 } else { 935 /* Fall back to non-DMA */ 936 hi3110_enable_dma = 0; 937 } 938 } 939 940 /* Allocate non-DMA buffers */ 941 if (!hi3110_enable_dma) { 942 priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 943 GFP_KERNEL); 944 if (!priv->spi_tx_buf) { 945 ret = -ENOMEM; 946 goto error_probe; 947 } 948 priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 949 GFP_KERNEL); 950 951 if (!priv->spi_rx_buf) { 952 ret = -ENOMEM; 953 goto error_probe; 954 } 955 } 956 957 SET_NETDEV_DEV(net, &spi->dev); 958 959 ret = hi3110_hw_probe(spi); 960 if (ret) { 961 if (ret == -ENODEV) 962 dev_err(&spi->dev, "Cannot initialize %x. Wrong wiring?\n", 963 priv->model); 964 goto error_probe; 965 } 966 hi3110_hw_sleep(spi); 967 968 ret = register_candev(net); 969 if (ret) 970 goto error_probe; 971 972 devm_can_led_init(net); 973 netdev_info(net, "%x successfully initialized.\n", priv->model); 974 975 return 0; 976 977 error_probe: 978 hi3110_power_enable(priv->power, 0); 979 980 out_clk: 981 if (!IS_ERR(clk)) 982 clk_disable_unprepare(clk); 983 984 out_free: 985 free_candev(net); 986 987 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret); 988 return ret; 989 } 990 991 static int hi3110_can_remove(struct spi_device *spi) 992 { 993 struct hi3110_priv *priv = spi_get_drvdata(spi); 994 struct net_device *net = priv->net; 995 996 unregister_candev(net); 997 998 hi3110_power_enable(priv->power, 0); 999 1000 if (!IS_ERR(priv->clk)) 1001 clk_disable_unprepare(priv->clk); 1002 1003 free_candev(net); 1004 1005 return 0; 1006 } 1007 1008 static int __maybe_unused hi3110_can_suspend(struct device *dev) 1009 { 1010 struct spi_device *spi = to_spi_device(dev); 1011 struct hi3110_priv *priv = spi_get_drvdata(spi); 1012 struct net_device *net = priv->net; 1013 1014 priv->force_quit = 1; 1015 disable_irq(spi->irq); 1016 1017 /* Note: at this point neither IST nor workqueues are running. 1018 * open/stop cannot be called anyway so locking is not needed 1019 */ 1020 if (netif_running(net)) { 1021 netif_device_detach(net); 1022 1023 hi3110_hw_sleep(spi); 1024 hi3110_power_enable(priv->transceiver, 0); 1025 priv->after_suspend = HI3110_AFTER_SUSPEND_UP; 1026 } else { 1027 priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN; 1028 } 1029 1030 if (!IS_ERR_OR_NULL(priv->power)) { 1031 regulator_disable(priv->power); 1032 priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER; 1033 } 1034 1035 return 0; 1036 } 1037 1038 static int __maybe_unused hi3110_can_resume(struct device *dev) 1039 { 1040 struct spi_device *spi = to_spi_device(dev); 1041 struct hi3110_priv *priv = spi_get_drvdata(spi); 1042 1043 if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER) 1044 hi3110_power_enable(priv->power, 1); 1045 1046 if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 1047 hi3110_power_enable(priv->transceiver, 1); 1048 queue_work(priv->wq, &priv->restart_work); 1049 } else { 1050 priv->after_suspend = 0; 1051 } 1052 1053 priv->force_quit = 0; 1054 enable_irq(spi->irq); 1055 return 0; 1056 } 1057 1058 static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume); 1059 1060 static struct spi_driver hi3110_can_driver = { 1061 .driver = { 1062 .name = DEVICE_NAME, 1063 .of_match_table = hi3110_of_match, 1064 .pm = &hi3110_can_pm_ops, 1065 }, 1066 .id_table = hi3110_id_table, 1067 .probe = hi3110_can_probe, 1068 .remove = hi3110_can_remove, 1069 }; 1070 1071 module_spi_driver(hi3110_can_driver); 1072 1073 MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>"); 1074 MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>"); 1075 MODULE_DESCRIPTION("Holt HI-3110 CAN driver"); 1076 MODULE_LICENSE("GPL v2"); 1077