1 // SPDX-License-Identifier: GPL-2.0-only 2 /* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface 3 * 4 * Copyright(C) Timesys Corporation 2016 5 * 6 * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver 7 * Copyright 2009 Christian Pellegrin EVOL S.r.l. 8 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. 9 * Copyright 2006 Arcom Control Systems Ltd. 10 * 11 * Based on CAN bus driver for the CCAN controller written by 12 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix 13 * - Simon Kallweit, intefo AG 14 * Copyright 2007 15 */ 16 17 #include <linux/can/core.h> 18 #include <linux/can/dev.h> 19 #include <linux/clk.h> 20 #include <linux/completion.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/freezer.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/kernel.h> 27 #include <linux/mod_devicetable.h> 28 #include <linux/module.h> 29 #include <linux/netdevice.h> 30 #include <linux/platform_device.h> 31 #include <linux/property.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/slab.h> 34 #include <linux/spi/spi.h> 35 #include <linux/uaccess.h> 36 37 #define HI3110_MASTER_RESET 0x56 38 #define HI3110_READ_CTRL0 0xD2 39 #define HI3110_READ_CTRL1 0xD4 40 #define HI3110_READ_STATF 0xE2 41 #define HI3110_WRITE_CTRL0 0x14 42 #define HI3110_WRITE_CTRL1 0x16 43 #define HI3110_WRITE_INTE 0x1C 44 #define HI3110_WRITE_BTR0 0x18 45 #define HI3110_WRITE_BTR1 0x1A 46 #define HI3110_READ_BTR0 0xD6 47 #define HI3110_READ_BTR1 0xD8 48 #define HI3110_READ_INTF 0xDE 49 #define HI3110_READ_ERR 0xDC 50 #define HI3110_READ_FIFO_WOTIME 0x48 51 #define HI3110_WRITE_FIFO 0x12 52 #define HI3110_READ_MESSTAT 0xDA 53 #define HI3110_READ_REC 0xEA 54 #define HI3110_READ_TEC 0xEC 55 56 #define HI3110_CTRL0_MODE_MASK (7 << 5) 57 #define HI3110_CTRL0_NORMAL_MODE (0 << 5) 58 #define HI3110_CTRL0_LOOPBACK_MODE (1 << 5) 59 #define HI3110_CTRL0_MONITOR_MODE (2 << 5) 60 #define HI3110_CTRL0_SLEEP_MODE (3 << 5) 61 #define HI3110_CTRL0_INIT_MODE (4 << 5) 62 63 #define HI3110_CTRL1_TXEN BIT(7) 64 65 #define HI3110_INT_RXTMP BIT(7) 66 #define HI3110_INT_RXFIFO BIT(6) 67 #define HI3110_INT_TXCPLT BIT(5) 68 #define HI3110_INT_BUSERR BIT(4) 69 #define HI3110_INT_MCHG BIT(3) 70 #define HI3110_INT_WAKEUP BIT(2) 71 #define HI3110_INT_F1MESS BIT(1) 72 #define HI3110_INT_F0MESS BIT(0) 73 74 #define HI3110_ERR_BUSOFF BIT(7) 75 #define HI3110_ERR_TXERRP BIT(6) 76 #define HI3110_ERR_RXERRP BIT(5) 77 #define HI3110_ERR_BITERR BIT(4) 78 #define HI3110_ERR_FRMERR BIT(3) 79 #define HI3110_ERR_CRCERR BIT(2) 80 #define HI3110_ERR_ACKERR BIT(1) 81 #define HI3110_ERR_STUFERR BIT(0) 82 #define HI3110_ERR_PROTOCOL_MASK (0x1F) 83 #define HI3110_ERR_PASSIVE_MASK (0x60) 84 85 #define HI3110_STAT_RXFMTY BIT(1) 86 #define HI3110_STAT_BUSOFF BIT(2) 87 #define HI3110_STAT_ERRP BIT(3) 88 #define HI3110_STAT_ERRW BIT(4) 89 #define HI3110_STAT_TXMTY BIT(7) 90 91 #define HI3110_BTR0_SJW_SHIFT 6 92 #define HI3110_BTR0_BRP_SHIFT 0 93 94 #define HI3110_BTR1_SAMP_3PERBIT (1 << 7) 95 #define HI3110_BTR1_SAMP_1PERBIT (0 << 7) 96 #define HI3110_BTR1_TSEG2_SHIFT 4 97 #define HI3110_BTR1_TSEG1_SHIFT 0 98 99 #define HI3110_FIFO_WOTIME_TAG_OFF 0 100 #define HI3110_FIFO_WOTIME_ID_OFF 1 101 #define HI3110_FIFO_WOTIME_DLC_OFF 5 102 #define HI3110_FIFO_WOTIME_DAT_OFF 6 103 104 #define HI3110_FIFO_WOTIME_TAG_IDE BIT(7) 105 #define HI3110_FIFO_WOTIME_ID_RTR BIT(0) 106 107 #define HI3110_FIFO_TAG_OFF 0 108 #define HI3110_FIFO_ID_OFF 1 109 #define HI3110_FIFO_STD_DLC_OFF 3 110 #define HI3110_FIFO_STD_DATA_OFF 4 111 #define HI3110_FIFO_EXT_DLC_OFF 5 112 #define HI3110_FIFO_EXT_DATA_OFF 6 113 114 #define HI3110_CAN_MAX_DATA_LEN 8 115 #define HI3110_RX_BUF_LEN 15 116 #define HI3110_TX_STD_BUF_LEN 12 117 #define HI3110_TX_EXT_BUF_LEN 14 118 #define HI3110_CAN_FRAME_MAX_BITS 128 119 #define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */ 120 121 #define HI3110_TX_ECHO_SKB_MAX 1 122 123 #define HI3110_OST_DELAY_MS (10) 124 125 #define DEVICE_NAME "hi3110" 126 127 static const struct can_bittiming_const hi3110_bittiming_const = { 128 .name = DEVICE_NAME, 129 .tseg1_min = 2, 130 .tseg1_max = 16, 131 .tseg2_min = 2, 132 .tseg2_max = 8, 133 .sjw_max = 4, 134 .brp_min = 1, 135 .brp_max = 64, 136 .brp_inc = 1, 137 }; 138 139 enum hi3110_model { 140 CAN_HI3110_HI3110 = 0x3110, 141 }; 142 143 struct hi3110_priv { 144 struct can_priv can; 145 struct net_device *net; 146 struct spi_device *spi; 147 enum hi3110_model model; 148 149 struct mutex hi3110_lock; /* SPI device lock */ 150 151 u8 *spi_tx_buf; 152 u8 *spi_rx_buf; 153 154 struct sk_buff *tx_skb; 155 156 struct workqueue_struct *wq; 157 struct work_struct tx_work; 158 struct work_struct restart_work; 159 160 int force_quit; 161 int after_suspend; 162 #define HI3110_AFTER_SUSPEND_UP 1 163 #define HI3110_AFTER_SUSPEND_DOWN 2 164 #define HI3110_AFTER_SUSPEND_POWER 4 165 #define HI3110_AFTER_SUSPEND_RESTART 8 166 int restart_tx; 167 bool tx_busy; 168 169 struct regulator *power; 170 struct regulator *transceiver; 171 struct clk *clk; 172 }; 173 174 static void hi3110_clean(struct net_device *net) 175 { 176 struct hi3110_priv *priv = netdev_priv(net); 177 178 if (priv->tx_skb || priv->tx_busy) 179 net->stats.tx_errors++; 180 dev_kfree_skb(priv->tx_skb); 181 if (priv->tx_busy) 182 can_free_echo_skb(priv->net, 0, NULL); 183 priv->tx_skb = NULL; 184 priv->tx_busy = false; 185 } 186 187 /* Note about handling of error return of hi3110_spi_trans: accessing 188 * registers via SPI is not really different conceptually than using 189 * normal I/O assembler instructions, although it's much more 190 * complicated from a practical POV. So it's not advisable to always 191 * check the return value of this function. Imagine that every 192 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) 193 * error();", it would be a great mess (well there are some situation 194 * when exception handling C++ like could be useful after all). So we 195 * just check that transfers are OK at the beginning of our 196 * conversation with the chip and to avoid doing really nasty things 197 * (like injecting bogus packets in the network stack). 198 */ 199 static int hi3110_spi_trans(struct spi_device *spi, int len) 200 { 201 struct hi3110_priv *priv = spi_get_drvdata(spi); 202 struct spi_transfer t = { 203 .tx_buf = priv->spi_tx_buf, 204 .rx_buf = priv->spi_rx_buf, 205 .len = len, 206 .cs_change = 0, 207 }; 208 struct spi_message m; 209 int ret; 210 211 spi_message_init(&m); 212 spi_message_add_tail(&t, &m); 213 214 ret = spi_sync(spi, &m); 215 216 if (ret) 217 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); 218 return ret; 219 } 220 221 static int hi3110_cmd(struct spi_device *spi, u8 command) 222 { 223 struct hi3110_priv *priv = spi_get_drvdata(spi); 224 225 priv->spi_tx_buf[0] = command; 226 dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command); 227 228 return hi3110_spi_trans(spi, 1); 229 } 230 231 static u8 hi3110_read(struct spi_device *spi, u8 command) 232 { 233 struct hi3110_priv *priv = spi_get_drvdata(spi); 234 u8 val = 0; 235 236 priv->spi_tx_buf[0] = command; 237 hi3110_spi_trans(spi, 2); 238 val = priv->spi_rx_buf[1]; 239 240 return val; 241 } 242 243 static void hi3110_write(struct spi_device *spi, u8 reg, u8 val) 244 { 245 struct hi3110_priv *priv = spi_get_drvdata(spi); 246 247 priv->spi_tx_buf[0] = reg; 248 priv->spi_tx_buf[1] = val; 249 hi3110_spi_trans(spi, 2); 250 } 251 252 static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len) 253 { 254 struct hi3110_priv *priv = spi_get_drvdata(spi); 255 256 priv->spi_tx_buf[0] = HI3110_WRITE_FIFO; 257 memcpy(priv->spi_tx_buf + 1, buf, len); 258 hi3110_spi_trans(spi, len + 1); 259 } 260 261 static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame) 262 { 263 u8 buf[HI3110_TX_EXT_BUF_LEN]; 264 265 buf[HI3110_FIFO_TAG_OFF] = 0; 266 267 if (frame->can_id & CAN_EFF_FLAG) { 268 /* Extended frame */ 269 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21; 270 buf[HI3110_FIFO_ID_OFF + 1] = 271 (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) | 272 HI3110_EFF_FLAGS | 273 (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07); 274 buf[HI3110_FIFO_ID_OFF + 2] = 275 (frame->can_id & CAN_EFF_MASK) >> 7; 276 buf[HI3110_FIFO_ID_OFF + 3] = 277 ((frame->can_id & CAN_EFF_MASK) << 1) | 278 ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0); 279 280 buf[HI3110_FIFO_EXT_DLC_OFF] = frame->len; 281 282 memcpy(buf + HI3110_FIFO_EXT_DATA_OFF, 283 frame->data, frame->len); 284 285 hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN - 286 (HI3110_CAN_MAX_DATA_LEN - frame->len)); 287 } else { 288 /* Standard frame */ 289 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3; 290 buf[HI3110_FIFO_ID_OFF + 1] = 291 ((frame->can_id & CAN_SFF_MASK) << 5) | 292 ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0); 293 294 buf[HI3110_FIFO_STD_DLC_OFF] = frame->len; 295 296 memcpy(buf + HI3110_FIFO_STD_DATA_OFF, 297 frame->data, frame->len); 298 299 hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN - 300 (HI3110_CAN_MAX_DATA_LEN - frame->len)); 301 } 302 } 303 304 static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf) 305 { 306 struct hi3110_priv *priv = spi_get_drvdata(spi); 307 308 priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME; 309 hi3110_spi_trans(spi, HI3110_RX_BUF_LEN); 310 memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1); 311 } 312 313 static void hi3110_hw_rx(struct spi_device *spi) 314 { 315 struct hi3110_priv *priv = spi_get_drvdata(spi); 316 struct sk_buff *skb; 317 struct can_frame *frame; 318 u8 buf[HI3110_RX_BUF_LEN - 1]; 319 320 skb = alloc_can_skb(priv->net, &frame); 321 if (!skb) { 322 priv->net->stats.rx_dropped++; 323 return; 324 } 325 326 hi3110_hw_rx_frame(spi, buf); 327 if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) { 328 /* IDE is recessive (1), indicating extended 29-bit frame */ 329 frame->can_id = CAN_EFF_FLAG; 330 frame->can_id |= 331 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) | 332 (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) | 333 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) | 334 (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) | 335 (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1); 336 } else { 337 /* IDE is dominant (0), frame indicating standard 11-bit */ 338 frame->can_id = 339 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) | 340 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5); 341 } 342 343 /* Data length */ 344 frame->len = can_cc_dlc2len(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F); 345 346 if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR) { 347 frame->can_id |= CAN_RTR_FLAG; 348 } else { 349 memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF, 350 frame->len); 351 352 priv->net->stats.rx_bytes += frame->len; 353 } 354 priv->net->stats.rx_packets++; 355 356 netif_rx(skb); 357 } 358 359 static void hi3110_hw_sleep(struct spi_device *spi) 360 { 361 hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE); 362 } 363 364 static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb, 365 struct net_device *net) 366 { 367 struct hi3110_priv *priv = netdev_priv(net); 368 struct spi_device *spi = priv->spi; 369 370 if (priv->tx_skb || priv->tx_busy) { 371 dev_err(&spi->dev, "hard_xmit called while tx busy\n"); 372 return NETDEV_TX_BUSY; 373 } 374 375 if (can_dropped_invalid_skb(net, skb)) 376 return NETDEV_TX_OK; 377 378 netif_stop_queue(net); 379 priv->tx_skb = skb; 380 queue_work(priv->wq, &priv->tx_work); 381 382 return NETDEV_TX_OK; 383 } 384 385 static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode) 386 { 387 struct hi3110_priv *priv = netdev_priv(net); 388 389 switch (mode) { 390 case CAN_MODE_START: 391 hi3110_clean(net); 392 /* We have to delay work since SPI I/O may sleep */ 393 priv->can.state = CAN_STATE_ERROR_ACTIVE; 394 priv->restart_tx = 1; 395 if (priv->can.restart_ms == 0) 396 priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART; 397 queue_work(priv->wq, &priv->restart_work); 398 break; 399 default: 400 return -EOPNOTSUPP; 401 } 402 403 return 0; 404 } 405 406 static int hi3110_get_berr_counter(const struct net_device *net, 407 struct can_berr_counter *bec) 408 { 409 struct hi3110_priv *priv = netdev_priv(net); 410 struct spi_device *spi = priv->spi; 411 412 mutex_lock(&priv->hi3110_lock); 413 bec->txerr = hi3110_read(spi, HI3110_READ_TEC); 414 bec->rxerr = hi3110_read(spi, HI3110_READ_REC); 415 mutex_unlock(&priv->hi3110_lock); 416 417 return 0; 418 } 419 420 static int hi3110_set_normal_mode(struct spi_device *spi) 421 { 422 struct hi3110_priv *priv = spi_get_drvdata(spi); 423 u8 reg = 0; 424 425 hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR | 426 HI3110_INT_RXFIFO | HI3110_INT_TXCPLT); 427 428 /* Enable TX */ 429 hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN); 430 431 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 432 reg = HI3110_CTRL0_LOOPBACK_MODE; 433 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 434 reg = HI3110_CTRL0_MONITOR_MODE; 435 else 436 reg = HI3110_CTRL0_NORMAL_MODE; 437 438 hi3110_write(spi, HI3110_WRITE_CTRL0, reg); 439 440 /* Wait for the device to enter the mode */ 441 mdelay(HI3110_OST_DELAY_MS); 442 reg = hi3110_read(spi, HI3110_READ_CTRL0); 443 if ((reg & HI3110_CTRL0_MODE_MASK) != reg) 444 return -EBUSY; 445 446 priv->can.state = CAN_STATE_ERROR_ACTIVE; 447 return 0; 448 } 449 450 static int hi3110_do_set_bittiming(struct net_device *net) 451 { 452 struct hi3110_priv *priv = netdev_priv(net); 453 struct can_bittiming *bt = &priv->can.bittiming; 454 struct spi_device *spi = priv->spi; 455 456 hi3110_write(spi, HI3110_WRITE_BTR0, 457 ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) | 458 ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT)); 459 460 hi3110_write(spi, HI3110_WRITE_BTR1, 461 (priv->can.ctrlmode & 462 CAN_CTRLMODE_3_SAMPLES ? 463 HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) | 464 ((bt->phase_seg1 + bt->prop_seg - 1) 465 << HI3110_BTR1_TSEG1_SHIFT) | 466 ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT)); 467 468 dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n", 469 hi3110_read(spi, HI3110_READ_BTR0), 470 hi3110_read(spi, HI3110_READ_BTR1)); 471 472 return 0; 473 } 474 475 static int hi3110_setup(struct net_device *net) 476 { 477 hi3110_do_set_bittiming(net); 478 return 0; 479 } 480 481 static int hi3110_hw_reset(struct spi_device *spi) 482 { 483 u8 reg; 484 int ret; 485 486 /* Wait for oscillator startup timer after power up */ 487 mdelay(HI3110_OST_DELAY_MS); 488 489 ret = hi3110_cmd(spi, HI3110_MASTER_RESET); 490 if (ret) 491 return ret; 492 493 /* Wait for oscillator startup timer after reset */ 494 mdelay(HI3110_OST_DELAY_MS); 495 496 reg = hi3110_read(spi, HI3110_READ_CTRL0); 497 if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE) 498 return -ENODEV; 499 500 /* As per the datasheet it appears the error flags are 501 * not cleared on reset. Explicitly clear them by performing a read 502 */ 503 hi3110_read(spi, HI3110_READ_ERR); 504 505 return 0; 506 } 507 508 static int hi3110_hw_probe(struct spi_device *spi) 509 { 510 u8 statf; 511 512 hi3110_hw_reset(spi); 513 514 /* Confirm correct operation by checking against reset values 515 * in datasheet 516 */ 517 statf = hi3110_read(spi, HI3110_READ_STATF); 518 519 dev_dbg(&spi->dev, "statf: %02X\n", statf); 520 521 if (statf != 0x82) 522 return -ENODEV; 523 524 return 0; 525 } 526 527 static int hi3110_power_enable(struct regulator *reg, int enable) 528 { 529 if (IS_ERR_OR_NULL(reg)) 530 return 0; 531 532 if (enable) 533 return regulator_enable(reg); 534 else 535 return regulator_disable(reg); 536 } 537 538 static int hi3110_stop(struct net_device *net) 539 { 540 struct hi3110_priv *priv = netdev_priv(net); 541 struct spi_device *spi = priv->spi; 542 543 close_candev(net); 544 545 priv->force_quit = 1; 546 free_irq(spi->irq, priv); 547 destroy_workqueue(priv->wq); 548 priv->wq = NULL; 549 550 mutex_lock(&priv->hi3110_lock); 551 552 /* Disable transmit, interrupts and clear flags */ 553 hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0); 554 hi3110_write(spi, HI3110_WRITE_INTE, 0x0); 555 hi3110_read(spi, HI3110_READ_INTF); 556 557 hi3110_clean(net); 558 559 hi3110_hw_sleep(spi); 560 561 hi3110_power_enable(priv->transceiver, 0); 562 563 priv->can.state = CAN_STATE_STOPPED; 564 565 mutex_unlock(&priv->hi3110_lock); 566 567 return 0; 568 } 569 570 static void hi3110_tx_work_handler(struct work_struct *ws) 571 { 572 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 573 tx_work); 574 struct spi_device *spi = priv->spi; 575 struct net_device *net = priv->net; 576 struct can_frame *frame; 577 578 mutex_lock(&priv->hi3110_lock); 579 if (priv->tx_skb) { 580 if (priv->can.state == CAN_STATE_BUS_OFF) { 581 hi3110_clean(net); 582 } else { 583 frame = (struct can_frame *)priv->tx_skb->data; 584 hi3110_hw_tx(spi, frame); 585 priv->tx_busy = true; 586 can_put_echo_skb(priv->tx_skb, net, 0, 0); 587 priv->tx_skb = NULL; 588 } 589 } 590 mutex_unlock(&priv->hi3110_lock); 591 } 592 593 static void hi3110_restart_work_handler(struct work_struct *ws) 594 { 595 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv, 596 restart_work); 597 struct spi_device *spi = priv->spi; 598 struct net_device *net = priv->net; 599 600 mutex_lock(&priv->hi3110_lock); 601 if (priv->after_suspend) { 602 hi3110_hw_reset(spi); 603 hi3110_setup(net); 604 if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) { 605 hi3110_set_normal_mode(spi); 606 } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 607 netif_device_attach(net); 608 hi3110_clean(net); 609 hi3110_set_normal_mode(spi); 610 netif_wake_queue(net); 611 } else { 612 hi3110_hw_sleep(spi); 613 } 614 priv->after_suspend = 0; 615 priv->force_quit = 0; 616 } 617 618 if (priv->restart_tx) { 619 priv->restart_tx = 0; 620 hi3110_hw_reset(spi); 621 hi3110_setup(net); 622 hi3110_clean(net); 623 hi3110_set_normal_mode(spi); 624 netif_wake_queue(net); 625 } 626 mutex_unlock(&priv->hi3110_lock); 627 } 628 629 static irqreturn_t hi3110_can_ist(int irq, void *dev_id) 630 { 631 struct hi3110_priv *priv = dev_id; 632 struct spi_device *spi = priv->spi; 633 struct net_device *net = priv->net; 634 635 mutex_lock(&priv->hi3110_lock); 636 637 while (!priv->force_quit) { 638 enum can_state new_state; 639 u8 intf, eflag, statf; 640 641 while (!(HI3110_STAT_RXFMTY & 642 (statf = hi3110_read(spi, HI3110_READ_STATF)))) { 643 hi3110_hw_rx(spi); 644 } 645 646 intf = hi3110_read(spi, HI3110_READ_INTF); 647 eflag = hi3110_read(spi, HI3110_READ_ERR); 648 /* Update can state */ 649 if (eflag & HI3110_ERR_BUSOFF) 650 new_state = CAN_STATE_BUS_OFF; 651 else if (eflag & HI3110_ERR_PASSIVE_MASK) 652 new_state = CAN_STATE_ERROR_PASSIVE; 653 else if (statf & HI3110_STAT_ERRW) 654 new_state = CAN_STATE_ERROR_WARNING; 655 else 656 new_state = CAN_STATE_ERROR_ACTIVE; 657 658 if (new_state != priv->can.state) { 659 struct can_frame *cf; 660 struct sk_buff *skb; 661 enum can_state rx_state, tx_state; 662 u8 rxerr, txerr; 663 664 skb = alloc_can_err_skb(net, &cf); 665 if (!skb) 666 break; 667 668 txerr = hi3110_read(spi, HI3110_READ_TEC); 669 rxerr = hi3110_read(spi, HI3110_READ_REC); 670 cf->data[6] = txerr; 671 cf->data[7] = rxerr; 672 tx_state = txerr >= rxerr ? new_state : 0; 673 rx_state = txerr <= rxerr ? new_state : 0; 674 can_change_state(net, cf, tx_state, rx_state); 675 netif_rx(skb); 676 677 if (new_state == CAN_STATE_BUS_OFF) { 678 can_bus_off(net); 679 if (priv->can.restart_ms == 0) { 680 priv->force_quit = 1; 681 hi3110_hw_sleep(spi); 682 break; 683 } 684 } 685 } 686 687 /* Update bus errors */ 688 if ((intf & HI3110_INT_BUSERR) && 689 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 690 struct can_frame *cf; 691 struct sk_buff *skb; 692 693 /* Check for protocol errors */ 694 if (eflag & HI3110_ERR_PROTOCOL_MASK) { 695 skb = alloc_can_err_skb(net, &cf); 696 if (!skb) 697 break; 698 699 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 700 priv->can.can_stats.bus_error++; 701 priv->net->stats.rx_errors++; 702 if (eflag & HI3110_ERR_BITERR) 703 cf->data[2] |= CAN_ERR_PROT_BIT; 704 else if (eflag & HI3110_ERR_FRMERR) 705 cf->data[2] |= CAN_ERR_PROT_FORM; 706 else if (eflag & HI3110_ERR_STUFERR) 707 cf->data[2] |= CAN_ERR_PROT_STUFF; 708 else if (eflag & HI3110_ERR_CRCERR) 709 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 710 else if (eflag & HI3110_ERR_ACKERR) 711 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 712 713 cf->data[6] = hi3110_read(spi, HI3110_READ_TEC); 714 cf->data[7] = hi3110_read(spi, HI3110_READ_REC); 715 netdev_dbg(priv->net, "Bus Error\n"); 716 netif_rx(skb); 717 } 718 } 719 720 if (priv->tx_busy && statf & HI3110_STAT_TXMTY) { 721 net->stats.tx_packets++; 722 net->stats.tx_bytes += can_get_echo_skb(net, 0, NULL); 723 priv->tx_busy = false; 724 netif_wake_queue(net); 725 } 726 727 if (intf == 0) 728 break; 729 } 730 mutex_unlock(&priv->hi3110_lock); 731 return IRQ_HANDLED; 732 } 733 734 static int hi3110_open(struct net_device *net) 735 { 736 struct hi3110_priv *priv = netdev_priv(net); 737 struct spi_device *spi = priv->spi; 738 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH; 739 int ret; 740 741 ret = open_candev(net); 742 if (ret) 743 return ret; 744 745 mutex_lock(&priv->hi3110_lock); 746 hi3110_power_enable(priv->transceiver, 1); 747 748 priv->force_quit = 0; 749 priv->tx_skb = NULL; 750 priv->tx_busy = false; 751 752 ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist, 753 flags, DEVICE_NAME, priv); 754 if (ret) { 755 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); 756 goto out_close; 757 } 758 759 priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, 760 0); 761 if (!priv->wq) { 762 ret = -ENOMEM; 763 goto out_free_irq; 764 } 765 INIT_WORK(&priv->tx_work, hi3110_tx_work_handler); 766 INIT_WORK(&priv->restart_work, hi3110_restart_work_handler); 767 768 ret = hi3110_hw_reset(spi); 769 if (ret) 770 goto out_free_wq; 771 772 ret = hi3110_setup(net); 773 if (ret) 774 goto out_free_wq; 775 776 ret = hi3110_set_normal_mode(spi); 777 if (ret) 778 goto out_free_wq; 779 780 netif_wake_queue(net); 781 mutex_unlock(&priv->hi3110_lock); 782 783 return 0; 784 785 out_free_wq: 786 destroy_workqueue(priv->wq); 787 out_free_irq: 788 free_irq(spi->irq, priv); 789 hi3110_hw_sleep(spi); 790 out_close: 791 hi3110_power_enable(priv->transceiver, 0); 792 close_candev(net); 793 mutex_unlock(&priv->hi3110_lock); 794 return ret; 795 } 796 797 static const struct net_device_ops hi3110_netdev_ops = { 798 .ndo_open = hi3110_open, 799 .ndo_stop = hi3110_stop, 800 .ndo_start_xmit = hi3110_hard_start_xmit, 801 }; 802 803 static const struct of_device_id hi3110_of_match[] = { 804 { 805 .compatible = "holt,hi3110", 806 .data = (void *)CAN_HI3110_HI3110, 807 }, 808 { } 809 }; 810 MODULE_DEVICE_TABLE(of, hi3110_of_match); 811 812 static const struct spi_device_id hi3110_id_table[] = { 813 { 814 .name = "hi3110", 815 .driver_data = (kernel_ulong_t)CAN_HI3110_HI3110, 816 }, 817 { } 818 }; 819 MODULE_DEVICE_TABLE(spi, hi3110_id_table); 820 821 static int hi3110_can_probe(struct spi_device *spi) 822 { 823 struct device *dev = &spi->dev; 824 struct net_device *net; 825 struct hi3110_priv *priv; 826 const void *match; 827 struct clk *clk; 828 u32 freq; 829 int ret; 830 831 clk = devm_clk_get_optional(&spi->dev, NULL); 832 if (IS_ERR(clk)) 833 return dev_err_probe(dev, PTR_ERR(clk), "no CAN clock source defined\n"); 834 835 if (clk) { 836 freq = clk_get_rate(clk); 837 } else { 838 ret = device_property_read_u32(dev, "clock-frequency", &freq); 839 if (ret) 840 return dev_err_probe(dev, ret, "Failed to get clock-frequency!\n"); 841 } 842 843 /* Sanity check */ 844 if (freq > 40000000) 845 return -ERANGE; 846 847 /* Allocate can/net device */ 848 net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX); 849 if (!net) 850 return -ENOMEM; 851 852 ret = clk_prepare_enable(clk); 853 if (ret) 854 goto out_free; 855 856 net->netdev_ops = &hi3110_netdev_ops; 857 net->flags |= IFF_ECHO; 858 859 priv = netdev_priv(net); 860 priv->can.bittiming_const = &hi3110_bittiming_const; 861 priv->can.do_set_mode = hi3110_do_set_mode; 862 priv->can.do_get_berr_counter = hi3110_get_berr_counter; 863 priv->can.clock.freq = freq / 2; 864 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 865 CAN_CTRLMODE_LOOPBACK | 866 CAN_CTRLMODE_LISTENONLY | 867 CAN_CTRLMODE_BERR_REPORTING; 868 869 match = device_get_match_data(dev); 870 if (match) 871 priv->model = (enum hi3110_model)(uintptr_t)match; 872 else 873 priv->model = spi_get_device_id(spi)->driver_data; 874 priv->net = net; 875 priv->clk = clk; 876 877 spi_set_drvdata(spi, priv); 878 879 /* Configure the SPI bus */ 880 spi->bits_per_word = 8; 881 ret = spi_setup(spi); 882 if (ret) 883 goto out_clk; 884 885 priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); 886 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 887 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || 888 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { 889 ret = -EPROBE_DEFER; 890 goto out_clk; 891 } 892 893 ret = hi3110_power_enable(priv->power, 1); 894 if (ret) 895 goto out_clk; 896 897 priv->spi = spi; 898 mutex_init(&priv->hi3110_lock); 899 900 priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 901 GFP_KERNEL); 902 if (!priv->spi_tx_buf) { 903 ret = -ENOMEM; 904 goto error_probe; 905 } 906 priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN, 907 GFP_KERNEL); 908 909 if (!priv->spi_rx_buf) { 910 ret = -ENOMEM; 911 goto error_probe; 912 } 913 914 SET_NETDEV_DEV(net, &spi->dev); 915 916 ret = hi3110_hw_probe(spi); 917 if (ret) { 918 dev_err_probe(dev, ret, "Cannot initialize %x. Wrong wiring?\n", priv->model); 919 goto error_probe; 920 } 921 hi3110_hw_sleep(spi); 922 923 ret = register_candev(net); 924 if (ret) 925 goto error_probe; 926 927 netdev_info(net, "%x successfully initialized.\n", priv->model); 928 929 return 0; 930 931 error_probe: 932 hi3110_power_enable(priv->power, 0); 933 934 out_clk: 935 clk_disable_unprepare(clk); 936 937 out_free: 938 free_candev(net); 939 940 return dev_err_probe(dev, ret, "Probe failed\n"); 941 } 942 943 static void hi3110_can_remove(struct spi_device *spi) 944 { 945 struct hi3110_priv *priv = spi_get_drvdata(spi); 946 struct net_device *net = priv->net; 947 948 unregister_candev(net); 949 950 hi3110_power_enable(priv->power, 0); 951 952 clk_disable_unprepare(priv->clk); 953 954 free_candev(net); 955 } 956 957 static int __maybe_unused hi3110_can_suspend(struct device *dev) 958 { 959 struct spi_device *spi = to_spi_device(dev); 960 struct hi3110_priv *priv = spi_get_drvdata(spi); 961 struct net_device *net = priv->net; 962 963 priv->force_quit = 1; 964 disable_irq(spi->irq); 965 966 /* Note: at this point neither IST nor workqueues are running. 967 * open/stop cannot be called anyway so locking is not needed 968 */ 969 if (netif_running(net)) { 970 netif_device_detach(net); 971 972 hi3110_hw_sleep(spi); 973 hi3110_power_enable(priv->transceiver, 0); 974 priv->after_suspend = HI3110_AFTER_SUSPEND_UP; 975 } else { 976 priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN; 977 } 978 979 if (!IS_ERR_OR_NULL(priv->power)) { 980 regulator_disable(priv->power); 981 priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER; 982 } 983 984 return 0; 985 } 986 987 static int __maybe_unused hi3110_can_resume(struct device *dev) 988 { 989 struct spi_device *spi = to_spi_device(dev); 990 struct hi3110_priv *priv = spi_get_drvdata(spi); 991 992 if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER) 993 hi3110_power_enable(priv->power, 1); 994 995 if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) { 996 hi3110_power_enable(priv->transceiver, 1); 997 queue_work(priv->wq, &priv->restart_work); 998 } else { 999 priv->after_suspend = 0; 1000 } 1001 1002 priv->force_quit = 0; 1003 enable_irq(spi->irq); 1004 return 0; 1005 } 1006 1007 static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume); 1008 1009 static struct spi_driver hi3110_can_driver = { 1010 .driver = { 1011 .name = DEVICE_NAME, 1012 .of_match_table = hi3110_of_match, 1013 .pm = &hi3110_can_pm_ops, 1014 }, 1015 .id_table = hi3110_id_table, 1016 .probe = hi3110_can_probe, 1017 .remove = hi3110_can_remove, 1018 }; 1019 1020 module_spi_driver(hi3110_can_driver); 1021 1022 MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>"); 1023 MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>"); 1024 MODULE_DESCRIPTION("Holt HI-3110 CAN driver"); 1025 MODULE_LICENSE("GPL v2"); 1026