1 /* 2 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su> 3 * 4 * Derived from the ems_pci.c driver: 5 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 6 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> 7 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/netdevice.h> 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 #include <linux/pci.h> 29 #include <linux/can/dev.h> 30 #include <linux/io.h> 31 32 #include "sja1000.h" 33 34 #define DRV_NAME "sja1000_plx_pci" 35 36 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>"); 37 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with " 38 "the SJA1000 chips"); 39 MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, " 40 "Adlink PCI-7841/cPCI-7841 SE, " 41 "Marathon CAN-bus-PCI, " 42 "Marathon CAN-bus-PCIe, " 43 "TEWS TECHNOLOGIES TPMC810, " 44 "esd CAN-PCI/CPCI/PCI104/200, " 45 "esd CAN-PCI/PMC/266, " 46 "esd CAN-PCIe/2000, " 47 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001), " 48 "IXXAT PC-I 04/PCI, " 49 "ELCUS CAN-200-PCI, " 50 "ASEM DUAL CAN-RAW") 51 MODULE_LICENSE("GPL v2"); 52 53 #define PLX_PCI_MAX_CHAN 2 54 55 struct plx_pci_card { 56 int channels; /* detected channels count */ 57 struct net_device *net_dev[PLX_PCI_MAX_CHAN]; 58 void __iomem *conf_addr; 59 60 /* Pointer to device-dependent reset function */ 61 void (*reset_func)(struct pci_dev *pdev); 62 }; 63 64 #define PLX_PCI_CAN_CLOCK (16000000 / 2) 65 66 /* PLX9030/9050/9052 registers */ 67 #define PLX_INTCSR 0x4c /* Interrupt Control/Status */ 68 #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response, 69 * Serial EEPROM, and Initialization 70 * Control register 71 */ 72 73 #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */ 74 #define PLX_LINT1_POL (1 << 1) /* Local interrupt 1 polarity */ 75 #define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */ 76 #define PLX_LINT2_POL (1 << 4) /* Local interrupt 2 polarity */ 77 #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */ 78 #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */ 79 80 /* PLX9056 registers */ 81 #define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */ 82 #define PLX9056_CNTRL 0x6c /* Control / Software Reset */ 83 84 #define PLX9056_LINTI (1 << 11) 85 #define PLX9056_PCI_INT_EN (1 << 8) 86 #define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */ 87 88 /* 89 * The board configuration is probably following: 90 * RX1 is connected to ground. 91 * TX1 is not connected. 92 * CLKO is not connected. 93 * Setting the OCR register to 0xDA is a good idea. 94 * This means normal output mode, push-pull and the correct polarity. 95 */ 96 #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) 97 98 /* OCR setting for ASEM Dual CAN raw */ 99 #define ASEM_PCI_OCR 0xfe 100 101 /* 102 * In the CDR register, you should set CBP to 1. 103 * You will probably also want to set the clock divider value to 7 104 * (meaning direct oscillator output) because the second SJA1000 chip 105 * is driven by the first one CLKOUT output. 106 */ 107 #define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 108 109 /* SJA1000 Control Register in the BasicCAN Mode */ 110 #define REG_CR 0x00 111 112 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/ 113 #define REG_CR_BASICCAN_INITIAL 0x21 114 #define REG_CR_BASICCAN_INITIAL_MASK 0xa1 115 #define REG_SR_BASICCAN_INITIAL 0x0c 116 #define REG_IR_BASICCAN_INITIAL 0xe0 117 118 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/ 119 #define REG_MOD_PELICAN_INITIAL 0x01 120 #define REG_SR_PELICAN_INITIAL 0x3c 121 #define REG_IR_PELICAN_INITIAL 0x00 122 123 #define ADLINK_PCI_VENDOR_ID 0x144A 124 #define ADLINK_PCI_DEVICE_ID 0x7841 125 126 #define ESD_PCI_SUB_SYS_ID_PCI200 0x0004 127 #define ESD_PCI_SUB_SYS_ID_PCI266 0x0009 128 #define ESD_PCI_SUB_SYS_ID_PMC266 0x000e 129 #define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b 130 #define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200 131 #define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501 132 133 #define CAN200PCI_DEVICE_ID 0x9030 134 #define CAN200PCI_VENDOR_ID 0x10b5 135 #define CAN200PCI_SUB_DEVICE_ID 0x0301 136 #define CAN200PCI_SUB_VENDOR_ID 0xe1c5 137 138 #define IXXAT_PCI_VENDOR_ID 0x10b5 139 #define IXXAT_PCI_DEVICE_ID 0x9050 140 #define IXXAT_PCI_SUB_SYS_ID 0x2540 141 142 #define MARATHON_PCI_DEVICE_ID 0x2715 143 #define MARATHON_PCIE_DEVICE_ID 0x3432 144 145 #define TEWS_PCI_VENDOR_ID 0x1498 146 #define TEWS_PCI_DEVICE_ID_TMPC810 0x032A 147 148 #define CTI_PCI_VENDOR_ID 0x12c4 149 #define CTI_PCI_DEVICE_ID_CRG001 0x0900 150 151 #define MOXA_PCI_VENDOR_ID 0x1393 152 #define MOXA_PCI_DEVICE_ID 0x0100 153 154 #define ASEM_RAW_CAN_VENDOR_ID 0x10b5 155 #define ASEM_RAW_CAN_DEVICE_ID 0x9030 156 #define ASEM_RAW_CAN_SUB_VENDOR_ID 0x3000 157 #define ASEM_RAW_CAN_SUB_DEVICE_ID 0x1001 158 #define ASEM_RAW_CAN_SUB_DEVICE_ID_BIS 0x1002 159 #define ASEM_RAW_CAN_RST_REGISTER 0x54 160 #define ASEM_RAW_CAN_RST_MASK_CAN1 0x20 161 #define ASEM_RAW_CAN_RST_MASK_CAN2 0x04 162 163 static void plx_pci_reset_common(struct pci_dev *pdev); 164 static void plx9056_pci_reset_common(struct pci_dev *pdev); 165 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev); 166 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev); 167 static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev); 168 169 struct plx_pci_channel_map { 170 u32 bar; 171 u32 offset; 172 u32 size; /* 0x00 - auto, e.g. length of entire bar */ 173 }; 174 175 struct plx_pci_card_info { 176 const char *name; 177 int channel_count; 178 u32 can_clock; 179 u8 ocr; /* output control register */ 180 u8 cdr; /* clock divider register */ 181 182 /* Parameters for mapping local configuration space */ 183 struct plx_pci_channel_map conf_map; 184 185 /* Parameters for mapping the SJA1000 chips */ 186 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN]; 187 188 /* Pointer to device-dependent reset function */ 189 void (*reset_func)(struct pci_dev *pdev); 190 }; 191 192 static struct plx_pci_card_info plx_pci_card_info_adlink = { 193 "Adlink PCI-7841/cPCI-7841", 2, 194 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 195 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 196 &plx_pci_reset_common 197 /* based on PLX9052 */ 198 }; 199 200 static struct plx_pci_card_info plx_pci_card_info_adlink_se = { 201 "Adlink PCI-7841/cPCI-7841 SE", 2, 202 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 203 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 204 &plx_pci_reset_common 205 /* based on PLX9052 */ 206 }; 207 208 static struct plx_pci_card_info plx_pci_card_info_esd200 = { 209 "esd CAN-PCI/CPCI/PCI104/200", 2, 210 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 211 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 212 &plx_pci_reset_common 213 /* based on PLX9030/9050 */ 214 }; 215 216 static struct plx_pci_card_info plx_pci_card_info_esd266 = { 217 "esd CAN-PCI/PMC/266", 2, 218 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 219 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 220 &plx9056_pci_reset_common 221 /* based on PLX9056 */ 222 }; 223 224 static struct plx_pci_card_info plx_pci_card_info_esd2000 = { 225 "esd CAN-PCIe/2000", 2, 226 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 227 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 228 &plx9056_pci_reset_common 229 /* based on PEX8311 */ 230 }; 231 232 static struct plx_pci_card_info plx_pci_card_info_ixxat = { 233 "IXXAT PC-I 04/PCI", 2, 234 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 235 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} }, 236 &plx_pci_reset_common 237 /* based on PLX9050 */ 238 }; 239 240 static struct plx_pci_card_info plx_pci_card_info_marathon_pci = { 241 "Marathon CAN-bus-PCI", 2, 242 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 243 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, 244 &plx_pci_reset_marathon_pci 245 /* based on PLX9052 */ 246 }; 247 248 static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = { 249 "Marathon CAN-bus-PCIe", 2, 250 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 251 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {3, 0x80, 0x00} }, 252 &plx_pci_reset_marathon_pcie 253 /* based on PEX8311 */ 254 }; 255 256 static struct plx_pci_card_info plx_pci_card_info_tews = { 257 "TEWS TECHNOLOGIES TPMC810", 2, 258 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 259 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 260 &plx_pci_reset_common 261 /* based on PLX9030 */ 262 }; 263 264 static struct plx_pci_card_info plx_pci_card_info_cti = { 265 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2, 266 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 267 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 268 &plx_pci_reset_common 269 /* based on PLX9030 */ 270 }; 271 272 static struct plx_pci_card_info plx_pci_card_info_elcus = { 273 "Eclus CAN-200-PCI", 2, 274 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 275 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} }, 276 &plx_pci_reset_common 277 /* based on PLX9030 */ 278 }; 279 280 static struct plx_pci_card_info plx_pci_card_info_moxa = { 281 "MOXA", 2, 282 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 283 {0, 0x00, 0x00}, { {0, 0x00, 0x80}, {1, 0x00, 0x80} }, 284 &plx_pci_reset_common 285 /* based on PLX9052 */ 286 }; 287 288 static struct plx_pci_card_info plx_pci_card_info_asem_dual_can = { 289 "ASEM Dual CAN raw PCI", 2, 290 PLX_PCI_CAN_CLOCK, ASEM_PCI_OCR, PLX_PCI_CDR, 291 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, 292 &plx_pci_reset_asem_dual_can_raw 293 /* based on PLX9030 */ 294 }; 295 296 static const struct pci_device_id plx_pci_tbl[] = { 297 { 298 /* Adlink PCI-7841/cPCI-7841 */ 299 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 300 PCI_ANY_ID, PCI_ANY_ID, 301 PCI_CLASS_NETWORK_OTHER << 8, ~0, 302 (kernel_ulong_t)&plx_pci_card_info_adlink 303 }, 304 { 305 /* Adlink PCI-7841/cPCI-7841 SE */ 306 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 307 PCI_ANY_ID, PCI_ANY_ID, 308 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0, 309 (kernel_ulong_t)&plx_pci_card_info_adlink_se 310 }, 311 { 312 /* esd CAN-PCI/200 */ 313 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 314 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200, 315 0, 0, 316 (kernel_ulong_t)&plx_pci_card_info_esd200 317 }, 318 { 319 /* esd CAN-CPCI/200 */ 320 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 321 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200, 322 0, 0, 323 (kernel_ulong_t)&plx_pci_card_info_esd200 324 }, 325 { 326 /* esd CAN-PCI104/200 */ 327 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 328 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200, 329 0, 0, 330 (kernel_ulong_t)&plx_pci_card_info_esd200 331 }, 332 { 333 /* esd CAN-PCI/266 */ 334 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 335 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266, 336 0, 0, 337 (kernel_ulong_t)&plx_pci_card_info_esd266 338 }, 339 { 340 /* esd CAN-PMC/266 */ 341 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 342 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266, 343 0, 0, 344 (kernel_ulong_t)&plx_pci_card_info_esd266 345 }, 346 { 347 /* esd CAN-PCIE/2000 */ 348 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 349 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000, 350 0, 0, 351 (kernel_ulong_t)&plx_pci_card_info_esd2000 352 }, 353 { 354 /* IXXAT PC-I 04/PCI card */ 355 IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID, 356 PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID, 357 0, 0, 358 (kernel_ulong_t)&plx_pci_card_info_ixxat 359 }, 360 { 361 /* Marathon CAN-bus-PCI card */ 362 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID, 363 PCI_ANY_ID, PCI_ANY_ID, 364 0, 0, 365 (kernel_ulong_t)&plx_pci_card_info_marathon_pci 366 }, 367 { 368 /* Marathon CAN-bus-PCIe card */ 369 PCI_VENDOR_ID_PLX, MARATHON_PCIE_DEVICE_ID, 370 PCI_ANY_ID, PCI_ANY_ID, 371 0, 0, 372 (kernel_ulong_t)&plx_pci_card_info_marathon_pcie 373 }, 374 { 375 /* TEWS TECHNOLOGIES TPMC810 card */ 376 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810, 377 PCI_ANY_ID, PCI_ANY_ID, 378 0, 0, 379 (kernel_ulong_t)&plx_pci_card_info_tews 380 }, 381 { 382 /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */ 383 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 384 CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001, 385 0, 0, 386 (kernel_ulong_t)&plx_pci_card_info_cti 387 }, 388 { 389 /* Elcus CAN-200-PCI */ 390 CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID, 391 CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID, 392 0, 0, 393 (kernel_ulong_t)&plx_pci_card_info_elcus 394 }, 395 { 396 /* moxa */ 397 MOXA_PCI_VENDOR_ID, MOXA_PCI_DEVICE_ID, 398 PCI_ANY_ID, PCI_ANY_ID, 399 0, 0, 400 (kernel_ulong_t)&plx_pci_card_info_moxa 401 }, 402 { 403 /* ASEM Dual CAN raw */ 404 ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID, 405 ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID, 406 0, 0, 407 (kernel_ulong_t)&plx_pci_card_info_asem_dual_can 408 }, 409 { 410 /* ASEM Dual CAN raw -new model */ 411 ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID, 412 ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID_BIS, 413 0, 0, 414 (kernel_ulong_t)&plx_pci_card_info_asem_dual_can 415 }, 416 { 0,} 417 }; 418 MODULE_DEVICE_TABLE(pci, plx_pci_tbl); 419 420 static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port) 421 { 422 return ioread8(priv->reg_base + port); 423 } 424 425 static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) 426 { 427 iowrite8(val, priv->reg_base + port); 428 } 429 430 /* 431 * Check if a CAN controller is present at the specified location 432 * by trying to switch 'em from the Basic mode into the PeliCAN mode. 433 * Also check states of some registers in reset mode. 434 */ 435 static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) 436 { 437 int flag = 0; 438 439 /* 440 * Check registers after hardware reset (the Basic mode) 441 * See states on p. 10 of the Datasheet. 442 */ 443 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == 444 REG_CR_BASICCAN_INITIAL && 445 (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) && 446 (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL)) 447 flag = 1; 448 449 /* Bring the SJA1000 into the PeliCAN mode*/ 450 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); 451 452 /* 453 * Check registers after reset in the PeliCAN mode. 454 * See states on p. 23 of the Datasheet. 455 */ 456 if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL && 457 priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL && 458 priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL) 459 return flag; 460 461 return 0; 462 } 463 464 /* 465 * PLX9030/50/52 software reset 466 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired). 467 * For most cards it's enough for reset the SJA1000 chips. 468 */ 469 static void plx_pci_reset_common(struct pci_dev *pdev) 470 { 471 struct plx_pci_card *card = pci_get_drvdata(pdev); 472 u32 cntrl; 473 474 cntrl = ioread32(card->conf_addr + PLX_CNTRL); 475 cntrl |= PLX_PCI_RESET; 476 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 477 udelay(100); 478 cntrl ^= PLX_PCI_RESET; 479 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 480 }; 481 482 /* 483 * PLX9056 software reset 484 * Assert LRESET# and reset device(s) on the Local Bus (if wired). 485 */ 486 static void plx9056_pci_reset_common(struct pci_dev *pdev) 487 { 488 struct plx_pci_card *card = pci_get_drvdata(pdev); 489 u32 cntrl; 490 491 /* issue a local bus reset */ 492 cntrl = ioread32(card->conf_addr + PLX9056_CNTRL); 493 cntrl |= PLX_PCI_RESET; 494 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 495 udelay(100); 496 cntrl ^= PLX_PCI_RESET; 497 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 498 499 /* reload local configuration from EEPROM */ 500 cntrl |= PLX9056_PCI_RCR; 501 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 502 503 /* 504 * There is no safe way to poll for the end 505 * of reconfiguration process. Waiting for 10ms 506 * is safe. 507 */ 508 mdelay(10); 509 510 cntrl ^= PLX9056_PCI_RCR; 511 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 512 }; 513 514 /* Special reset function for Marathon CAN-bus-PCI card */ 515 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev) 516 { 517 void __iomem *reset_addr; 518 int i; 519 static const int reset_bar[2] = {3, 5}; 520 521 plx_pci_reset_common(pdev); 522 523 for (i = 0; i < 2; i++) { 524 reset_addr = pci_iomap(pdev, reset_bar[i], 0); 525 if (!reset_addr) { 526 dev_err(&pdev->dev, "Failed to remap reset " 527 "space %d (BAR%d)\n", i, reset_bar[i]); 528 } else { 529 /* reset the SJA1000 chip */ 530 iowrite8(0x1, reset_addr); 531 udelay(100); 532 pci_iounmap(pdev, reset_addr); 533 } 534 } 535 } 536 537 /* Special reset function for Marathon CAN-bus-PCIe card */ 538 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev) 539 { 540 void __iomem *addr; 541 void __iomem *reset_addr; 542 int i; 543 544 plx9056_pci_reset_common(pdev); 545 546 for (i = 0; i < 2; i++) { 547 struct plx_pci_channel_map *chan_map = 548 &plx_pci_card_info_marathon_pcie.chan_map_tbl[i]; 549 addr = pci_iomap(pdev, chan_map->bar, chan_map->size); 550 if (!addr) { 551 dev_err(&pdev->dev, "Failed to remap reset " 552 "space %d (BAR%d)\n", i, chan_map->bar); 553 } else { 554 /* reset the SJA1000 chip */ 555 #define MARATHON_PCIE_RESET_OFFSET 32 556 reset_addr = addr + chan_map->offset + 557 MARATHON_PCIE_RESET_OFFSET; 558 iowrite8(0x1, reset_addr); 559 udelay(100); 560 pci_iounmap(pdev, addr); 561 } 562 } 563 } 564 565 /* Special reset function for ASEM Dual CAN raw card */ 566 static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev) 567 { 568 void __iomem *bar0_addr; 569 u8 tmpval; 570 571 plx_pci_reset_common(pdev); 572 573 bar0_addr = pci_iomap(pdev, 0, 0); 574 if (!bar0_addr) { 575 dev_err(&pdev->dev, "Failed to remap reset space 0 (BAR0)\n"); 576 return; 577 } 578 579 /* reset the two SJA1000 chips */ 580 tmpval = ioread8(bar0_addr + ASEM_RAW_CAN_RST_REGISTER); 581 tmpval &= ~(ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2); 582 iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER); 583 usleep_range(300, 400); 584 tmpval |= ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2; 585 iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER); 586 usleep_range(300, 400); 587 pci_iounmap(pdev, bar0_addr); 588 } 589 590 static void plx_pci_del_card(struct pci_dev *pdev) 591 { 592 struct plx_pci_card *card = pci_get_drvdata(pdev); 593 struct net_device *dev; 594 struct sja1000_priv *priv; 595 int i = 0; 596 597 for (i = 0; i < PLX_PCI_MAX_CHAN; i++) { 598 dev = card->net_dev[i]; 599 if (!dev) 600 continue; 601 602 dev_info(&pdev->dev, "Removing %s\n", dev->name); 603 unregister_sja1000dev(dev); 604 priv = netdev_priv(dev); 605 if (priv->reg_base) 606 pci_iounmap(pdev, priv->reg_base); 607 free_sja1000dev(dev); 608 } 609 610 card->reset_func(pdev); 611 612 /* 613 * Disable interrupts from PCI-card and disable local 614 * interrupts 615 */ 616 if (pdev->device != PCI_DEVICE_ID_PLX_9056 && 617 pdev->device != MARATHON_PCIE_DEVICE_ID) 618 iowrite32(0x0, card->conf_addr + PLX_INTCSR); 619 else 620 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR); 621 622 if (card->conf_addr) 623 pci_iounmap(pdev, card->conf_addr); 624 625 kfree(card); 626 627 pci_disable_device(pdev); 628 } 629 630 /* 631 * Probe PLX90xx based device for the SJA1000 chips and register each 632 * available CAN channel to SJA1000 Socket-CAN subsystem. 633 */ 634 static int plx_pci_add_card(struct pci_dev *pdev, 635 const struct pci_device_id *ent) 636 { 637 struct sja1000_priv *priv; 638 struct net_device *dev; 639 struct plx_pci_card *card; 640 struct plx_pci_card_info *ci; 641 int err, i; 642 u32 val; 643 void __iomem *addr; 644 645 ci = (struct plx_pci_card_info *)ent->driver_data; 646 647 if (pci_enable_device(pdev) < 0) { 648 dev_err(&pdev->dev, "Failed to enable PCI device\n"); 649 return -ENODEV; 650 } 651 652 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n", 653 ci->name, PCI_SLOT(pdev->devfn)); 654 655 /* Allocate card structures to hold addresses, ... */ 656 card = kzalloc(sizeof(*card), GFP_KERNEL); 657 if (!card) { 658 pci_disable_device(pdev); 659 return -ENOMEM; 660 } 661 662 pci_set_drvdata(pdev, card); 663 664 card->channels = 0; 665 666 /* Remap PLX90xx configuration space */ 667 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size); 668 if (!addr) { 669 err = -ENOMEM; 670 dev_err(&pdev->dev, "Failed to remap configuration space " 671 "(BAR%d)\n", ci->conf_map.bar); 672 goto failure_cleanup; 673 } 674 card->conf_addr = addr + ci->conf_map.offset; 675 676 ci->reset_func(pdev); 677 card->reset_func = ci->reset_func; 678 679 /* Detect available channels */ 680 for (i = 0; i < ci->channel_count; i++) { 681 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i]; 682 683 dev = alloc_sja1000dev(0); 684 if (!dev) { 685 err = -ENOMEM; 686 goto failure_cleanup; 687 } 688 689 card->net_dev[i] = dev; 690 priv = netdev_priv(dev); 691 priv->priv = card; 692 priv->irq_flags = IRQF_SHARED; 693 694 dev->irq = pdev->irq; 695 696 /* 697 * Remap IO space of the SJA1000 chips 698 * This is device-dependent mapping 699 */ 700 addr = pci_iomap(pdev, cm->bar, cm->size); 701 if (!addr) { 702 err = -ENOMEM; 703 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar); 704 goto failure_cleanup; 705 } 706 707 priv->reg_base = addr + cm->offset; 708 priv->read_reg = plx_pci_read_reg; 709 priv->write_reg = plx_pci_write_reg; 710 711 /* Check if channel is present */ 712 if (plx_pci_check_sja1000(priv)) { 713 priv->can.clock.freq = ci->can_clock; 714 priv->ocr = ci->ocr; 715 priv->cdr = ci->cdr; 716 717 SET_NETDEV_DEV(dev, &pdev->dev); 718 dev->dev_id = i; 719 720 /* Register SJA1000 device */ 721 err = register_sja1000dev(dev); 722 if (err) { 723 dev_err(&pdev->dev, "Registering device failed " 724 "(err=%d)\n", err); 725 goto failure_cleanup; 726 } 727 728 card->channels++; 729 730 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d " 731 "registered as %s\n", i + 1, priv->reg_base, 732 dev->irq, dev->name); 733 } else { 734 dev_err(&pdev->dev, "Channel #%d not detected\n", 735 i + 1); 736 free_sja1000dev(dev); 737 card->net_dev[i] = NULL; 738 } 739 } 740 741 if (!card->channels) { 742 err = -ENODEV; 743 goto failure_cleanup; 744 } 745 746 /* 747 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1, 748 * Local_2 interrupts from the SJA1000 chips 749 */ 750 if (pdev->device != PCI_DEVICE_ID_PLX_9056 && 751 pdev->device != MARATHON_PCIE_DEVICE_ID) { 752 val = ioread32(card->conf_addr + PLX_INTCSR); 753 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH) 754 val |= PLX_LINT1_EN | PLX_PCI_INT_EN; 755 else 756 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN; 757 iowrite32(val, card->conf_addr + PLX_INTCSR); 758 } else { 759 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN, 760 card->conf_addr + PLX9056_INTCSR); 761 } 762 return 0; 763 764 failure_cleanup: 765 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err); 766 767 plx_pci_del_card(pdev); 768 769 return err; 770 } 771 772 static struct pci_driver plx_pci_driver = { 773 .name = DRV_NAME, 774 .id_table = plx_pci_tbl, 775 .probe = plx_pci_add_card, 776 .remove = plx_pci_del_card, 777 }; 778 779 module_pci_driver(plx_pci_driver); 780