1 /* 2 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su> 3 * 4 * Derived from the ems_pci.c driver: 5 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 6 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> 7 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/netdevice.h> 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 #include <linux/pci.h> 29 #include <linux/can/dev.h> 30 #include <linux/io.h> 31 32 #include "sja1000.h" 33 34 #define DRV_NAME "sja1000_plx_pci" 35 36 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>"); 37 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with " 38 "the SJA1000 chips"); 39 MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, " 40 "Adlink PCI-7841/cPCI-7841 SE, " 41 "Marathon CAN-bus-PCI, " 42 "Marathon CAN-bus-PCIe, " 43 "TEWS TECHNOLOGIES TPMC810, " 44 "esd CAN-PCI/CPCI/PCI104/200, " 45 "esd CAN-PCI/PMC/266, " 46 "esd CAN-PCIe/2000, " 47 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001), " 48 "IXXAT PC-I 04/PCI, " 49 "ELCUS CAN-200-PCI") 50 MODULE_LICENSE("GPL v2"); 51 52 #define PLX_PCI_MAX_CHAN 2 53 54 struct plx_pci_card { 55 int channels; /* detected channels count */ 56 struct net_device *net_dev[PLX_PCI_MAX_CHAN]; 57 void __iomem *conf_addr; 58 59 /* Pointer to device-dependent reset function */ 60 void (*reset_func)(struct pci_dev *pdev); 61 }; 62 63 #define PLX_PCI_CAN_CLOCK (16000000 / 2) 64 65 /* PLX9030/9050/9052 registers */ 66 #define PLX_INTCSR 0x4c /* Interrupt Control/Status */ 67 #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response, 68 * Serial EEPROM, and Initialization 69 * Control register 70 */ 71 72 #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */ 73 #define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */ 74 #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */ 75 #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */ 76 77 /* PLX9056 registers */ 78 #define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */ 79 #define PLX9056_CNTRL 0x6c /* Control / Software Reset */ 80 81 #define PLX9056_LINTI (1 << 11) 82 #define PLX9056_PCI_INT_EN (1 << 8) 83 #define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */ 84 85 /* 86 * The board configuration is probably following: 87 * RX1 is connected to ground. 88 * TX1 is not connected. 89 * CLKO is not connected. 90 * Setting the OCR register to 0xDA is a good idea. 91 * This means normal output mode, push-pull and the correct polarity. 92 */ 93 #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) 94 95 /* 96 * In the CDR register, you should set CBP to 1. 97 * You will probably also want to set the clock divider value to 7 98 * (meaning direct oscillator output) because the second SJA1000 chip 99 * is driven by the first one CLKOUT output. 100 */ 101 #define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 102 103 /* SJA1000 Control Register in the BasicCAN Mode */ 104 #define REG_CR 0x00 105 106 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/ 107 #define REG_CR_BASICCAN_INITIAL 0x21 108 #define REG_CR_BASICCAN_INITIAL_MASK 0xa1 109 #define REG_SR_BASICCAN_INITIAL 0x0c 110 #define REG_IR_BASICCAN_INITIAL 0xe0 111 112 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/ 113 #define REG_MOD_PELICAN_INITIAL 0x01 114 #define REG_SR_PELICAN_INITIAL 0x3c 115 #define REG_IR_PELICAN_INITIAL 0x00 116 117 #define ADLINK_PCI_VENDOR_ID 0x144A 118 #define ADLINK_PCI_DEVICE_ID 0x7841 119 120 #define ESD_PCI_SUB_SYS_ID_PCI200 0x0004 121 #define ESD_PCI_SUB_SYS_ID_PCI266 0x0009 122 #define ESD_PCI_SUB_SYS_ID_PMC266 0x000e 123 #define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b 124 #define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200 125 #define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501 126 127 #define CAN200PCI_DEVICE_ID 0x9030 128 #define CAN200PCI_VENDOR_ID 0x10b5 129 #define CAN200PCI_SUB_DEVICE_ID 0x0301 130 #define CAN200PCI_SUB_VENDOR_ID 0xe1c5 131 132 #define IXXAT_PCI_VENDOR_ID 0x10b5 133 #define IXXAT_PCI_DEVICE_ID 0x9050 134 #define IXXAT_PCI_SUB_SYS_ID 0x2540 135 136 #define MARATHON_PCI_DEVICE_ID 0x2715 137 #define MARATHON_PCIE_DEVICE_ID 0x3432 138 139 #define TEWS_PCI_VENDOR_ID 0x1498 140 #define TEWS_PCI_DEVICE_ID_TMPC810 0x032A 141 142 #define CTI_PCI_VENDOR_ID 0x12c4 143 #define CTI_PCI_DEVICE_ID_CRG001 0x0900 144 145 #define MOXA_PCI_VENDOR_ID 0x1393 146 #define MOXA_PCI_DEVICE_ID 0x0100 147 148 static void plx_pci_reset_common(struct pci_dev *pdev); 149 static void plx9056_pci_reset_common(struct pci_dev *pdev); 150 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev); 151 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev); 152 153 struct plx_pci_channel_map { 154 u32 bar; 155 u32 offset; 156 u32 size; /* 0x00 - auto, e.g. length of entire bar */ 157 }; 158 159 struct plx_pci_card_info { 160 const char *name; 161 int channel_count; 162 u32 can_clock; 163 u8 ocr; /* output control register */ 164 u8 cdr; /* clock divider register */ 165 166 /* Parameters for mapping local configuration space */ 167 struct plx_pci_channel_map conf_map; 168 169 /* Parameters for mapping the SJA1000 chips */ 170 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN]; 171 172 /* Pointer to device-dependent reset function */ 173 void (*reset_func)(struct pci_dev *pdev); 174 }; 175 176 static struct plx_pci_card_info plx_pci_card_info_adlink = { 177 "Adlink PCI-7841/cPCI-7841", 2, 178 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 179 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 180 &plx_pci_reset_common 181 /* based on PLX9052 */ 182 }; 183 184 static struct plx_pci_card_info plx_pci_card_info_adlink_se = { 185 "Adlink PCI-7841/cPCI-7841 SE", 2, 186 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 187 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 188 &plx_pci_reset_common 189 /* based on PLX9052 */ 190 }; 191 192 static struct plx_pci_card_info plx_pci_card_info_esd200 = { 193 "esd CAN-PCI/CPCI/PCI104/200", 2, 194 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 195 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 196 &plx_pci_reset_common 197 /* based on PLX9030/9050 */ 198 }; 199 200 static struct plx_pci_card_info plx_pci_card_info_esd266 = { 201 "esd CAN-PCI/PMC/266", 2, 202 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 203 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 204 &plx9056_pci_reset_common 205 /* based on PLX9056 */ 206 }; 207 208 static struct plx_pci_card_info plx_pci_card_info_esd2000 = { 209 "esd CAN-PCIe/2000", 2, 210 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 211 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 212 &plx9056_pci_reset_common 213 /* based on PEX8311 */ 214 }; 215 216 static struct plx_pci_card_info plx_pci_card_info_ixxat = { 217 "IXXAT PC-I 04/PCI", 2, 218 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 219 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} }, 220 &plx_pci_reset_common 221 /* based on PLX9050 */ 222 }; 223 224 static struct plx_pci_card_info plx_pci_card_info_marathon_pci = { 225 "Marathon CAN-bus-PCI", 2, 226 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 227 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, 228 &plx_pci_reset_marathon_pci 229 /* based on PLX9052 */ 230 }; 231 232 static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = { 233 "Marathon CAN-bus-PCIe", 2, 234 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 235 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {3, 0x80, 0x00} }, 236 &plx_pci_reset_marathon_pcie 237 /* based on PEX8311 */ 238 }; 239 240 static struct plx_pci_card_info plx_pci_card_info_tews = { 241 "TEWS TECHNOLOGIES TPMC810", 2, 242 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 243 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 244 &plx_pci_reset_common 245 /* based on PLX9030 */ 246 }; 247 248 static struct plx_pci_card_info plx_pci_card_info_cti = { 249 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2, 250 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 251 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 252 &plx_pci_reset_common 253 /* based on PLX9030 */ 254 }; 255 256 static struct plx_pci_card_info plx_pci_card_info_elcus = { 257 "Eclus CAN-200-PCI", 2, 258 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 259 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} }, 260 &plx_pci_reset_common 261 /* based on PLX9030 */ 262 }; 263 264 static struct plx_pci_card_info plx_pci_card_info_moxa = { 265 "MOXA", 2, 266 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 267 {0, 0x00, 0x00}, { {0, 0x00, 0x80}, {1, 0x00, 0x80} }, 268 &plx_pci_reset_common 269 /* based on PLX9052 */ 270 }; 271 272 static const struct pci_device_id plx_pci_tbl[] = { 273 { 274 /* Adlink PCI-7841/cPCI-7841 */ 275 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 276 PCI_ANY_ID, PCI_ANY_ID, 277 PCI_CLASS_NETWORK_OTHER << 8, ~0, 278 (kernel_ulong_t)&plx_pci_card_info_adlink 279 }, 280 { 281 /* Adlink PCI-7841/cPCI-7841 SE */ 282 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID, 283 PCI_ANY_ID, PCI_ANY_ID, 284 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0, 285 (kernel_ulong_t)&plx_pci_card_info_adlink_se 286 }, 287 { 288 /* esd CAN-PCI/200 */ 289 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 290 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200, 291 0, 0, 292 (kernel_ulong_t)&plx_pci_card_info_esd200 293 }, 294 { 295 /* esd CAN-CPCI/200 */ 296 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 297 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200, 298 0, 0, 299 (kernel_ulong_t)&plx_pci_card_info_esd200 300 }, 301 { 302 /* esd CAN-PCI104/200 */ 303 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 304 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200, 305 0, 0, 306 (kernel_ulong_t)&plx_pci_card_info_esd200 307 }, 308 { 309 /* esd CAN-PCI/266 */ 310 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 311 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266, 312 0, 0, 313 (kernel_ulong_t)&plx_pci_card_info_esd266 314 }, 315 { 316 /* esd CAN-PMC/266 */ 317 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 318 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266, 319 0, 0, 320 (kernel_ulong_t)&plx_pci_card_info_esd266 321 }, 322 { 323 /* esd CAN-PCIE/2000 */ 324 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056, 325 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000, 326 0, 0, 327 (kernel_ulong_t)&plx_pci_card_info_esd2000 328 }, 329 { 330 /* IXXAT PC-I 04/PCI card */ 331 IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID, 332 PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID, 333 0, 0, 334 (kernel_ulong_t)&plx_pci_card_info_ixxat 335 }, 336 { 337 /* Marathon CAN-bus-PCI card */ 338 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID, 339 PCI_ANY_ID, PCI_ANY_ID, 340 0, 0, 341 (kernel_ulong_t)&plx_pci_card_info_marathon_pci 342 }, 343 { 344 /* Marathon CAN-bus-PCIe card */ 345 PCI_VENDOR_ID_PLX, MARATHON_PCIE_DEVICE_ID, 346 PCI_ANY_ID, PCI_ANY_ID, 347 0, 0, 348 (kernel_ulong_t)&plx_pci_card_info_marathon_pcie 349 }, 350 { 351 /* TEWS TECHNOLOGIES TPMC810 card */ 352 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810, 353 PCI_ANY_ID, PCI_ANY_ID, 354 0, 0, 355 (kernel_ulong_t)&plx_pci_card_info_tews 356 }, 357 { 358 /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */ 359 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 360 CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001, 361 0, 0, 362 (kernel_ulong_t)&plx_pci_card_info_cti 363 }, 364 { 365 /* Elcus CAN-200-PCI */ 366 CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID, 367 CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID, 368 0, 0, 369 (kernel_ulong_t)&plx_pci_card_info_elcus 370 }, 371 { 372 /* moxa */ 373 MOXA_PCI_VENDOR_ID, MOXA_PCI_DEVICE_ID, 374 PCI_ANY_ID, PCI_ANY_ID, 375 0, 0, 376 (kernel_ulong_t)&plx_pci_card_info_moxa 377 }, 378 { 0,} 379 }; 380 MODULE_DEVICE_TABLE(pci, plx_pci_tbl); 381 382 static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port) 383 { 384 return ioread8(priv->reg_base + port); 385 } 386 387 static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) 388 { 389 iowrite8(val, priv->reg_base + port); 390 } 391 392 /* 393 * Check if a CAN controller is present at the specified location 394 * by trying to switch 'em from the Basic mode into the PeliCAN mode. 395 * Also check states of some registers in reset mode. 396 */ 397 static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) 398 { 399 int flag = 0; 400 401 /* 402 * Check registers after hardware reset (the Basic mode) 403 * See states on p. 10 of the Datasheet. 404 */ 405 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == 406 REG_CR_BASICCAN_INITIAL && 407 (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) && 408 (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL)) 409 flag = 1; 410 411 /* Bring the SJA1000 into the PeliCAN mode*/ 412 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); 413 414 /* 415 * Check registers after reset in the PeliCAN mode. 416 * See states on p. 23 of the Datasheet. 417 */ 418 if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL && 419 priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL && 420 priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL) 421 return flag; 422 423 return 0; 424 } 425 426 /* 427 * PLX9030/50/52 software reset 428 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired). 429 * For most cards it's enough for reset the SJA1000 chips. 430 */ 431 static void plx_pci_reset_common(struct pci_dev *pdev) 432 { 433 struct plx_pci_card *card = pci_get_drvdata(pdev); 434 u32 cntrl; 435 436 cntrl = ioread32(card->conf_addr + PLX_CNTRL); 437 cntrl |= PLX_PCI_RESET; 438 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 439 udelay(100); 440 cntrl ^= PLX_PCI_RESET; 441 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 442 }; 443 444 /* 445 * PLX9056 software reset 446 * Assert LRESET# and reset device(s) on the Local Bus (if wired). 447 */ 448 static void plx9056_pci_reset_common(struct pci_dev *pdev) 449 { 450 struct plx_pci_card *card = pci_get_drvdata(pdev); 451 u32 cntrl; 452 453 /* issue a local bus reset */ 454 cntrl = ioread32(card->conf_addr + PLX9056_CNTRL); 455 cntrl |= PLX_PCI_RESET; 456 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 457 udelay(100); 458 cntrl ^= PLX_PCI_RESET; 459 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 460 461 /* reload local configuration from EEPROM */ 462 cntrl |= PLX9056_PCI_RCR; 463 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 464 465 /* 466 * There is no safe way to poll for the end 467 * of reconfiguration process. Waiting for 10ms 468 * is safe. 469 */ 470 mdelay(10); 471 472 cntrl ^= PLX9056_PCI_RCR; 473 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 474 }; 475 476 /* Special reset function for Marathon CAN-bus-PCI card */ 477 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev) 478 { 479 void __iomem *reset_addr; 480 int i; 481 static const int reset_bar[2] = {3, 5}; 482 483 plx_pci_reset_common(pdev); 484 485 for (i = 0; i < 2; i++) { 486 reset_addr = pci_iomap(pdev, reset_bar[i], 0); 487 if (!reset_addr) { 488 dev_err(&pdev->dev, "Failed to remap reset " 489 "space %d (BAR%d)\n", i, reset_bar[i]); 490 } else { 491 /* reset the SJA1000 chip */ 492 iowrite8(0x1, reset_addr); 493 udelay(100); 494 pci_iounmap(pdev, reset_addr); 495 } 496 } 497 } 498 499 /* Special reset function for Marathon CAN-bus-PCIe card */ 500 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev) 501 { 502 void __iomem *addr; 503 void __iomem *reset_addr; 504 int i; 505 506 plx9056_pci_reset_common(pdev); 507 508 for (i = 0; i < 2; i++) { 509 struct plx_pci_channel_map *chan_map = 510 &plx_pci_card_info_marathon_pcie.chan_map_tbl[i]; 511 addr = pci_iomap(pdev, chan_map->bar, chan_map->size); 512 if (!addr) { 513 dev_err(&pdev->dev, "Failed to remap reset " 514 "space %d (BAR%d)\n", i, chan_map->bar); 515 } else { 516 /* reset the SJA1000 chip */ 517 #define MARATHON_PCIE_RESET_OFFSET 32 518 reset_addr = addr + chan_map->offset + 519 MARATHON_PCIE_RESET_OFFSET; 520 iowrite8(0x1, reset_addr); 521 udelay(100); 522 pci_iounmap(pdev, addr); 523 } 524 } 525 } 526 527 static void plx_pci_del_card(struct pci_dev *pdev) 528 { 529 struct plx_pci_card *card = pci_get_drvdata(pdev); 530 struct net_device *dev; 531 struct sja1000_priv *priv; 532 int i = 0; 533 534 for (i = 0; i < PLX_PCI_MAX_CHAN; i++) { 535 dev = card->net_dev[i]; 536 if (!dev) 537 continue; 538 539 dev_info(&pdev->dev, "Removing %s\n", dev->name); 540 unregister_sja1000dev(dev); 541 priv = netdev_priv(dev); 542 if (priv->reg_base) 543 pci_iounmap(pdev, priv->reg_base); 544 free_sja1000dev(dev); 545 } 546 547 card->reset_func(pdev); 548 549 /* 550 * Disable interrupts from PCI-card and disable local 551 * interrupts 552 */ 553 if (pdev->device != PCI_DEVICE_ID_PLX_9056 && 554 pdev->device != MARATHON_PCIE_DEVICE_ID) 555 iowrite32(0x0, card->conf_addr + PLX_INTCSR); 556 else 557 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR); 558 559 if (card->conf_addr) 560 pci_iounmap(pdev, card->conf_addr); 561 562 kfree(card); 563 564 pci_disable_device(pdev); 565 } 566 567 /* 568 * Probe PLX90xx based device for the SJA1000 chips and register each 569 * available CAN channel to SJA1000 Socket-CAN subsystem. 570 */ 571 static int plx_pci_add_card(struct pci_dev *pdev, 572 const struct pci_device_id *ent) 573 { 574 struct sja1000_priv *priv; 575 struct net_device *dev; 576 struct plx_pci_card *card; 577 struct plx_pci_card_info *ci; 578 int err, i; 579 u32 val; 580 void __iomem *addr; 581 582 ci = (struct plx_pci_card_info *)ent->driver_data; 583 584 if (pci_enable_device(pdev) < 0) { 585 dev_err(&pdev->dev, "Failed to enable PCI device\n"); 586 return -ENODEV; 587 } 588 589 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n", 590 ci->name, PCI_SLOT(pdev->devfn)); 591 592 /* Allocate card structures to hold addresses, ... */ 593 card = kzalloc(sizeof(*card), GFP_KERNEL); 594 if (!card) { 595 pci_disable_device(pdev); 596 return -ENOMEM; 597 } 598 599 pci_set_drvdata(pdev, card); 600 601 card->channels = 0; 602 603 /* Remap PLX90xx configuration space */ 604 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size); 605 if (!addr) { 606 err = -ENOMEM; 607 dev_err(&pdev->dev, "Failed to remap configuration space " 608 "(BAR%d)\n", ci->conf_map.bar); 609 goto failure_cleanup; 610 } 611 card->conf_addr = addr + ci->conf_map.offset; 612 613 ci->reset_func(pdev); 614 card->reset_func = ci->reset_func; 615 616 /* Detect available channels */ 617 for (i = 0; i < ci->channel_count; i++) { 618 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i]; 619 620 dev = alloc_sja1000dev(0); 621 if (!dev) { 622 err = -ENOMEM; 623 goto failure_cleanup; 624 } 625 626 card->net_dev[i] = dev; 627 priv = netdev_priv(dev); 628 priv->priv = card; 629 priv->irq_flags = IRQF_SHARED; 630 631 dev->irq = pdev->irq; 632 633 /* 634 * Remap IO space of the SJA1000 chips 635 * This is device-dependent mapping 636 */ 637 addr = pci_iomap(pdev, cm->bar, cm->size); 638 if (!addr) { 639 err = -ENOMEM; 640 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar); 641 goto failure_cleanup; 642 } 643 644 priv->reg_base = addr + cm->offset; 645 priv->read_reg = plx_pci_read_reg; 646 priv->write_reg = plx_pci_write_reg; 647 648 /* Check if channel is present */ 649 if (plx_pci_check_sja1000(priv)) { 650 priv->can.clock.freq = ci->can_clock; 651 priv->ocr = ci->ocr; 652 priv->cdr = ci->cdr; 653 654 SET_NETDEV_DEV(dev, &pdev->dev); 655 dev->dev_id = i; 656 657 /* Register SJA1000 device */ 658 err = register_sja1000dev(dev); 659 if (err) { 660 dev_err(&pdev->dev, "Registering device failed " 661 "(err=%d)\n", err); 662 goto failure_cleanup; 663 } 664 665 card->channels++; 666 667 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d " 668 "registered as %s\n", i + 1, priv->reg_base, 669 dev->irq, dev->name); 670 } else { 671 dev_err(&pdev->dev, "Channel #%d not detected\n", 672 i + 1); 673 free_sja1000dev(dev); 674 card->net_dev[i] = NULL; 675 } 676 } 677 678 if (!card->channels) { 679 err = -ENODEV; 680 goto failure_cleanup; 681 } 682 683 /* 684 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1, 685 * Local_2 interrupts from the SJA1000 chips 686 */ 687 if (pdev->device != PCI_DEVICE_ID_PLX_9056 && 688 pdev->device != MARATHON_PCIE_DEVICE_ID) { 689 val = ioread32(card->conf_addr + PLX_INTCSR); 690 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH) 691 val |= PLX_LINT1_EN | PLX_PCI_INT_EN; 692 else 693 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN; 694 iowrite32(val, card->conf_addr + PLX_INTCSR); 695 } else { 696 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN, 697 card->conf_addr + PLX9056_INTCSR); 698 } 699 return 0; 700 701 failure_cleanup: 702 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err); 703 704 plx_pci_del_card(pdev); 705 706 return err; 707 } 708 709 static struct pci_driver plx_pci_driver = { 710 .name = DRV_NAME, 711 .id_table = plx_pci_tbl, 712 .probe = plx_pci_add_card, 713 .remove = plx_pci_del_card, 714 }; 715 716 module_pci_driver(plx_pci_driver); 717