1 // SPDX-License-Identifier: GPL-2.0 2 /* Fintek F81601 PCIE to 2 CAN controller driver 3 * 4 * Copyright (C) 2019 Peter Hong <peter_hong@fintek.com.tw> 5 * Copyright (C) 2019 Linux Foundation 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/netdevice.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/can/dev.h> 16 #include <linux/io.h> 17 #include <linux/version.h> 18 19 #include "sja1000.h" 20 21 #define F81601_PCI_MAX_CHAN 2 22 23 #define F81601_DECODE_REG 0x209 24 #define F81601_IO_MODE BIT(7) 25 #define F81601_MEM_MODE BIT(6) 26 #define F81601_CFG_MODE BIT(5) 27 #define F81601_CAN2_INTERNAL_CLK BIT(3) 28 #define F81601_CAN1_INTERNAL_CLK BIT(2) 29 #define F81601_CAN2_EN BIT(1) 30 #define F81601_CAN1_EN BIT(0) 31 32 #define F81601_TRAP_REG 0x20a 33 #define F81601_CAN2_HAS_EN BIT(4) 34 35 struct f81601_pci_card { 36 void __iomem *addr; 37 spinlock_t lock; /* use this spin lock only for write access */ 38 struct pci_dev *dev; 39 struct net_device *net_dev[F81601_PCI_MAX_CHAN]; 40 }; 41 42 static const struct pci_device_id f81601_pci_tbl[] = { 43 { PCI_DEVICE(0x1c29, 0x1703) }, 44 { /* sentinel */ }, 45 }; 46 47 MODULE_DEVICE_TABLE(pci, f81601_pci_tbl); 48 49 static bool internal_clk = true; 50 module_param(internal_clk, bool, 0444); 51 MODULE_PARM_DESC(internal_clk, "Use internal clock, default true (24MHz)"); 52 53 static unsigned int external_clk; 54 module_param(external_clk, uint, 0444); 55 MODULE_PARM_DESC(external_clk, "External clock when internal_clk disabled"); 56 57 static u8 f81601_pci_read_reg(const struct sja1000_priv *priv, int port) 58 { 59 return readb(priv->reg_base + port); 60 } 61 62 static void f81601_pci_write_reg(const struct sja1000_priv *priv, int port, 63 u8 val) 64 { 65 struct f81601_pci_card *card = priv->priv; 66 unsigned long flags; 67 68 spin_lock_irqsave(&card->lock, flags); 69 writeb(val, priv->reg_base + port); 70 readb(priv->reg_base); 71 spin_unlock_irqrestore(&card->lock, flags); 72 } 73 74 static void f81601_pci_remove(struct pci_dev *pdev) 75 { 76 struct f81601_pci_card *card = pci_get_drvdata(pdev); 77 struct net_device *dev; 78 int i; 79 80 for (i = 0; i < ARRAY_SIZE(card->net_dev); i++) { 81 dev = card->net_dev[i]; 82 if (!dev) 83 continue; 84 85 dev_info(&pdev->dev, "%s: Removing %s\n", __func__, dev->name); 86 87 unregister_sja1000dev(dev); 88 free_sja1000dev(dev); 89 } 90 } 91 92 /* Probe F81601 based device for the SJA1000 chips and register each 93 * available CAN channel to SJA1000 Socket-CAN subsystem. 94 */ 95 static int f81601_pci_probe(struct pci_dev *pdev, 96 const struct pci_device_id *ent) 97 { 98 struct sja1000_priv *priv; 99 struct net_device *dev; 100 struct f81601_pci_card *card; 101 int err, i, count; 102 u8 tmp; 103 104 if (pcim_enable_device(pdev) < 0) { 105 dev_err(&pdev->dev, "Failed to enable PCI device\n"); 106 return -ENODEV; 107 } 108 109 dev_info(&pdev->dev, "Detected card at slot #%i\n", 110 PCI_SLOT(pdev->devfn)); 111 112 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL); 113 if (!card) 114 return -ENOMEM; 115 116 card->dev = pdev; 117 spin_lock_init(&card->lock); 118 119 pci_set_drvdata(pdev, card); 120 121 tmp = F81601_IO_MODE | F81601_MEM_MODE | F81601_CFG_MODE | 122 F81601_CAN2_EN | F81601_CAN1_EN; 123 124 if (internal_clk) { 125 tmp |= F81601_CAN2_INTERNAL_CLK | F81601_CAN1_INTERNAL_CLK; 126 127 dev_info(&pdev->dev, 128 "F81601 running with internal clock: 24Mhz\n"); 129 } else { 130 dev_info(&pdev->dev, 131 "F81601 running with external clock: %dMhz\n", 132 external_clk / 1000000); 133 } 134 135 pci_write_config_byte(pdev, F81601_DECODE_REG, tmp); 136 137 card->addr = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0)); 138 139 if (!card->addr) { 140 err = -ENOMEM; 141 dev_err(&pdev->dev, "%s: Failed to remap BAR\n", __func__); 142 goto failure_cleanup; 143 } 144 145 /* read CAN2_HW_EN strap pin to detect how many CANBUS do we have */ 146 count = ARRAY_SIZE(card->net_dev); 147 pci_read_config_byte(pdev, F81601_TRAP_REG, &tmp); 148 if (!(tmp & F81601_CAN2_HAS_EN)) 149 count = 1; 150 151 for (i = 0; i < count; i++) { 152 dev = alloc_sja1000dev(0); 153 if (!dev) { 154 err = -ENOMEM; 155 goto failure_cleanup; 156 } 157 158 priv = netdev_priv(dev); 159 priv->priv = card; 160 priv->irq_flags = IRQF_SHARED; 161 priv->reg_base = card->addr + 0x80 * i; 162 priv->read_reg = f81601_pci_read_reg; 163 priv->write_reg = f81601_pci_write_reg; 164 165 if (internal_clk) 166 priv->can.clock.freq = 24000000 / 2; 167 else 168 priv->can.clock.freq = external_clk / 2; 169 170 priv->ocr = OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL; 171 priv->cdr = CDR_CBP; 172 173 SET_NETDEV_DEV(dev, &pdev->dev); 174 dev->dev_id = i; 175 dev->irq = pdev->irq; 176 177 /* Register SJA1000 device */ 178 err = register_sja1000dev(dev); 179 if (err) { 180 dev_err(&pdev->dev, 181 "%s: Registering device failed: %x\n", __func__, 182 err); 183 free_sja1000dev(dev); 184 goto failure_cleanup; 185 } 186 187 card->net_dev[i] = dev; 188 dev_info(&pdev->dev, "Channel #%d, %s at 0x%p, irq %d\n", i, 189 dev->name, priv->reg_base, dev->irq); 190 } 191 192 return 0; 193 194 failure_cleanup: 195 dev_err(&pdev->dev, "%s: failed: %d. Cleaning Up.\n", __func__, err); 196 f81601_pci_remove(pdev); 197 198 return err; 199 } 200 201 static struct pci_driver f81601_pci_driver = { 202 .name = "f81601", 203 .id_table = f81601_pci_tbl, 204 .probe = f81601_pci_probe, 205 .remove = f81601_pci_remove, 206 }; 207 208 MODULE_DESCRIPTION("Fintek F81601 PCIE to 2 CANBUS adaptor driver"); 209 MODULE_AUTHOR("Peter Hong <peter_hong@fintek.com.tw>"); 210 MODULE_LICENSE("GPL v2"); 211 212 module_pci_driver(f81601_pci_driver); 213