1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Renesas R-Car CAN device driver 3 * 4 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/kernel.h> 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/errno.h> 13 #include <linux/netdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/can/led.h> 16 #include <linux/can/dev.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 20 #define RCAR_CAN_DRV_NAME "rcar_can" 21 22 /* Clock Select Register settings */ 23 enum CLKR { 24 CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */ 25 CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */ 26 CLKR_CLKEXT = 3, /* Externally input clock */ 27 }; 28 29 #define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ 30 BIT(CLKR_CLKEXT)) 31 32 /* Mailbox configuration: 33 * mailbox 60 - 63 - Rx FIFO mailboxes 34 * mailbox 56 - 59 - Tx FIFO mailboxes 35 * non-FIFO mailboxes are not used 36 */ 37 #define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ 38 #define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ 39 #define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ 40 #define RCAR_CAN_FIFO_DEPTH 4 41 42 /* Mailbox registers structure */ 43 struct rcar_can_mbox_regs { 44 u32 id; /* IDE and RTR bits, SID and EID */ 45 u8 stub; /* Not used */ 46 u8 dlc; /* Data Length Code - bits [0..3] */ 47 u8 data[8]; /* Data Bytes */ 48 u8 tsh; /* Time Stamp Higher Byte */ 49 u8 tsl; /* Time Stamp Lower Byte */ 50 }; 51 52 struct rcar_can_regs { 53 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ 54 u32 mkr_2_9[8]; /* Mask Registers 2-9 */ 55 u32 fidcr[2]; /* FIFO Received ID Compare Register */ 56 u32 mkivlr1; /* Mask Invalid Register 1 */ 57 u32 mier1; /* Mailbox Interrupt Enable Register 1 */ 58 u32 mkr_0_1[2]; /* Mask Registers 0-1 */ 59 u32 mkivlr0; /* Mask Invalid Register 0*/ 60 u32 mier0; /* Mailbox Interrupt Enable Register 0 */ 61 u8 pad_440[0x3c0]; 62 u8 mctl[64]; /* Message Control Registers */ 63 u16 ctlr; /* Control Register */ 64 u16 str; /* Status register */ 65 u8 bcr[3]; /* Bit Configuration Register */ 66 u8 clkr; /* Clock Select Register */ 67 u8 rfcr; /* Receive FIFO Control Register */ 68 u8 rfpcr; /* Receive FIFO Pointer Control Register */ 69 u8 tfcr; /* Transmit FIFO Control Register */ 70 u8 tfpcr; /* Transmit FIFO Pointer Control Register */ 71 u8 eier; /* Error Interrupt Enable Register */ 72 u8 eifr; /* Error Interrupt Factor Judge Register */ 73 u8 recr; /* Receive Error Count Register */ 74 u8 tecr; /* Transmit Error Count Register */ 75 u8 ecsr; /* Error Code Store Register */ 76 u8 cssr; /* Channel Search Support Register */ 77 u8 mssr; /* Mailbox Search Status Register */ 78 u8 msmr; /* Mailbox Search Mode Register */ 79 u16 tsr; /* Time Stamp Register */ 80 u8 afsr; /* Acceptance Filter Support Register */ 81 u8 pad_857; 82 u8 tcr; /* Test Control Register */ 83 u8 pad_859[7]; 84 u8 ier; /* Interrupt Enable Register */ 85 u8 isr; /* Interrupt Status Register */ 86 u8 pad_862; 87 u8 mbsmr; /* Mailbox Search Mask Register */ 88 }; 89 90 struct rcar_can_priv { 91 struct can_priv can; /* Must be the first member! */ 92 struct net_device *ndev; 93 struct napi_struct napi; 94 struct rcar_can_regs __iomem *regs; 95 struct clk *clk; 96 struct clk *can_clk; 97 u32 tx_head; 98 u32 tx_tail; 99 u8 clock_select; 100 u8 ier; 101 }; 102 103 static const struct can_bittiming_const rcar_can_bittiming_const = { 104 .name = RCAR_CAN_DRV_NAME, 105 .tseg1_min = 4, 106 .tseg1_max = 16, 107 .tseg2_min = 2, 108 .tseg2_max = 8, 109 .sjw_max = 4, 110 .brp_min = 1, 111 .brp_max = 1024, 112 .brp_inc = 1, 113 }; 114 115 /* Control Register bits */ 116 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ 117 #define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ 118 /* at bus-off entry */ 119 #define RCAR_CAN_CTLR_SLPM (1 << 10) 120 #define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ 121 #define RCAR_CAN_CTLR_CANM_HALT (1 << 9) 122 #define RCAR_CAN_CTLR_CANM_RESET (1 << 8) 123 #define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) 124 #define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ 125 #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ 126 #define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ 127 #define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ 128 129 /* Status Register bits */ 130 #define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ 131 132 /* FIFO Received ID Compare Registers 0 and 1 bits */ 133 #define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ 134 #define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ 135 136 /* Receive FIFO Control Register bits */ 137 #define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ 138 #define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ 139 140 /* Transmit FIFO Control Register bits */ 141 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ 142 /* Number Status Bits */ 143 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ 144 /* Message Number Status Bits */ 145 #define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ 146 147 #define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ 148 /* for Rx mailboxes 0-31 */ 149 #define RCAR_CAN_N_RX_MKREGS2 8 150 151 /* Bit Configuration Register settings */ 152 #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) 153 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) 154 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) 155 #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) 156 157 /* Mailbox and Mask Registers bits */ 158 #define RCAR_CAN_IDE (1 << 31) 159 #define RCAR_CAN_RTR (1 << 30) 160 #define RCAR_CAN_SID_SHIFT 18 161 162 /* Mailbox Interrupt Enable Register 1 bits */ 163 #define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ 164 #define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ 165 166 /* Interrupt Enable Register bits */ 167 #define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ 168 #define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ 169 /* Enable Bit */ 170 #define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ 171 /* Enable Bit */ 172 /* Interrupt Status Register bits */ 173 #define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ 174 #define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ 175 /* Status Bit */ 176 #define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ 177 /* Status Bit */ 178 179 /* Error Interrupt Enable Register bits */ 180 #define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ 181 #define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ 182 /* Interrupt Enable */ 183 #define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ 184 #define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ 185 #define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ 186 #define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ 187 #define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ 188 #define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ 189 190 /* Error Interrupt Factor Judge Register bits */ 191 #define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ 192 #define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ 193 /* Detect Flag */ 194 #define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ 195 #define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ 196 #define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ 197 #define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ 198 #define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ 199 #define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ 200 201 /* Error Code Store Register bits */ 202 #define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ 203 #define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ 204 #define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ 205 #define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ 206 #define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ 207 #define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ 208 #define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ 209 #define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ 210 211 #define RCAR_CAN_NAPI_WEIGHT 4 212 #define MAX_STR_READS 0x100 213 214 static void tx_failure_cleanup(struct net_device *ndev) 215 { 216 int i; 217 218 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) 219 can_free_echo_skb(ndev, i, NULL); 220 } 221 222 static void rcar_can_error(struct net_device *ndev) 223 { 224 struct rcar_can_priv *priv = netdev_priv(ndev); 225 struct can_frame *cf; 226 struct sk_buff *skb; 227 u8 eifr, txerr = 0, rxerr = 0; 228 229 /* Propagate the error condition to the CAN stack */ 230 skb = alloc_can_err_skb(ndev, &cf); 231 232 eifr = readb(&priv->regs->eifr); 233 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { 234 txerr = readb(&priv->regs->tecr); 235 rxerr = readb(&priv->regs->recr); 236 if (skb) { 237 cf->can_id |= CAN_ERR_CRTL; 238 cf->data[6] = txerr; 239 cf->data[7] = rxerr; 240 } 241 } 242 if (eifr & RCAR_CAN_EIFR_BEIF) { 243 int rx_errors = 0, tx_errors = 0; 244 u8 ecsr; 245 246 netdev_dbg(priv->ndev, "Bus error interrupt:\n"); 247 if (skb) 248 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 249 250 ecsr = readb(&priv->regs->ecsr); 251 if (ecsr & RCAR_CAN_ECSR_ADEF) { 252 netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); 253 tx_errors++; 254 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); 255 if (skb) 256 cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL; 257 } 258 if (ecsr & RCAR_CAN_ECSR_BE0F) { 259 netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); 260 tx_errors++; 261 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); 262 if (skb) 263 cf->data[2] |= CAN_ERR_PROT_BIT0; 264 } 265 if (ecsr & RCAR_CAN_ECSR_BE1F) { 266 netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); 267 tx_errors++; 268 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); 269 if (skb) 270 cf->data[2] |= CAN_ERR_PROT_BIT1; 271 } 272 if (ecsr & RCAR_CAN_ECSR_CEF) { 273 netdev_dbg(priv->ndev, "CRC Error\n"); 274 rx_errors++; 275 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); 276 if (skb) 277 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 278 } 279 if (ecsr & RCAR_CAN_ECSR_AEF) { 280 netdev_dbg(priv->ndev, "ACK Error\n"); 281 tx_errors++; 282 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); 283 if (skb) { 284 cf->can_id |= CAN_ERR_ACK; 285 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 286 } 287 } 288 if (ecsr & RCAR_CAN_ECSR_FEF) { 289 netdev_dbg(priv->ndev, "Form Error\n"); 290 rx_errors++; 291 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); 292 if (skb) 293 cf->data[2] |= CAN_ERR_PROT_FORM; 294 } 295 if (ecsr & RCAR_CAN_ECSR_SEF) { 296 netdev_dbg(priv->ndev, "Stuff Error\n"); 297 rx_errors++; 298 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); 299 if (skb) 300 cf->data[2] |= CAN_ERR_PROT_STUFF; 301 } 302 303 priv->can.can_stats.bus_error++; 304 ndev->stats.rx_errors += rx_errors; 305 ndev->stats.tx_errors += tx_errors; 306 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); 307 } 308 if (eifr & RCAR_CAN_EIFR_EWIF) { 309 netdev_dbg(priv->ndev, "Error warning interrupt\n"); 310 priv->can.state = CAN_STATE_ERROR_WARNING; 311 priv->can.can_stats.error_warning++; 312 /* Clear interrupt condition */ 313 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); 314 if (skb) 315 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 316 CAN_ERR_CRTL_RX_WARNING; 317 } 318 if (eifr & RCAR_CAN_EIFR_EPIF) { 319 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 320 priv->can.state = CAN_STATE_ERROR_PASSIVE; 321 priv->can.can_stats.error_passive++; 322 /* Clear interrupt condition */ 323 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); 324 if (skb) 325 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 326 CAN_ERR_CRTL_RX_PASSIVE; 327 } 328 if (eifr & RCAR_CAN_EIFR_BOEIF) { 329 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); 330 tx_failure_cleanup(ndev); 331 priv->ier = RCAR_CAN_IER_ERSIE; 332 writeb(priv->ier, &priv->regs->ier); 333 priv->can.state = CAN_STATE_BUS_OFF; 334 /* Clear interrupt condition */ 335 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); 336 priv->can.can_stats.bus_off++; 337 can_bus_off(ndev); 338 if (skb) 339 cf->can_id |= CAN_ERR_BUSOFF; 340 } 341 if (eifr & RCAR_CAN_EIFR_ORIF) { 342 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); 343 ndev->stats.rx_over_errors++; 344 ndev->stats.rx_errors++; 345 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); 346 if (skb) { 347 cf->can_id |= CAN_ERR_CRTL; 348 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 349 } 350 } 351 if (eifr & RCAR_CAN_EIFR_OLIF) { 352 netdev_dbg(priv->ndev, 353 "Overload Frame Transmission error interrupt\n"); 354 ndev->stats.rx_over_errors++; 355 ndev->stats.rx_errors++; 356 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); 357 if (skb) { 358 cf->can_id |= CAN_ERR_PROT; 359 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 360 } 361 } 362 363 if (skb) 364 netif_rx(skb); 365 } 366 367 static void rcar_can_tx_done(struct net_device *ndev) 368 { 369 struct rcar_can_priv *priv = netdev_priv(ndev); 370 struct net_device_stats *stats = &ndev->stats; 371 u8 isr; 372 373 while (1) { 374 u8 unsent = readb(&priv->regs->tfcr); 375 376 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> 377 RCAR_CAN_TFCR_TFUST_SHIFT; 378 if (priv->tx_head - priv->tx_tail <= unsent) 379 break; 380 stats->tx_packets++; 381 stats->tx_bytes += 382 can_get_echo_skb(ndev, 383 priv->tx_tail % RCAR_CAN_FIFO_DEPTH, 384 NULL); 385 386 priv->tx_tail++; 387 netif_wake_queue(ndev); 388 } 389 /* Clear interrupt */ 390 isr = readb(&priv->regs->isr); 391 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); 392 can_led_event(ndev, CAN_LED_EVENT_TX); 393 } 394 395 static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) 396 { 397 struct net_device *ndev = dev_id; 398 struct rcar_can_priv *priv = netdev_priv(ndev); 399 u8 isr; 400 401 isr = readb(&priv->regs->isr); 402 if (!(isr & priv->ier)) 403 return IRQ_NONE; 404 405 if (isr & RCAR_CAN_ISR_ERSF) 406 rcar_can_error(ndev); 407 408 if (isr & RCAR_CAN_ISR_TXFF) 409 rcar_can_tx_done(ndev); 410 411 if (isr & RCAR_CAN_ISR_RXFF) { 412 if (napi_schedule_prep(&priv->napi)) { 413 /* Disable Rx FIFO interrupts */ 414 priv->ier &= ~RCAR_CAN_IER_RXFIE; 415 writeb(priv->ier, &priv->regs->ier); 416 __napi_schedule(&priv->napi); 417 } 418 } 419 420 return IRQ_HANDLED; 421 } 422 423 static void rcar_can_set_bittiming(struct net_device *dev) 424 { 425 struct rcar_can_priv *priv = netdev_priv(dev); 426 struct can_bittiming *bt = &priv->can.bittiming; 427 u32 bcr; 428 429 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | 430 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | 431 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); 432 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. 433 * All the registers are big-endian but they get byte-swapped on 32-bit 434 * read/write (but not on 8-bit, contrary to the manuals)... 435 */ 436 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); 437 } 438 439 static void rcar_can_start(struct net_device *ndev) 440 { 441 struct rcar_can_priv *priv = netdev_priv(ndev); 442 u16 ctlr; 443 int i; 444 445 /* Set controller to known mode: 446 * - FIFO mailbox mode 447 * - accept all messages 448 * - overrun mode 449 * CAN is in sleep mode after MCU hardware or software reset. 450 */ 451 ctlr = readw(&priv->regs->ctlr); 452 ctlr &= ~RCAR_CAN_CTLR_SLPM; 453 writew(ctlr, &priv->regs->ctlr); 454 /* Go to reset mode */ 455 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 456 writew(ctlr, &priv->regs->ctlr); 457 for (i = 0; i < MAX_STR_READS; i++) { 458 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 459 break; 460 } 461 rcar_can_set_bittiming(ndev); 462 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ 463 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ 464 /* at bus-off */ 465 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ 466 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ 467 writew(ctlr, &priv->regs->ctlr); 468 469 /* Accept all SID and EID */ 470 writel(0, &priv->regs->mkr_2_9[6]); 471 writel(0, &priv->regs->mkr_2_9[7]); 472 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ 473 writel(0, &priv->regs->mkivlr1); 474 /* Accept all frames */ 475 writel(0, &priv->regs->fidcr[0]); 476 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); 477 /* Enable and configure FIFO mailbox interrupts */ 478 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); 479 480 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | 481 RCAR_CAN_IER_TXFIE; 482 writeb(priv->ier, &priv->regs->ier); 483 484 /* Accumulate error codes */ 485 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); 486 /* Enable error interrupts */ 487 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | 488 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? 489 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | 490 RCAR_CAN_EIER_OLIE, &priv->regs->eier); 491 priv->can.state = CAN_STATE_ERROR_ACTIVE; 492 493 /* Go to operation mode */ 494 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); 495 for (i = 0; i < MAX_STR_READS; i++) { 496 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) 497 break; 498 } 499 /* Enable Rx and Tx FIFO */ 500 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); 501 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); 502 } 503 504 static int rcar_can_open(struct net_device *ndev) 505 { 506 struct rcar_can_priv *priv = netdev_priv(ndev); 507 int err; 508 509 err = clk_prepare_enable(priv->clk); 510 if (err) { 511 netdev_err(ndev, 512 "failed to enable peripheral clock, error %d\n", 513 err); 514 goto out; 515 } 516 err = clk_prepare_enable(priv->can_clk); 517 if (err) { 518 netdev_err(ndev, "failed to enable CAN clock, error %d\n", 519 err); 520 goto out_clock; 521 } 522 err = open_candev(ndev); 523 if (err) { 524 netdev_err(ndev, "open_candev() failed, error %d\n", err); 525 goto out_can_clock; 526 } 527 napi_enable(&priv->napi); 528 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); 529 if (err) { 530 netdev_err(ndev, "request_irq(%d) failed, error %d\n", 531 ndev->irq, err); 532 goto out_close; 533 } 534 can_led_event(ndev, CAN_LED_EVENT_OPEN); 535 rcar_can_start(ndev); 536 netif_start_queue(ndev); 537 return 0; 538 out_close: 539 napi_disable(&priv->napi); 540 close_candev(ndev); 541 out_can_clock: 542 clk_disable_unprepare(priv->can_clk); 543 out_clock: 544 clk_disable_unprepare(priv->clk); 545 out: 546 return err; 547 } 548 549 static void rcar_can_stop(struct net_device *ndev) 550 { 551 struct rcar_can_priv *priv = netdev_priv(ndev); 552 u16 ctlr; 553 int i; 554 555 /* Go to (force) reset mode */ 556 ctlr = readw(&priv->regs->ctlr); 557 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 558 writew(ctlr, &priv->regs->ctlr); 559 for (i = 0; i < MAX_STR_READS; i++) { 560 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 561 break; 562 } 563 writel(0, &priv->regs->mier0); 564 writel(0, &priv->regs->mier1); 565 writeb(0, &priv->regs->ier); 566 writeb(0, &priv->regs->eier); 567 /* Go to sleep mode */ 568 ctlr |= RCAR_CAN_CTLR_SLPM; 569 writew(ctlr, &priv->regs->ctlr); 570 priv->can.state = CAN_STATE_STOPPED; 571 } 572 573 static int rcar_can_close(struct net_device *ndev) 574 { 575 struct rcar_can_priv *priv = netdev_priv(ndev); 576 577 netif_stop_queue(ndev); 578 rcar_can_stop(ndev); 579 free_irq(ndev->irq, ndev); 580 napi_disable(&priv->napi); 581 clk_disable_unprepare(priv->can_clk); 582 clk_disable_unprepare(priv->clk); 583 close_candev(ndev); 584 can_led_event(ndev, CAN_LED_EVENT_STOP); 585 return 0; 586 } 587 588 static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, 589 struct net_device *ndev) 590 { 591 struct rcar_can_priv *priv = netdev_priv(ndev); 592 struct can_frame *cf = (struct can_frame *)skb->data; 593 u32 data, i; 594 595 if (can_dropped_invalid_skb(ndev, skb)) 596 return NETDEV_TX_OK; 597 598 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 599 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; 600 else /* Standard frame format */ 601 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; 602 603 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ 604 data |= RCAR_CAN_RTR; 605 } else { 606 for (i = 0; i < cf->len; i++) 607 writeb(cf->data[i], 608 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); 609 } 610 611 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); 612 613 writeb(cf->len, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); 614 615 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH, 0); 616 priv->tx_head++; 617 /* Start Tx: write 0xff to the TFPCR register to increment 618 * the CPU-side pointer for the transmit FIFO to the next 619 * mailbox location 620 */ 621 writeb(0xff, &priv->regs->tfpcr); 622 /* Stop the queue if we've filled all FIFO entries */ 623 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) 624 netif_stop_queue(ndev); 625 626 return NETDEV_TX_OK; 627 } 628 629 static const struct net_device_ops rcar_can_netdev_ops = { 630 .ndo_open = rcar_can_open, 631 .ndo_stop = rcar_can_close, 632 .ndo_start_xmit = rcar_can_start_xmit, 633 .ndo_change_mtu = can_change_mtu, 634 }; 635 636 static void rcar_can_rx_pkt(struct rcar_can_priv *priv) 637 { 638 struct net_device_stats *stats = &priv->ndev->stats; 639 struct can_frame *cf; 640 struct sk_buff *skb; 641 u32 data; 642 u8 dlc; 643 644 skb = alloc_can_skb(priv->ndev, &cf); 645 if (!skb) { 646 stats->rx_dropped++; 647 return; 648 } 649 650 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); 651 if (data & RCAR_CAN_IDE) 652 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 653 else 654 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; 655 656 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); 657 cf->len = can_cc_dlc2len(dlc); 658 if (data & RCAR_CAN_RTR) { 659 cf->can_id |= CAN_RTR_FLAG; 660 } else { 661 for (dlc = 0; dlc < cf->len; dlc++) 662 cf->data[dlc] = 663 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); 664 665 stats->rx_bytes += cf->len; 666 } 667 stats->rx_packets++; 668 669 can_led_event(priv->ndev, CAN_LED_EVENT_RX); 670 671 netif_receive_skb(skb); 672 } 673 674 static int rcar_can_rx_poll(struct napi_struct *napi, int quota) 675 { 676 struct rcar_can_priv *priv = container_of(napi, 677 struct rcar_can_priv, napi); 678 int num_pkts; 679 680 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 681 u8 rfcr, isr; 682 683 isr = readb(&priv->regs->isr); 684 /* Clear interrupt bit */ 685 if (isr & RCAR_CAN_ISR_RXFF) 686 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); 687 rfcr = readb(&priv->regs->rfcr); 688 if (rfcr & RCAR_CAN_RFCR_RFEST) 689 break; 690 rcar_can_rx_pkt(priv); 691 /* Write 0xff to the RFPCR register to increment 692 * the CPU-side pointer for the receive FIFO 693 * to the next mailbox location 694 */ 695 writeb(0xff, &priv->regs->rfpcr); 696 } 697 /* All packets processed */ 698 if (num_pkts < quota) { 699 napi_complete_done(napi, num_pkts); 700 priv->ier |= RCAR_CAN_IER_RXFIE; 701 writeb(priv->ier, &priv->regs->ier); 702 } 703 return num_pkts; 704 } 705 706 static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 707 { 708 switch (mode) { 709 case CAN_MODE_START: 710 rcar_can_start(ndev); 711 netif_wake_queue(ndev); 712 return 0; 713 default: 714 return -EOPNOTSUPP; 715 } 716 } 717 718 static int rcar_can_get_berr_counter(const struct net_device *dev, 719 struct can_berr_counter *bec) 720 { 721 struct rcar_can_priv *priv = netdev_priv(dev); 722 int err; 723 724 err = clk_prepare_enable(priv->clk); 725 if (err) 726 return err; 727 bec->txerr = readb(&priv->regs->tecr); 728 bec->rxerr = readb(&priv->regs->recr); 729 clk_disable_unprepare(priv->clk); 730 return 0; 731 } 732 733 static const char * const clock_names[] = { 734 [CLKR_CLKP1] = "clkp1", 735 [CLKR_CLKP2] = "clkp2", 736 [CLKR_CLKEXT] = "can_clk", 737 }; 738 739 static int rcar_can_probe(struct platform_device *pdev) 740 { 741 struct rcar_can_priv *priv; 742 struct net_device *ndev; 743 void __iomem *addr; 744 u32 clock_select = CLKR_CLKP1; 745 int err = -ENODEV; 746 int irq; 747 748 of_property_read_u32(pdev->dev.of_node, "renesas,can-clock-select", 749 &clock_select); 750 751 irq = platform_get_irq(pdev, 0); 752 if (irq < 0) { 753 err = irq; 754 goto fail; 755 } 756 757 addr = devm_platform_ioremap_resource(pdev, 0); 758 if (IS_ERR(addr)) { 759 err = PTR_ERR(addr); 760 goto fail; 761 } 762 763 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); 764 if (!ndev) { 765 dev_err(&pdev->dev, "alloc_candev() failed\n"); 766 err = -ENOMEM; 767 goto fail; 768 } 769 770 priv = netdev_priv(ndev); 771 772 priv->clk = devm_clk_get(&pdev->dev, "clkp1"); 773 if (IS_ERR(priv->clk)) { 774 err = PTR_ERR(priv->clk); 775 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n", 776 err); 777 goto fail_clk; 778 } 779 780 if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) { 781 err = -EINVAL; 782 dev_err(&pdev->dev, "invalid CAN clock selected\n"); 783 goto fail_clk; 784 } 785 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); 786 if (IS_ERR(priv->can_clk)) { 787 err = PTR_ERR(priv->can_clk); 788 dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err); 789 goto fail_clk; 790 } 791 792 ndev->netdev_ops = &rcar_can_netdev_ops; 793 ndev->irq = irq; 794 ndev->flags |= IFF_ECHO; 795 priv->ndev = ndev; 796 priv->regs = addr; 797 priv->clock_select = clock_select; 798 priv->can.clock.freq = clk_get_rate(priv->can_clk); 799 priv->can.bittiming_const = &rcar_can_bittiming_const; 800 priv->can.do_set_mode = rcar_can_do_set_mode; 801 priv->can.do_get_berr_counter = rcar_can_get_berr_counter; 802 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 803 platform_set_drvdata(pdev, ndev); 804 SET_NETDEV_DEV(ndev, &pdev->dev); 805 806 netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll, 807 RCAR_CAN_NAPI_WEIGHT); 808 err = register_candev(ndev); 809 if (err) { 810 dev_err(&pdev->dev, "register_candev() failed, error %d\n", 811 err); 812 goto fail_candev; 813 } 814 815 devm_can_led_init(ndev); 816 817 dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq); 818 819 return 0; 820 fail_candev: 821 netif_napi_del(&priv->napi); 822 fail_clk: 823 free_candev(ndev); 824 fail: 825 return err; 826 } 827 828 static int rcar_can_remove(struct platform_device *pdev) 829 { 830 struct net_device *ndev = platform_get_drvdata(pdev); 831 struct rcar_can_priv *priv = netdev_priv(ndev); 832 833 unregister_candev(ndev); 834 netif_napi_del(&priv->napi); 835 free_candev(ndev); 836 return 0; 837 } 838 839 static int __maybe_unused rcar_can_suspend(struct device *dev) 840 { 841 struct net_device *ndev = dev_get_drvdata(dev); 842 struct rcar_can_priv *priv = netdev_priv(ndev); 843 u16 ctlr; 844 845 if (!netif_running(ndev)) 846 return 0; 847 848 netif_stop_queue(ndev); 849 netif_device_detach(ndev); 850 851 ctlr = readw(&priv->regs->ctlr); 852 ctlr |= RCAR_CAN_CTLR_CANM_HALT; 853 writew(ctlr, &priv->regs->ctlr); 854 ctlr |= RCAR_CAN_CTLR_SLPM; 855 writew(ctlr, &priv->regs->ctlr); 856 priv->can.state = CAN_STATE_SLEEPING; 857 858 clk_disable(priv->clk); 859 return 0; 860 } 861 862 static int __maybe_unused rcar_can_resume(struct device *dev) 863 { 864 struct net_device *ndev = dev_get_drvdata(dev); 865 struct rcar_can_priv *priv = netdev_priv(ndev); 866 u16 ctlr; 867 int err; 868 869 if (!netif_running(ndev)) 870 return 0; 871 872 err = clk_enable(priv->clk); 873 if (err) { 874 netdev_err(ndev, "clk_enable() failed, error %d\n", err); 875 return err; 876 } 877 878 ctlr = readw(&priv->regs->ctlr); 879 ctlr &= ~RCAR_CAN_CTLR_SLPM; 880 writew(ctlr, &priv->regs->ctlr); 881 ctlr &= ~RCAR_CAN_CTLR_CANM; 882 writew(ctlr, &priv->regs->ctlr); 883 priv->can.state = CAN_STATE_ERROR_ACTIVE; 884 885 netif_device_attach(ndev); 886 netif_start_queue(ndev); 887 888 return 0; 889 } 890 891 static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); 892 893 static const struct of_device_id rcar_can_of_table[] __maybe_unused = { 894 { .compatible = "renesas,can-r8a7778" }, 895 { .compatible = "renesas,can-r8a7779" }, 896 { .compatible = "renesas,can-r8a7790" }, 897 { .compatible = "renesas,can-r8a7791" }, 898 { .compatible = "renesas,rcar-gen1-can" }, 899 { .compatible = "renesas,rcar-gen2-can" }, 900 { .compatible = "renesas,rcar-gen3-can" }, 901 { } 902 }; 903 MODULE_DEVICE_TABLE(of, rcar_can_of_table); 904 905 static struct platform_driver rcar_can_driver = { 906 .driver = { 907 .name = RCAR_CAN_DRV_NAME, 908 .of_match_table = of_match_ptr(rcar_can_of_table), 909 .pm = &rcar_can_pm_ops, 910 }, 911 .probe = rcar_can_probe, 912 .remove = rcar_can_remove, 913 }; 914 915 module_platform_driver(rcar_can_driver); 916 917 MODULE_AUTHOR("Cogent Embedded, Inc."); 918 MODULE_LICENSE("GPL"); 919 MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); 920 MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); 921