1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Renesas R-Car CAN device driver 3 * 4 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/kernel.h> 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/errno.h> 13 #include <linux/netdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/can/led.h> 16 #include <linux/can/dev.h> 17 #include <linux/clk.h> 18 #include <linux/can/platform/rcar_can.h> 19 #include <linux/of.h> 20 21 #define RCAR_CAN_DRV_NAME "rcar_can" 22 23 #define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ 24 BIT(CLKR_CLKEXT)) 25 26 /* Mailbox configuration: 27 * mailbox 60 - 63 - Rx FIFO mailboxes 28 * mailbox 56 - 59 - Tx FIFO mailboxes 29 * non-FIFO mailboxes are not used 30 */ 31 #define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ 32 #define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ 33 #define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ 34 #define RCAR_CAN_FIFO_DEPTH 4 35 36 /* Mailbox registers structure */ 37 struct rcar_can_mbox_regs { 38 u32 id; /* IDE and RTR bits, SID and EID */ 39 u8 stub; /* Not used */ 40 u8 dlc; /* Data Length Code - bits [0..3] */ 41 u8 data[8]; /* Data Bytes */ 42 u8 tsh; /* Time Stamp Higher Byte */ 43 u8 tsl; /* Time Stamp Lower Byte */ 44 }; 45 46 struct rcar_can_regs { 47 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ 48 u32 mkr_2_9[8]; /* Mask Registers 2-9 */ 49 u32 fidcr[2]; /* FIFO Received ID Compare Register */ 50 u32 mkivlr1; /* Mask Invalid Register 1 */ 51 u32 mier1; /* Mailbox Interrupt Enable Register 1 */ 52 u32 mkr_0_1[2]; /* Mask Registers 0-1 */ 53 u32 mkivlr0; /* Mask Invalid Register 0*/ 54 u32 mier0; /* Mailbox Interrupt Enable Register 0 */ 55 u8 pad_440[0x3c0]; 56 u8 mctl[64]; /* Message Control Registers */ 57 u16 ctlr; /* Control Register */ 58 u16 str; /* Status register */ 59 u8 bcr[3]; /* Bit Configuration Register */ 60 u8 clkr; /* Clock Select Register */ 61 u8 rfcr; /* Receive FIFO Control Register */ 62 u8 rfpcr; /* Receive FIFO Pointer Control Register */ 63 u8 tfcr; /* Transmit FIFO Control Register */ 64 u8 tfpcr; /* Transmit FIFO Pointer Control Register */ 65 u8 eier; /* Error Interrupt Enable Register */ 66 u8 eifr; /* Error Interrupt Factor Judge Register */ 67 u8 recr; /* Receive Error Count Register */ 68 u8 tecr; /* Transmit Error Count Register */ 69 u8 ecsr; /* Error Code Store Register */ 70 u8 cssr; /* Channel Search Support Register */ 71 u8 mssr; /* Mailbox Search Status Register */ 72 u8 msmr; /* Mailbox Search Mode Register */ 73 u16 tsr; /* Time Stamp Register */ 74 u8 afsr; /* Acceptance Filter Support Register */ 75 u8 pad_857; 76 u8 tcr; /* Test Control Register */ 77 u8 pad_859[7]; 78 u8 ier; /* Interrupt Enable Register */ 79 u8 isr; /* Interrupt Status Register */ 80 u8 pad_862; 81 u8 mbsmr; /* Mailbox Search Mask Register */ 82 }; 83 84 struct rcar_can_priv { 85 struct can_priv can; /* Must be the first member! */ 86 struct net_device *ndev; 87 struct napi_struct napi; 88 struct rcar_can_regs __iomem *regs; 89 struct clk *clk; 90 struct clk *can_clk; 91 u8 tx_dlc[RCAR_CAN_FIFO_DEPTH]; 92 u32 tx_head; 93 u32 tx_tail; 94 u8 clock_select; 95 u8 ier; 96 }; 97 98 static const struct can_bittiming_const rcar_can_bittiming_const = { 99 .name = RCAR_CAN_DRV_NAME, 100 .tseg1_min = 4, 101 .tseg1_max = 16, 102 .tseg2_min = 2, 103 .tseg2_max = 8, 104 .sjw_max = 4, 105 .brp_min = 1, 106 .brp_max = 1024, 107 .brp_inc = 1, 108 }; 109 110 /* Control Register bits */ 111 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ 112 #define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ 113 /* at bus-off entry */ 114 #define RCAR_CAN_CTLR_SLPM (1 << 10) 115 #define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ 116 #define RCAR_CAN_CTLR_CANM_HALT (1 << 9) 117 #define RCAR_CAN_CTLR_CANM_RESET (1 << 8) 118 #define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) 119 #define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ 120 #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ 121 #define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ 122 #define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ 123 124 /* Status Register bits */ 125 #define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ 126 127 /* FIFO Received ID Compare Registers 0 and 1 bits */ 128 #define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ 129 #define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ 130 131 /* Receive FIFO Control Register bits */ 132 #define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ 133 #define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ 134 135 /* Transmit FIFO Control Register bits */ 136 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ 137 /* Number Status Bits */ 138 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ 139 /* Message Number Status Bits */ 140 #define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ 141 142 #define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ 143 /* for Rx mailboxes 0-31 */ 144 #define RCAR_CAN_N_RX_MKREGS2 8 145 146 /* Bit Configuration Register settings */ 147 #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) 148 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) 149 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) 150 #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) 151 152 /* Mailbox and Mask Registers bits */ 153 #define RCAR_CAN_IDE (1 << 31) 154 #define RCAR_CAN_RTR (1 << 30) 155 #define RCAR_CAN_SID_SHIFT 18 156 157 /* Mailbox Interrupt Enable Register 1 bits */ 158 #define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ 159 #define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ 160 161 /* Interrupt Enable Register bits */ 162 #define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ 163 #define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ 164 /* Enable Bit */ 165 #define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ 166 /* Enable Bit */ 167 /* Interrupt Status Register bits */ 168 #define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ 169 #define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ 170 /* Status Bit */ 171 #define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ 172 /* Status Bit */ 173 174 /* Error Interrupt Enable Register bits */ 175 #define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ 176 #define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ 177 /* Interrupt Enable */ 178 #define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ 179 #define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ 180 #define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ 181 #define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ 182 #define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ 183 #define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ 184 185 /* Error Interrupt Factor Judge Register bits */ 186 #define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ 187 #define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ 188 /* Detect Flag */ 189 #define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ 190 #define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ 191 #define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ 192 #define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ 193 #define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ 194 #define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ 195 196 /* Error Code Store Register bits */ 197 #define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ 198 #define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ 199 #define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ 200 #define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ 201 #define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ 202 #define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ 203 #define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ 204 #define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ 205 206 #define RCAR_CAN_NAPI_WEIGHT 4 207 #define MAX_STR_READS 0x100 208 209 static void tx_failure_cleanup(struct net_device *ndev) 210 { 211 int i; 212 213 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) 214 can_free_echo_skb(ndev, i); 215 } 216 217 static void rcar_can_error(struct net_device *ndev) 218 { 219 struct rcar_can_priv *priv = netdev_priv(ndev); 220 struct net_device_stats *stats = &ndev->stats; 221 struct can_frame *cf; 222 struct sk_buff *skb; 223 u8 eifr, txerr = 0, rxerr = 0; 224 225 /* Propagate the error condition to the CAN stack */ 226 skb = alloc_can_err_skb(ndev, &cf); 227 228 eifr = readb(&priv->regs->eifr); 229 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { 230 txerr = readb(&priv->regs->tecr); 231 rxerr = readb(&priv->regs->recr); 232 if (skb) { 233 cf->can_id |= CAN_ERR_CRTL; 234 cf->data[6] = txerr; 235 cf->data[7] = rxerr; 236 } 237 } 238 if (eifr & RCAR_CAN_EIFR_BEIF) { 239 int rx_errors = 0, tx_errors = 0; 240 u8 ecsr; 241 242 netdev_dbg(priv->ndev, "Bus error interrupt:\n"); 243 if (skb) 244 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 245 246 ecsr = readb(&priv->regs->ecsr); 247 if (ecsr & RCAR_CAN_ECSR_ADEF) { 248 netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); 249 tx_errors++; 250 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); 251 if (skb) 252 cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL; 253 } 254 if (ecsr & RCAR_CAN_ECSR_BE0F) { 255 netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); 256 tx_errors++; 257 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); 258 if (skb) 259 cf->data[2] |= CAN_ERR_PROT_BIT0; 260 } 261 if (ecsr & RCAR_CAN_ECSR_BE1F) { 262 netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); 263 tx_errors++; 264 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); 265 if (skb) 266 cf->data[2] |= CAN_ERR_PROT_BIT1; 267 } 268 if (ecsr & RCAR_CAN_ECSR_CEF) { 269 netdev_dbg(priv->ndev, "CRC Error\n"); 270 rx_errors++; 271 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); 272 if (skb) 273 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 274 } 275 if (ecsr & RCAR_CAN_ECSR_AEF) { 276 netdev_dbg(priv->ndev, "ACK Error\n"); 277 tx_errors++; 278 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); 279 if (skb) { 280 cf->can_id |= CAN_ERR_ACK; 281 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 282 } 283 } 284 if (ecsr & RCAR_CAN_ECSR_FEF) { 285 netdev_dbg(priv->ndev, "Form Error\n"); 286 rx_errors++; 287 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); 288 if (skb) 289 cf->data[2] |= CAN_ERR_PROT_FORM; 290 } 291 if (ecsr & RCAR_CAN_ECSR_SEF) { 292 netdev_dbg(priv->ndev, "Stuff Error\n"); 293 rx_errors++; 294 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); 295 if (skb) 296 cf->data[2] |= CAN_ERR_PROT_STUFF; 297 } 298 299 priv->can.can_stats.bus_error++; 300 ndev->stats.rx_errors += rx_errors; 301 ndev->stats.tx_errors += tx_errors; 302 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); 303 } 304 if (eifr & RCAR_CAN_EIFR_EWIF) { 305 netdev_dbg(priv->ndev, "Error warning interrupt\n"); 306 priv->can.state = CAN_STATE_ERROR_WARNING; 307 priv->can.can_stats.error_warning++; 308 /* Clear interrupt condition */ 309 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); 310 if (skb) 311 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 312 CAN_ERR_CRTL_RX_WARNING; 313 } 314 if (eifr & RCAR_CAN_EIFR_EPIF) { 315 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 316 priv->can.state = CAN_STATE_ERROR_PASSIVE; 317 priv->can.can_stats.error_passive++; 318 /* Clear interrupt condition */ 319 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); 320 if (skb) 321 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 322 CAN_ERR_CRTL_RX_PASSIVE; 323 } 324 if (eifr & RCAR_CAN_EIFR_BOEIF) { 325 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); 326 tx_failure_cleanup(ndev); 327 priv->ier = RCAR_CAN_IER_ERSIE; 328 writeb(priv->ier, &priv->regs->ier); 329 priv->can.state = CAN_STATE_BUS_OFF; 330 /* Clear interrupt condition */ 331 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); 332 priv->can.can_stats.bus_off++; 333 can_bus_off(ndev); 334 if (skb) 335 cf->can_id |= CAN_ERR_BUSOFF; 336 } 337 if (eifr & RCAR_CAN_EIFR_ORIF) { 338 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); 339 ndev->stats.rx_over_errors++; 340 ndev->stats.rx_errors++; 341 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); 342 if (skb) { 343 cf->can_id |= CAN_ERR_CRTL; 344 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 345 } 346 } 347 if (eifr & RCAR_CAN_EIFR_OLIF) { 348 netdev_dbg(priv->ndev, 349 "Overload Frame Transmission error interrupt\n"); 350 ndev->stats.rx_over_errors++; 351 ndev->stats.rx_errors++; 352 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); 353 if (skb) { 354 cf->can_id |= CAN_ERR_PROT; 355 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 356 } 357 } 358 359 if (skb) { 360 stats->rx_packets++; 361 stats->rx_bytes += cf->can_dlc; 362 netif_rx(skb); 363 } 364 } 365 366 static void rcar_can_tx_done(struct net_device *ndev) 367 { 368 struct rcar_can_priv *priv = netdev_priv(ndev); 369 struct net_device_stats *stats = &ndev->stats; 370 u8 isr; 371 372 while (1) { 373 u8 unsent = readb(&priv->regs->tfcr); 374 375 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> 376 RCAR_CAN_TFCR_TFUST_SHIFT; 377 if (priv->tx_head - priv->tx_tail <= unsent) 378 break; 379 stats->tx_packets++; 380 stats->tx_bytes += priv->tx_dlc[priv->tx_tail % 381 RCAR_CAN_FIFO_DEPTH]; 382 priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0; 383 can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH); 384 priv->tx_tail++; 385 netif_wake_queue(ndev); 386 } 387 /* Clear interrupt */ 388 isr = readb(&priv->regs->isr); 389 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); 390 can_led_event(ndev, CAN_LED_EVENT_TX); 391 } 392 393 static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) 394 { 395 struct net_device *ndev = dev_id; 396 struct rcar_can_priv *priv = netdev_priv(ndev); 397 u8 isr; 398 399 isr = readb(&priv->regs->isr); 400 if (!(isr & priv->ier)) 401 return IRQ_NONE; 402 403 if (isr & RCAR_CAN_ISR_ERSF) 404 rcar_can_error(ndev); 405 406 if (isr & RCAR_CAN_ISR_TXFF) 407 rcar_can_tx_done(ndev); 408 409 if (isr & RCAR_CAN_ISR_RXFF) { 410 if (napi_schedule_prep(&priv->napi)) { 411 /* Disable Rx FIFO interrupts */ 412 priv->ier &= ~RCAR_CAN_IER_RXFIE; 413 writeb(priv->ier, &priv->regs->ier); 414 __napi_schedule(&priv->napi); 415 } 416 } 417 418 return IRQ_HANDLED; 419 } 420 421 static void rcar_can_set_bittiming(struct net_device *dev) 422 { 423 struct rcar_can_priv *priv = netdev_priv(dev); 424 struct can_bittiming *bt = &priv->can.bittiming; 425 u32 bcr; 426 427 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | 428 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | 429 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); 430 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. 431 * All the registers are big-endian but they get byte-swapped on 32-bit 432 * read/write (but not on 8-bit, contrary to the manuals)... 433 */ 434 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); 435 } 436 437 static void rcar_can_start(struct net_device *ndev) 438 { 439 struct rcar_can_priv *priv = netdev_priv(ndev); 440 u16 ctlr; 441 int i; 442 443 /* Set controller to known mode: 444 * - FIFO mailbox mode 445 * - accept all messages 446 * - overrun mode 447 * CAN is in sleep mode after MCU hardware or software reset. 448 */ 449 ctlr = readw(&priv->regs->ctlr); 450 ctlr &= ~RCAR_CAN_CTLR_SLPM; 451 writew(ctlr, &priv->regs->ctlr); 452 /* Go to reset mode */ 453 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 454 writew(ctlr, &priv->regs->ctlr); 455 for (i = 0; i < MAX_STR_READS; i++) { 456 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 457 break; 458 } 459 rcar_can_set_bittiming(ndev); 460 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ 461 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ 462 /* at bus-off */ 463 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ 464 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ 465 writew(ctlr, &priv->regs->ctlr); 466 467 /* Accept all SID and EID */ 468 writel(0, &priv->regs->mkr_2_9[6]); 469 writel(0, &priv->regs->mkr_2_9[7]); 470 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ 471 writel(0, &priv->regs->mkivlr1); 472 /* Accept all frames */ 473 writel(0, &priv->regs->fidcr[0]); 474 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); 475 /* Enable and configure FIFO mailbox interrupts */ 476 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); 477 478 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | 479 RCAR_CAN_IER_TXFIE; 480 writeb(priv->ier, &priv->regs->ier); 481 482 /* Accumulate error codes */ 483 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); 484 /* Enable error interrupts */ 485 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | 486 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? 487 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | 488 RCAR_CAN_EIER_OLIE, &priv->regs->eier); 489 priv->can.state = CAN_STATE_ERROR_ACTIVE; 490 491 /* Go to operation mode */ 492 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); 493 for (i = 0; i < MAX_STR_READS; i++) { 494 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) 495 break; 496 } 497 /* Enable Rx and Tx FIFO */ 498 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); 499 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); 500 } 501 502 static int rcar_can_open(struct net_device *ndev) 503 { 504 struct rcar_can_priv *priv = netdev_priv(ndev); 505 int err; 506 507 err = clk_prepare_enable(priv->clk); 508 if (err) { 509 netdev_err(ndev, 510 "failed to enable peripheral clock, error %d\n", 511 err); 512 goto out; 513 } 514 err = clk_prepare_enable(priv->can_clk); 515 if (err) { 516 netdev_err(ndev, "failed to enable CAN clock, error %d\n", 517 err); 518 goto out_clock; 519 } 520 err = open_candev(ndev); 521 if (err) { 522 netdev_err(ndev, "open_candev() failed, error %d\n", err); 523 goto out_can_clock; 524 } 525 napi_enable(&priv->napi); 526 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); 527 if (err) { 528 netdev_err(ndev, "request_irq(%d) failed, error %d\n", 529 ndev->irq, err); 530 goto out_close; 531 } 532 can_led_event(ndev, CAN_LED_EVENT_OPEN); 533 rcar_can_start(ndev); 534 netif_start_queue(ndev); 535 return 0; 536 out_close: 537 napi_disable(&priv->napi); 538 close_candev(ndev); 539 out_can_clock: 540 clk_disable_unprepare(priv->can_clk); 541 out_clock: 542 clk_disable_unprepare(priv->clk); 543 out: 544 return err; 545 } 546 547 static void rcar_can_stop(struct net_device *ndev) 548 { 549 struct rcar_can_priv *priv = netdev_priv(ndev); 550 u16 ctlr; 551 int i; 552 553 /* Go to (force) reset mode */ 554 ctlr = readw(&priv->regs->ctlr); 555 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 556 writew(ctlr, &priv->regs->ctlr); 557 for (i = 0; i < MAX_STR_READS; i++) { 558 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 559 break; 560 } 561 writel(0, &priv->regs->mier0); 562 writel(0, &priv->regs->mier1); 563 writeb(0, &priv->regs->ier); 564 writeb(0, &priv->regs->eier); 565 /* Go to sleep mode */ 566 ctlr |= RCAR_CAN_CTLR_SLPM; 567 writew(ctlr, &priv->regs->ctlr); 568 priv->can.state = CAN_STATE_STOPPED; 569 } 570 571 static int rcar_can_close(struct net_device *ndev) 572 { 573 struct rcar_can_priv *priv = netdev_priv(ndev); 574 575 netif_stop_queue(ndev); 576 rcar_can_stop(ndev); 577 free_irq(ndev->irq, ndev); 578 napi_disable(&priv->napi); 579 clk_disable_unprepare(priv->can_clk); 580 clk_disable_unprepare(priv->clk); 581 close_candev(ndev); 582 can_led_event(ndev, CAN_LED_EVENT_STOP); 583 return 0; 584 } 585 586 static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, 587 struct net_device *ndev) 588 { 589 struct rcar_can_priv *priv = netdev_priv(ndev); 590 struct can_frame *cf = (struct can_frame *)skb->data; 591 u32 data, i; 592 593 if (can_dropped_invalid_skb(ndev, skb)) 594 return NETDEV_TX_OK; 595 596 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 597 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; 598 else /* Standard frame format */ 599 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; 600 601 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ 602 data |= RCAR_CAN_RTR; 603 } else { 604 for (i = 0; i < cf->can_dlc; i++) 605 writeb(cf->data[i], 606 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); 607 } 608 609 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); 610 611 writeb(cf->can_dlc, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); 612 613 priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->can_dlc; 614 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH); 615 priv->tx_head++; 616 /* Start Tx: write 0xff to the TFPCR register to increment 617 * the CPU-side pointer for the transmit FIFO to the next 618 * mailbox location 619 */ 620 writeb(0xff, &priv->regs->tfpcr); 621 /* Stop the queue if we've filled all FIFO entries */ 622 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) 623 netif_stop_queue(ndev); 624 625 return NETDEV_TX_OK; 626 } 627 628 static const struct net_device_ops rcar_can_netdev_ops = { 629 .ndo_open = rcar_can_open, 630 .ndo_stop = rcar_can_close, 631 .ndo_start_xmit = rcar_can_start_xmit, 632 .ndo_change_mtu = can_change_mtu, 633 }; 634 635 static void rcar_can_rx_pkt(struct rcar_can_priv *priv) 636 { 637 struct net_device_stats *stats = &priv->ndev->stats; 638 struct can_frame *cf; 639 struct sk_buff *skb; 640 u32 data; 641 u8 dlc; 642 643 skb = alloc_can_skb(priv->ndev, &cf); 644 if (!skb) { 645 stats->rx_dropped++; 646 return; 647 } 648 649 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); 650 if (data & RCAR_CAN_IDE) 651 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 652 else 653 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; 654 655 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); 656 cf->can_dlc = get_can_dlc(dlc); 657 if (data & RCAR_CAN_RTR) { 658 cf->can_id |= CAN_RTR_FLAG; 659 } else { 660 for (dlc = 0; dlc < cf->can_dlc; dlc++) 661 cf->data[dlc] = 662 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); 663 } 664 665 can_led_event(priv->ndev, CAN_LED_EVENT_RX); 666 667 stats->rx_bytes += cf->can_dlc; 668 stats->rx_packets++; 669 netif_receive_skb(skb); 670 } 671 672 static int rcar_can_rx_poll(struct napi_struct *napi, int quota) 673 { 674 struct rcar_can_priv *priv = container_of(napi, 675 struct rcar_can_priv, napi); 676 int num_pkts; 677 678 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 679 u8 rfcr, isr; 680 681 isr = readb(&priv->regs->isr); 682 /* Clear interrupt bit */ 683 if (isr & RCAR_CAN_ISR_RXFF) 684 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); 685 rfcr = readb(&priv->regs->rfcr); 686 if (rfcr & RCAR_CAN_RFCR_RFEST) 687 break; 688 rcar_can_rx_pkt(priv); 689 /* Write 0xff to the RFPCR register to increment 690 * the CPU-side pointer for the receive FIFO 691 * to the next mailbox location 692 */ 693 writeb(0xff, &priv->regs->rfpcr); 694 } 695 /* All packets processed */ 696 if (num_pkts < quota) { 697 napi_complete_done(napi, num_pkts); 698 priv->ier |= RCAR_CAN_IER_RXFIE; 699 writeb(priv->ier, &priv->regs->ier); 700 } 701 return num_pkts; 702 } 703 704 static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 705 { 706 switch (mode) { 707 case CAN_MODE_START: 708 rcar_can_start(ndev); 709 netif_wake_queue(ndev); 710 return 0; 711 default: 712 return -EOPNOTSUPP; 713 } 714 } 715 716 static int rcar_can_get_berr_counter(const struct net_device *dev, 717 struct can_berr_counter *bec) 718 { 719 struct rcar_can_priv *priv = netdev_priv(dev); 720 int err; 721 722 err = clk_prepare_enable(priv->clk); 723 if (err) 724 return err; 725 bec->txerr = readb(&priv->regs->tecr); 726 bec->rxerr = readb(&priv->regs->recr); 727 clk_disable_unprepare(priv->clk); 728 return 0; 729 } 730 731 static const char * const clock_names[] = { 732 [CLKR_CLKP1] = "clkp1", 733 [CLKR_CLKP2] = "clkp2", 734 [CLKR_CLKEXT] = "can_clk", 735 }; 736 737 static int rcar_can_probe(struct platform_device *pdev) 738 { 739 struct rcar_can_platform_data *pdata; 740 struct rcar_can_priv *priv; 741 struct net_device *ndev; 742 struct resource *mem; 743 void __iomem *addr; 744 u32 clock_select = CLKR_CLKP1; 745 int err = -ENODEV; 746 int irq; 747 748 if (pdev->dev.of_node) { 749 of_property_read_u32(pdev->dev.of_node, 750 "renesas,can-clock-select", &clock_select); 751 } else { 752 pdata = dev_get_platdata(&pdev->dev); 753 if (!pdata) { 754 dev_err(&pdev->dev, "No platform data provided!\n"); 755 goto fail; 756 } 757 clock_select = pdata->clock_select; 758 } 759 760 irq = platform_get_irq(pdev, 0); 761 if (irq < 0) { 762 dev_err(&pdev->dev, "No IRQ resource\n"); 763 err = irq; 764 goto fail; 765 } 766 767 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 768 addr = devm_ioremap_resource(&pdev->dev, mem); 769 if (IS_ERR(addr)) { 770 err = PTR_ERR(addr); 771 goto fail; 772 } 773 774 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); 775 if (!ndev) { 776 dev_err(&pdev->dev, "alloc_candev() failed\n"); 777 err = -ENOMEM; 778 goto fail; 779 } 780 781 priv = netdev_priv(ndev); 782 783 priv->clk = devm_clk_get(&pdev->dev, "clkp1"); 784 if (IS_ERR(priv->clk)) { 785 err = PTR_ERR(priv->clk); 786 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n", 787 err); 788 goto fail_clk; 789 } 790 791 if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) { 792 err = -EINVAL; 793 dev_err(&pdev->dev, "invalid CAN clock selected\n"); 794 goto fail_clk; 795 } 796 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); 797 if (IS_ERR(priv->can_clk)) { 798 err = PTR_ERR(priv->can_clk); 799 dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err); 800 goto fail_clk; 801 } 802 803 ndev->netdev_ops = &rcar_can_netdev_ops; 804 ndev->irq = irq; 805 ndev->flags |= IFF_ECHO; 806 priv->ndev = ndev; 807 priv->regs = addr; 808 priv->clock_select = clock_select; 809 priv->can.clock.freq = clk_get_rate(priv->can_clk); 810 priv->can.bittiming_const = &rcar_can_bittiming_const; 811 priv->can.do_set_mode = rcar_can_do_set_mode; 812 priv->can.do_get_berr_counter = rcar_can_get_berr_counter; 813 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 814 platform_set_drvdata(pdev, ndev); 815 SET_NETDEV_DEV(ndev, &pdev->dev); 816 817 netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll, 818 RCAR_CAN_NAPI_WEIGHT); 819 err = register_candev(ndev); 820 if (err) { 821 dev_err(&pdev->dev, "register_candev() failed, error %d\n", 822 err); 823 goto fail_candev; 824 } 825 826 devm_can_led_init(ndev); 827 828 dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq); 829 830 return 0; 831 fail_candev: 832 netif_napi_del(&priv->napi); 833 fail_clk: 834 free_candev(ndev); 835 fail: 836 return err; 837 } 838 839 static int rcar_can_remove(struct platform_device *pdev) 840 { 841 struct net_device *ndev = platform_get_drvdata(pdev); 842 struct rcar_can_priv *priv = netdev_priv(ndev); 843 844 unregister_candev(ndev); 845 netif_napi_del(&priv->napi); 846 free_candev(ndev); 847 return 0; 848 } 849 850 static int __maybe_unused rcar_can_suspend(struct device *dev) 851 { 852 struct net_device *ndev = dev_get_drvdata(dev); 853 struct rcar_can_priv *priv = netdev_priv(ndev); 854 u16 ctlr; 855 856 if (netif_running(ndev)) { 857 netif_stop_queue(ndev); 858 netif_device_detach(ndev); 859 } 860 ctlr = readw(&priv->regs->ctlr); 861 ctlr |= RCAR_CAN_CTLR_CANM_HALT; 862 writew(ctlr, &priv->regs->ctlr); 863 ctlr |= RCAR_CAN_CTLR_SLPM; 864 writew(ctlr, &priv->regs->ctlr); 865 priv->can.state = CAN_STATE_SLEEPING; 866 867 clk_disable(priv->clk); 868 return 0; 869 } 870 871 static int __maybe_unused rcar_can_resume(struct device *dev) 872 { 873 struct net_device *ndev = dev_get_drvdata(dev); 874 struct rcar_can_priv *priv = netdev_priv(ndev); 875 u16 ctlr; 876 int err; 877 878 err = clk_enable(priv->clk); 879 if (err) { 880 netdev_err(ndev, "clk_enable() failed, error %d\n", err); 881 return err; 882 } 883 884 ctlr = readw(&priv->regs->ctlr); 885 ctlr &= ~RCAR_CAN_CTLR_SLPM; 886 writew(ctlr, &priv->regs->ctlr); 887 ctlr &= ~RCAR_CAN_CTLR_CANM; 888 writew(ctlr, &priv->regs->ctlr); 889 priv->can.state = CAN_STATE_ERROR_ACTIVE; 890 891 if (netif_running(ndev)) { 892 netif_device_attach(ndev); 893 netif_start_queue(ndev); 894 } 895 return 0; 896 } 897 898 static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); 899 900 static const struct of_device_id rcar_can_of_table[] __maybe_unused = { 901 { .compatible = "renesas,can-r8a7778" }, 902 { .compatible = "renesas,can-r8a7779" }, 903 { .compatible = "renesas,can-r8a7790" }, 904 { .compatible = "renesas,can-r8a7791" }, 905 { .compatible = "renesas,rcar-gen1-can" }, 906 { .compatible = "renesas,rcar-gen2-can" }, 907 { .compatible = "renesas,rcar-gen3-can" }, 908 { } 909 }; 910 MODULE_DEVICE_TABLE(of, rcar_can_of_table); 911 912 static struct platform_driver rcar_can_driver = { 913 .driver = { 914 .name = RCAR_CAN_DRV_NAME, 915 .of_match_table = of_match_ptr(rcar_can_of_table), 916 .pm = &rcar_can_pm_ops, 917 }, 918 .probe = rcar_can_probe, 919 .remove = rcar_can_remove, 920 }; 921 922 module_platform_driver(rcar_can_driver); 923 924 MODULE_AUTHOR("Cogent Embedded, Inc."); 925 MODULE_LICENSE("GPL"); 926 MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); 927 MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); 928