1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Renesas R-Car CAN device driver 3 * 4 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/kernel.h> 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/errno.h> 13 #include <linux/netdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/can/led.h> 16 #include <linux/can/dev.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 20 #define RCAR_CAN_DRV_NAME "rcar_can" 21 22 /* Clock Select Register settings */ 23 enum CLKR { 24 CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */ 25 CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */ 26 CLKR_CLKEXT = 3, /* Externally input clock */ 27 }; 28 29 #define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ 30 BIT(CLKR_CLKEXT)) 31 32 /* Mailbox configuration: 33 * mailbox 60 - 63 - Rx FIFO mailboxes 34 * mailbox 56 - 59 - Tx FIFO mailboxes 35 * non-FIFO mailboxes are not used 36 */ 37 #define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ 38 #define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ 39 #define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ 40 #define RCAR_CAN_FIFO_DEPTH 4 41 42 /* Mailbox registers structure */ 43 struct rcar_can_mbox_regs { 44 u32 id; /* IDE and RTR bits, SID and EID */ 45 u8 stub; /* Not used */ 46 u8 dlc; /* Data Length Code - bits [0..3] */ 47 u8 data[8]; /* Data Bytes */ 48 u8 tsh; /* Time Stamp Higher Byte */ 49 u8 tsl; /* Time Stamp Lower Byte */ 50 }; 51 52 struct rcar_can_regs { 53 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ 54 u32 mkr_2_9[8]; /* Mask Registers 2-9 */ 55 u32 fidcr[2]; /* FIFO Received ID Compare Register */ 56 u32 mkivlr1; /* Mask Invalid Register 1 */ 57 u32 mier1; /* Mailbox Interrupt Enable Register 1 */ 58 u32 mkr_0_1[2]; /* Mask Registers 0-1 */ 59 u32 mkivlr0; /* Mask Invalid Register 0*/ 60 u32 mier0; /* Mailbox Interrupt Enable Register 0 */ 61 u8 pad_440[0x3c0]; 62 u8 mctl[64]; /* Message Control Registers */ 63 u16 ctlr; /* Control Register */ 64 u16 str; /* Status register */ 65 u8 bcr[3]; /* Bit Configuration Register */ 66 u8 clkr; /* Clock Select Register */ 67 u8 rfcr; /* Receive FIFO Control Register */ 68 u8 rfpcr; /* Receive FIFO Pointer Control Register */ 69 u8 tfcr; /* Transmit FIFO Control Register */ 70 u8 tfpcr; /* Transmit FIFO Pointer Control Register */ 71 u8 eier; /* Error Interrupt Enable Register */ 72 u8 eifr; /* Error Interrupt Factor Judge Register */ 73 u8 recr; /* Receive Error Count Register */ 74 u8 tecr; /* Transmit Error Count Register */ 75 u8 ecsr; /* Error Code Store Register */ 76 u8 cssr; /* Channel Search Support Register */ 77 u8 mssr; /* Mailbox Search Status Register */ 78 u8 msmr; /* Mailbox Search Mode Register */ 79 u16 tsr; /* Time Stamp Register */ 80 u8 afsr; /* Acceptance Filter Support Register */ 81 u8 pad_857; 82 u8 tcr; /* Test Control Register */ 83 u8 pad_859[7]; 84 u8 ier; /* Interrupt Enable Register */ 85 u8 isr; /* Interrupt Status Register */ 86 u8 pad_862; 87 u8 mbsmr; /* Mailbox Search Mask Register */ 88 }; 89 90 struct rcar_can_priv { 91 struct can_priv can; /* Must be the first member! */ 92 struct net_device *ndev; 93 struct napi_struct napi; 94 struct rcar_can_regs __iomem *regs; 95 struct clk *clk; 96 struct clk *can_clk; 97 u8 tx_dlc[RCAR_CAN_FIFO_DEPTH]; 98 u32 tx_head; 99 u32 tx_tail; 100 u8 clock_select; 101 u8 ier; 102 }; 103 104 static const struct can_bittiming_const rcar_can_bittiming_const = { 105 .name = RCAR_CAN_DRV_NAME, 106 .tseg1_min = 4, 107 .tseg1_max = 16, 108 .tseg2_min = 2, 109 .tseg2_max = 8, 110 .sjw_max = 4, 111 .brp_min = 1, 112 .brp_max = 1024, 113 .brp_inc = 1, 114 }; 115 116 /* Control Register bits */ 117 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ 118 #define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ 119 /* at bus-off entry */ 120 #define RCAR_CAN_CTLR_SLPM (1 << 10) 121 #define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ 122 #define RCAR_CAN_CTLR_CANM_HALT (1 << 9) 123 #define RCAR_CAN_CTLR_CANM_RESET (1 << 8) 124 #define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) 125 #define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ 126 #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ 127 #define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ 128 #define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ 129 130 /* Status Register bits */ 131 #define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ 132 133 /* FIFO Received ID Compare Registers 0 and 1 bits */ 134 #define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ 135 #define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ 136 137 /* Receive FIFO Control Register bits */ 138 #define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ 139 #define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ 140 141 /* Transmit FIFO Control Register bits */ 142 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ 143 /* Number Status Bits */ 144 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ 145 /* Message Number Status Bits */ 146 #define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ 147 148 #define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ 149 /* for Rx mailboxes 0-31 */ 150 #define RCAR_CAN_N_RX_MKREGS2 8 151 152 /* Bit Configuration Register settings */ 153 #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) 154 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) 155 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) 156 #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) 157 158 /* Mailbox and Mask Registers bits */ 159 #define RCAR_CAN_IDE (1 << 31) 160 #define RCAR_CAN_RTR (1 << 30) 161 #define RCAR_CAN_SID_SHIFT 18 162 163 /* Mailbox Interrupt Enable Register 1 bits */ 164 #define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ 165 #define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ 166 167 /* Interrupt Enable Register bits */ 168 #define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ 169 #define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ 170 /* Enable Bit */ 171 #define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ 172 /* Enable Bit */ 173 /* Interrupt Status Register bits */ 174 #define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ 175 #define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ 176 /* Status Bit */ 177 #define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ 178 /* Status Bit */ 179 180 /* Error Interrupt Enable Register bits */ 181 #define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ 182 #define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ 183 /* Interrupt Enable */ 184 #define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ 185 #define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ 186 #define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ 187 #define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ 188 #define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ 189 #define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ 190 191 /* Error Interrupt Factor Judge Register bits */ 192 #define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ 193 #define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ 194 /* Detect Flag */ 195 #define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ 196 #define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ 197 #define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ 198 #define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ 199 #define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ 200 #define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ 201 202 /* Error Code Store Register bits */ 203 #define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ 204 #define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ 205 #define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ 206 #define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ 207 #define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ 208 #define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ 209 #define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ 210 #define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ 211 212 #define RCAR_CAN_NAPI_WEIGHT 4 213 #define MAX_STR_READS 0x100 214 215 static void tx_failure_cleanup(struct net_device *ndev) 216 { 217 int i; 218 219 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) 220 can_free_echo_skb(ndev, i); 221 } 222 223 static void rcar_can_error(struct net_device *ndev) 224 { 225 struct rcar_can_priv *priv = netdev_priv(ndev); 226 struct net_device_stats *stats = &ndev->stats; 227 struct can_frame *cf; 228 struct sk_buff *skb; 229 u8 eifr, txerr = 0, rxerr = 0; 230 231 /* Propagate the error condition to the CAN stack */ 232 skb = alloc_can_err_skb(ndev, &cf); 233 234 eifr = readb(&priv->regs->eifr); 235 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { 236 txerr = readb(&priv->regs->tecr); 237 rxerr = readb(&priv->regs->recr); 238 if (skb) { 239 cf->can_id |= CAN_ERR_CRTL; 240 cf->data[6] = txerr; 241 cf->data[7] = rxerr; 242 } 243 } 244 if (eifr & RCAR_CAN_EIFR_BEIF) { 245 int rx_errors = 0, tx_errors = 0; 246 u8 ecsr; 247 248 netdev_dbg(priv->ndev, "Bus error interrupt:\n"); 249 if (skb) 250 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 251 252 ecsr = readb(&priv->regs->ecsr); 253 if (ecsr & RCAR_CAN_ECSR_ADEF) { 254 netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); 255 tx_errors++; 256 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); 257 if (skb) 258 cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL; 259 } 260 if (ecsr & RCAR_CAN_ECSR_BE0F) { 261 netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); 262 tx_errors++; 263 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); 264 if (skb) 265 cf->data[2] |= CAN_ERR_PROT_BIT0; 266 } 267 if (ecsr & RCAR_CAN_ECSR_BE1F) { 268 netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); 269 tx_errors++; 270 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); 271 if (skb) 272 cf->data[2] |= CAN_ERR_PROT_BIT1; 273 } 274 if (ecsr & RCAR_CAN_ECSR_CEF) { 275 netdev_dbg(priv->ndev, "CRC Error\n"); 276 rx_errors++; 277 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); 278 if (skb) 279 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 280 } 281 if (ecsr & RCAR_CAN_ECSR_AEF) { 282 netdev_dbg(priv->ndev, "ACK Error\n"); 283 tx_errors++; 284 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); 285 if (skb) { 286 cf->can_id |= CAN_ERR_ACK; 287 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 288 } 289 } 290 if (ecsr & RCAR_CAN_ECSR_FEF) { 291 netdev_dbg(priv->ndev, "Form Error\n"); 292 rx_errors++; 293 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); 294 if (skb) 295 cf->data[2] |= CAN_ERR_PROT_FORM; 296 } 297 if (ecsr & RCAR_CAN_ECSR_SEF) { 298 netdev_dbg(priv->ndev, "Stuff Error\n"); 299 rx_errors++; 300 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); 301 if (skb) 302 cf->data[2] |= CAN_ERR_PROT_STUFF; 303 } 304 305 priv->can.can_stats.bus_error++; 306 ndev->stats.rx_errors += rx_errors; 307 ndev->stats.tx_errors += tx_errors; 308 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); 309 } 310 if (eifr & RCAR_CAN_EIFR_EWIF) { 311 netdev_dbg(priv->ndev, "Error warning interrupt\n"); 312 priv->can.state = CAN_STATE_ERROR_WARNING; 313 priv->can.can_stats.error_warning++; 314 /* Clear interrupt condition */ 315 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); 316 if (skb) 317 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 318 CAN_ERR_CRTL_RX_WARNING; 319 } 320 if (eifr & RCAR_CAN_EIFR_EPIF) { 321 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 322 priv->can.state = CAN_STATE_ERROR_PASSIVE; 323 priv->can.can_stats.error_passive++; 324 /* Clear interrupt condition */ 325 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); 326 if (skb) 327 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 328 CAN_ERR_CRTL_RX_PASSIVE; 329 } 330 if (eifr & RCAR_CAN_EIFR_BOEIF) { 331 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); 332 tx_failure_cleanup(ndev); 333 priv->ier = RCAR_CAN_IER_ERSIE; 334 writeb(priv->ier, &priv->regs->ier); 335 priv->can.state = CAN_STATE_BUS_OFF; 336 /* Clear interrupt condition */ 337 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); 338 priv->can.can_stats.bus_off++; 339 can_bus_off(ndev); 340 if (skb) 341 cf->can_id |= CAN_ERR_BUSOFF; 342 } 343 if (eifr & RCAR_CAN_EIFR_ORIF) { 344 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); 345 ndev->stats.rx_over_errors++; 346 ndev->stats.rx_errors++; 347 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); 348 if (skb) { 349 cf->can_id |= CAN_ERR_CRTL; 350 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 351 } 352 } 353 if (eifr & RCAR_CAN_EIFR_OLIF) { 354 netdev_dbg(priv->ndev, 355 "Overload Frame Transmission error interrupt\n"); 356 ndev->stats.rx_over_errors++; 357 ndev->stats.rx_errors++; 358 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); 359 if (skb) { 360 cf->can_id |= CAN_ERR_PROT; 361 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 362 } 363 } 364 365 if (skb) { 366 stats->rx_packets++; 367 stats->rx_bytes += cf->len; 368 netif_rx(skb); 369 } 370 } 371 372 static void rcar_can_tx_done(struct net_device *ndev) 373 { 374 struct rcar_can_priv *priv = netdev_priv(ndev); 375 struct net_device_stats *stats = &ndev->stats; 376 u8 isr; 377 378 while (1) { 379 u8 unsent = readb(&priv->regs->tfcr); 380 381 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> 382 RCAR_CAN_TFCR_TFUST_SHIFT; 383 if (priv->tx_head - priv->tx_tail <= unsent) 384 break; 385 stats->tx_packets++; 386 stats->tx_bytes += priv->tx_dlc[priv->tx_tail % 387 RCAR_CAN_FIFO_DEPTH]; 388 priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0; 389 can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH); 390 priv->tx_tail++; 391 netif_wake_queue(ndev); 392 } 393 /* Clear interrupt */ 394 isr = readb(&priv->regs->isr); 395 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); 396 can_led_event(ndev, CAN_LED_EVENT_TX); 397 } 398 399 static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) 400 { 401 struct net_device *ndev = dev_id; 402 struct rcar_can_priv *priv = netdev_priv(ndev); 403 u8 isr; 404 405 isr = readb(&priv->regs->isr); 406 if (!(isr & priv->ier)) 407 return IRQ_NONE; 408 409 if (isr & RCAR_CAN_ISR_ERSF) 410 rcar_can_error(ndev); 411 412 if (isr & RCAR_CAN_ISR_TXFF) 413 rcar_can_tx_done(ndev); 414 415 if (isr & RCAR_CAN_ISR_RXFF) { 416 if (napi_schedule_prep(&priv->napi)) { 417 /* Disable Rx FIFO interrupts */ 418 priv->ier &= ~RCAR_CAN_IER_RXFIE; 419 writeb(priv->ier, &priv->regs->ier); 420 __napi_schedule(&priv->napi); 421 } 422 } 423 424 return IRQ_HANDLED; 425 } 426 427 static void rcar_can_set_bittiming(struct net_device *dev) 428 { 429 struct rcar_can_priv *priv = netdev_priv(dev); 430 struct can_bittiming *bt = &priv->can.bittiming; 431 u32 bcr; 432 433 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | 434 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | 435 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); 436 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. 437 * All the registers are big-endian but they get byte-swapped on 32-bit 438 * read/write (but not on 8-bit, contrary to the manuals)... 439 */ 440 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); 441 } 442 443 static void rcar_can_start(struct net_device *ndev) 444 { 445 struct rcar_can_priv *priv = netdev_priv(ndev); 446 u16 ctlr; 447 int i; 448 449 /* Set controller to known mode: 450 * - FIFO mailbox mode 451 * - accept all messages 452 * - overrun mode 453 * CAN is in sleep mode after MCU hardware or software reset. 454 */ 455 ctlr = readw(&priv->regs->ctlr); 456 ctlr &= ~RCAR_CAN_CTLR_SLPM; 457 writew(ctlr, &priv->regs->ctlr); 458 /* Go to reset mode */ 459 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 460 writew(ctlr, &priv->regs->ctlr); 461 for (i = 0; i < MAX_STR_READS; i++) { 462 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 463 break; 464 } 465 rcar_can_set_bittiming(ndev); 466 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ 467 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ 468 /* at bus-off */ 469 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ 470 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ 471 writew(ctlr, &priv->regs->ctlr); 472 473 /* Accept all SID and EID */ 474 writel(0, &priv->regs->mkr_2_9[6]); 475 writel(0, &priv->regs->mkr_2_9[7]); 476 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ 477 writel(0, &priv->regs->mkivlr1); 478 /* Accept all frames */ 479 writel(0, &priv->regs->fidcr[0]); 480 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); 481 /* Enable and configure FIFO mailbox interrupts */ 482 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); 483 484 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | 485 RCAR_CAN_IER_TXFIE; 486 writeb(priv->ier, &priv->regs->ier); 487 488 /* Accumulate error codes */ 489 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); 490 /* Enable error interrupts */ 491 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | 492 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? 493 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | 494 RCAR_CAN_EIER_OLIE, &priv->regs->eier); 495 priv->can.state = CAN_STATE_ERROR_ACTIVE; 496 497 /* Go to operation mode */ 498 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); 499 for (i = 0; i < MAX_STR_READS; i++) { 500 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) 501 break; 502 } 503 /* Enable Rx and Tx FIFO */ 504 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); 505 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); 506 } 507 508 static int rcar_can_open(struct net_device *ndev) 509 { 510 struct rcar_can_priv *priv = netdev_priv(ndev); 511 int err; 512 513 err = clk_prepare_enable(priv->clk); 514 if (err) { 515 netdev_err(ndev, 516 "failed to enable peripheral clock, error %d\n", 517 err); 518 goto out; 519 } 520 err = clk_prepare_enable(priv->can_clk); 521 if (err) { 522 netdev_err(ndev, "failed to enable CAN clock, error %d\n", 523 err); 524 goto out_clock; 525 } 526 err = open_candev(ndev); 527 if (err) { 528 netdev_err(ndev, "open_candev() failed, error %d\n", err); 529 goto out_can_clock; 530 } 531 napi_enable(&priv->napi); 532 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); 533 if (err) { 534 netdev_err(ndev, "request_irq(%d) failed, error %d\n", 535 ndev->irq, err); 536 goto out_close; 537 } 538 can_led_event(ndev, CAN_LED_EVENT_OPEN); 539 rcar_can_start(ndev); 540 netif_start_queue(ndev); 541 return 0; 542 out_close: 543 napi_disable(&priv->napi); 544 close_candev(ndev); 545 out_can_clock: 546 clk_disable_unprepare(priv->can_clk); 547 out_clock: 548 clk_disable_unprepare(priv->clk); 549 out: 550 return err; 551 } 552 553 static void rcar_can_stop(struct net_device *ndev) 554 { 555 struct rcar_can_priv *priv = netdev_priv(ndev); 556 u16 ctlr; 557 int i; 558 559 /* Go to (force) reset mode */ 560 ctlr = readw(&priv->regs->ctlr); 561 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 562 writew(ctlr, &priv->regs->ctlr); 563 for (i = 0; i < MAX_STR_READS; i++) { 564 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 565 break; 566 } 567 writel(0, &priv->regs->mier0); 568 writel(0, &priv->regs->mier1); 569 writeb(0, &priv->regs->ier); 570 writeb(0, &priv->regs->eier); 571 /* Go to sleep mode */ 572 ctlr |= RCAR_CAN_CTLR_SLPM; 573 writew(ctlr, &priv->regs->ctlr); 574 priv->can.state = CAN_STATE_STOPPED; 575 } 576 577 static int rcar_can_close(struct net_device *ndev) 578 { 579 struct rcar_can_priv *priv = netdev_priv(ndev); 580 581 netif_stop_queue(ndev); 582 rcar_can_stop(ndev); 583 free_irq(ndev->irq, ndev); 584 napi_disable(&priv->napi); 585 clk_disable_unprepare(priv->can_clk); 586 clk_disable_unprepare(priv->clk); 587 close_candev(ndev); 588 can_led_event(ndev, CAN_LED_EVENT_STOP); 589 return 0; 590 } 591 592 static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, 593 struct net_device *ndev) 594 { 595 struct rcar_can_priv *priv = netdev_priv(ndev); 596 struct can_frame *cf = (struct can_frame *)skb->data; 597 u32 data, i; 598 599 if (can_dropped_invalid_skb(ndev, skb)) 600 return NETDEV_TX_OK; 601 602 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 603 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; 604 else /* Standard frame format */ 605 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; 606 607 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ 608 data |= RCAR_CAN_RTR; 609 } else { 610 for (i = 0; i < cf->len; i++) 611 writeb(cf->data[i], 612 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); 613 } 614 615 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); 616 617 writeb(cf->len, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); 618 619 priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->len; 620 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH); 621 priv->tx_head++; 622 /* Start Tx: write 0xff to the TFPCR register to increment 623 * the CPU-side pointer for the transmit FIFO to the next 624 * mailbox location 625 */ 626 writeb(0xff, &priv->regs->tfpcr); 627 /* Stop the queue if we've filled all FIFO entries */ 628 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) 629 netif_stop_queue(ndev); 630 631 return NETDEV_TX_OK; 632 } 633 634 static const struct net_device_ops rcar_can_netdev_ops = { 635 .ndo_open = rcar_can_open, 636 .ndo_stop = rcar_can_close, 637 .ndo_start_xmit = rcar_can_start_xmit, 638 .ndo_change_mtu = can_change_mtu, 639 }; 640 641 static void rcar_can_rx_pkt(struct rcar_can_priv *priv) 642 { 643 struct net_device_stats *stats = &priv->ndev->stats; 644 struct can_frame *cf; 645 struct sk_buff *skb; 646 u32 data; 647 u8 dlc; 648 649 skb = alloc_can_skb(priv->ndev, &cf); 650 if (!skb) { 651 stats->rx_dropped++; 652 return; 653 } 654 655 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); 656 if (data & RCAR_CAN_IDE) 657 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 658 else 659 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; 660 661 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); 662 cf->len = can_cc_dlc2len(dlc); 663 if (data & RCAR_CAN_RTR) { 664 cf->can_id |= CAN_RTR_FLAG; 665 } else { 666 for (dlc = 0; dlc < cf->len; dlc++) 667 cf->data[dlc] = 668 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); 669 } 670 671 can_led_event(priv->ndev, CAN_LED_EVENT_RX); 672 673 stats->rx_bytes += cf->len; 674 stats->rx_packets++; 675 netif_receive_skb(skb); 676 } 677 678 static int rcar_can_rx_poll(struct napi_struct *napi, int quota) 679 { 680 struct rcar_can_priv *priv = container_of(napi, 681 struct rcar_can_priv, napi); 682 int num_pkts; 683 684 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 685 u8 rfcr, isr; 686 687 isr = readb(&priv->regs->isr); 688 /* Clear interrupt bit */ 689 if (isr & RCAR_CAN_ISR_RXFF) 690 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); 691 rfcr = readb(&priv->regs->rfcr); 692 if (rfcr & RCAR_CAN_RFCR_RFEST) 693 break; 694 rcar_can_rx_pkt(priv); 695 /* Write 0xff to the RFPCR register to increment 696 * the CPU-side pointer for the receive FIFO 697 * to the next mailbox location 698 */ 699 writeb(0xff, &priv->regs->rfpcr); 700 } 701 /* All packets processed */ 702 if (num_pkts < quota) { 703 napi_complete_done(napi, num_pkts); 704 priv->ier |= RCAR_CAN_IER_RXFIE; 705 writeb(priv->ier, &priv->regs->ier); 706 } 707 return num_pkts; 708 } 709 710 static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 711 { 712 switch (mode) { 713 case CAN_MODE_START: 714 rcar_can_start(ndev); 715 netif_wake_queue(ndev); 716 return 0; 717 default: 718 return -EOPNOTSUPP; 719 } 720 } 721 722 static int rcar_can_get_berr_counter(const struct net_device *dev, 723 struct can_berr_counter *bec) 724 { 725 struct rcar_can_priv *priv = netdev_priv(dev); 726 int err; 727 728 err = clk_prepare_enable(priv->clk); 729 if (err) 730 return err; 731 bec->txerr = readb(&priv->regs->tecr); 732 bec->rxerr = readb(&priv->regs->recr); 733 clk_disable_unprepare(priv->clk); 734 return 0; 735 } 736 737 static const char * const clock_names[] = { 738 [CLKR_CLKP1] = "clkp1", 739 [CLKR_CLKP2] = "clkp2", 740 [CLKR_CLKEXT] = "can_clk", 741 }; 742 743 static int rcar_can_probe(struct platform_device *pdev) 744 { 745 struct rcar_can_priv *priv; 746 struct net_device *ndev; 747 void __iomem *addr; 748 u32 clock_select = CLKR_CLKP1; 749 int err = -ENODEV; 750 int irq; 751 752 of_property_read_u32(pdev->dev.of_node, "renesas,can-clock-select", 753 &clock_select); 754 755 irq = platform_get_irq(pdev, 0); 756 if (irq < 0) { 757 err = irq; 758 goto fail; 759 } 760 761 addr = devm_platform_ioremap_resource(pdev, 0); 762 if (IS_ERR(addr)) { 763 err = PTR_ERR(addr); 764 goto fail; 765 } 766 767 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); 768 if (!ndev) { 769 dev_err(&pdev->dev, "alloc_candev() failed\n"); 770 err = -ENOMEM; 771 goto fail; 772 } 773 774 priv = netdev_priv(ndev); 775 776 priv->clk = devm_clk_get(&pdev->dev, "clkp1"); 777 if (IS_ERR(priv->clk)) { 778 err = PTR_ERR(priv->clk); 779 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n", 780 err); 781 goto fail_clk; 782 } 783 784 if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) { 785 err = -EINVAL; 786 dev_err(&pdev->dev, "invalid CAN clock selected\n"); 787 goto fail_clk; 788 } 789 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); 790 if (IS_ERR(priv->can_clk)) { 791 err = PTR_ERR(priv->can_clk); 792 dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err); 793 goto fail_clk; 794 } 795 796 ndev->netdev_ops = &rcar_can_netdev_ops; 797 ndev->irq = irq; 798 ndev->flags |= IFF_ECHO; 799 priv->ndev = ndev; 800 priv->regs = addr; 801 priv->clock_select = clock_select; 802 priv->can.clock.freq = clk_get_rate(priv->can_clk); 803 priv->can.bittiming_const = &rcar_can_bittiming_const; 804 priv->can.do_set_mode = rcar_can_do_set_mode; 805 priv->can.do_get_berr_counter = rcar_can_get_berr_counter; 806 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 807 platform_set_drvdata(pdev, ndev); 808 SET_NETDEV_DEV(ndev, &pdev->dev); 809 810 netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll, 811 RCAR_CAN_NAPI_WEIGHT); 812 err = register_candev(ndev); 813 if (err) { 814 dev_err(&pdev->dev, "register_candev() failed, error %d\n", 815 err); 816 goto fail_candev; 817 } 818 819 devm_can_led_init(ndev); 820 821 dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq); 822 823 return 0; 824 fail_candev: 825 netif_napi_del(&priv->napi); 826 fail_clk: 827 free_candev(ndev); 828 fail: 829 return err; 830 } 831 832 static int rcar_can_remove(struct platform_device *pdev) 833 { 834 struct net_device *ndev = platform_get_drvdata(pdev); 835 struct rcar_can_priv *priv = netdev_priv(ndev); 836 837 unregister_candev(ndev); 838 netif_napi_del(&priv->napi); 839 free_candev(ndev); 840 return 0; 841 } 842 843 static int __maybe_unused rcar_can_suspend(struct device *dev) 844 { 845 struct net_device *ndev = dev_get_drvdata(dev); 846 struct rcar_can_priv *priv = netdev_priv(ndev); 847 u16 ctlr; 848 849 if (netif_running(ndev)) { 850 netif_stop_queue(ndev); 851 netif_device_detach(ndev); 852 } 853 ctlr = readw(&priv->regs->ctlr); 854 ctlr |= RCAR_CAN_CTLR_CANM_HALT; 855 writew(ctlr, &priv->regs->ctlr); 856 ctlr |= RCAR_CAN_CTLR_SLPM; 857 writew(ctlr, &priv->regs->ctlr); 858 priv->can.state = CAN_STATE_SLEEPING; 859 860 clk_disable(priv->clk); 861 return 0; 862 } 863 864 static int __maybe_unused rcar_can_resume(struct device *dev) 865 { 866 struct net_device *ndev = dev_get_drvdata(dev); 867 struct rcar_can_priv *priv = netdev_priv(ndev); 868 u16 ctlr; 869 int err; 870 871 err = clk_enable(priv->clk); 872 if (err) { 873 netdev_err(ndev, "clk_enable() failed, error %d\n", err); 874 return err; 875 } 876 877 ctlr = readw(&priv->regs->ctlr); 878 ctlr &= ~RCAR_CAN_CTLR_SLPM; 879 writew(ctlr, &priv->regs->ctlr); 880 ctlr &= ~RCAR_CAN_CTLR_CANM; 881 writew(ctlr, &priv->regs->ctlr); 882 priv->can.state = CAN_STATE_ERROR_ACTIVE; 883 884 if (netif_running(ndev)) { 885 netif_device_attach(ndev); 886 netif_start_queue(ndev); 887 } 888 return 0; 889 } 890 891 static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); 892 893 static const struct of_device_id rcar_can_of_table[] __maybe_unused = { 894 { .compatible = "renesas,can-r8a7778" }, 895 { .compatible = "renesas,can-r8a7779" }, 896 { .compatible = "renesas,can-r8a7790" }, 897 { .compatible = "renesas,can-r8a7791" }, 898 { .compatible = "renesas,rcar-gen1-can" }, 899 { .compatible = "renesas,rcar-gen2-can" }, 900 { .compatible = "renesas,rcar-gen3-can" }, 901 { } 902 }; 903 MODULE_DEVICE_TABLE(of, rcar_can_of_table); 904 905 static struct platform_driver rcar_can_driver = { 906 .driver = { 907 .name = RCAR_CAN_DRV_NAME, 908 .of_match_table = of_match_ptr(rcar_can_of_table), 909 .pm = &rcar_can_pm_ops, 910 }, 911 .probe = rcar_can_probe, 912 .remove = rcar_can_remove, 913 }; 914 915 module_platform_driver(rcar_can_driver); 916 917 MODULE_AUTHOR("Cogent Embedded, Inc."); 918 MODULE_LICENSE("GPL"); 919 MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); 920 MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); 921