1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Renesas R-Car CAN device driver 3 * 4 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/kernel.h> 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/errno.h> 13 #include <linux/netdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/can/dev.h> 16 #include <linux/clk.h> 17 #include <linux/of.h> 18 19 #define RCAR_CAN_DRV_NAME "rcar_can" 20 21 /* Clock Select Register settings */ 22 enum CLKR { 23 CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */ 24 CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */ 25 CLKR_CLKEXT = 3, /* Externally input clock */ 26 }; 27 28 #define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ 29 BIT(CLKR_CLKEXT)) 30 31 /* Mailbox configuration: 32 * mailbox 60 - 63 - Rx FIFO mailboxes 33 * mailbox 56 - 59 - Tx FIFO mailboxes 34 * non-FIFO mailboxes are not used 35 */ 36 #define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ 37 #define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ 38 #define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ 39 #define RCAR_CAN_FIFO_DEPTH 4 40 41 /* Mailbox registers structure */ 42 struct rcar_can_mbox_regs { 43 u32 id; /* IDE and RTR bits, SID and EID */ 44 u8 stub; /* Not used */ 45 u8 dlc; /* Data Length Code - bits [0..3] */ 46 u8 data[8]; /* Data Bytes */ 47 u8 tsh; /* Time Stamp Higher Byte */ 48 u8 tsl; /* Time Stamp Lower Byte */ 49 }; 50 51 struct rcar_can_regs { 52 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ 53 u32 mkr_2_9[8]; /* Mask Registers 2-9 */ 54 u32 fidcr[2]; /* FIFO Received ID Compare Register */ 55 u32 mkivlr1; /* Mask Invalid Register 1 */ 56 u32 mier1; /* Mailbox Interrupt Enable Register 1 */ 57 u32 mkr_0_1[2]; /* Mask Registers 0-1 */ 58 u32 mkivlr0; /* Mask Invalid Register 0*/ 59 u32 mier0; /* Mailbox Interrupt Enable Register 0 */ 60 u8 pad_440[0x3c0]; 61 u8 mctl[64]; /* Message Control Registers */ 62 u16 ctlr; /* Control Register */ 63 u16 str; /* Status register */ 64 u8 bcr[3]; /* Bit Configuration Register */ 65 u8 clkr; /* Clock Select Register */ 66 u8 rfcr; /* Receive FIFO Control Register */ 67 u8 rfpcr; /* Receive FIFO Pointer Control Register */ 68 u8 tfcr; /* Transmit FIFO Control Register */ 69 u8 tfpcr; /* Transmit FIFO Pointer Control Register */ 70 u8 eier; /* Error Interrupt Enable Register */ 71 u8 eifr; /* Error Interrupt Factor Judge Register */ 72 u8 recr; /* Receive Error Count Register */ 73 u8 tecr; /* Transmit Error Count Register */ 74 u8 ecsr; /* Error Code Store Register */ 75 u8 cssr; /* Channel Search Support Register */ 76 u8 mssr; /* Mailbox Search Status Register */ 77 u8 msmr; /* Mailbox Search Mode Register */ 78 u16 tsr; /* Time Stamp Register */ 79 u8 afsr; /* Acceptance Filter Support Register */ 80 u8 pad_857; 81 u8 tcr; /* Test Control Register */ 82 u8 pad_859[7]; 83 u8 ier; /* Interrupt Enable Register */ 84 u8 isr; /* Interrupt Status Register */ 85 u8 pad_862; 86 u8 mbsmr; /* Mailbox Search Mask Register */ 87 }; 88 89 struct rcar_can_priv { 90 struct can_priv can; /* Must be the first member! */ 91 struct net_device *ndev; 92 struct napi_struct napi; 93 struct rcar_can_regs __iomem *regs; 94 struct clk *clk; 95 struct clk *can_clk; 96 u32 tx_head; 97 u32 tx_tail; 98 u8 clock_select; 99 u8 ier; 100 }; 101 102 static const struct can_bittiming_const rcar_can_bittiming_const = { 103 .name = RCAR_CAN_DRV_NAME, 104 .tseg1_min = 4, 105 .tseg1_max = 16, 106 .tseg2_min = 2, 107 .tseg2_max = 8, 108 .sjw_max = 4, 109 .brp_min = 1, 110 .brp_max = 1024, 111 .brp_inc = 1, 112 }; 113 114 /* Control Register bits */ 115 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ 116 #define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ 117 /* at bus-off entry */ 118 #define RCAR_CAN_CTLR_SLPM (1 << 10) 119 #define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ 120 #define RCAR_CAN_CTLR_CANM_HALT (1 << 9) 121 #define RCAR_CAN_CTLR_CANM_RESET (1 << 8) 122 #define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) 123 #define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ 124 #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ 125 #define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ 126 #define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ 127 128 /* Status Register bits */ 129 #define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ 130 131 /* FIFO Received ID Compare Registers 0 and 1 bits */ 132 #define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ 133 #define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ 134 135 /* Receive FIFO Control Register bits */ 136 #define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ 137 #define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ 138 139 /* Transmit FIFO Control Register bits */ 140 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ 141 /* Number Status Bits */ 142 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ 143 /* Message Number Status Bits */ 144 #define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ 145 146 #define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ 147 /* for Rx mailboxes 0-31 */ 148 #define RCAR_CAN_N_RX_MKREGS2 8 149 150 /* Bit Configuration Register settings */ 151 #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) 152 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) 153 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) 154 #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) 155 156 /* Mailbox and Mask Registers bits */ 157 #define RCAR_CAN_IDE (1 << 31) 158 #define RCAR_CAN_RTR (1 << 30) 159 #define RCAR_CAN_SID_SHIFT 18 160 161 /* Mailbox Interrupt Enable Register 1 bits */ 162 #define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ 163 #define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ 164 165 /* Interrupt Enable Register bits */ 166 #define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ 167 #define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ 168 /* Enable Bit */ 169 #define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ 170 /* Enable Bit */ 171 /* Interrupt Status Register bits */ 172 #define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ 173 #define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ 174 /* Status Bit */ 175 #define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ 176 /* Status Bit */ 177 178 /* Error Interrupt Enable Register bits */ 179 #define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ 180 #define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ 181 /* Interrupt Enable */ 182 #define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ 183 #define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ 184 #define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ 185 #define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ 186 #define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ 187 #define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ 188 189 /* Error Interrupt Factor Judge Register bits */ 190 #define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ 191 #define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ 192 /* Detect Flag */ 193 #define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ 194 #define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ 195 #define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ 196 #define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ 197 #define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ 198 #define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ 199 200 /* Error Code Store Register bits */ 201 #define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ 202 #define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ 203 #define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ 204 #define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ 205 #define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ 206 #define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ 207 #define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ 208 #define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ 209 210 #define RCAR_CAN_NAPI_WEIGHT 4 211 #define MAX_STR_READS 0x100 212 213 static void tx_failure_cleanup(struct net_device *ndev) 214 { 215 int i; 216 217 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) 218 can_free_echo_skb(ndev, i, NULL); 219 } 220 221 static void rcar_can_error(struct net_device *ndev) 222 { 223 struct rcar_can_priv *priv = netdev_priv(ndev); 224 struct can_frame *cf; 225 struct sk_buff *skb; 226 u8 eifr, txerr = 0, rxerr = 0; 227 228 /* Propagate the error condition to the CAN stack */ 229 skb = alloc_can_err_skb(ndev, &cf); 230 231 eifr = readb(&priv->regs->eifr); 232 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { 233 txerr = readb(&priv->regs->tecr); 234 rxerr = readb(&priv->regs->recr); 235 if (skb) 236 cf->can_id |= CAN_ERR_CRTL; 237 } 238 if (eifr & RCAR_CAN_EIFR_BEIF) { 239 int rx_errors = 0, tx_errors = 0; 240 u8 ecsr; 241 242 netdev_dbg(priv->ndev, "Bus error interrupt:\n"); 243 if (skb) 244 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 245 246 ecsr = readb(&priv->regs->ecsr); 247 if (ecsr & RCAR_CAN_ECSR_ADEF) { 248 netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); 249 tx_errors++; 250 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); 251 if (skb) 252 cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL; 253 } 254 if (ecsr & RCAR_CAN_ECSR_BE0F) { 255 netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); 256 tx_errors++; 257 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); 258 if (skb) 259 cf->data[2] |= CAN_ERR_PROT_BIT0; 260 } 261 if (ecsr & RCAR_CAN_ECSR_BE1F) { 262 netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); 263 tx_errors++; 264 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); 265 if (skb) 266 cf->data[2] |= CAN_ERR_PROT_BIT1; 267 } 268 if (ecsr & RCAR_CAN_ECSR_CEF) { 269 netdev_dbg(priv->ndev, "CRC Error\n"); 270 rx_errors++; 271 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); 272 if (skb) 273 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 274 } 275 if (ecsr & RCAR_CAN_ECSR_AEF) { 276 netdev_dbg(priv->ndev, "ACK Error\n"); 277 tx_errors++; 278 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); 279 if (skb) { 280 cf->can_id |= CAN_ERR_ACK; 281 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 282 } 283 } 284 if (ecsr & RCAR_CAN_ECSR_FEF) { 285 netdev_dbg(priv->ndev, "Form Error\n"); 286 rx_errors++; 287 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); 288 if (skb) 289 cf->data[2] |= CAN_ERR_PROT_FORM; 290 } 291 if (ecsr & RCAR_CAN_ECSR_SEF) { 292 netdev_dbg(priv->ndev, "Stuff Error\n"); 293 rx_errors++; 294 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); 295 if (skb) 296 cf->data[2] |= CAN_ERR_PROT_STUFF; 297 } 298 299 priv->can.can_stats.bus_error++; 300 ndev->stats.rx_errors += rx_errors; 301 ndev->stats.tx_errors += tx_errors; 302 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); 303 } 304 if (eifr & RCAR_CAN_EIFR_EWIF) { 305 netdev_dbg(priv->ndev, "Error warning interrupt\n"); 306 priv->can.state = CAN_STATE_ERROR_WARNING; 307 priv->can.can_stats.error_warning++; 308 /* Clear interrupt condition */ 309 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); 310 if (skb) 311 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 312 CAN_ERR_CRTL_RX_WARNING; 313 } 314 if (eifr & RCAR_CAN_EIFR_EPIF) { 315 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 316 priv->can.state = CAN_STATE_ERROR_PASSIVE; 317 priv->can.can_stats.error_passive++; 318 /* Clear interrupt condition */ 319 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); 320 if (skb) 321 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 322 CAN_ERR_CRTL_RX_PASSIVE; 323 } 324 if (eifr & RCAR_CAN_EIFR_BOEIF) { 325 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); 326 tx_failure_cleanup(ndev); 327 priv->ier = RCAR_CAN_IER_ERSIE; 328 writeb(priv->ier, &priv->regs->ier); 329 priv->can.state = CAN_STATE_BUS_OFF; 330 /* Clear interrupt condition */ 331 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); 332 priv->can.can_stats.bus_off++; 333 can_bus_off(ndev); 334 if (skb) 335 cf->can_id |= CAN_ERR_BUSOFF; 336 } else if (skb) { 337 cf->can_id |= CAN_ERR_CNT; 338 cf->data[6] = txerr; 339 cf->data[7] = rxerr; 340 } 341 if (eifr & RCAR_CAN_EIFR_ORIF) { 342 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); 343 ndev->stats.rx_over_errors++; 344 ndev->stats.rx_errors++; 345 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); 346 if (skb) { 347 cf->can_id |= CAN_ERR_CRTL; 348 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 349 } 350 } 351 if (eifr & RCAR_CAN_EIFR_OLIF) { 352 netdev_dbg(priv->ndev, 353 "Overload Frame Transmission error interrupt\n"); 354 ndev->stats.rx_over_errors++; 355 ndev->stats.rx_errors++; 356 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); 357 if (skb) { 358 cf->can_id |= CAN_ERR_PROT; 359 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 360 } 361 } 362 363 if (skb) 364 netif_rx(skb); 365 } 366 367 static void rcar_can_tx_done(struct net_device *ndev) 368 { 369 struct rcar_can_priv *priv = netdev_priv(ndev); 370 struct net_device_stats *stats = &ndev->stats; 371 u8 isr; 372 373 while (1) { 374 u8 unsent = readb(&priv->regs->tfcr); 375 376 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> 377 RCAR_CAN_TFCR_TFUST_SHIFT; 378 if (priv->tx_head - priv->tx_tail <= unsent) 379 break; 380 stats->tx_packets++; 381 stats->tx_bytes += 382 can_get_echo_skb(ndev, 383 priv->tx_tail % RCAR_CAN_FIFO_DEPTH, 384 NULL); 385 386 priv->tx_tail++; 387 netif_wake_queue(ndev); 388 } 389 /* Clear interrupt */ 390 isr = readb(&priv->regs->isr); 391 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); 392 } 393 394 static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) 395 { 396 struct net_device *ndev = dev_id; 397 struct rcar_can_priv *priv = netdev_priv(ndev); 398 u8 isr; 399 400 isr = readb(&priv->regs->isr); 401 if (!(isr & priv->ier)) 402 return IRQ_NONE; 403 404 if (isr & RCAR_CAN_ISR_ERSF) 405 rcar_can_error(ndev); 406 407 if (isr & RCAR_CAN_ISR_TXFF) 408 rcar_can_tx_done(ndev); 409 410 if (isr & RCAR_CAN_ISR_RXFF) { 411 if (napi_schedule_prep(&priv->napi)) { 412 /* Disable Rx FIFO interrupts */ 413 priv->ier &= ~RCAR_CAN_IER_RXFIE; 414 writeb(priv->ier, &priv->regs->ier); 415 __napi_schedule(&priv->napi); 416 } 417 } 418 419 return IRQ_HANDLED; 420 } 421 422 static void rcar_can_set_bittiming(struct net_device *dev) 423 { 424 struct rcar_can_priv *priv = netdev_priv(dev); 425 struct can_bittiming *bt = &priv->can.bittiming; 426 u32 bcr; 427 428 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | 429 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | 430 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); 431 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. 432 * All the registers are big-endian but they get byte-swapped on 32-bit 433 * read/write (but not on 8-bit, contrary to the manuals)... 434 */ 435 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); 436 } 437 438 static void rcar_can_start(struct net_device *ndev) 439 { 440 struct rcar_can_priv *priv = netdev_priv(ndev); 441 u16 ctlr; 442 int i; 443 444 /* Set controller to known mode: 445 * - FIFO mailbox mode 446 * - accept all messages 447 * - overrun mode 448 * CAN is in sleep mode after MCU hardware or software reset. 449 */ 450 ctlr = readw(&priv->regs->ctlr); 451 ctlr &= ~RCAR_CAN_CTLR_SLPM; 452 writew(ctlr, &priv->regs->ctlr); 453 /* Go to reset mode */ 454 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 455 writew(ctlr, &priv->regs->ctlr); 456 for (i = 0; i < MAX_STR_READS; i++) { 457 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 458 break; 459 } 460 rcar_can_set_bittiming(ndev); 461 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ 462 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ 463 /* at bus-off */ 464 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ 465 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ 466 writew(ctlr, &priv->regs->ctlr); 467 468 /* Accept all SID and EID */ 469 writel(0, &priv->regs->mkr_2_9[6]); 470 writel(0, &priv->regs->mkr_2_9[7]); 471 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ 472 writel(0, &priv->regs->mkivlr1); 473 /* Accept all frames */ 474 writel(0, &priv->regs->fidcr[0]); 475 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); 476 /* Enable and configure FIFO mailbox interrupts */ 477 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); 478 479 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | 480 RCAR_CAN_IER_TXFIE; 481 writeb(priv->ier, &priv->regs->ier); 482 483 /* Accumulate error codes */ 484 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); 485 /* Enable error interrupts */ 486 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | 487 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? 488 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | 489 RCAR_CAN_EIER_OLIE, &priv->regs->eier); 490 priv->can.state = CAN_STATE_ERROR_ACTIVE; 491 492 /* Go to operation mode */ 493 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); 494 for (i = 0; i < MAX_STR_READS; i++) { 495 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) 496 break; 497 } 498 /* Enable Rx and Tx FIFO */ 499 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); 500 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); 501 } 502 503 static int rcar_can_open(struct net_device *ndev) 504 { 505 struct rcar_can_priv *priv = netdev_priv(ndev); 506 int err; 507 508 err = clk_prepare_enable(priv->clk); 509 if (err) { 510 netdev_err(ndev, 511 "failed to enable peripheral clock, error %d\n", 512 err); 513 goto out; 514 } 515 err = clk_prepare_enable(priv->can_clk); 516 if (err) { 517 netdev_err(ndev, "failed to enable CAN clock, error %d\n", 518 err); 519 goto out_clock; 520 } 521 err = open_candev(ndev); 522 if (err) { 523 netdev_err(ndev, "open_candev() failed, error %d\n", err); 524 goto out_can_clock; 525 } 526 napi_enable(&priv->napi); 527 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); 528 if (err) { 529 netdev_err(ndev, "request_irq(%d) failed, error %d\n", 530 ndev->irq, err); 531 goto out_close; 532 } 533 rcar_can_start(ndev); 534 netif_start_queue(ndev); 535 return 0; 536 out_close: 537 napi_disable(&priv->napi); 538 close_candev(ndev); 539 out_can_clock: 540 clk_disable_unprepare(priv->can_clk); 541 out_clock: 542 clk_disable_unprepare(priv->clk); 543 out: 544 return err; 545 } 546 547 static void rcar_can_stop(struct net_device *ndev) 548 { 549 struct rcar_can_priv *priv = netdev_priv(ndev); 550 u16 ctlr; 551 int i; 552 553 /* Go to (force) reset mode */ 554 ctlr = readw(&priv->regs->ctlr); 555 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 556 writew(ctlr, &priv->regs->ctlr); 557 for (i = 0; i < MAX_STR_READS; i++) { 558 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 559 break; 560 } 561 writel(0, &priv->regs->mier0); 562 writel(0, &priv->regs->mier1); 563 writeb(0, &priv->regs->ier); 564 writeb(0, &priv->regs->eier); 565 /* Go to sleep mode */ 566 ctlr |= RCAR_CAN_CTLR_SLPM; 567 writew(ctlr, &priv->regs->ctlr); 568 priv->can.state = CAN_STATE_STOPPED; 569 } 570 571 static int rcar_can_close(struct net_device *ndev) 572 { 573 struct rcar_can_priv *priv = netdev_priv(ndev); 574 575 netif_stop_queue(ndev); 576 rcar_can_stop(ndev); 577 free_irq(ndev->irq, ndev); 578 napi_disable(&priv->napi); 579 clk_disable_unprepare(priv->can_clk); 580 clk_disable_unprepare(priv->clk); 581 close_candev(ndev); 582 return 0; 583 } 584 585 static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, 586 struct net_device *ndev) 587 { 588 struct rcar_can_priv *priv = netdev_priv(ndev); 589 struct can_frame *cf = (struct can_frame *)skb->data; 590 u32 data, i; 591 592 if (can_dropped_invalid_skb(ndev, skb)) 593 return NETDEV_TX_OK; 594 595 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 596 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; 597 else /* Standard frame format */ 598 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; 599 600 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ 601 data |= RCAR_CAN_RTR; 602 } else { 603 for (i = 0; i < cf->len; i++) 604 writeb(cf->data[i], 605 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); 606 } 607 608 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); 609 610 writeb(cf->len, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); 611 612 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH, 0); 613 priv->tx_head++; 614 /* Start Tx: write 0xff to the TFPCR register to increment 615 * the CPU-side pointer for the transmit FIFO to the next 616 * mailbox location 617 */ 618 writeb(0xff, &priv->regs->tfpcr); 619 /* Stop the queue if we've filled all FIFO entries */ 620 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) 621 netif_stop_queue(ndev); 622 623 return NETDEV_TX_OK; 624 } 625 626 static const struct net_device_ops rcar_can_netdev_ops = { 627 .ndo_open = rcar_can_open, 628 .ndo_stop = rcar_can_close, 629 .ndo_start_xmit = rcar_can_start_xmit, 630 .ndo_change_mtu = can_change_mtu, 631 }; 632 633 static void rcar_can_rx_pkt(struct rcar_can_priv *priv) 634 { 635 struct net_device_stats *stats = &priv->ndev->stats; 636 struct can_frame *cf; 637 struct sk_buff *skb; 638 u32 data; 639 u8 dlc; 640 641 skb = alloc_can_skb(priv->ndev, &cf); 642 if (!skb) { 643 stats->rx_dropped++; 644 return; 645 } 646 647 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); 648 if (data & RCAR_CAN_IDE) 649 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 650 else 651 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; 652 653 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); 654 cf->len = can_cc_dlc2len(dlc); 655 if (data & RCAR_CAN_RTR) { 656 cf->can_id |= CAN_RTR_FLAG; 657 } else { 658 for (dlc = 0; dlc < cf->len; dlc++) 659 cf->data[dlc] = 660 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); 661 662 stats->rx_bytes += cf->len; 663 } 664 stats->rx_packets++; 665 666 netif_receive_skb(skb); 667 } 668 669 static int rcar_can_rx_poll(struct napi_struct *napi, int quota) 670 { 671 struct rcar_can_priv *priv = container_of(napi, 672 struct rcar_can_priv, napi); 673 int num_pkts; 674 675 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 676 u8 rfcr, isr; 677 678 isr = readb(&priv->regs->isr); 679 /* Clear interrupt bit */ 680 if (isr & RCAR_CAN_ISR_RXFF) 681 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); 682 rfcr = readb(&priv->regs->rfcr); 683 if (rfcr & RCAR_CAN_RFCR_RFEST) 684 break; 685 rcar_can_rx_pkt(priv); 686 /* Write 0xff to the RFPCR register to increment 687 * the CPU-side pointer for the receive FIFO 688 * to the next mailbox location 689 */ 690 writeb(0xff, &priv->regs->rfpcr); 691 } 692 /* All packets processed */ 693 if (num_pkts < quota) { 694 napi_complete_done(napi, num_pkts); 695 priv->ier |= RCAR_CAN_IER_RXFIE; 696 writeb(priv->ier, &priv->regs->ier); 697 } 698 return num_pkts; 699 } 700 701 static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 702 { 703 switch (mode) { 704 case CAN_MODE_START: 705 rcar_can_start(ndev); 706 netif_wake_queue(ndev); 707 return 0; 708 default: 709 return -EOPNOTSUPP; 710 } 711 } 712 713 static int rcar_can_get_berr_counter(const struct net_device *dev, 714 struct can_berr_counter *bec) 715 { 716 struct rcar_can_priv *priv = netdev_priv(dev); 717 int err; 718 719 err = clk_prepare_enable(priv->clk); 720 if (err) 721 return err; 722 bec->txerr = readb(&priv->regs->tecr); 723 bec->rxerr = readb(&priv->regs->recr); 724 clk_disable_unprepare(priv->clk); 725 return 0; 726 } 727 728 static const char * const clock_names[] = { 729 [CLKR_CLKP1] = "clkp1", 730 [CLKR_CLKP2] = "clkp2", 731 [CLKR_CLKEXT] = "can_clk", 732 }; 733 734 static int rcar_can_probe(struct platform_device *pdev) 735 { 736 struct rcar_can_priv *priv; 737 struct net_device *ndev; 738 void __iomem *addr; 739 u32 clock_select = CLKR_CLKP1; 740 int err = -ENODEV; 741 int irq; 742 743 of_property_read_u32(pdev->dev.of_node, "renesas,can-clock-select", 744 &clock_select); 745 746 irq = platform_get_irq(pdev, 0); 747 if (irq < 0) { 748 err = irq; 749 goto fail; 750 } 751 752 addr = devm_platform_ioremap_resource(pdev, 0); 753 if (IS_ERR(addr)) { 754 err = PTR_ERR(addr); 755 goto fail; 756 } 757 758 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); 759 if (!ndev) { 760 dev_err(&pdev->dev, "alloc_candev() failed\n"); 761 err = -ENOMEM; 762 goto fail; 763 } 764 765 priv = netdev_priv(ndev); 766 767 priv->clk = devm_clk_get(&pdev->dev, "clkp1"); 768 if (IS_ERR(priv->clk)) { 769 err = PTR_ERR(priv->clk); 770 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n", 771 err); 772 goto fail_clk; 773 } 774 775 if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) { 776 err = -EINVAL; 777 dev_err(&pdev->dev, "invalid CAN clock selected\n"); 778 goto fail_clk; 779 } 780 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); 781 if (IS_ERR(priv->can_clk)) { 782 err = PTR_ERR(priv->can_clk); 783 dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err); 784 goto fail_clk; 785 } 786 787 ndev->netdev_ops = &rcar_can_netdev_ops; 788 ndev->irq = irq; 789 ndev->flags |= IFF_ECHO; 790 priv->ndev = ndev; 791 priv->regs = addr; 792 priv->clock_select = clock_select; 793 priv->can.clock.freq = clk_get_rate(priv->can_clk); 794 priv->can.bittiming_const = &rcar_can_bittiming_const; 795 priv->can.do_set_mode = rcar_can_do_set_mode; 796 priv->can.do_get_berr_counter = rcar_can_get_berr_counter; 797 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 798 platform_set_drvdata(pdev, ndev); 799 SET_NETDEV_DEV(ndev, &pdev->dev); 800 801 netif_napi_add_weight(ndev, &priv->napi, rcar_can_rx_poll, 802 RCAR_CAN_NAPI_WEIGHT); 803 err = register_candev(ndev); 804 if (err) { 805 dev_err(&pdev->dev, "register_candev() failed, error %d\n", 806 err); 807 goto fail_candev; 808 } 809 810 dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq); 811 812 return 0; 813 fail_candev: 814 netif_napi_del(&priv->napi); 815 fail_clk: 816 free_candev(ndev); 817 fail: 818 return err; 819 } 820 821 static int rcar_can_remove(struct platform_device *pdev) 822 { 823 struct net_device *ndev = platform_get_drvdata(pdev); 824 struct rcar_can_priv *priv = netdev_priv(ndev); 825 826 unregister_candev(ndev); 827 netif_napi_del(&priv->napi); 828 free_candev(ndev); 829 return 0; 830 } 831 832 static int __maybe_unused rcar_can_suspend(struct device *dev) 833 { 834 struct net_device *ndev = dev_get_drvdata(dev); 835 struct rcar_can_priv *priv = netdev_priv(ndev); 836 u16 ctlr; 837 838 if (!netif_running(ndev)) 839 return 0; 840 841 netif_stop_queue(ndev); 842 netif_device_detach(ndev); 843 844 ctlr = readw(&priv->regs->ctlr); 845 ctlr |= RCAR_CAN_CTLR_CANM_HALT; 846 writew(ctlr, &priv->regs->ctlr); 847 ctlr |= RCAR_CAN_CTLR_SLPM; 848 writew(ctlr, &priv->regs->ctlr); 849 priv->can.state = CAN_STATE_SLEEPING; 850 851 clk_disable(priv->clk); 852 return 0; 853 } 854 855 static int __maybe_unused rcar_can_resume(struct device *dev) 856 { 857 struct net_device *ndev = dev_get_drvdata(dev); 858 struct rcar_can_priv *priv = netdev_priv(ndev); 859 u16 ctlr; 860 int err; 861 862 if (!netif_running(ndev)) 863 return 0; 864 865 err = clk_enable(priv->clk); 866 if (err) { 867 netdev_err(ndev, "clk_enable() failed, error %d\n", err); 868 return err; 869 } 870 871 ctlr = readw(&priv->regs->ctlr); 872 ctlr &= ~RCAR_CAN_CTLR_SLPM; 873 writew(ctlr, &priv->regs->ctlr); 874 ctlr &= ~RCAR_CAN_CTLR_CANM; 875 writew(ctlr, &priv->regs->ctlr); 876 priv->can.state = CAN_STATE_ERROR_ACTIVE; 877 878 netif_device_attach(ndev); 879 netif_start_queue(ndev); 880 881 return 0; 882 } 883 884 static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); 885 886 static const struct of_device_id rcar_can_of_table[] __maybe_unused = { 887 { .compatible = "renesas,can-r8a7778" }, 888 { .compatible = "renesas,can-r8a7779" }, 889 { .compatible = "renesas,can-r8a7790" }, 890 { .compatible = "renesas,can-r8a7791" }, 891 { .compatible = "renesas,rcar-gen1-can" }, 892 { .compatible = "renesas,rcar-gen2-can" }, 893 { .compatible = "renesas,rcar-gen3-can" }, 894 { } 895 }; 896 MODULE_DEVICE_TABLE(of, rcar_can_of_table); 897 898 static struct platform_driver rcar_can_driver = { 899 .driver = { 900 .name = RCAR_CAN_DRV_NAME, 901 .of_match_table = of_match_ptr(rcar_can_of_table), 902 .pm = &rcar_can_pm_ops, 903 }, 904 .probe = rcar_can_probe, 905 .remove = rcar_can_remove, 906 }; 907 908 module_platform_driver(rcar_can_driver); 909 910 MODULE_AUTHOR("Cogent Embedded, Inc."); 911 MODULE_LICENSE("GPL"); 912 MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); 913 MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); 914