1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Renesas R-Car CAN device driver 3 * 4 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/kernel.h> 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/errno.h> 13 #include <linux/netdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/can/dev.h> 16 #include <linux/clk.h> 17 #include <linux/of.h> 18 19 #define RCAR_CAN_DRV_NAME "rcar_can" 20 21 /* Clock Select Register settings */ 22 enum CLKR { 23 CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */ 24 CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */ 25 CLKR_CLKEXT = 3, /* Externally input clock */ 26 }; 27 28 #define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ 29 BIT(CLKR_CLKEXT)) 30 31 /* Mailbox configuration: 32 * mailbox 60 - 63 - Rx FIFO mailboxes 33 * mailbox 56 - 59 - Tx FIFO mailboxes 34 * non-FIFO mailboxes are not used 35 */ 36 #define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ 37 #define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ 38 #define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ 39 #define RCAR_CAN_FIFO_DEPTH 4 40 41 /* Mailbox registers structure */ 42 struct rcar_can_mbox_regs { 43 u32 id; /* IDE and RTR bits, SID and EID */ 44 u8 stub; /* Not used */ 45 u8 dlc; /* Data Length Code - bits [0..3] */ 46 u8 data[8]; /* Data Bytes */ 47 u8 tsh; /* Time Stamp Higher Byte */ 48 u8 tsl; /* Time Stamp Lower Byte */ 49 }; 50 51 struct rcar_can_regs { 52 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ 53 u32 mkr_2_9[8]; /* Mask Registers 2-9 */ 54 u32 fidcr[2]; /* FIFO Received ID Compare Register */ 55 u32 mkivlr1; /* Mask Invalid Register 1 */ 56 u32 mier1; /* Mailbox Interrupt Enable Register 1 */ 57 u32 mkr_0_1[2]; /* Mask Registers 0-1 */ 58 u32 mkivlr0; /* Mask Invalid Register 0*/ 59 u32 mier0; /* Mailbox Interrupt Enable Register 0 */ 60 u8 pad_440[0x3c0]; 61 u8 mctl[64]; /* Message Control Registers */ 62 u16 ctlr; /* Control Register */ 63 u16 str; /* Status register */ 64 u8 bcr[3]; /* Bit Configuration Register */ 65 u8 clkr; /* Clock Select Register */ 66 u8 rfcr; /* Receive FIFO Control Register */ 67 u8 rfpcr; /* Receive FIFO Pointer Control Register */ 68 u8 tfcr; /* Transmit FIFO Control Register */ 69 u8 tfpcr; /* Transmit FIFO Pointer Control Register */ 70 u8 eier; /* Error Interrupt Enable Register */ 71 u8 eifr; /* Error Interrupt Factor Judge Register */ 72 u8 recr; /* Receive Error Count Register */ 73 u8 tecr; /* Transmit Error Count Register */ 74 u8 ecsr; /* Error Code Store Register */ 75 u8 cssr; /* Channel Search Support Register */ 76 u8 mssr; /* Mailbox Search Status Register */ 77 u8 msmr; /* Mailbox Search Mode Register */ 78 u16 tsr; /* Time Stamp Register */ 79 u8 afsr; /* Acceptance Filter Support Register */ 80 u8 pad_857; 81 u8 tcr; /* Test Control Register */ 82 u8 pad_859[7]; 83 u8 ier; /* Interrupt Enable Register */ 84 u8 isr; /* Interrupt Status Register */ 85 u8 pad_862; 86 u8 mbsmr; /* Mailbox Search Mask Register */ 87 }; 88 89 struct rcar_can_priv { 90 struct can_priv can; /* Must be the first member! */ 91 struct net_device *ndev; 92 struct napi_struct napi; 93 struct rcar_can_regs __iomem *regs; 94 struct clk *clk; 95 struct clk *can_clk; 96 u32 tx_head; 97 u32 tx_tail; 98 u8 clock_select; 99 u8 ier; 100 }; 101 102 static const struct can_bittiming_const rcar_can_bittiming_const = { 103 .name = RCAR_CAN_DRV_NAME, 104 .tseg1_min = 4, 105 .tseg1_max = 16, 106 .tseg2_min = 2, 107 .tseg2_max = 8, 108 .sjw_max = 4, 109 .brp_min = 1, 110 .brp_max = 1024, 111 .brp_inc = 1, 112 }; 113 114 /* Control Register bits */ 115 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ 116 #define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ 117 /* at bus-off entry */ 118 #define RCAR_CAN_CTLR_SLPM (1 << 10) 119 #define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ 120 #define RCAR_CAN_CTLR_CANM_HALT (1 << 9) 121 #define RCAR_CAN_CTLR_CANM_RESET (1 << 8) 122 #define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) 123 #define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ 124 #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ 125 #define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ 126 #define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ 127 128 /* Status Register bits */ 129 #define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ 130 131 /* FIFO Received ID Compare Registers 0 and 1 bits */ 132 #define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ 133 #define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ 134 135 /* Receive FIFO Control Register bits */ 136 #define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ 137 #define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ 138 139 /* Transmit FIFO Control Register bits */ 140 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ 141 /* Number Status Bits */ 142 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ 143 /* Message Number Status Bits */ 144 #define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ 145 146 #define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ 147 /* for Rx mailboxes 0-31 */ 148 #define RCAR_CAN_N_RX_MKREGS2 8 149 150 /* Bit Configuration Register settings */ 151 #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) 152 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) 153 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) 154 #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) 155 156 /* Mailbox and Mask Registers bits */ 157 #define RCAR_CAN_IDE (1 << 31) 158 #define RCAR_CAN_RTR (1 << 30) 159 #define RCAR_CAN_SID_SHIFT 18 160 161 /* Mailbox Interrupt Enable Register 1 bits */ 162 #define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ 163 #define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ 164 165 /* Interrupt Enable Register bits */ 166 #define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ 167 #define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ 168 /* Enable Bit */ 169 #define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ 170 /* Enable Bit */ 171 /* Interrupt Status Register bits */ 172 #define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ 173 #define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ 174 /* Status Bit */ 175 #define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ 176 /* Status Bit */ 177 178 /* Error Interrupt Enable Register bits */ 179 #define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ 180 #define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ 181 /* Interrupt Enable */ 182 #define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ 183 #define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ 184 #define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ 185 #define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ 186 #define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ 187 #define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ 188 189 /* Error Interrupt Factor Judge Register bits */ 190 #define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ 191 #define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ 192 /* Detect Flag */ 193 #define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ 194 #define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ 195 #define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ 196 #define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ 197 #define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ 198 #define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ 199 200 /* Error Code Store Register bits */ 201 #define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ 202 #define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ 203 #define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ 204 #define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ 205 #define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ 206 #define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ 207 #define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ 208 #define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ 209 210 #define RCAR_CAN_NAPI_WEIGHT 4 211 #define MAX_STR_READS 0x100 212 213 static void tx_failure_cleanup(struct net_device *ndev) 214 { 215 int i; 216 217 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) 218 can_free_echo_skb(ndev, i, NULL); 219 } 220 221 static void rcar_can_error(struct net_device *ndev) 222 { 223 struct rcar_can_priv *priv = netdev_priv(ndev); 224 struct can_frame *cf; 225 struct sk_buff *skb; 226 u8 eifr, txerr = 0, rxerr = 0; 227 228 /* Propagate the error condition to the CAN stack */ 229 skb = alloc_can_err_skb(ndev, &cf); 230 231 eifr = readb(&priv->regs->eifr); 232 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { 233 txerr = readb(&priv->regs->tecr); 234 rxerr = readb(&priv->regs->recr); 235 if (skb) { 236 cf->can_id |= CAN_ERR_CRTL; 237 cf->data[6] = txerr; 238 cf->data[7] = rxerr; 239 } 240 } 241 if (eifr & RCAR_CAN_EIFR_BEIF) { 242 int rx_errors = 0, tx_errors = 0; 243 u8 ecsr; 244 245 netdev_dbg(priv->ndev, "Bus error interrupt:\n"); 246 if (skb) 247 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 248 249 ecsr = readb(&priv->regs->ecsr); 250 if (ecsr & RCAR_CAN_ECSR_ADEF) { 251 netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); 252 tx_errors++; 253 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); 254 if (skb) 255 cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL; 256 } 257 if (ecsr & RCAR_CAN_ECSR_BE0F) { 258 netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); 259 tx_errors++; 260 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); 261 if (skb) 262 cf->data[2] |= CAN_ERR_PROT_BIT0; 263 } 264 if (ecsr & RCAR_CAN_ECSR_BE1F) { 265 netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); 266 tx_errors++; 267 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); 268 if (skb) 269 cf->data[2] |= CAN_ERR_PROT_BIT1; 270 } 271 if (ecsr & RCAR_CAN_ECSR_CEF) { 272 netdev_dbg(priv->ndev, "CRC Error\n"); 273 rx_errors++; 274 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); 275 if (skb) 276 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 277 } 278 if (ecsr & RCAR_CAN_ECSR_AEF) { 279 netdev_dbg(priv->ndev, "ACK Error\n"); 280 tx_errors++; 281 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); 282 if (skb) { 283 cf->can_id |= CAN_ERR_ACK; 284 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 285 } 286 } 287 if (ecsr & RCAR_CAN_ECSR_FEF) { 288 netdev_dbg(priv->ndev, "Form Error\n"); 289 rx_errors++; 290 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); 291 if (skb) 292 cf->data[2] |= CAN_ERR_PROT_FORM; 293 } 294 if (ecsr & RCAR_CAN_ECSR_SEF) { 295 netdev_dbg(priv->ndev, "Stuff Error\n"); 296 rx_errors++; 297 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); 298 if (skb) 299 cf->data[2] |= CAN_ERR_PROT_STUFF; 300 } 301 302 priv->can.can_stats.bus_error++; 303 ndev->stats.rx_errors += rx_errors; 304 ndev->stats.tx_errors += tx_errors; 305 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); 306 } 307 if (eifr & RCAR_CAN_EIFR_EWIF) { 308 netdev_dbg(priv->ndev, "Error warning interrupt\n"); 309 priv->can.state = CAN_STATE_ERROR_WARNING; 310 priv->can.can_stats.error_warning++; 311 /* Clear interrupt condition */ 312 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); 313 if (skb) 314 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 315 CAN_ERR_CRTL_RX_WARNING; 316 } 317 if (eifr & RCAR_CAN_EIFR_EPIF) { 318 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 319 priv->can.state = CAN_STATE_ERROR_PASSIVE; 320 priv->can.can_stats.error_passive++; 321 /* Clear interrupt condition */ 322 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); 323 if (skb) 324 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 325 CAN_ERR_CRTL_RX_PASSIVE; 326 } 327 if (eifr & RCAR_CAN_EIFR_BOEIF) { 328 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); 329 tx_failure_cleanup(ndev); 330 priv->ier = RCAR_CAN_IER_ERSIE; 331 writeb(priv->ier, &priv->regs->ier); 332 priv->can.state = CAN_STATE_BUS_OFF; 333 /* Clear interrupt condition */ 334 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); 335 priv->can.can_stats.bus_off++; 336 can_bus_off(ndev); 337 if (skb) 338 cf->can_id |= CAN_ERR_BUSOFF; 339 } 340 if (eifr & RCAR_CAN_EIFR_ORIF) { 341 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); 342 ndev->stats.rx_over_errors++; 343 ndev->stats.rx_errors++; 344 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); 345 if (skb) { 346 cf->can_id |= CAN_ERR_CRTL; 347 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 348 } 349 } 350 if (eifr & RCAR_CAN_EIFR_OLIF) { 351 netdev_dbg(priv->ndev, 352 "Overload Frame Transmission error interrupt\n"); 353 ndev->stats.rx_over_errors++; 354 ndev->stats.rx_errors++; 355 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); 356 if (skb) { 357 cf->can_id |= CAN_ERR_PROT; 358 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 359 } 360 } 361 362 if (skb) 363 netif_rx(skb); 364 } 365 366 static void rcar_can_tx_done(struct net_device *ndev) 367 { 368 struct rcar_can_priv *priv = netdev_priv(ndev); 369 struct net_device_stats *stats = &ndev->stats; 370 u8 isr; 371 372 while (1) { 373 u8 unsent = readb(&priv->regs->tfcr); 374 375 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> 376 RCAR_CAN_TFCR_TFUST_SHIFT; 377 if (priv->tx_head - priv->tx_tail <= unsent) 378 break; 379 stats->tx_packets++; 380 stats->tx_bytes += 381 can_get_echo_skb(ndev, 382 priv->tx_tail % RCAR_CAN_FIFO_DEPTH, 383 NULL); 384 385 priv->tx_tail++; 386 netif_wake_queue(ndev); 387 } 388 /* Clear interrupt */ 389 isr = readb(&priv->regs->isr); 390 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); 391 } 392 393 static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) 394 { 395 struct net_device *ndev = dev_id; 396 struct rcar_can_priv *priv = netdev_priv(ndev); 397 u8 isr; 398 399 isr = readb(&priv->regs->isr); 400 if (!(isr & priv->ier)) 401 return IRQ_NONE; 402 403 if (isr & RCAR_CAN_ISR_ERSF) 404 rcar_can_error(ndev); 405 406 if (isr & RCAR_CAN_ISR_TXFF) 407 rcar_can_tx_done(ndev); 408 409 if (isr & RCAR_CAN_ISR_RXFF) { 410 if (napi_schedule_prep(&priv->napi)) { 411 /* Disable Rx FIFO interrupts */ 412 priv->ier &= ~RCAR_CAN_IER_RXFIE; 413 writeb(priv->ier, &priv->regs->ier); 414 __napi_schedule(&priv->napi); 415 } 416 } 417 418 return IRQ_HANDLED; 419 } 420 421 static void rcar_can_set_bittiming(struct net_device *dev) 422 { 423 struct rcar_can_priv *priv = netdev_priv(dev); 424 struct can_bittiming *bt = &priv->can.bittiming; 425 u32 bcr; 426 427 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | 428 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | 429 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); 430 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. 431 * All the registers are big-endian but they get byte-swapped on 32-bit 432 * read/write (but not on 8-bit, contrary to the manuals)... 433 */ 434 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); 435 } 436 437 static void rcar_can_start(struct net_device *ndev) 438 { 439 struct rcar_can_priv *priv = netdev_priv(ndev); 440 u16 ctlr; 441 int i; 442 443 /* Set controller to known mode: 444 * - FIFO mailbox mode 445 * - accept all messages 446 * - overrun mode 447 * CAN is in sleep mode after MCU hardware or software reset. 448 */ 449 ctlr = readw(&priv->regs->ctlr); 450 ctlr &= ~RCAR_CAN_CTLR_SLPM; 451 writew(ctlr, &priv->regs->ctlr); 452 /* Go to reset mode */ 453 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 454 writew(ctlr, &priv->regs->ctlr); 455 for (i = 0; i < MAX_STR_READS; i++) { 456 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 457 break; 458 } 459 rcar_can_set_bittiming(ndev); 460 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ 461 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ 462 /* at bus-off */ 463 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ 464 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ 465 writew(ctlr, &priv->regs->ctlr); 466 467 /* Accept all SID and EID */ 468 writel(0, &priv->regs->mkr_2_9[6]); 469 writel(0, &priv->regs->mkr_2_9[7]); 470 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ 471 writel(0, &priv->regs->mkivlr1); 472 /* Accept all frames */ 473 writel(0, &priv->regs->fidcr[0]); 474 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); 475 /* Enable and configure FIFO mailbox interrupts */ 476 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); 477 478 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | 479 RCAR_CAN_IER_TXFIE; 480 writeb(priv->ier, &priv->regs->ier); 481 482 /* Accumulate error codes */ 483 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); 484 /* Enable error interrupts */ 485 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | 486 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? 487 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | 488 RCAR_CAN_EIER_OLIE, &priv->regs->eier); 489 priv->can.state = CAN_STATE_ERROR_ACTIVE; 490 491 /* Go to operation mode */ 492 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); 493 for (i = 0; i < MAX_STR_READS; i++) { 494 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) 495 break; 496 } 497 /* Enable Rx and Tx FIFO */ 498 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); 499 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); 500 } 501 502 static int rcar_can_open(struct net_device *ndev) 503 { 504 struct rcar_can_priv *priv = netdev_priv(ndev); 505 int err; 506 507 err = clk_prepare_enable(priv->clk); 508 if (err) { 509 netdev_err(ndev, 510 "failed to enable peripheral clock, error %d\n", 511 err); 512 goto out; 513 } 514 err = clk_prepare_enable(priv->can_clk); 515 if (err) { 516 netdev_err(ndev, "failed to enable CAN clock, error %d\n", 517 err); 518 goto out_clock; 519 } 520 err = open_candev(ndev); 521 if (err) { 522 netdev_err(ndev, "open_candev() failed, error %d\n", err); 523 goto out_can_clock; 524 } 525 napi_enable(&priv->napi); 526 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); 527 if (err) { 528 netdev_err(ndev, "request_irq(%d) failed, error %d\n", 529 ndev->irq, err); 530 goto out_close; 531 } 532 rcar_can_start(ndev); 533 netif_start_queue(ndev); 534 return 0; 535 out_close: 536 napi_disable(&priv->napi); 537 close_candev(ndev); 538 out_can_clock: 539 clk_disable_unprepare(priv->can_clk); 540 out_clock: 541 clk_disable_unprepare(priv->clk); 542 out: 543 return err; 544 } 545 546 static void rcar_can_stop(struct net_device *ndev) 547 { 548 struct rcar_can_priv *priv = netdev_priv(ndev); 549 u16 ctlr; 550 int i; 551 552 /* Go to (force) reset mode */ 553 ctlr = readw(&priv->regs->ctlr); 554 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 555 writew(ctlr, &priv->regs->ctlr); 556 for (i = 0; i < MAX_STR_READS; i++) { 557 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 558 break; 559 } 560 writel(0, &priv->regs->mier0); 561 writel(0, &priv->regs->mier1); 562 writeb(0, &priv->regs->ier); 563 writeb(0, &priv->regs->eier); 564 /* Go to sleep mode */ 565 ctlr |= RCAR_CAN_CTLR_SLPM; 566 writew(ctlr, &priv->regs->ctlr); 567 priv->can.state = CAN_STATE_STOPPED; 568 } 569 570 static int rcar_can_close(struct net_device *ndev) 571 { 572 struct rcar_can_priv *priv = netdev_priv(ndev); 573 574 netif_stop_queue(ndev); 575 rcar_can_stop(ndev); 576 free_irq(ndev->irq, ndev); 577 napi_disable(&priv->napi); 578 clk_disable_unprepare(priv->can_clk); 579 clk_disable_unprepare(priv->clk); 580 close_candev(ndev); 581 return 0; 582 } 583 584 static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, 585 struct net_device *ndev) 586 { 587 struct rcar_can_priv *priv = netdev_priv(ndev); 588 struct can_frame *cf = (struct can_frame *)skb->data; 589 u32 data, i; 590 591 if (can_dropped_invalid_skb(ndev, skb)) 592 return NETDEV_TX_OK; 593 594 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 595 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; 596 else /* Standard frame format */ 597 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; 598 599 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ 600 data |= RCAR_CAN_RTR; 601 } else { 602 for (i = 0; i < cf->len; i++) 603 writeb(cf->data[i], 604 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); 605 } 606 607 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); 608 609 writeb(cf->len, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); 610 611 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH, 0); 612 priv->tx_head++; 613 /* Start Tx: write 0xff to the TFPCR register to increment 614 * the CPU-side pointer for the transmit FIFO to the next 615 * mailbox location 616 */ 617 writeb(0xff, &priv->regs->tfpcr); 618 /* Stop the queue if we've filled all FIFO entries */ 619 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) 620 netif_stop_queue(ndev); 621 622 return NETDEV_TX_OK; 623 } 624 625 static const struct net_device_ops rcar_can_netdev_ops = { 626 .ndo_open = rcar_can_open, 627 .ndo_stop = rcar_can_close, 628 .ndo_start_xmit = rcar_can_start_xmit, 629 .ndo_change_mtu = can_change_mtu, 630 }; 631 632 static void rcar_can_rx_pkt(struct rcar_can_priv *priv) 633 { 634 struct net_device_stats *stats = &priv->ndev->stats; 635 struct can_frame *cf; 636 struct sk_buff *skb; 637 u32 data; 638 u8 dlc; 639 640 skb = alloc_can_skb(priv->ndev, &cf); 641 if (!skb) { 642 stats->rx_dropped++; 643 return; 644 } 645 646 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); 647 if (data & RCAR_CAN_IDE) 648 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 649 else 650 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; 651 652 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); 653 cf->len = can_cc_dlc2len(dlc); 654 if (data & RCAR_CAN_RTR) { 655 cf->can_id |= CAN_RTR_FLAG; 656 } else { 657 for (dlc = 0; dlc < cf->len; dlc++) 658 cf->data[dlc] = 659 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); 660 661 stats->rx_bytes += cf->len; 662 } 663 stats->rx_packets++; 664 665 netif_receive_skb(skb); 666 } 667 668 static int rcar_can_rx_poll(struct napi_struct *napi, int quota) 669 { 670 struct rcar_can_priv *priv = container_of(napi, 671 struct rcar_can_priv, napi); 672 int num_pkts; 673 674 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 675 u8 rfcr, isr; 676 677 isr = readb(&priv->regs->isr); 678 /* Clear interrupt bit */ 679 if (isr & RCAR_CAN_ISR_RXFF) 680 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); 681 rfcr = readb(&priv->regs->rfcr); 682 if (rfcr & RCAR_CAN_RFCR_RFEST) 683 break; 684 rcar_can_rx_pkt(priv); 685 /* Write 0xff to the RFPCR register to increment 686 * the CPU-side pointer for the receive FIFO 687 * to the next mailbox location 688 */ 689 writeb(0xff, &priv->regs->rfpcr); 690 } 691 /* All packets processed */ 692 if (num_pkts < quota) { 693 napi_complete_done(napi, num_pkts); 694 priv->ier |= RCAR_CAN_IER_RXFIE; 695 writeb(priv->ier, &priv->regs->ier); 696 } 697 return num_pkts; 698 } 699 700 static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 701 { 702 switch (mode) { 703 case CAN_MODE_START: 704 rcar_can_start(ndev); 705 netif_wake_queue(ndev); 706 return 0; 707 default: 708 return -EOPNOTSUPP; 709 } 710 } 711 712 static int rcar_can_get_berr_counter(const struct net_device *dev, 713 struct can_berr_counter *bec) 714 { 715 struct rcar_can_priv *priv = netdev_priv(dev); 716 int err; 717 718 err = clk_prepare_enable(priv->clk); 719 if (err) 720 return err; 721 bec->txerr = readb(&priv->regs->tecr); 722 bec->rxerr = readb(&priv->regs->recr); 723 clk_disable_unprepare(priv->clk); 724 return 0; 725 } 726 727 static const char * const clock_names[] = { 728 [CLKR_CLKP1] = "clkp1", 729 [CLKR_CLKP2] = "clkp2", 730 [CLKR_CLKEXT] = "can_clk", 731 }; 732 733 static int rcar_can_probe(struct platform_device *pdev) 734 { 735 struct rcar_can_priv *priv; 736 struct net_device *ndev; 737 void __iomem *addr; 738 u32 clock_select = CLKR_CLKP1; 739 int err = -ENODEV; 740 int irq; 741 742 of_property_read_u32(pdev->dev.of_node, "renesas,can-clock-select", 743 &clock_select); 744 745 irq = platform_get_irq(pdev, 0); 746 if (irq < 0) { 747 err = irq; 748 goto fail; 749 } 750 751 addr = devm_platform_ioremap_resource(pdev, 0); 752 if (IS_ERR(addr)) { 753 err = PTR_ERR(addr); 754 goto fail; 755 } 756 757 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); 758 if (!ndev) { 759 dev_err(&pdev->dev, "alloc_candev() failed\n"); 760 err = -ENOMEM; 761 goto fail; 762 } 763 764 priv = netdev_priv(ndev); 765 766 priv->clk = devm_clk_get(&pdev->dev, "clkp1"); 767 if (IS_ERR(priv->clk)) { 768 err = PTR_ERR(priv->clk); 769 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n", 770 err); 771 goto fail_clk; 772 } 773 774 if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) { 775 err = -EINVAL; 776 dev_err(&pdev->dev, "invalid CAN clock selected\n"); 777 goto fail_clk; 778 } 779 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); 780 if (IS_ERR(priv->can_clk)) { 781 err = PTR_ERR(priv->can_clk); 782 dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err); 783 goto fail_clk; 784 } 785 786 ndev->netdev_ops = &rcar_can_netdev_ops; 787 ndev->irq = irq; 788 ndev->flags |= IFF_ECHO; 789 priv->ndev = ndev; 790 priv->regs = addr; 791 priv->clock_select = clock_select; 792 priv->can.clock.freq = clk_get_rate(priv->can_clk); 793 priv->can.bittiming_const = &rcar_can_bittiming_const; 794 priv->can.do_set_mode = rcar_can_do_set_mode; 795 priv->can.do_get_berr_counter = rcar_can_get_berr_counter; 796 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 797 platform_set_drvdata(pdev, ndev); 798 SET_NETDEV_DEV(ndev, &pdev->dev); 799 800 netif_napi_add_weight(ndev, &priv->napi, rcar_can_rx_poll, 801 RCAR_CAN_NAPI_WEIGHT); 802 err = register_candev(ndev); 803 if (err) { 804 dev_err(&pdev->dev, "register_candev() failed, error %d\n", 805 err); 806 goto fail_candev; 807 } 808 809 dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq); 810 811 return 0; 812 fail_candev: 813 netif_napi_del(&priv->napi); 814 fail_clk: 815 free_candev(ndev); 816 fail: 817 return err; 818 } 819 820 static int rcar_can_remove(struct platform_device *pdev) 821 { 822 struct net_device *ndev = platform_get_drvdata(pdev); 823 struct rcar_can_priv *priv = netdev_priv(ndev); 824 825 unregister_candev(ndev); 826 netif_napi_del(&priv->napi); 827 free_candev(ndev); 828 return 0; 829 } 830 831 static int __maybe_unused rcar_can_suspend(struct device *dev) 832 { 833 struct net_device *ndev = dev_get_drvdata(dev); 834 struct rcar_can_priv *priv = netdev_priv(ndev); 835 u16 ctlr; 836 837 if (!netif_running(ndev)) 838 return 0; 839 840 netif_stop_queue(ndev); 841 netif_device_detach(ndev); 842 843 ctlr = readw(&priv->regs->ctlr); 844 ctlr |= RCAR_CAN_CTLR_CANM_HALT; 845 writew(ctlr, &priv->regs->ctlr); 846 ctlr |= RCAR_CAN_CTLR_SLPM; 847 writew(ctlr, &priv->regs->ctlr); 848 priv->can.state = CAN_STATE_SLEEPING; 849 850 clk_disable(priv->clk); 851 return 0; 852 } 853 854 static int __maybe_unused rcar_can_resume(struct device *dev) 855 { 856 struct net_device *ndev = dev_get_drvdata(dev); 857 struct rcar_can_priv *priv = netdev_priv(ndev); 858 u16 ctlr; 859 int err; 860 861 if (!netif_running(ndev)) 862 return 0; 863 864 err = clk_enable(priv->clk); 865 if (err) { 866 netdev_err(ndev, "clk_enable() failed, error %d\n", err); 867 return err; 868 } 869 870 ctlr = readw(&priv->regs->ctlr); 871 ctlr &= ~RCAR_CAN_CTLR_SLPM; 872 writew(ctlr, &priv->regs->ctlr); 873 ctlr &= ~RCAR_CAN_CTLR_CANM; 874 writew(ctlr, &priv->regs->ctlr); 875 priv->can.state = CAN_STATE_ERROR_ACTIVE; 876 877 netif_device_attach(ndev); 878 netif_start_queue(ndev); 879 880 return 0; 881 } 882 883 static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); 884 885 static const struct of_device_id rcar_can_of_table[] __maybe_unused = { 886 { .compatible = "renesas,can-r8a7778" }, 887 { .compatible = "renesas,can-r8a7779" }, 888 { .compatible = "renesas,can-r8a7790" }, 889 { .compatible = "renesas,can-r8a7791" }, 890 { .compatible = "renesas,rcar-gen1-can" }, 891 { .compatible = "renesas,rcar-gen2-can" }, 892 { .compatible = "renesas,rcar-gen3-can" }, 893 { } 894 }; 895 MODULE_DEVICE_TABLE(of, rcar_can_of_table); 896 897 static struct platform_driver rcar_can_driver = { 898 .driver = { 899 .name = RCAR_CAN_DRV_NAME, 900 .of_match_table = of_match_ptr(rcar_can_of_table), 901 .pm = &rcar_can_pm_ops, 902 }, 903 .probe = rcar_can_probe, 904 .remove = rcar_can_remove, 905 }; 906 907 module_platform_driver(rcar_can_driver); 908 909 MODULE_AUTHOR("Cogent Embedded, Inc."); 910 MODULE_LICENSE("GPL"); 911 MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); 912 MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); 913