1 /* Renesas R-Car CAN device driver 2 * 3 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/types.h> 15 #include <linux/interrupt.h> 16 #include <linux/errno.h> 17 #include <linux/netdevice.h> 18 #include <linux/platform_device.h> 19 #include <linux/can/led.h> 20 #include <linux/can/dev.h> 21 #include <linux/clk.h> 22 #include <linux/can/platform/rcar_can.h> 23 #include <linux/of.h> 24 25 #define RCAR_CAN_DRV_NAME "rcar_can" 26 27 #define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ 28 BIT(CLKR_CLKEXT)) 29 30 /* Mailbox configuration: 31 * mailbox 60 - 63 - Rx FIFO mailboxes 32 * mailbox 56 - 59 - Tx FIFO mailboxes 33 * non-FIFO mailboxes are not used 34 */ 35 #define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ 36 #define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ 37 #define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ 38 #define RCAR_CAN_FIFO_DEPTH 4 39 40 /* Mailbox registers structure */ 41 struct rcar_can_mbox_regs { 42 u32 id; /* IDE and RTR bits, SID and EID */ 43 u8 stub; /* Not used */ 44 u8 dlc; /* Data Length Code - bits [0..3] */ 45 u8 data[8]; /* Data Bytes */ 46 u8 tsh; /* Time Stamp Higher Byte */ 47 u8 tsl; /* Time Stamp Lower Byte */ 48 }; 49 50 struct rcar_can_regs { 51 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ 52 u32 mkr_2_9[8]; /* Mask Registers 2-9 */ 53 u32 fidcr[2]; /* FIFO Received ID Compare Register */ 54 u32 mkivlr1; /* Mask Invalid Register 1 */ 55 u32 mier1; /* Mailbox Interrupt Enable Register 1 */ 56 u32 mkr_0_1[2]; /* Mask Registers 0-1 */ 57 u32 mkivlr0; /* Mask Invalid Register 0*/ 58 u32 mier0; /* Mailbox Interrupt Enable Register 0 */ 59 u8 pad_440[0x3c0]; 60 u8 mctl[64]; /* Message Control Registers */ 61 u16 ctlr; /* Control Register */ 62 u16 str; /* Status register */ 63 u8 bcr[3]; /* Bit Configuration Register */ 64 u8 clkr; /* Clock Select Register */ 65 u8 rfcr; /* Receive FIFO Control Register */ 66 u8 rfpcr; /* Receive FIFO Pointer Control Register */ 67 u8 tfcr; /* Transmit FIFO Control Register */ 68 u8 tfpcr; /* Transmit FIFO Pointer Control Register */ 69 u8 eier; /* Error Interrupt Enable Register */ 70 u8 eifr; /* Error Interrupt Factor Judge Register */ 71 u8 recr; /* Receive Error Count Register */ 72 u8 tecr; /* Transmit Error Count Register */ 73 u8 ecsr; /* Error Code Store Register */ 74 u8 cssr; /* Channel Search Support Register */ 75 u8 mssr; /* Mailbox Search Status Register */ 76 u8 msmr; /* Mailbox Search Mode Register */ 77 u16 tsr; /* Time Stamp Register */ 78 u8 afsr; /* Acceptance Filter Support Register */ 79 u8 pad_857; 80 u8 tcr; /* Test Control Register */ 81 u8 pad_859[7]; 82 u8 ier; /* Interrupt Enable Register */ 83 u8 isr; /* Interrupt Status Register */ 84 u8 pad_862; 85 u8 mbsmr; /* Mailbox Search Mask Register */ 86 }; 87 88 struct rcar_can_priv { 89 struct can_priv can; /* Must be the first member! */ 90 struct net_device *ndev; 91 struct napi_struct napi; 92 struct rcar_can_regs __iomem *regs; 93 struct clk *clk; 94 struct clk *can_clk; 95 u8 tx_dlc[RCAR_CAN_FIFO_DEPTH]; 96 u32 tx_head; 97 u32 tx_tail; 98 u8 clock_select; 99 u8 ier; 100 }; 101 102 static const struct can_bittiming_const rcar_can_bittiming_const = { 103 .name = RCAR_CAN_DRV_NAME, 104 .tseg1_min = 4, 105 .tseg1_max = 16, 106 .tseg2_min = 2, 107 .tseg2_max = 8, 108 .sjw_max = 4, 109 .brp_min = 1, 110 .brp_max = 1024, 111 .brp_inc = 1, 112 }; 113 114 /* Control Register bits */ 115 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ 116 #define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ 117 /* at bus-off entry */ 118 #define RCAR_CAN_CTLR_SLPM (1 << 10) 119 #define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ 120 #define RCAR_CAN_CTLR_CANM_HALT (1 << 9) 121 #define RCAR_CAN_CTLR_CANM_RESET (1 << 8) 122 #define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) 123 #define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ 124 #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ 125 #define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ 126 #define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ 127 128 /* Status Register bits */ 129 #define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ 130 131 /* FIFO Received ID Compare Registers 0 and 1 bits */ 132 #define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ 133 #define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ 134 135 /* Receive FIFO Control Register bits */ 136 #define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ 137 #define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ 138 139 /* Transmit FIFO Control Register bits */ 140 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ 141 /* Number Status Bits */ 142 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ 143 /* Message Number Status Bits */ 144 #define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ 145 146 #define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ 147 /* for Rx mailboxes 0-31 */ 148 #define RCAR_CAN_N_RX_MKREGS2 8 149 150 /* Bit Configuration Register settings */ 151 #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) 152 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) 153 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) 154 #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) 155 156 /* Mailbox and Mask Registers bits */ 157 #define RCAR_CAN_IDE (1 << 31) 158 #define RCAR_CAN_RTR (1 << 30) 159 #define RCAR_CAN_SID_SHIFT 18 160 161 /* Mailbox Interrupt Enable Register 1 bits */ 162 #define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ 163 #define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ 164 165 /* Interrupt Enable Register bits */ 166 #define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ 167 #define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ 168 /* Enable Bit */ 169 #define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ 170 /* Enable Bit */ 171 /* Interrupt Status Register bits */ 172 #define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ 173 #define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ 174 /* Status Bit */ 175 #define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ 176 /* Status Bit */ 177 178 /* Error Interrupt Enable Register bits */ 179 #define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ 180 #define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ 181 /* Interrupt Enable */ 182 #define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ 183 #define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ 184 #define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ 185 #define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ 186 #define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ 187 #define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ 188 189 /* Error Interrupt Factor Judge Register bits */ 190 #define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ 191 #define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ 192 /* Detect Flag */ 193 #define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ 194 #define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ 195 #define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ 196 #define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ 197 #define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ 198 #define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ 199 200 /* Error Code Store Register bits */ 201 #define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ 202 #define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ 203 #define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ 204 #define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ 205 #define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ 206 #define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ 207 #define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ 208 #define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ 209 210 #define RCAR_CAN_NAPI_WEIGHT 4 211 #define MAX_STR_READS 0x100 212 213 static void tx_failure_cleanup(struct net_device *ndev) 214 { 215 int i; 216 217 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) 218 can_free_echo_skb(ndev, i); 219 } 220 221 static void rcar_can_error(struct net_device *ndev) 222 { 223 struct rcar_can_priv *priv = netdev_priv(ndev); 224 struct net_device_stats *stats = &ndev->stats; 225 struct can_frame *cf; 226 struct sk_buff *skb; 227 u8 eifr, txerr = 0, rxerr = 0; 228 229 /* Propagate the error condition to the CAN stack */ 230 skb = alloc_can_err_skb(ndev, &cf); 231 232 eifr = readb(&priv->regs->eifr); 233 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { 234 txerr = readb(&priv->regs->tecr); 235 rxerr = readb(&priv->regs->recr); 236 if (skb) { 237 cf->can_id |= CAN_ERR_CRTL; 238 cf->data[6] = txerr; 239 cf->data[7] = rxerr; 240 } 241 } 242 if (eifr & RCAR_CAN_EIFR_BEIF) { 243 int rx_errors = 0, tx_errors = 0; 244 u8 ecsr; 245 246 netdev_dbg(priv->ndev, "Bus error interrupt:\n"); 247 if (skb) 248 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 249 250 ecsr = readb(&priv->regs->ecsr); 251 if (ecsr & RCAR_CAN_ECSR_ADEF) { 252 netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); 253 tx_errors++; 254 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); 255 if (skb) 256 cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL; 257 } 258 if (ecsr & RCAR_CAN_ECSR_BE0F) { 259 netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); 260 tx_errors++; 261 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); 262 if (skb) 263 cf->data[2] |= CAN_ERR_PROT_BIT0; 264 } 265 if (ecsr & RCAR_CAN_ECSR_BE1F) { 266 netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); 267 tx_errors++; 268 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); 269 if (skb) 270 cf->data[2] |= CAN_ERR_PROT_BIT1; 271 } 272 if (ecsr & RCAR_CAN_ECSR_CEF) { 273 netdev_dbg(priv->ndev, "CRC Error\n"); 274 rx_errors++; 275 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); 276 if (skb) 277 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 278 } 279 if (ecsr & RCAR_CAN_ECSR_AEF) { 280 netdev_dbg(priv->ndev, "ACK Error\n"); 281 tx_errors++; 282 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); 283 if (skb) { 284 cf->can_id |= CAN_ERR_ACK; 285 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 286 } 287 } 288 if (ecsr & RCAR_CAN_ECSR_FEF) { 289 netdev_dbg(priv->ndev, "Form Error\n"); 290 rx_errors++; 291 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); 292 if (skb) 293 cf->data[2] |= CAN_ERR_PROT_FORM; 294 } 295 if (ecsr & RCAR_CAN_ECSR_SEF) { 296 netdev_dbg(priv->ndev, "Stuff Error\n"); 297 rx_errors++; 298 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); 299 if (skb) 300 cf->data[2] |= CAN_ERR_PROT_STUFF; 301 } 302 303 priv->can.can_stats.bus_error++; 304 ndev->stats.rx_errors += rx_errors; 305 ndev->stats.tx_errors += tx_errors; 306 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); 307 } 308 if (eifr & RCAR_CAN_EIFR_EWIF) { 309 netdev_dbg(priv->ndev, "Error warning interrupt\n"); 310 priv->can.state = CAN_STATE_ERROR_WARNING; 311 priv->can.can_stats.error_warning++; 312 /* Clear interrupt condition */ 313 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); 314 if (skb) 315 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 316 CAN_ERR_CRTL_RX_WARNING; 317 } 318 if (eifr & RCAR_CAN_EIFR_EPIF) { 319 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 320 priv->can.state = CAN_STATE_ERROR_PASSIVE; 321 priv->can.can_stats.error_passive++; 322 /* Clear interrupt condition */ 323 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); 324 if (skb) 325 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 326 CAN_ERR_CRTL_RX_PASSIVE; 327 } 328 if (eifr & RCAR_CAN_EIFR_BOEIF) { 329 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); 330 tx_failure_cleanup(ndev); 331 priv->ier = RCAR_CAN_IER_ERSIE; 332 writeb(priv->ier, &priv->regs->ier); 333 priv->can.state = CAN_STATE_BUS_OFF; 334 /* Clear interrupt condition */ 335 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); 336 priv->can.can_stats.bus_off++; 337 can_bus_off(ndev); 338 if (skb) 339 cf->can_id |= CAN_ERR_BUSOFF; 340 } 341 if (eifr & RCAR_CAN_EIFR_ORIF) { 342 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); 343 ndev->stats.rx_over_errors++; 344 ndev->stats.rx_errors++; 345 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); 346 if (skb) { 347 cf->can_id |= CAN_ERR_CRTL; 348 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 349 } 350 } 351 if (eifr & RCAR_CAN_EIFR_OLIF) { 352 netdev_dbg(priv->ndev, 353 "Overload Frame Transmission error interrupt\n"); 354 ndev->stats.rx_over_errors++; 355 ndev->stats.rx_errors++; 356 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); 357 if (skb) { 358 cf->can_id |= CAN_ERR_PROT; 359 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 360 } 361 } 362 363 if (skb) { 364 stats->rx_packets++; 365 stats->rx_bytes += cf->can_dlc; 366 netif_rx(skb); 367 } 368 } 369 370 static void rcar_can_tx_done(struct net_device *ndev) 371 { 372 struct rcar_can_priv *priv = netdev_priv(ndev); 373 struct net_device_stats *stats = &ndev->stats; 374 u8 isr; 375 376 while (1) { 377 u8 unsent = readb(&priv->regs->tfcr); 378 379 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> 380 RCAR_CAN_TFCR_TFUST_SHIFT; 381 if (priv->tx_head - priv->tx_tail <= unsent) 382 break; 383 stats->tx_packets++; 384 stats->tx_bytes += priv->tx_dlc[priv->tx_tail % 385 RCAR_CAN_FIFO_DEPTH]; 386 priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0; 387 can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH); 388 priv->tx_tail++; 389 netif_wake_queue(ndev); 390 } 391 /* Clear interrupt */ 392 isr = readb(&priv->regs->isr); 393 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); 394 can_led_event(ndev, CAN_LED_EVENT_TX); 395 } 396 397 static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) 398 { 399 struct net_device *ndev = dev_id; 400 struct rcar_can_priv *priv = netdev_priv(ndev); 401 u8 isr; 402 403 isr = readb(&priv->regs->isr); 404 if (!(isr & priv->ier)) 405 return IRQ_NONE; 406 407 if (isr & RCAR_CAN_ISR_ERSF) 408 rcar_can_error(ndev); 409 410 if (isr & RCAR_CAN_ISR_TXFF) 411 rcar_can_tx_done(ndev); 412 413 if (isr & RCAR_CAN_ISR_RXFF) { 414 if (napi_schedule_prep(&priv->napi)) { 415 /* Disable Rx FIFO interrupts */ 416 priv->ier &= ~RCAR_CAN_IER_RXFIE; 417 writeb(priv->ier, &priv->regs->ier); 418 __napi_schedule(&priv->napi); 419 } 420 } 421 422 return IRQ_HANDLED; 423 } 424 425 static void rcar_can_set_bittiming(struct net_device *dev) 426 { 427 struct rcar_can_priv *priv = netdev_priv(dev); 428 struct can_bittiming *bt = &priv->can.bittiming; 429 u32 bcr; 430 431 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | 432 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | 433 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); 434 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. 435 * All the registers are big-endian but they get byte-swapped on 32-bit 436 * read/write (but not on 8-bit, contrary to the manuals)... 437 */ 438 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); 439 } 440 441 static void rcar_can_start(struct net_device *ndev) 442 { 443 struct rcar_can_priv *priv = netdev_priv(ndev); 444 u16 ctlr; 445 int i; 446 447 /* Set controller to known mode: 448 * - FIFO mailbox mode 449 * - accept all messages 450 * - overrun mode 451 * CAN is in sleep mode after MCU hardware or software reset. 452 */ 453 ctlr = readw(&priv->regs->ctlr); 454 ctlr &= ~RCAR_CAN_CTLR_SLPM; 455 writew(ctlr, &priv->regs->ctlr); 456 /* Go to reset mode */ 457 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 458 writew(ctlr, &priv->regs->ctlr); 459 for (i = 0; i < MAX_STR_READS; i++) { 460 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 461 break; 462 } 463 rcar_can_set_bittiming(ndev); 464 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ 465 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ 466 /* at bus-off */ 467 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ 468 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ 469 writew(ctlr, &priv->regs->ctlr); 470 471 /* Accept all SID and EID */ 472 writel(0, &priv->regs->mkr_2_9[6]); 473 writel(0, &priv->regs->mkr_2_9[7]); 474 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ 475 writel(0, &priv->regs->mkivlr1); 476 /* Accept all frames */ 477 writel(0, &priv->regs->fidcr[0]); 478 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); 479 /* Enable and configure FIFO mailbox interrupts */ 480 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); 481 482 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | 483 RCAR_CAN_IER_TXFIE; 484 writeb(priv->ier, &priv->regs->ier); 485 486 /* Accumulate error codes */ 487 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); 488 /* Enable error interrupts */ 489 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | 490 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? 491 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | 492 RCAR_CAN_EIER_OLIE, &priv->regs->eier); 493 priv->can.state = CAN_STATE_ERROR_ACTIVE; 494 495 /* Go to operation mode */ 496 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); 497 for (i = 0; i < MAX_STR_READS; i++) { 498 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) 499 break; 500 } 501 /* Enable Rx and Tx FIFO */ 502 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); 503 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); 504 } 505 506 static int rcar_can_open(struct net_device *ndev) 507 { 508 struct rcar_can_priv *priv = netdev_priv(ndev); 509 int err; 510 511 err = clk_prepare_enable(priv->clk); 512 if (err) { 513 netdev_err(ndev, 514 "failed to enable peripheral clock, error %d\n", 515 err); 516 goto out; 517 } 518 err = clk_prepare_enable(priv->can_clk); 519 if (err) { 520 netdev_err(ndev, "failed to enable CAN clock, error %d\n", 521 err); 522 goto out_clock; 523 } 524 err = open_candev(ndev); 525 if (err) { 526 netdev_err(ndev, "open_candev() failed, error %d\n", err); 527 goto out_can_clock; 528 } 529 napi_enable(&priv->napi); 530 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); 531 if (err) { 532 netdev_err(ndev, "request_irq(%d) failed, error %d\n", 533 ndev->irq, err); 534 goto out_close; 535 } 536 can_led_event(ndev, CAN_LED_EVENT_OPEN); 537 rcar_can_start(ndev); 538 netif_start_queue(ndev); 539 return 0; 540 out_close: 541 napi_disable(&priv->napi); 542 close_candev(ndev); 543 out_can_clock: 544 clk_disable_unprepare(priv->can_clk); 545 out_clock: 546 clk_disable_unprepare(priv->clk); 547 out: 548 return err; 549 } 550 551 static void rcar_can_stop(struct net_device *ndev) 552 { 553 struct rcar_can_priv *priv = netdev_priv(ndev); 554 u16 ctlr; 555 int i; 556 557 /* Go to (force) reset mode */ 558 ctlr = readw(&priv->regs->ctlr); 559 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 560 writew(ctlr, &priv->regs->ctlr); 561 for (i = 0; i < MAX_STR_READS; i++) { 562 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 563 break; 564 } 565 writel(0, &priv->regs->mier0); 566 writel(0, &priv->regs->mier1); 567 writeb(0, &priv->regs->ier); 568 writeb(0, &priv->regs->eier); 569 /* Go to sleep mode */ 570 ctlr |= RCAR_CAN_CTLR_SLPM; 571 writew(ctlr, &priv->regs->ctlr); 572 priv->can.state = CAN_STATE_STOPPED; 573 } 574 575 static int rcar_can_close(struct net_device *ndev) 576 { 577 struct rcar_can_priv *priv = netdev_priv(ndev); 578 579 netif_stop_queue(ndev); 580 rcar_can_stop(ndev); 581 free_irq(ndev->irq, ndev); 582 napi_disable(&priv->napi); 583 clk_disable_unprepare(priv->can_clk); 584 clk_disable_unprepare(priv->clk); 585 close_candev(ndev); 586 can_led_event(ndev, CAN_LED_EVENT_STOP); 587 return 0; 588 } 589 590 static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, 591 struct net_device *ndev) 592 { 593 struct rcar_can_priv *priv = netdev_priv(ndev); 594 struct can_frame *cf = (struct can_frame *)skb->data; 595 u32 data, i; 596 597 if (can_dropped_invalid_skb(ndev, skb)) 598 return NETDEV_TX_OK; 599 600 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 601 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; 602 else /* Standard frame format */ 603 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; 604 605 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ 606 data |= RCAR_CAN_RTR; 607 } else { 608 for (i = 0; i < cf->can_dlc; i++) 609 writeb(cf->data[i], 610 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); 611 } 612 613 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); 614 615 writeb(cf->can_dlc, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); 616 617 priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->can_dlc; 618 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH); 619 priv->tx_head++; 620 /* Start Tx: write 0xff to the TFPCR register to increment 621 * the CPU-side pointer for the transmit FIFO to the next 622 * mailbox location 623 */ 624 writeb(0xff, &priv->regs->tfpcr); 625 /* Stop the queue if we've filled all FIFO entries */ 626 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) 627 netif_stop_queue(ndev); 628 629 return NETDEV_TX_OK; 630 } 631 632 static const struct net_device_ops rcar_can_netdev_ops = { 633 .ndo_open = rcar_can_open, 634 .ndo_stop = rcar_can_close, 635 .ndo_start_xmit = rcar_can_start_xmit, 636 .ndo_change_mtu = can_change_mtu, 637 }; 638 639 static void rcar_can_rx_pkt(struct rcar_can_priv *priv) 640 { 641 struct net_device_stats *stats = &priv->ndev->stats; 642 struct can_frame *cf; 643 struct sk_buff *skb; 644 u32 data; 645 u8 dlc; 646 647 skb = alloc_can_skb(priv->ndev, &cf); 648 if (!skb) { 649 stats->rx_dropped++; 650 return; 651 } 652 653 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); 654 if (data & RCAR_CAN_IDE) 655 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 656 else 657 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; 658 659 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); 660 cf->can_dlc = get_can_dlc(dlc); 661 if (data & RCAR_CAN_RTR) { 662 cf->can_id |= CAN_RTR_FLAG; 663 } else { 664 for (dlc = 0; dlc < cf->can_dlc; dlc++) 665 cf->data[dlc] = 666 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); 667 } 668 669 can_led_event(priv->ndev, CAN_LED_EVENT_RX); 670 671 stats->rx_bytes += cf->can_dlc; 672 stats->rx_packets++; 673 netif_receive_skb(skb); 674 } 675 676 static int rcar_can_rx_poll(struct napi_struct *napi, int quota) 677 { 678 struct rcar_can_priv *priv = container_of(napi, 679 struct rcar_can_priv, napi); 680 int num_pkts; 681 682 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 683 u8 rfcr, isr; 684 685 isr = readb(&priv->regs->isr); 686 /* Clear interrupt bit */ 687 if (isr & RCAR_CAN_ISR_RXFF) 688 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); 689 rfcr = readb(&priv->regs->rfcr); 690 if (rfcr & RCAR_CAN_RFCR_RFEST) 691 break; 692 rcar_can_rx_pkt(priv); 693 /* Write 0xff to the RFPCR register to increment 694 * the CPU-side pointer for the receive FIFO 695 * to the next mailbox location 696 */ 697 writeb(0xff, &priv->regs->rfpcr); 698 } 699 /* All packets processed */ 700 if (num_pkts < quota) { 701 napi_complete_done(napi, num_pkts); 702 priv->ier |= RCAR_CAN_IER_RXFIE; 703 writeb(priv->ier, &priv->regs->ier); 704 } 705 return num_pkts; 706 } 707 708 static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 709 { 710 switch (mode) { 711 case CAN_MODE_START: 712 rcar_can_start(ndev); 713 netif_wake_queue(ndev); 714 return 0; 715 default: 716 return -EOPNOTSUPP; 717 } 718 } 719 720 static int rcar_can_get_berr_counter(const struct net_device *dev, 721 struct can_berr_counter *bec) 722 { 723 struct rcar_can_priv *priv = netdev_priv(dev); 724 int err; 725 726 err = clk_prepare_enable(priv->clk); 727 if (err) 728 return err; 729 bec->txerr = readb(&priv->regs->tecr); 730 bec->rxerr = readb(&priv->regs->recr); 731 clk_disable_unprepare(priv->clk); 732 return 0; 733 } 734 735 static const char * const clock_names[] = { 736 [CLKR_CLKP1] = "clkp1", 737 [CLKR_CLKP2] = "clkp2", 738 [CLKR_CLKEXT] = "can_clk", 739 }; 740 741 static int rcar_can_probe(struct platform_device *pdev) 742 { 743 struct rcar_can_platform_data *pdata; 744 struct rcar_can_priv *priv; 745 struct net_device *ndev; 746 struct resource *mem; 747 void __iomem *addr; 748 u32 clock_select = CLKR_CLKP1; 749 int err = -ENODEV; 750 int irq; 751 752 if (pdev->dev.of_node) { 753 of_property_read_u32(pdev->dev.of_node, 754 "renesas,can-clock-select", &clock_select); 755 } else { 756 pdata = dev_get_platdata(&pdev->dev); 757 if (!pdata) { 758 dev_err(&pdev->dev, "No platform data provided!\n"); 759 goto fail; 760 } 761 clock_select = pdata->clock_select; 762 } 763 764 irq = platform_get_irq(pdev, 0); 765 if (irq < 0) { 766 dev_err(&pdev->dev, "No IRQ resource\n"); 767 err = irq; 768 goto fail; 769 } 770 771 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 772 addr = devm_ioremap_resource(&pdev->dev, mem); 773 if (IS_ERR(addr)) { 774 err = PTR_ERR(addr); 775 goto fail; 776 } 777 778 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); 779 if (!ndev) { 780 dev_err(&pdev->dev, "alloc_candev() failed\n"); 781 err = -ENOMEM; 782 goto fail; 783 } 784 785 priv = netdev_priv(ndev); 786 787 priv->clk = devm_clk_get(&pdev->dev, "clkp1"); 788 if (IS_ERR(priv->clk)) { 789 err = PTR_ERR(priv->clk); 790 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n", 791 err); 792 goto fail_clk; 793 } 794 795 if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) { 796 err = -EINVAL; 797 dev_err(&pdev->dev, "invalid CAN clock selected\n"); 798 goto fail_clk; 799 } 800 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); 801 if (IS_ERR(priv->can_clk)) { 802 err = PTR_ERR(priv->can_clk); 803 dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err); 804 goto fail_clk; 805 } 806 807 ndev->netdev_ops = &rcar_can_netdev_ops; 808 ndev->irq = irq; 809 ndev->flags |= IFF_ECHO; 810 priv->ndev = ndev; 811 priv->regs = addr; 812 priv->clock_select = clock_select; 813 priv->can.clock.freq = clk_get_rate(priv->can_clk); 814 priv->can.bittiming_const = &rcar_can_bittiming_const; 815 priv->can.do_set_mode = rcar_can_do_set_mode; 816 priv->can.do_get_berr_counter = rcar_can_get_berr_counter; 817 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 818 platform_set_drvdata(pdev, ndev); 819 SET_NETDEV_DEV(ndev, &pdev->dev); 820 821 netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll, 822 RCAR_CAN_NAPI_WEIGHT); 823 err = register_candev(ndev); 824 if (err) { 825 dev_err(&pdev->dev, "register_candev() failed, error %d\n", 826 err); 827 goto fail_candev; 828 } 829 830 devm_can_led_init(ndev); 831 832 dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq); 833 834 return 0; 835 fail_candev: 836 netif_napi_del(&priv->napi); 837 fail_clk: 838 free_candev(ndev); 839 fail: 840 return err; 841 } 842 843 static int rcar_can_remove(struct platform_device *pdev) 844 { 845 struct net_device *ndev = platform_get_drvdata(pdev); 846 struct rcar_can_priv *priv = netdev_priv(ndev); 847 848 unregister_candev(ndev); 849 netif_napi_del(&priv->napi); 850 free_candev(ndev); 851 return 0; 852 } 853 854 static int __maybe_unused rcar_can_suspend(struct device *dev) 855 { 856 struct net_device *ndev = dev_get_drvdata(dev); 857 struct rcar_can_priv *priv = netdev_priv(ndev); 858 u16 ctlr; 859 860 if (netif_running(ndev)) { 861 netif_stop_queue(ndev); 862 netif_device_detach(ndev); 863 } 864 ctlr = readw(&priv->regs->ctlr); 865 ctlr |= RCAR_CAN_CTLR_CANM_HALT; 866 writew(ctlr, &priv->regs->ctlr); 867 ctlr |= RCAR_CAN_CTLR_SLPM; 868 writew(ctlr, &priv->regs->ctlr); 869 priv->can.state = CAN_STATE_SLEEPING; 870 871 clk_disable(priv->clk); 872 return 0; 873 } 874 875 static int __maybe_unused rcar_can_resume(struct device *dev) 876 { 877 struct net_device *ndev = dev_get_drvdata(dev); 878 struct rcar_can_priv *priv = netdev_priv(ndev); 879 u16 ctlr; 880 int err; 881 882 err = clk_enable(priv->clk); 883 if (err) { 884 netdev_err(ndev, "clk_enable() failed, error %d\n", err); 885 return err; 886 } 887 888 ctlr = readw(&priv->regs->ctlr); 889 ctlr &= ~RCAR_CAN_CTLR_SLPM; 890 writew(ctlr, &priv->regs->ctlr); 891 ctlr &= ~RCAR_CAN_CTLR_CANM; 892 writew(ctlr, &priv->regs->ctlr); 893 priv->can.state = CAN_STATE_ERROR_ACTIVE; 894 895 if (netif_running(ndev)) { 896 netif_device_attach(ndev); 897 netif_start_queue(ndev); 898 } 899 return 0; 900 } 901 902 static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); 903 904 static const struct of_device_id rcar_can_of_table[] __maybe_unused = { 905 { .compatible = "renesas,can-r8a7778" }, 906 { .compatible = "renesas,can-r8a7779" }, 907 { .compatible = "renesas,can-r8a7790" }, 908 { .compatible = "renesas,can-r8a7791" }, 909 { .compatible = "renesas,rcar-gen1-can" }, 910 { .compatible = "renesas,rcar-gen2-can" }, 911 { .compatible = "renesas,rcar-gen3-can" }, 912 { } 913 }; 914 MODULE_DEVICE_TABLE(of, rcar_can_of_table); 915 916 static struct platform_driver rcar_can_driver = { 917 .driver = { 918 .name = RCAR_CAN_DRV_NAME, 919 .of_match_table = of_match_ptr(rcar_can_of_table), 920 .pm = &rcar_can_pm_ops, 921 }, 922 .probe = rcar_can_probe, 923 .remove = rcar_can_remove, 924 }; 925 926 module_platform_driver(rcar_can_driver); 927 928 MODULE_AUTHOR("Cogent Embedded, Inc."); 929 MODULE_LICENSE("GPL"); 930 MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); 931 MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); 932