1 /* 2 * Copyright (C) 2007, 2011 Wolfgang Grandegger <wg@grandegger.com> 3 * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com> 4 * 5 * Derived from the PCAN project file driver/src/pcan_pci.c: 6 * 7 * Copyright (C) 2001-2006 PEAK System-Technik GmbH 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/interrupt.h> 22 #include <linux/netdevice.h> 23 #include <linux/delay.h> 24 #include <linux/pci.h> 25 #include <linux/io.h> 26 #include <linux/can.h> 27 #include <linux/can/dev.h> 28 29 #include "peak_canfd_user.h" 30 31 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>"); 32 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCIe FD family cards"); 33 MODULE_SUPPORTED_DEVICE("PEAK PCAN PCIe FD CAN cards"); 34 MODULE_LICENSE("GPL v2"); 35 36 #define PCIEFD_DRV_NAME "peak_pciefd" 37 38 #define PEAK_PCI_VENDOR_ID 0x001c /* The PCI device and vendor IDs */ 39 #define PEAK_PCIEFD_ID 0x0013 /* for PCIe slot cards */ 40 41 /* PEAK PCIe board access description */ 42 #define PCIEFD_BAR0_SIZE (64 * 1024) 43 #define PCIEFD_RX_DMA_SIZE (4 * 1024) 44 #define PCIEFD_TX_DMA_SIZE (4 * 1024) 45 46 #define PCIEFD_TX_PAGE_SIZE (2 * 1024) 47 48 /* System Control Registers */ 49 #define PCIEFD_REG_SYS_CTL_SET 0x0000 /* set bits */ 50 #define PCIEFD_REG_SYS_CTL_CLR 0x0004 /* clear bits */ 51 52 /* Version info registers */ 53 #define PCIEFD_REG_SYS_VER1 0x0040 /* version reg #1 */ 54 #define PCIEFD_REG_SYS_VER2 0x0044 /* version reg #2 */ 55 56 /* System Control Registers Bits */ 57 #define PCIEFD_SYS_CTL_TS_RST 0x00000001 /* timestamp clock */ 58 #define PCIEFD_SYS_CTL_CLK_EN 0x00000002 /* system clock */ 59 60 /* CAN-FD channel addresses */ 61 #define PCIEFD_CANX_OFF(c) (((c) + 1) * 0x1000) 62 63 #define PCIEFD_ECHO_SKB_MAX PCANFD_ECHO_SKB_DEF 64 65 /* CAN-FD channel registers */ 66 #define PCIEFD_REG_CAN_MISC 0x0000 /* Misc. control */ 67 #define PCIEFD_REG_CAN_CLK_SEL 0x0008 /* Clock selector */ 68 #define PCIEFD_REG_CAN_CMD_PORT_L 0x0010 /* 64-bits command port */ 69 #define PCIEFD_REG_CAN_CMD_PORT_H 0x0014 70 #define PCIEFD_REG_CAN_TX_REQ_ACC 0x0020 /* Tx request accumulator */ 71 #define PCIEFD_REG_CAN_TX_CTL_SET 0x0030 /* Tx control set register */ 72 #define PCIEFD_REG_CAN_TX_CTL_CLR 0x0038 /* Tx control clear register */ 73 #define PCIEFD_REG_CAN_TX_DMA_ADDR_L 0x0040 /* 64-bits addr for Tx DMA */ 74 #define PCIEFD_REG_CAN_TX_DMA_ADDR_H 0x0044 75 #define PCIEFD_REG_CAN_RX_CTL_SET 0x0050 /* Rx control set register */ 76 #define PCIEFD_REG_CAN_RX_CTL_CLR 0x0058 /* Rx control clear register */ 77 #define PCIEFD_REG_CAN_RX_CTL_WRT 0x0060 /* Rx control write register */ 78 #define PCIEFD_REG_CAN_RX_CTL_ACK 0x0068 /* Rx control ACK register */ 79 #define PCIEFD_REG_CAN_RX_DMA_ADDR_L 0x0070 /* 64-bits addr for Rx DMA */ 80 #define PCIEFD_REG_CAN_RX_DMA_ADDR_H 0x0074 81 82 /* CAN-FD channel misc register bits */ 83 #define CANFD_MISC_TS_RST 0x00000001 /* timestamp cnt rst */ 84 85 /* CAN-FD channel Clock SELector Source & DIVider */ 86 #define CANFD_CLK_SEL_DIV_MASK 0x00000007 87 #define CANFD_CLK_SEL_DIV_60MHZ 0x00000000 /* SRC=240MHz only */ 88 #define CANFD_CLK_SEL_DIV_40MHZ 0x00000001 /* SRC=240MHz only */ 89 #define CANFD_CLK_SEL_DIV_30MHZ 0x00000002 /* SRC=240MHz only */ 90 #define CANFD_CLK_SEL_DIV_24MHZ 0x00000003 /* SRC=240MHz only */ 91 #define CANFD_CLK_SEL_DIV_20MHZ 0x00000004 /* SRC=240MHz only */ 92 93 #define CANFD_CLK_SEL_SRC_MASK 0x00000008 /* 0=80MHz, 1=240MHz */ 94 #define CANFD_CLK_SEL_SRC_240MHZ 0x00000008 95 #define CANFD_CLK_SEL_SRC_80MHZ (~CANFD_CLK_SEL_SRC_240MHZ & \ 96 CANFD_CLK_SEL_SRC_MASK) 97 98 #define CANFD_CLK_SEL_20MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 99 CANFD_CLK_SEL_DIV_20MHZ) 100 #define CANFD_CLK_SEL_24MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 101 CANFD_CLK_SEL_DIV_24MHZ) 102 #define CANFD_CLK_SEL_30MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 103 CANFD_CLK_SEL_DIV_30MHZ) 104 #define CANFD_CLK_SEL_40MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 105 CANFD_CLK_SEL_DIV_40MHZ) 106 #define CANFD_CLK_SEL_60MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 107 CANFD_CLK_SEL_DIV_60MHZ) 108 #define CANFD_CLK_SEL_80MHZ (CANFD_CLK_SEL_SRC_80MHZ) 109 110 /* CAN-FD channel Rx/Tx control register bits */ 111 #define CANFD_CTL_UNC_BIT 0x00010000 /* Uncached DMA mem */ 112 #define CANFD_CTL_RST_BIT 0x00020000 /* reset DMA action */ 113 #define CANFD_CTL_IEN_BIT 0x00040000 /* IRQ enable */ 114 115 /* Rx IRQ Count and Time Limits */ 116 #define CANFD_CTL_IRQ_CL_DEF 16 /* Rx msg max nb per IRQ in Rx DMA */ 117 #define CANFD_CTL_IRQ_TL_DEF 10 /* Time before IRQ if < CL (x100 µs) */ 118 119 #define CANFD_OPTIONS_SET (CANFD_OPTION_ERROR | CANFD_OPTION_BUSLOAD) 120 121 /* Tx anticipation window (link logical address should be aligned on 2K 122 * boundary) 123 */ 124 #define PCIEFD_TX_PAGE_COUNT (PCIEFD_TX_DMA_SIZE / PCIEFD_TX_PAGE_SIZE) 125 126 #define CANFD_MSG_LNK_TX 0x1001 /* Tx msgs link */ 127 128 /* 32-bits IRQ status fields, heading Rx DMA area */ 129 static inline int pciefd_irq_tag(u32 irq_status) 130 { 131 return irq_status & 0x0000000f; 132 } 133 134 static inline int pciefd_irq_rx_cnt(u32 irq_status) 135 { 136 return (irq_status & 0x000007f0) >> 4; 137 } 138 139 static inline int pciefd_irq_is_lnk(u32 irq_status) 140 { 141 return irq_status & 0x00010000; 142 } 143 144 /* Rx record */ 145 struct pciefd_rx_dma { 146 __le32 irq_status; 147 __le32 sys_time_low; 148 __le32 sys_time_high; 149 struct pucan_rx_msg msg[0]; 150 } __packed __aligned(4); 151 152 /* Tx Link record */ 153 struct pciefd_tx_link { 154 __le16 size; 155 __le16 type; 156 __le32 laddr_lo; 157 __le32 laddr_hi; 158 } __packed __aligned(4); 159 160 /* Tx page descriptor */ 161 struct pciefd_page { 162 void *vbase; /* page virtual address */ 163 dma_addr_t lbase; /* page logical address */ 164 u32 offset; 165 u32 size; 166 }; 167 168 #define CANFD_IRQ_SET 0x00000001 169 #define CANFD_TX_PATH_SET 0x00000002 170 171 /* CAN-FD channel object */ 172 struct pciefd_board; 173 struct pciefd_can { 174 struct peak_canfd_priv ucan; /* must be the first member */ 175 void __iomem *reg_base; /* channel config base addr */ 176 struct pciefd_board *board; /* reverse link */ 177 178 struct pucan_command pucan_cmd; /* command buffer */ 179 180 dma_addr_t rx_dma_laddr; /* DMA virtual and logical addr */ 181 void *rx_dma_vaddr; /* for Rx and Tx areas */ 182 dma_addr_t tx_dma_laddr; 183 void *tx_dma_vaddr; 184 185 struct pciefd_page tx_pages[PCIEFD_TX_PAGE_COUNT]; 186 u16 tx_pages_free; /* free Tx pages counter */ 187 u16 tx_page_index; /* current page used for Tx */ 188 spinlock_t tx_lock; 189 190 u32 irq_status; 191 u32 irq_tag; /* next irq tag */ 192 }; 193 194 /* PEAK-PCIe FD board object */ 195 struct pciefd_board { 196 void __iomem *reg_base; 197 struct pci_dev *pci_dev; 198 int can_count; 199 spinlock_t cmd_lock; /* 64-bits cmds must be atomic */ 200 struct pciefd_can *can[0]; /* array of network devices */ 201 }; 202 203 /* supported device ids. */ 204 static const struct pci_device_id peak_pciefd_tbl[] = { 205 {PEAK_PCI_VENDOR_ID, PEAK_PCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,}, 206 {0,} 207 }; 208 209 MODULE_DEVICE_TABLE(pci, peak_pciefd_tbl); 210 211 /* read a 32 bits value from a SYS block register */ 212 static inline u32 pciefd_sys_readreg(const struct pciefd_board *priv, u16 reg) 213 { 214 return readl(priv->reg_base + reg); 215 } 216 217 /* write a 32 bits value into a SYS block register */ 218 static inline void pciefd_sys_writereg(const struct pciefd_board *priv, 219 u32 val, u16 reg) 220 { 221 writel(val, priv->reg_base + reg); 222 } 223 224 /* read a 32 bits value from CAN-FD block register */ 225 static inline u32 pciefd_can_readreg(const struct pciefd_can *priv, u16 reg) 226 { 227 return readl(priv->reg_base + reg); 228 } 229 230 /* write a 32 bits value into a CAN-FD block register */ 231 static inline void pciefd_can_writereg(const struct pciefd_can *priv, 232 u32 val, u16 reg) 233 { 234 writel(val, priv->reg_base + reg); 235 } 236 237 /* give a channel logical Rx DMA address to the board */ 238 static void pciefd_can_setup_rx_dma(struct pciefd_can *priv) 239 { 240 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 241 const u32 dma_addr_h = (u32)(priv->rx_dma_laddr >> 32); 242 #else 243 const u32 dma_addr_h = 0; 244 #endif 245 246 /* (DMA must be reset for Rx) */ 247 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET); 248 249 /* write the logical address of the Rx DMA area for this channel */ 250 pciefd_can_writereg(priv, (u32)priv->rx_dma_laddr, 251 PCIEFD_REG_CAN_RX_DMA_ADDR_L); 252 pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_RX_DMA_ADDR_H); 253 254 /* also indicates that Rx DMA is cacheable */ 255 pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_RX_CTL_CLR); 256 } 257 258 /* clear channel logical Rx DMA address from the board */ 259 static void pciefd_can_clear_rx_dma(struct pciefd_can *priv) 260 { 261 /* DMA must be reset for Rx */ 262 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET); 263 264 /* clear the logical address of the Rx DMA area for this channel */ 265 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_L); 266 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_H); 267 } 268 269 /* give a channel logical Tx DMA address to the board */ 270 static void pciefd_can_setup_tx_dma(struct pciefd_can *priv) 271 { 272 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 273 const u32 dma_addr_h = (u32)(priv->tx_dma_laddr >> 32); 274 #else 275 const u32 dma_addr_h = 0; 276 #endif 277 278 /* (DMA must be reset for Tx) */ 279 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET); 280 281 /* write the logical address of the Tx DMA area for this channel */ 282 pciefd_can_writereg(priv, (u32)priv->tx_dma_laddr, 283 PCIEFD_REG_CAN_TX_DMA_ADDR_L); 284 pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_TX_DMA_ADDR_H); 285 286 /* also indicates that Tx DMA is cacheable */ 287 pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_TX_CTL_CLR); 288 } 289 290 /* clear channel logical Tx DMA address from the board */ 291 static void pciefd_can_clear_tx_dma(struct pciefd_can *priv) 292 { 293 /* DMA must be reset for Tx */ 294 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET); 295 296 /* clear the logical address of the Tx DMA area for this channel */ 297 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_L); 298 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_H); 299 } 300 301 static void pciefd_can_ack_rx_dma(struct pciefd_can *priv) 302 { 303 /* read value of current IRQ tag and inc it for next one */ 304 priv->irq_tag = le32_to_cpu(*(__le32 *)priv->rx_dma_vaddr); 305 priv->irq_tag++; 306 priv->irq_tag &= 0xf; 307 308 /* write the next IRQ tag for this CAN */ 309 pciefd_can_writereg(priv, priv->irq_tag, PCIEFD_REG_CAN_RX_CTL_ACK); 310 } 311 312 /* IRQ handler */ 313 static irqreturn_t pciefd_irq_handler(int irq, void *arg) 314 { 315 struct pciefd_can *priv = arg; 316 struct pciefd_rx_dma *rx_dma = priv->rx_dma_vaddr; 317 318 /* INTA mode only to sync with PCIe transaction */ 319 if (!pci_dev_msi_enabled(priv->board->pci_dev)) 320 (void)pciefd_sys_readreg(priv->board, PCIEFD_REG_SYS_VER1); 321 322 /* read IRQ status from the first 32-bits of the Rx DMA area */ 323 priv->irq_status = le32_to_cpu(rx_dma->irq_status); 324 325 /* check if this (shared) IRQ is for this CAN */ 326 if (pciefd_irq_tag(priv->irq_status) != priv->irq_tag) 327 return IRQ_NONE; 328 329 /* handle rx messages (if any) */ 330 peak_canfd_handle_msgs_list(&priv->ucan, 331 rx_dma->msg, 332 pciefd_irq_rx_cnt(priv->irq_status)); 333 334 /* handle tx link interrupt (if any) */ 335 if (pciefd_irq_is_lnk(priv->irq_status)) { 336 unsigned long flags; 337 338 spin_lock_irqsave(&priv->tx_lock, flags); 339 priv->tx_pages_free++; 340 spin_unlock_irqrestore(&priv->tx_lock, flags); 341 342 /* wake producer up */ 343 netif_wake_queue(priv->ucan.ndev); 344 } 345 346 /* re-enable Rx DMA transfer for this CAN */ 347 pciefd_can_ack_rx_dma(priv); 348 349 return IRQ_HANDLED; 350 } 351 352 static int pciefd_enable_tx_path(struct peak_canfd_priv *ucan) 353 { 354 struct pciefd_can *priv = (struct pciefd_can *)ucan; 355 int i; 356 357 /* initialize the Tx pages descriptors */ 358 priv->tx_pages_free = PCIEFD_TX_PAGE_COUNT - 1; 359 priv->tx_page_index = 0; 360 361 priv->tx_pages[0].vbase = priv->tx_dma_vaddr; 362 priv->tx_pages[0].lbase = priv->tx_dma_laddr; 363 364 for (i = 0; i < PCIEFD_TX_PAGE_COUNT; i++) { 365 priv->tx_pages[i].offset = 0; 366 priv->tx_pages[i].size = PCIEFD_TX_PAGE_SIZE - 367 sizeof(struct pciefd_tx_link); 368 if (i) { 369 priv->tx_pages[i].vbase = 370 priv->tx_pages[i - 1].vbase + 371 PCIEFD_TX_PAGE_SIZE; 372 priv->tx_pages[i].lbase = 373 priv->tx_pages[i - 1].lbase + 374 PCIEFD_TX_PAGE_SIZE; 375 } 376 } 377 378 /* setup Tx DMA addresses into IP core */ 379 pciefd_can_setup_tx_dma(priv); 380 381 /* start (TX_RST=0) Tx Path */ 382 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_CLR); 383 384 return 0; 385 } 386 387 /* board specific CANFD command pre-processing */ 388 static int pciefd_pre_cmd(struct peak_canfd_priv *ucan) 389 { 390 struct pciefd_can *priv = (struct pciefd_can *)ucan; 391 u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd); 392 int err; 393 394 /* pre-process command */ 395 switch (cmd) { 396 case PUCAN_CMD_NORMAL_MODE: 397 case PUCAN_CMD_LISTEN_ONLY_MODE: 398 399 if (ucan->can.state == CAN_STATE_BUS_OFF) 400 break; 401 402 /* going into operational mode: setup IRQ handler */ 403 err = request_irq(priv->board->pci_dev->irq, 404 pciefd_irq_handler, 405 IRQF_SHARED, 406 PCIEFD_DRV_NAME, 407 priv); 408 if (err) 409 return err; 410 411 /* setup Rx DMA address */ 412 pciefd_can_setup_rx_dma(priv); 413 414 /* setup max count of msgs per IRQ */ 415 pciefd_can_writereg(priv, (CANFD_CTL_IRQ_TL_DEF) << 8 | 416 CANFD_CTL_IRQ_CL_DEF, 417 PCIEFD_REG_CAN_RX_CTL_WRT); 418 419 /* clear DMA RST for Rx (Rx start) */ 420 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, 421 PCIEFD_REG_CAN_RX_CTL_CLR); 422 423 /* reset timestamps */ 424 pciefd_can_writereg(priv, !CANFD_MISC_TS_RST, 425 PCIEFD_REG_CAN_MISC); 426 427 /* do an initial ACK */ 428 pciefd_can_ack_rx_dma(priv); 429 430 /* enable IRQ for this CAN after having set next irq_tag */ 431 pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT, 432 PCIEFD_REG_CAN_RX_CTL_SET); 433 434 /* Tx path will be setup as soon as RX_BARRIER is received */ 435 break; 436 default: 437 break; 438 } 439 440 return 0; 441 } 442 443 /* write a command */ 444 static int pciefd_write_cmd(struct peak_canfd_priv *ucan) 445 { 446 struct pciefd_can *priv = (struct pciefd_can *)ucan; 447 unsigned long flags; 448 449 /* 64-bits command is atomic */ 450 spin_lock_irqsave(&priv->board->cmd_lock, flags); 451 452 pciefd_can_writereg(priv, *(u32 *)ucan->cmd_buffer, 453 PCIEFD_REG_CAN_CMD_PORT_L); 454 pciefd_can_writereg(priv, *(u32 *)(ucan->cmd_buffer + 4), 455 PCIEFD_REG_CAN_CMD_PORT_H); 456 457 spin_unlock_irqrestore(&priv->board->cmd_lock, flags); 458 459 return 0; 460 } 461 462 /* board specific CANFD command post-processing */ 463 static int pciefd_post_cmd(struct peak_canfd_priv *ucan) 464 { 465 struct pciefd_can *priv = (struct pciefd_can *)ucan; 466 u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd); 467 468 switch (cmd) { 469 case PUCAN_CMD_RESET_MODE: 470 471 if (ucan->can.state == CAN_STATE_STOPPED) 472 break; 473 474 /* controller now in reset mode: */ 475 476 /* stop and reset DMA addresses in Tx/Rx engines */ 477 pciefd_can_clear_tx_dma(priv); 478 pciefd_can_clear_rx_dma(priv); 479 480 /* disable IRQ for this CAN */ 481 pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT, 482 PCIEFD_REG_CAN_RX_CTL_CLR); 483 484 free_irq(priv->board->pci_dev->irq, priv); 485 486 ucan->can.state = CAN_STATE_STOPPED; 487 488 break; 489 } 490 491 return 0; 492 } 493 494 static void *pciefd_alloc_tx_msg(struct peak_canfd_priv *ucan, u16 msg_size, 495 int *room_left) 496 { 497 struct pciefd_can *priv = (struct pciefd_can *)ucan; 498 struct pciefd_page *page = priv->tx_pages + priv->tx_page_index; 499 unsigned long flags; 500 void *msg; 501 502 spin_lock_irqsave(&priv->tx_lock, flags); 503 504 if (page->offset + msg_size > page->size) { 505 struct pciefd_tx_link *lk; 506 507 /* not enough space in this page: try another one */ 508 if (!priv->tx_pages_free) { 509 spin_unlock_irqrestore(&priv->tx_lock, flags); 510 511 /* Tx overflow */ 512 return NULL; 513 } 514 515 priv->tx_pages_free--; 516 517 /* keep address of the very last free slot of current page */ 518 lk = page->vbase + page->offset; 519 520 /* next, move on a new free page */ 521 priv->tx_page_index = (priv->tx_page_index + 1) % 522 PCIEFD_TX_PAGE_COUNT; 523 page = priv->tx_pages + priv->tx_page_index; 524 525 /* put link record to this new page at the end of prev one */ 526 lk->size = cpu_to_le16(sizeof(*lk)); 527 lk->type = cpu_to_le16(CANFD_MSG_LNK_TX); 528 lk->laddr_lo = cpu_to_le32(page->lbase); 529 530 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 531 lk->laddr_hi = cpu_to_le32(page->lbase >> 32); 532 #else 533 lk->laddr_hi = 0; 534 #endif 535 /* next msgs will be put from the begininng of this new page */ 536 page->offset = 0; 537 } 538 539 *room_left = priv->tx_pages_free * page->size; 540 541 spin_unlock_irqrestore(&priv->tx_lock, flags); 542 543 msg = page->vbase + page->offset; 544 545 /* give back room left in the tx ring */ 546 *room_left += page->size - (page->offset + msg_size); 547 548 return msg; 549 } 550 551 static int pciefd_write_tx_msg(struct peak_canfd_priv *ucan, 552 struct pucan_tx_msg *msg) 553 { 554 struct pciefd_can *priv = (struct pciefd_can *)ucan; 555 struct pciefd_page *page = priv->tx_pages + priv->tx_page_index; 556 557 /* this slot is now reserved for writing the frame */ 558 page->offset += le16_to_cpu(msg->size); 559 560 /* tell the board a frame has been written in Tx DMA area */ 561 pciefd_can_writereg(priv, 1, PCIEFD_REG_CAN_TX_REQ_ACC); 562 563 return 0; 564 } 565 566 /* probe for CAN-FD channel #pciefd_board->can_count */ 567 static int pciefd_can_probe(struct pciefd_board *pciefd) 568 { 569 struct net_device *ndev; 570 struct pciefd_can *priv; 571 u32 clk; 572 int err; 573 574 /* allocate the candev object with default isize of echo skbs ring */ 575 ndev = alloc_peak_canfd_dev(sizeof(*priv), pciefd->can_count, 576 PCIEFD_ECHO_SKB_MAX); 577 if (!ndev) { 578 dev_err(&pciefd->pci_dev->dev, 579 "failed to alloc candev object\n"); 580 goto failure; 581 } 582 583 priv = netdev_priv(ndev); 584 585 /* fill-in candev private object: */ 586 587 /* setup PCIe-FD own callbacks */ 588 priv->ucan.pre_cmd = pciefd_pre_cmd; 589 priv->ucan.write_cmd = pciefd_write_cmd; 590 priv->ucan.post_cmd = pciefd_post_cmd; 591 priv->ucan.enable_tx_path = pciefd_enable_tx_path; 592 priv->ucan.alloc_tx_msg = pciefd_alloc_tx_msg; 593 priv->ucan.write_tx_msg = pciefd_write_tx_msg; 594 595 /* setup PCIe-FD own command buffer */ 596 priv->ucan.cmd_buffer = &priv->pucan_cmd; 597 priv->ucan.cmd_maxlen = sizeof(priv->pucan_cmd); 598 599 priv->board = pciefd; 600 601 /* CAN config regs block address */ 602 priv->reg_base = pciefd->reg_base + PCIEFD_CANX_OFF(priv->ucan.index); 603 604 /* allocate non-cacheable DMA'able 4KB memory area for Rx */ 605 priv->rx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev, 606 PCIEFD_RX_DMA_SIZE, 607 &priv->rx_dma_laddr, 608 GFP_KERNEL); 609 if (!priv->rx_dma_vaddr) { 610 dev_err(&pciefd->pci_dev->dev, 611 "Rx dmam_alloc_coherent(%u) failure\n", 612 PCIEFD_RX_DMA_SIZE); 613 goto err_free_candev; 614 } 615 616 /* allocate non-cacheable DMA'able 4KB memory area for Tx */ 617 priv->tx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev, 618 PCIEFD_TX_DMA_SIZE, 619 &priv->tx_dma_laddr, 620 GFP_KERNEL); 621 if (!priv->tx_dma_vaddr) { 622 dev_err(&pciefd->pci_dev->dev, 623 "Tx dmaim_alloc_coherent(%u) failure\n", 624 PCIEFD_TX_DMA_SIZE); 625 goto err_free_candev; 626 } 627 628 /* CAN clock in RST mode */ 629 pciefd_can_writereg(priv, CANFD_MISC_TS_RST, PCIEFD_REG_CAN_MISC); 630 631 /* read current clock value */ 632 clk = pciefd_can_readreg(priv, PCIEFD_REG_CAN_CLK_SEL); 633 switch (clk) { 634 case CANFD_CLK_SEL_20MHZ: 635 priv->ucan.can.clock.freq = 20 * 1000 * 1000; 636 break; 637 case CANFD_CLK_SEL_24MHZ: 638 priv->ucan.can.clock.freq = 24 * 1000 * 1000; 639 break; 640 case CANFD_CLK_SEL_30MHZ: 641 priv->ucan.can.clock.freq = 30 * 1000 * 1000; 642 break; 643 case CANFD_CLK_SEL_40MHZ: 644 priv->ucan.can.clock.freq = 40 * 1000 * 1000; 645 break; 646 case CANFD_CLK_SEL_60MHZ: 647 priv->ucan.can.clock.freq = 60 * 1000 * 1000; 648 break; 649 default: 650 pciefd_can_writereg(priv, CANFD_CLK_SEL_80MHZ, 651 PCIEFD_REG_CAN_CLK_SEL); 652 653 /* fallthough */ 654 case CANFD_CLK_SEL_80MHZ: 655 priv->ucan.can.clock.freq = 80 * 1000 * 1000; 656 break; 657 } 658 659 ndev->irq = pciefd->pci_dev->irq; 660 661 SET_NETDEV_DEV(ndev, &pciefd->pci_dev->dev); 662 663 err = register_candev(ndev); 664 if (err) { 665 dev_err(&pciefd->pci_dev->dev, 666 "couldn't register CAN device: %d\n", err); 667 goto err_free_candev; 668 } 669 670 spin_lock_init(&priv->tx_lock); 671 672 /* save the object address in the board structure */ 673 pciefd->can[pciefd->can_count] = priv; 674 675 dev_info(&pciefd->pci_dev->dev, "%s at reg_base=0x%p irq=%d\n", 676 ndev->name, priv->reg_base, pciefd->pci_dev->irq); 677 678 return 0; 679 680 err_free_candev: 681 free_candev(ndev); 682 683 failure: 684 return -ENOMEM; 685 } 686 687 /* remove a CAN-FD channel by releasing all of its resources */ 688 static void pciefd_can_remove(struct pciefd_can *priv) 689 { 690 /* unregister (close) the can device to go back to RST mode first */ 691 unregister_candev(priv->ucan.ndev); 692 693 /* finally, free the candev object */ 694 free_candev(priv->ucan.ndev); 695 } 696 697 /* remove all CAN-FD channels by releasing their own resources */ 698 static void pciefd_can_remove_all(struct pciefd_board *pciefd) 699 { 700 while (pciefd->can_count > 0) 701 pciefd_can_remove(pciefd->can[--pciefd->can_count]); 702 } 703 704 /* probe for the entire device */ 705 static int peak_pciefd_probe(struct pci_dev *pdev, 706 const struct pci_device_id *ent) 707 { 708 struct pciefd_board *pciefd; 709 int err, can_count; 710 u16 sub_sys_id; 711 u8 hw_ver_major; 712 u8 hw_ver_minor; 713 u8 hw_ver_sub; 714 u32 v2; 715 716 err = pci_enable_device(pdev); 717 if (err) 718 return err; 719 err = pci_request_regions(pdev, PCIEFD_DRV_NAME); 720 if (err) 721 goto err_disable_pci; 722 723 /* the number of channels depends on sub-system id */ 724 err = pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sub_sys_id); 725 if (err) 726 goto err_release_regions; 727 728 dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n", 729 pdev->vendor, pdev->device, sub_sys_id); 730 731 if (sub_sys_id >= 0x0012) 732 can_count = 4; 733 else if (sub_sys_id >= 0x0010) 734 can_count = 3; 735 else if (sub_sys_id >= 0x0004) 736 can_count = 2; 737 else 738 can_count = 1; 739 740 /* allocate board structure object */ 741 pciefd = devm_kzalloc(&pdev->dev, sizeof(*pciefd) + 742 can_count * sizeof(*pciefd->can), 743 GFP_KERNEL); 744 if (!pciefd) { 745 err = -ENOMEM; 746 goto err_release_regions; 747 } 748 749 /* initialize the board structure */ 750 pciefd->pci_dev = pdev; 751 spin_lock_init(&pciefd->cmd_lock); 752 753 /* save the PCI BAR0 virtual address for further system regs access */ 754 pciefd->reg_base = pci_iomap(pdev, 0, PCIEFD_BAR0_SIZE); 755 if (!pciefd->reg_base) { 756 dev_err(&pdev->dev, "failed to map PCI resource #0\n"); 757 err = -ENOMEM; 758 goto err_release_regions; 759 } 760 761 /* read the firmware version number */ 762 v2 = pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER2); 763 764 hw_ver_major = (v2 & 0x0000f000) >> 12; 765 hw_ver_minor = (v2 & 0x00000f00) >> 8; 766 hw_ver_sub = (v2 & 0x000000f0) >> 4; 767 768 dev_info(&pdev->dev, 769 "%ux CAN-FD PCAN-PCIe FPGA v%u.%u.%u:\n", can_count, 770 hw_ver_major, hw_ver_minor, hw_ver_sub); 771 772 /* stop system clock */ 773 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN, 774 PCIEFD_REG_SYS_CTL_CLR); 775 776 pci_set_master(pdev); 777 778 /* create now the corresponding channels objects */ 779 while (pciefd->can_count < can_count) { 780 err = pciefd_can_probe(pciefd); 781 if (err) 782 goto err_free_canfd; 783 784 pciefd->can_count++; 785 } 786 787 /* set system timestamps counter in RST mode */ 788 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST, 789 PCIEFD_REG_SYS_CTL_SET); 790 791 /* wait a bit (read cycle) */ 792 (void)pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER1); 793 794 /* free all clocks */ 795 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST, 796 PCIEFD_REG_SYS_CTL_CLR); 797 798 /* start system clock */ 799 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN, 800 PCIEFD_REG_SYS_CTL_SET); 801 802 /* remember the board structure address in the device user data */ 803 pci_set_drvdata(pdev, pciefd); 804 805 return 0; 806 807 err_free_canfd: 808 pciefd_can_remove_all(pciefd); 809 810 pci_iounmap(pdev, pciefd->reg_base); 811 812 err_release_regions: 813 pci_release_regions(pdev); 814 815 err_disable_pci: 816 pci_disable_device(pdev); 817 818 return err; 819 } 820 821 /* free the board structure object, as well as its resources: */ 822 static void peak_pciefd_remove(struct pci_dev *pdev) 823 { 824 struct pciefd_board *pciefd = pci_get_drvdata(pdev); 825 826 /* release CAN-FD channels resources */ 827 pciefd_can_remove_all(pciefd); 828 829 pci_iounmap(pdev, pciefd->reg_base); 830 831 pci_release_regions(pdev); 832 pci_disable_device(pdev); 833 } 834 835 static struct pci_driver peak_pciefd_driver = { 836 .name = PCIEFD_DRV_NAME, 837 .id_table = peak_pciefd_tbl, 838 .probe = peak_pciefd_probe, 839 .remove = peak_pciefd_remove, 840 }; 841 842 module_pci_driver(peak_pciefd_driver); 843