1 /* 2 * Definitions of consts/structs to drive the Freescale MSCAN. 3 * 4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>, 5 * Varma Electronics Oy 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the version 2 of the GNU General Public License 9 * as published by the Free Software Foundation 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21 #ifndef __MSCAN_H__ 22 #define __MSCAN_H__ 23 24 #include <linux/clk.h> 25 #include <linux/types.h> 26 27 /* MSCAN control register 0 (CANCTL0) bits */ 28 #define MSCAN_RXFRM 0x80 29 #define MSCAN_RXACT 0x40 30 #define MSCAN_CSWAI 0x20 31 #define MSCAN_SYNCH 0x10 32 #define MSCAN_TIME 0x08 33 #define MSCAN_WUPE 0x04 34 #define MSCAN_SLPRQ 0x02 35 #define MSCAN_INITRQ 0x01 36 37 /* MSCAN control register 1 (CANCTL1) bits */ 38 #define MSCAN_CANE 0x80 39 #define MSCAN_CLKSRC 0x40 40 #define MSCAN_LOOPB 0x20 41 #define MSCAN_LISTEN 0x10 42 #define MSCAN_BORM 0x08 43 #define MSCAN_WUPM 0x04 44 #define MSCAN_SLPAK 0x02 45 #define MSCAN_INITAK 0x01 46 47 /* Use the MPC5XXX MSCAN variant? */ 48 #ifdef CONFIG_PPC 49 #define MSCAN_FOR_MPC5XXX 50 #endif 51 52 #ifdef MSCAN_FOR_MPC5XXX 53 #define MSCAN_CLKSRC_BUS 0 54 #define MSCAN_CLKSRC_XTAL MSCAN_CLKSRC 55 #define MSCAN_CLKSRC_IPS MSCAN_CLKSRC 56 #else 57 #define MSCAN_CLKSRC_BUS MSCAN_CLKSRC 58 #define MSCAN_CLKSRC_XTAL 0 59 #endif 60 61 /* MSCAN receiver flag register (CANRFLG) bits */ 62 #define MSCAN_WUPIF 0x80 63 #define MSCAN_CSCIF 0x40 64 #define MSCAN_RSTAT1 0x20 65 #define MSCAN_RSTAT0 0x10 66 #define MSCAN_TSTAT1 0x08 67 #define MSCAN_TSTAT0 0x04 68 #define MSCAN_OVRIF 0x02 69 #define MSCAN_RXF 0x01 70 #define MSCAN_ERR_IF (MSCAN_OVRIF | MSCAN_CSCIF) 71 #define MSCAN_RSTAT_MSK (MSCAN_RSTAT1 | MSCAN_RSTAT0) 72 #define MSCAN_TSTAT_MSK (MSCAN_TSTAT1 | MSCAN_TSTAT0) 73 #define MSCAN_STAT_MSK (MSCAN_RSTAT_MSK | MSCAN_TSTAT_MSK) 74 75 #define MSCAN_STATE_BUS_OFF (MSCAN_RSTAT1 | MSCAN_RSTAT0 | \ 76 MSCAN_TSTAT1 | MSCAN_TSTAT0) 77 #define MSCAN_STATE_TX(canrflg) (((canrflg)&MSCAN_TSTAT_MSK)>>2) 78 #define MSCAN_STATE_RX(canrflg) (((canrflg)&MSCAN_RSTAT_MSK)>>4) 79 #define MSCAN_STATE_ACTIVE 0 80 #define MSCAN_STATE_WARNING 1 81 #define MSCAN_STATE_PASSIVE 2 82 #define MSCAN_STATE_BUSOFF 3 83 84 /* MSCAN receiver interrupt enable register (CANRIER) bits */ 85 #define MSCAN_WUPIE 0x80 86 #define MSCAN_CSCIE 0x40 87 #define MSCAN_RSTATE1 0x20 88 #define MSCAN_RSTATE0 0x10 89 #define MSCAN_TSTATE1 0x08 90 #define MSCAN_TSTATE0 0x04 91 #define MSCAN_OVRIE 0x02 92 #define MSCAN_RXFIE 0x01 93 94 /* MSCAN transmitter flag register (CANTFLG) bits */ 95 #define MSCAN_TXE2 0x04 96 #define MSCAN_TXE1 0x02 97 #define MSCAN_TXE0 0x01 98 #define MSCAN_TXE (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0) 99 100 /* MSCAN transmitter interrupt enable register (CANTIER) bits */ 101 #define MSCAN_TXIE2 0x04 102 #define MSCAN_TXIE1 0x02 103 #define MSCAN_TXIE0 0x01 104 #define MSCAN_TXIE (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0) 105 106 /* MSCAN transmitter message abort request (CANTARQ) bits */ 107 #define MSCAN_ABTRQ2 0x04 108 #define MSCAN_ABTRQ1 0x02 109 #define MSCAN_ABTRQ0 0x01 110 111 /* MSCAN transmitter message abort ack (CANTAAK) bits */ 112 #define MSCAN_ABTAK2 0x04 113 #define MSCAN_ABTAK1 0x02 114 #define MSCAN_ABTAK0 0x01 115 116 /* MSCAN transmit buffer selection (CANTBSEL) bits */ 117 #define MSCAN_TX2 0x04 118 #define MSCAN_TX1 0x02 119 #define MSCAN_TX0 0x01 120 121 /* MSCAN ID acceptance control register (CANIDAC) bits */ 122 #define MSCAN_IDAM1 0x20 123 #define MSCAN_IDAM0 0x10 124 #define MSCAN_IDHIT2 0x04 125 #define MSCAN_IDHIT1 0x02 126 #define MSCAN_IDHIT0 0x01 127 128 #define MSCAN_AF_32BIT 0x00 129 #define MSCAN_AF_16BIT MSCAN_IDAM0 130 #define MSCAN_AF_8BIT MSCAN_IDAM1 131 #define MSCAN_AF_CLOSED (MSCAN_IDAM0|MSCAN_IDAM1) 132 #define MSCAN_AF_MASK (~(MSCAN_IDAM0|MSCAN_IDAM1)) 133 134 /* MSCAN Miscellaneous Register (CANMISC) bits */ 135 #define MSCAN_BOHOLD 0x01 136 137 /* MSCAN Identifier Register (IDR) bits */ 138 #define MSCAN_SFF_RTR_SHIFT 4 139 #define MSCAN_EFF_RTR_SHIFT 0 140 #define MSCAN_EFF_FLAGS 0x18 /* IDE + SRR */ 141 142 #ifdef MSCAN_FOR_MPC5XXX 143 #define _MSCAN_RESERVED_(n, num) u8 _res##n[num] 144 #define _MSCAN_RESERVED_DSR_SIZE 2 145 #else 146 #define _MSCAN_RESERVED_(n, num) 147 #define _MSCAN_RESERVED_DSR_SIZE 0 148 #endif 149 150 /* Structure of the hardware registers */ 151 struct mscan_regs { 152 /* (see doc S12MSCANV3/D) MPC5200 MSCAN */ 153 u8 canctl0; /* + 0x00 0x00 */ 154 u8 canctl1; /* + 0x01 0x01 */ 155 _MSCAN_RESERVED_(1, 2); /* + 0x02 */ 156 u8 canbtr0; /* + 0x04 0x02 */ 157 u8 canbtr1; /* + 0x05 0x03 */ 158 _MSCAN_RESERVED_(2, 2); /* + 0x06 */ 159 u8 canrflg; /* + 0x08 0x04 */ 160 u8 canrier; /* + 0x09 0x05 */ 161 _MSCAN_RESERVED_(3, 2); /* + 0x0a */ 162 u8 cantflg; /* + 0x0c 0x06 */ 163 u8 cantier; /* + 0x0d 0x07 */ 164 _MSCAN_RESERVED_(4, 2); /* + 0x0e */ 165 u8 cantarq; /* + 0x10 0x08 */ 166 u8 cantaak; /* + 0x11 0x09 */ 167 _MSCAN_RESERVED_(5, 2); /* + 0x12 */ 168 u8 cantbsel; /* + 0x14 0x0a */ 169 u8 canidac; /* + 0x15 0x0b */ 170 u8 reserved; /* + 0x16 0x0c */ 171 _MSCAN_RESERVED_(6, 2); /* + 0x17 */ 172 u8 canmisc; /* + 0x19 0x0d */ 173 _MSCAN_RESERVED_(7, 2); /* + 0x1a */ 174 u8 canrxerr; /* + 0x1c 0x0e */ 175 u8 cantxerr; /* + 0x1d 0x0f */ 176 _MSCAN_RESERVED_(8, 2); /* + 0x1e */ 177 u16 canidar1_0; /* + 0x20 0x10 */ 178 _MSCAN_RESERVED_(9, 2); /* + 0x22 */ 179 u16 canidar3_2; /* + 0x24 0x12 */ 180 _MSCAN_RESERVED_(10, 2); /* + 0x26 */ 181 u16 canidmr1_0; /* + 0x28 0x14 */ 182 _MSCAN_RESERVED_(11, 2); /* + 0x2a */ 183 u16 canidmr3_2; /* + 0x2c 0x16 */ 184 _MSCAN_RESERVED_(12, 2); /* + 0x2e */ 185 u16 canidar5_4; /* + 0x30 0x18 */ 186 _MSCAN_RESERVED_(13, 2); /* + 0x32 */ 187 u16 canidar7_6; /* + 0x34 0x1a */ 188 _MSCAN_RESERVED_(14, 2); /* + 0x36 */ 189 u16 canidmr5_4; /* + 0x38 0x1c */ 190 _MSCAN_RESERVED_(15, 2); /* + 0x3a */ 191 u16 canidmr7_6; /* + 0x3c 0x1e */ 192 _MSCAN_RESERVED_(16, 2); /* + 0x3e */ 193 struct { 194 u16 idr1_0; /* + 0x40 0x20 */ 195 _MSCAN_RESERVED_(17, 2); /* + 0x42 */ 196 u16 idr3_2; /* + 0x44 0x22 */ 197 _MSCAN_RESERVED_(18, 2); /* + 0x46 */ 198 u16 dsr1_0; /* + 0x48 0x24 */ 199 _MSCAN_RESERVED_(19, 2); /* + 0x4a */ 200 u16 dsr3_2; /* + 0x4c 0x26 */ 201 _MSCAN_RESERVED_(20, 2); /* + 0x4e */ 202 u16 dsr5_4; /* + 0x50 0x28 */ 203 _MSCAN_RESERVED_(21, 2); /* + 0x52 */ 204 u16 dsr7_6; /* + 0x54 0x2a */ 205 _MSCAN_RESERVED_(22, 2); /* + 0x56 */ 206 u8 dlr; /* + 0x58 0x2c */ 207 u8 reserved; /* + 0x59 0x2d */ 208 _MSCAN_RESERVED_(23, 2); /* + 0x5a */ 209 u16 time; /* + 0x5c 0x2e */ 210 } rx; 211 _MSCAN_RESERVED_(24, 2); /* + 0x5e */ 212 struct { 213 u16 idr1_0; /* + 0x60 0x30 */ 214 _MSCAN_RESERVED_(25, 2); /* + 0x62 */ 215 u16 idr3_2; /* + 0x64 0x32 */ 216 _MSCAN_RESERVED_(26, 2); /* + 0x66 */ 217 u16 dsr1_0; /* + 0x68 0x34 */ 218 _MSCAN_RESERVED_(27, 2); /* + 0x6a */ 219 u16 dsr3_2; /* + 0x6c 0x36 */ 220 _MSCAN_RESERVED_(28, 2); /* + 0x6e */ 221 u16 dsr5_4; /* + 0x70 0x38 */ 222 _MSCAN_RESERVED_(29, 2); /* + 0x72 */ 223 u16 dsr7_6; /* + 0x74 0x3a */ 224 _MSCAN_RESERVED_(30, 2); /* + 0x76 */ 225 u8 dlr; /* + 0x78 0x3c */ 226 u8 tbpr; /* + 0x79 0x3d */ 227 _MSCAN_RESERVED_(31, 2); /* + 0x7a */ 228 u16 time; /* + 0x7c 0x3e */ 229 } tx; 230 _MSCAN_RESERVED_(32, 2); /* + 0x7e */ 231 } __packed; 232 233 #undef _MSCAN_RESERVED_ 234 #define MSCAN_REGION sizeof(struct mscan) 235 236 #define MSCAN_NORMAL_MODE 0 237 #define MSCAN_SLEEP_MODE MSCAN_SLPRQ 238 #define MSCAN_INIT_MODE (MSCAN_INITRQ | MSCAN_SLPRQ) 239 #define MSCAN_POWEROFF_MODE (MSCAN_CSWAI | MSCAN_SLPRQ) 240 #define MSCAN_SET_MODE_RETRIES 255 241 #define MSCAN_ECHO_SKB_MAX 3 242 #define MSCAN_RX_INTS_ENABLE (MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | \ 243 MSCAN_RSTATE1 | MSCAN_RSTATE0 | \ 244 MSCAN_TSTATE1 | MSCAN_TSTATE0) 245 246 /* MSCAN type variants */ 247 enum { 248 MSCAN_TYPE_MPC5200, 249 MSCAN_TYPE_MPC5121 250 }; 251 252 #define BTR0_BRP_MASK 0x3f 253 #define BTR0_SJW_SHIFT 6 254 #define BTR0_SJW_MASK (0x3 << BTR0_SJW_SHIFT) 255 256 #define BTR1_TSEG1_MASK 0xf 257 #define BTR1_TSEG2_SHIFT 4 258 #define BTR1_TSEG2_MASK (0x7 << BTR1_TSEG2_SHIFT) 259 #define BTR1_SAM_SHIFT 7 260 261 #define BTR0_SET_BRP(brp) (((brp) - 1) & BTR0_BRP_MASK) 262 #define BTR0_SET_SJW(sjw) ((((sjw) - 1) << BTR0_SJW_SHIFT) & \ 263 BTR0_SJW_MASK) 264 265 #define BTR1_SET_TSEG1(tseg1) (((tseg1) - 1) & BTR1_TSEG1_MASK) 266 #define BTR1_SET_TSEG2(tseg2) ((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \ 267 BTR1_TSEG2_MASK) 268 #define BTR1_SET_SAM(sam) ((sam) ? 1 << BTR1_SAM_SHIFT : 0) 269 270 #define F_RX_PROGRESS 0 271 #define F_TX_PROGRESS 1 272 #define F_TX_WAIT_ALL 2 273 274 #define TX_QUEUE_SIZE 3 275 276 struct tx_queue_entry { 277 struct list_head list; 278 u8 mask; 279 u8 id; 280 }; 281 282 struct mscan_priv { 283 struct can_priv can; /* must be the first member */ 284 unsigned int type; /* MSCAN type variants */ 285 unsigned long flags; 286 void __iomem *reg_base; /* ioremap'ed address to registers */ 287 struct clk *clk_ipg; /* clock for registers */ 288 struct clk *clk_can; /* clock for bitrates */ 289 u8 shadow_statflg; 290 u8 shadow_canrier; 291 u8 cur_pri; 292 u8 prev_buf_id; 293 u8 tx_active; 294 295 struct list_head tx_head; 296 struct tx_queue_entry tx_queue[TX_QUEUE_SIZE]; 297 struct napi_struct napi; 298 }; 299 300 struct net_device *alloc_mscandev(void); 301 int register_mscandev(struct net_device *dev, int mscan_clksrc); 302 void unregister_mscandev(struct net_device *dev); 303 304 #endif /* __MSCAN_H__ */ 305