1 /* 2 * CAN bus driver for the Freescale MPC5xxx embedded CPU. 3 * 4 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>, 5 * Varma Electronics Oy 6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> 7 * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the version 2 of the GNU General Public License 11 * as published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/interrupt.h> 26 #include <linux/platform_device.h> 27 #include <linux/netdevice.h> 28 #include <linux/can/dev.h> 29 #include <linux/of_platform.h> 30 #include <sysdev/fsl_soc.h> 31 #include <linux/clk.h> 32 #include <linux/io.h> 33 #include <asm/mpc52xx.h> 34 35 #include "mscan.h" 36 37 #define DRV_NAME "mpc5xxx_can" 38 39 struct mpc5xxx_can_data { 40 unsigned int type; 41 u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name, 42 int *mscan_clksrc); 43 void (*put_clock)(struct platform_device *ofdev); 44 }; 45 46 #ifdef CONFIG_PPC_MPC52xx 47 static struct of_device_id mpc52xx_cdm_ids[] = { 48 { .compatible = "fsl,mpc5200-cdm", }, 49 {} 50 }; 51 52 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev, 53 const char *clock_name, int *mscan_clksrc) 54 { 55 unsigned int pvr; 56 struct mpc52xx_cdm __iomem *cdm; 57 struct device_node *np_cdm; 58 unsigned int freq; 59 u32 val; 60 61 pvr = mfspr(SPRN_PVR); 62 63 /* 64 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock 65 * (IP_CLK) can be selected as MSCAN clock source. According to 66 * the MPC5200 user's manual, the oscillator clock is the better 67 * choice as it has less jitter. For this reason, it is selected 68 * by default. Unfortunately, it can not be selected for the old 69 * MPC5200 Rev. A chips due to a hardware bug (check errata). 70 */ 71 if (clock_name && strcmp(clock_name, "ip") == 0) 72 *mscan_clksrc = MSCAN_CLKSRC_BUS; 73 else 74 *mscan_clksrc = MSCAN_CLKSRC_XTAL; 75 76 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); 77 if (!freq) 78 return 0; 79 80 if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011) 81 return freq; 82 83 /* Determine SYS_XTAL_IN frequency from the clock domain settings */ 84 np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids); 85 if (!np_cdm) { 86 dev_err(&ofdev->dev, "can't get clock node!\n"); 87 return 0; 88 } 89 cdm = of_iomap(np_cdm, 0); 90 91 if (in_8(&cdm->ipb_clk_sel) & 0x1) 92 freq *= 2; 93 val = in_be32(&cdm->rstcfg); 94 95 freq *= (val & (1 << 5)) ? 8 : 4; 96 freq /= (val & (1 << 6)) ? 12 : 16; 97 98 of_node_put(np_cdm); 99 iounmap(cdm); 100 101 return freq; 102 } 103 #else /* !CONFIG_PPC_MPC52xx */ 104 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev, 105 const char *clock_name, int *mscan_clksrc) 106 { 107 return 0; 108 } 109 #endif /* CONFIG_PPC_MPC52xx */ 110 111 #ifdef CONFIG_PPC_MPC512x 112 struct mpc512x_clockctl { 113 u32 spmr; /* System PLL Mode Reg */ 114 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */ 115 u32 scfr1; /* System Clk Freq Reg 1 */ 116 u32 scfr2; /* System Clk Freq Reg 2 */ 117 u32 reserved; 118 u32 bcr; /* Bread Crumb Reg */ 119 u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */ 120 u32 spccr; /* SPDIF Clk Ctrl Reg */ 121 u32 cccr; /* CFM Clk Ctrl Reg */ 122 u32 dccr; /* DIU Clk Cnfg Reg */ 123 u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */ 124 }; 125 126 static struct of_device_id mpc512x_clock_ids[] = { 127 { .compatible = "fsl,mpc5121-clock", }, 128 {} 129 }; 130 131 static u32 mpc512x_can_get_clock(struct platform_device *ofdev, 132 const char *clock_name, int *mscan_clksrc) 133 { 134 struct mpc512x_clockctl __iomem *clockctl; 135 struct device_node *np_clock; 136 struct clk *sys_clk, *ref_clk; 137 int plen, clockidx, clocksrc = -1; 138 u32 sys_freq, val, clockdiv = 1, freq = 0; 139 const u32 *pval; 140 141 np_clock = of_find_matching_node(NULL, mpc512x_clock_ids); 142 if (!np_clock) { 143 dev_err(&ofdev->dev, "couldn't find clock node\n"); 144 return 0; 145 } 146 clockctl = of_iomap(np_clock, 0); 147 if (!clockctl) { 148 dev_err(&ofdev->dev, "couldn't map clock registers\n"); 149 goto exit_put; 150 } 151 152 /* Determine the MSCAN device index from the peripheral's 153 * physical address. Register address offsets against the 154 * IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380 155 */ 156 pval = of_get_property(ofdev->dev.of_node, "reg", &plen); 157 BUG_ON(!pval || plen < sizeof(*pval)); 158 clockidx = (*pval & 0x80) ? 1 : 0; 159 if (*pval & 0x2000) 160 clockidx += 2; 161 162 /* 163 * Clock source and divider selection: 3 different clock sources 164 * can be selected: "ip", "ref" or "sys". For the latter two, a 165 * clock divider can be defined as well. If the clock source is 166 * not specified by the device tree, we first try to find an 167 * optimal CAN source clock based on the system clock. If that 168 * is not posslible, the reference clock will be used. 169 */ 170 if (clock_name && !strcmp(clock_name, "ip")) { 171 *mscan_clksrc = MSCAN_CLKSRC_IPS; 172 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); 173 } else { 174 *mscan_clksrc = MSCAN_CLKSRC_BUS; 175 176 pval = of_get_property(ofdev->dev.of_node, 177 "fsl,mscan-clock-divider", &plen); 178 if (pval && plen == sizeof(*pval)) 179 clockdiv = *pval; 180 if (!clockdiv) 181 clockdiv = 1; 182 183 if (!clock_name || !strcmp(clock_name, "sys")) { 184 sys_clk = devm_clk_get(&ofdev->dev, "sys_clk"); 185 if (IS_ERR(sys_clk)) { 186 dev_err(&ofdev->dev, "couldn't get sys_clk\n"); 187 goto exit_unmap; 188 } 189 /* Get and round up/down sys clock rate */ 190 sys_freq = 1000000 * 191 ((clk_get_rate(sys_clk) + 499999) / 1000000); 192 193 if (!clock_name) { 194 /* A multiple of 16 MHz would be optimal */ 195 if ((sys_freq % 16000000) == 0) { 196 clocksrc = 0; 197 clockdiv = sys_freq / 16000000; 198 freq = sys_freq / clockdiv; 199 } 200 } else { 201 clocksrc = 0; 202 freq = sys_freq / clockdiv; 203 } 204 } 205 206 if (clocksrc < 0) { 207 ref_clk = devm_clk_get(&ofdev->dev, "ref_clk"); 208 if (IS_ERR(ref_clk)) { 209 dev_err(&ofdev->dev, "couldn't get ref_clk\n"); 210 goto exit_unmap; 211 } 212 clocksrc = 1; 213 freq = clk_get_rate(ref_clk) / clockdiv; 214 } 215 } 216 217 /* Disable clock */ 218 out_be32(&clockctl->mccr[clockidx], 0x0); 219 if (clocksrc >= 0) { 220 /* Set source and divider */ 221 val = (clocksrc << 14) | ((clockdiv - 1) << 17); 222 out_be32(&clockctl->mccr[clockidx], val); 223 /* Enable clock */ 224 out_be32(&clockctl->mccr[clockidx], val | 0x10000); 225 } 226 227 /* Enable MSCAN clock domain */ 228 val = in_be32(&clockctl->sccr[1]); 229 if (!(val & (1 << 25))) 230 out_be32(&clockctl->sccr[1], val | (1 << 25)); 231 232 dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n", 233 *mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" : 234 clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv); 235 236 exit_unmap: 237 iounmap(clockctl); 238 exit_put: 239 of_node_put(np_clock); 240 return freq; 241 } 242 #else /* !CONFIG_PPC_MPC512x */ 243 static u32 mpc512x_can_get_clock(struct platform_device *ofdev, 244 const char *clock_name, int *mscan_clksrc) 245 { 246 return 0; 247 } 248 #endif /* CONFIG_PPC_MPC512x */ 249 250 static const struct of_device_id mpc5xxx_can_table[]; 251 static int mpc5xxx_can_probe(struct platform_device *ofdev) 252 { 253 const struct of_device_id *match; 254 const struct mpc5xxx_can_data *data; 255 struct device_node *np = ofdev->dev.of_node; 256 struct net_device *dev; 257 struct mscan_priv *priv; 258 void __iomem *base; 259 const char *clock_name = NULL; 260 int irq, mscan_clksrc = 0; 261 int err = -ENOMEM; 262 263 match = of_match_device(mpc5xxx_can_table, &ofdev->dev); 264 if (!match) 265 return -EINVAL; 266 data = match->data; 267 268 base = of_iomap(np, 0); 269 if (!base) { 270 dev_err(&ofdev->dev, "couldn't ioremap\n"); 271 return err; 272 } 273 274 irq = irq_of_parse_and_map(np, 0); 275 if (!irq) { 276 dev_err(&ofdev->dev, "no irq found\n"); 277 err = -ENODEV; 278 goto exit_unmap_mem; 279 } 280 281 dev = alloc_mscandev(); 282 if (!dev) 283 goto exit_dispose_irq; 284 platform_set_drvdata(ofdev, dev); 285 SET_NETDEV_DEV(dev, &ofdev->dev); 286 287 priv = netdev_priv(dev); 288 priv->reg_base = base; 289 dev->irq = irq; 290 291 clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL); 292 293 BUG_ON(!data); 294 priv->type = data->type; 295 priv->can.clock.freq = data->get_clock(ofdev, clock_name, 296 &mscan_clksrc); 297 if (!priv->can.clock.freq) { 298 dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n"); 299 goto exit_free_mscan; 300 } 301 302 err = register_mscandev(dev, mscan_clksrc); 303 if (err) { 304 dev_err(&ofdev->dev, "registering %s failed (err=%d)\n", 305 DRV_NAME, err); 306 goto exit_free_mscan; 307 } 308 309 dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n", 310 priv->reg_base, dev->irq, priv->can.clock.freq); 311 312 return 0; 313 314 exit_free_mscan: 315 free_candev(dev); 316 exit_dispose_irq: 317 irq_dispose_mapping(irq); 318 exit_unmap_mem: 319 iounmap(base); 320 321 return err; 322 } 323 324 static int mpc5xxx_can_remove(struct platform_device *ofdev) 325 { 326 const struct of_device_id *match; 327 const struct mpc5xxx_can_data *data; 328 struct net_device *dev = platform_get_drvdata(ofdev); 329 struct mscan_priv *priv = netdev_priv(dev); 330 331 match = of_match_device(mpc5xxx_can_table, &ofdev->dev); 332 data = match ? match->data : NULL; 333 334 unregister_mscandev(dev); 335 if (data && data->put_clock) 336 data->put_clock(ofdev); 337 iounmap(priv->reg_base); 338 irq_dispose_mapping(dev->irq); 339 free_candev(dev); 340 341 return 0; 342 } 343 344 #ifdef CONFIG_PM 345 static struct mscan_regs saved_regs; 346 static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state) 347 { 348 struct net_device *dev = platform_get_drvdata(ofdev); 349 struct mscan_priv *priv = netdev_priv(dev); 350 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 351 352 _memcpy_fromio(&saved_regs, regs, sizeof(*regs)); 353 354 return 0; 355 } 356 357 static int mpc5xxx_can_resume(struct platform_device *ofdev) 358 { 359 struct net_device *dev = platform_get_drvdata(ofdev); 360 struct mscan_priv *priv = netdev_priv(dev); 361 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; 362 363 regs->canctl0 |= MSCAN_INITRQ; 364 while (!(regs->canctl1 & MSCAN_INITAK)) 365 udelay(10); 366 367 regs->canctl1 = saved_regs.canctl1; 368 regs->canbtr0 = saved_regs.canbtr0; 369 regs->canbtr1 = saved_regs.canbtr1; 370 regs->canidac = saved_regs.canidac; 371 372 /* restore masks, buffers etc. */ 373 _memcpy_toio(®s->canidar1_0, (void *)&saved_regs.canidar1_0, 374 sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0)); 375 376 regs->canctl0 &= ~MSCAN_INITRQ; 377 regs->cantbsel = saved_regs.cantbsel; 378 regs->canrier = saved_regs.canrier; 379 regs->cantier = saved_regs.cantier; 380 regs->canctl0 = saved_regs.canctl0; 381 382 return 0; 383 } 384 #endif 385 386 static const struct mpc5xxx_can_data mpc5200_can_data = { 387 .type = MSCAN_TYPE_MPC5200, 388 .get_clock = mpc52xx_can_get_clock, 389 }; 390 391 static const struct mpc5xxx_can_data mpc5121_can_data = { 392 .type = MSCAN_TYPE_MPC5121, 393 .get_clock = mpc512x_can_get_clock, 394 }; 395 396 static const struct of_device_id mpc5xxx_can_table[] = { 397 { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, }, 398 /* Note that only MPC5121 Rev. 2 (and later) is supported */ 399 { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, }, 400 {}, 401 }; 402 MODULE_DEVICE_TABLE(of, mpc5xxx_can_table); 403 404 static struct platform_driver mpc5xxx_can_driver = { 405 .driver = { 406 .name = "mpc5xxx_can", 407 .owner = THIS_MODULE, 408 .of_match_table = mpc5xxx_can_table, 409 }, 410 .probe = mpc5xxx_can_probe, 411 .remove = mpc5xxx_can_remove, 412 #ifdef CONFIG_PM 413 .suspend = mpc5xxx_can_suspend, 414 .resume = mpc5xxx_can_resume, 415 #endif 416 }; 417 418 module_platform_driver(mpc5xxx_can_driver); 419 420 MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>"); 421 MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver"); 422 MODULE_LICENSE("GPL v2"); 423