1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * CAN bus driver for the Freescale MPC5xxx embedded CPU.
4  *
5  * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
6  *                         Varma Electronics Oy
7  * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
8  * Copyright (C) 2009 Wolfram Sang, Pengutronix <kernel@pengutronix.de>
9  */
10 
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <linux/netdevice.h>
16 #include <linux/can/dev.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <sysdev/fsl_soc.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <asm/mpc52xx.h>
24 
25 #include "mscan.h"
26 
27 #define DRV_NAME "mpc5xxx_can"
28 
29 struct mpc5xxx_can_data {
30 	unsigned int type;
31 	u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name,
32 			 int *mscan_clksrc);
33 	void (*put_clock)(struct platform_device *ofdev);
34 };
35 
36 #ifdef CONFIG_PPC_MPC52xx
37 static const struct of_device_id mpc52xx_cdm_ids[] = {
38 	{ .compatible = "fsl,mpc5200-cdm", },
39 	{}
40 };
41 
42 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
43 				 const char *clock_name, int *mscan_clksrc)
44 {
45 	unsigned int pvr;
46 	struct mpc52xx_cdm  __iomem *cdm;
47 	struct device_node *np_cdm;
48 	unsigned int freq;
49 	u32 val;
50 
51 	pvr = mfspr(SPRN_PVR);
52 
53 	/*
54 	 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
55 	 * (IP_CLK) can be selected as MSCAN clock source. According to
56 	 * the MPC5200 user's manual, the oscillator clock is the better
57 	 * choice as it has less jitter. For this reason, it is selected
58 	 * by default. Unfortunately, it can not be selected for the old
59 	 * MPC5200 Rev. A chips due to a hardware bug (check errata).
60 	 */
61 	if (clock_name && strcmp(clock_name, "ip") == 0)
62 		*mscan_clksrc = MSCAN_CLKSRC_BUS;
63 	else
64 		*mscan_clksrc = MSCAN_CLKSRC_XTAL;
65 
66 	freq = mpc5xxx_get_bus_frequency(&ofdev->dev);
67 	if (!freq)
68 		return 0;
69 
70 	if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
71 		return freq;
72 
73 	/* Determine SYS_XTAL_IN frequency from the clock domain settings */
74 	np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
75 	if (!np_cdm) {
76 		dev_err(&ofdev->dev, "can't get clock node!\n");
77 		return 0;
78 	}
79 	cdm = of_iomap(np_cdm, 0);
80 	if (!cdm) {
81 		of_node_put(np_cdm);
82 		dev_err(&ofdev->dev, "can't map clock node!\n");
83 		return 0;
84 	}
85 
86 	if (in_8(&cdm->ipb_clk_sel) & 0x1)
87 		freq *= 2;
88 	val = in_be32(&cdm->rstcfg);
89 
90 	freq *= (val & (1 << 5)) ? 8 : 4;
91 	freq /= (val & (1 << 6)) ? 12 : 16;
92 
93 	of_node_put(np_cdm);
94 	iounmap(cdm);
95 
96 	return freq;
97 }
98 #else /* !CONFIG_PPC_MPC52xx */
99 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
100 				 const char *clock_name, int *mscan_clksrc)
101 {
102 	return 0;
103 }
104 #endif /* CONFIG_PPC_MPC52xx */
105 
106 #ifdef CONFIG_PPC_MPC512x
107 static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
108 				 const char *clock_source, int *mscan_clksrc)
109 {
110 	struct device_node *np;
111 	u32 clockdiv;
112 	enum {
113 		CLK_FROM_AUTO,
114 		CLK_FROM_IPS,
115 		CLK_FROM_SYS,
116 		CLK_FROM_REF,
117 	} clk_from;
118 	struct clk *clk_in, *clk_can;
119 	unsigned long freq_calc;
120 	struct mscan_priv *priv;
121 	struct clk *clk_ipg;
122 
123 	/* the caller passed in the clock source spec that was read from
124 	 * the device tree, get the optional clock divider as well
125 	 */
126 	np = ofdev->dev.of_node;
127 	clockdiv = 1;
128 	of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
129 	dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
130 		clock_source ? clock_source : "<NULL>", clockdiv);
131 
132 	/* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
133 	 * get set, and the 'ips' clock is the input to the MSCAN
134 	 * component
135 	 *
136 	 * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
137 	 * bit needs to get cleared, an optional clock-divider may have
138 	 * been specified (the default value is 1), the appropriate
139 	 * MSCAN related MCLK is the input to the MSCAN component
140 	 *
141 	 * in the absence of a clock-source spec, first an optimal clock
142 	 * gets determined based on the 'sys' clock, if that fails the
143 	 * 'ref' clock is used
144 	 */
145 	clk_from = CLK_FROM_AUTO;
146 	if (clock_source) {
147 		/* interpret the device tree's spec for the clock source */
148 		if (!strcmp(clock_source, "ip"))
149 			clk_from = CLK_FROM_IPS;
150 		else if (!strcmp(clock_source, "sys"))
151 			clk_from = CLK_FROM_SYS;
152 		else if (!strcmp(clock_source, "ref"))
153 			clk_from = CLK_FROM_REF;
154 		else
155 			goto err_invalid;
156 		dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
157 	}
158 	if (clk_from == CLK_FROM_AUTO) {
159 		/* no spec so far, try the 'sys' clock; round to the
160 		 * next MHz and see if we can get a multiple of 16MHz
161 		 */
162 		dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
163 		clk_in = devm_clk_get(&ofdev->dev, "sys");
164 		if (IS_ERR(clk_in))
165 			goto err_notavail;
166 		freq_calc = clk_get_rate(clk_in);
167 		freq_calc +=  499999;
168 		freq_calc /= 1000000;
169 		freq_calc *= 1000000;
170 		if ((freq_calc % 16000000) == 0) {
171 			clk_from = CLK_FROM_SYS;
172 			clockdiv = freq_calc / 16000000;
173 			dev_dbg(&ofdev->dev,
174 				"clk fit, sys[%lu] div[%d] freq[%lu]\n",
175 				freq_calc, clockdiv, freq_calc / clockdiv);
176 		}
177 	}
178 	if (clk_from == CLK_FROM_AUTO) {
179 		/* no spec so far, use the 'ref' clock */
180 		dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
181 		clk_in = devm_clk_get(&ofdev->dev, "ref");
182 		if (IS_ERR(clk_in))
183 			goto err_notavail;
184 		clk_from = CLK_FROM_REF;
185 		freq_calc = clk_get_rate(clk_in);
186 		dev_dbg(&ofdev->dev,
187 			"clk fit, ref[%lu] (no div) freq[%lu]\n",
188 			freq_calc, freq_calc);
189 	}
190 
191 	/* select IPS or MCLK as the MSCAN input (returned to the caller),
192 	 * setup the MCLK mux source and rate if applicable, apply the
193 	 * optionally specified or derived above divider, and determine
194 	 * the actual resulting clock rate to return to the caller
195 	 */
196 	switch (clk_from) {
197 	case CLK_FROM_IPS:
198 		clk_can = devm_clk_get(&ofdev->dev, "ips");
199 		if (IS_ERR(clk_can))
200 			goto err_notavail;
201 		priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
202 		priv->clk_can = clk_can;
203 		freq_calc = clk_get_rate(clk_can);
204 		*mscan_clksrc = MSCAN_CLKSRC_IPS;
205 		dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
206 			*mscan_clksrc, freq_calc);
207 		break;
208 	case CLK_FROM_SYS:
209 	case CLK_FROM_REF:
210 		clk_can = devm_clk_get(&ofdev->dev, "mclk");
211 		if (IS_ERR(clk_can))
212 			goto err_notavail;
213 		priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
214 		priv->clk_can = clk_can;
215 		if (clk_from == CLK_FROM_SYS)
216 			clk_in = devm_clk_get(&ofdev->dev, "sys");
217 		if (clk_from == CLK_FROM_REF)
218 			clk_in = devm_clk_get(&ofdev->dev, "ref");
219 		if (IS_ERR(clk_in))
220 			goto err_notavail;
221 		clk_set_parent(clk_can, clk_in);
222 		freq_calc = clk_get_rate(clk_in);
223 		freq_calc /= clockdiv;
224 		clk_set_rate(clk_can, freq_calc);
225 		freq_calc = clk_get_rate(clk_can);
226 		*mscan_clksrc = MSCAN_CLKSRC_BUS;
227 		dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
228 			*mscan_clksrc, freq_calc);
229 		break;
230 	default:
231 		goto err_invalid;
232 	}
233 
234 	/* the above clk_can item is used for the bitrate, access to
235 	 * the peripheral's register set needs the clk_ipg item
236 	 */
237 	clk_ipg = devm_clk_get(&ofdev->dev, "ipg");
238 	if (IS_ERR(clk_ipg))
239 		goto err_notavail_ipg;
240 	if (clk_prepare_enable(clk_ipg))
241 		goto err_notavail_ipg;
242 	priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
243 	priv->clk_ipg = clk_ipg;
244 
245 	/* return the determined clock source rate */
246 	return freq_calc;
247 
248 err_invalid:
249 	dev_err(&ofdev->dev, "invalid clock source specification\n");
250 	/* clock source rate could not get determined */
251 	return 0;
252 
253 err_notavail:
254 	dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n");
255 	/* clock source rate could not get determined */
256 	return 0;
257 
258 err_notavail_ipg:
259 	dev_err(&ofdev->dev, "cannot acquire or setup register clock\n");
260 	/* clock source rate could not get determined */
261 	return 0;
262 }
263 
264 static void mpc512x_can_put_clock(struct platform_device *ofdev)
265 {
266 	struct mscan_priv *priv;
267 
268 	priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
269 	if (priv->clk_ipg)
270 		clk_disable_unprepare(priv->clk_ipg);
271 }
272 #else /* !CONFIG_PPC_MPC512x */
273 static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
274 				 const char *clock_name, int *mscan_clksrc)
275 {
276 	return 0;
277 }
278 #define mpc512x_can_put_clock NULL
279 #endif /* CONFIG_PPC_MPC512x */
280 
281 static const struct of_device_id mpc5xxx_can_table[];
282 static int mpc5xxx_can_probe(struct platform_device *ofdev)
283 {
284 	const struct mpc5xxx_can_data *data;
285 	struct device_node *np = ofdev->dev.of_node;
286 	struct net_device *dev;
287 	struct mscan_priv *priv;
288 	void __iomem *base;
289 	const char *clock_name = NULL;
290 	int irq, mscan_clksrc = 0;
291 	int err = -ENOMEM;
292 
293 	data = of_device_get_match_data(&ofdev->dev);
294 	if (!data)
295 		return -EINVAL;
296 
297 	base = of_iomap(np, 0);
298 	if (!base)
299 		return dev_err_probe(&ofdev->dev, err, "couldn't ioremap\n");
300 
301 	irq = irq_of_parse_and_map(np, 0);
302 	if (!irq) {
303 		dev_err(&ofdev->dev, "no irq found\n");
304 		err = -ENODEV;
305 		goto exit_unmap_mem;
306 	}
307 
308 	dev = alloc_mscandev();
309 	if (!dev)
310 		goto exit_dispose_irq;
311 	platform_set_drvdata(ofdev, dev);
312 	SET_NETDEV_DEV(dev, &ofdev->dev);
313 
314 	priv = netdev_priv(dev);
315 	priv->reg_base = base;
316 	dev->irq = irq;
317 
318 	clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
319 
320 	priv->type = data->type;
321 	priv->can.clock.freq = data->get_clock(ofdev, clock_name,
322 					       &mscan_clksrc);
323 	if (!priv->can.clock.freq) {
324 		dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
325 		goto exit_free_mscan;
326 	}
327 
328 	err = register_mscandev(dev, mscan_clksrc);
329 	if (err) {
330 		dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
331 			DRV_NAME, err);
332 		goto exit_free_mscan;
333 	}
334 
335 	dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
336 		 priv->reg_base, dev->irq, priv->can.clock.freq);
337 
338 	return 0;
339 
340 exit_free_mscan:
341 	free_candev(dev);
342 exit_dispose_irq:
343 	irq_dispose_mapping(irq);
344 exit_unmap_mem:
345 	iounmap(base);
346 
347 	return err;
348 }
349 
350 static int mpc5xxx_can_remove(struct platform_device *ofdev)
351 {
352 	const struct of_device_id *match;
353 	const struct mpc5xxx_can_data *data;
354 	struct net_device *dev = platform_get_drvdata(ofdev);
355 	struct mscan_priv *priv = netdev_priv(dev);
356 
357 	match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
358 	data = match ? match->data : NULL;
359 
360 	unregister_mscandev(dev);
361 	if (data && data->put_clock)
362 		data->put_clock(ofdev);
363 	iounmap(priv->reg_base);
364 	irq_dispose_mapping(dev->irq);
365 	free_candev(dev);
366 
367 	return 0;
368 }
369 
370 #ifdef CONFIG_PM
371 static struct mscan_regs saved_regs;
372 static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state)
373 {
374 	struct net_device *dev = platform_get_drvdata(ofdev);
375 	struct mscan_priv *priv = netdev_priv(dev);
376 	struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
377 
378 	_memcpy_fromio(&saved_regs, regs, sizeof(*regs));
379 
380 	return 0;
381 }
382 
383 static int mpc5xxx_can_resume(struct platform_device *ofdev)
384 {
385 	struct net_device *dev = platform_get_drvdata(ofdev);
386 	struct mscan_priv *priv = netdev_priv(dev);
387 	struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
388 
389 	regs->canctl0 |= MSCAN_INITRQ;
390 	while (!(regs->canctl1 & MSCAN_INITAK))
391 		udelay(10);
392 
393 	regs->canctl1 = saved_regs.canctl1;
394 	regs->canbtr0 = saved_regs.canbtr0;
395 	regs->canbtr1 = saved_regs.canbtr1;
396 	regs->canidac = saved_regs.canidac;
397 
398 	/* restore masks, buffers etc. */
399 	_memcpy_toio(&regs->canidar1_0, (void *)&saved_regs.canidar1_0,
400 		     sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
401 
402 	regs->canctl0 &= ~MSCAN_INITRQ;
403 	regs->cantbsel = saved_regs.cantbsel;
404 	regs->canrier = saved_regs.canrier;
405 	regs->cantier = saved_regs.cantier;
406 	regs->canctl0 = saved_regs.canctl0;
407 
408 	return 0;
409 }
410 #endif
411 
412 static const struct mpc5xxx_can_data mpc5200_can_data = {
413 	.type = MSCAN_TYPE_MPC5200,
414 	.get_clock = mpc52xx_can_get_clock,
415 	/* .put_clock not applicable */
416 };
417 
418 static const struct mpc5xxx_can_data mpc5121_can_data = {
419 	.type = MSCAN_TYPE_MPC5121,
420 	.get_clock = mpc512x_can_get_clock,
421 	.put_clock = mpc512x_can_put_clock,
422 };
423 
424 static const struct of_device_id mpc5xxx_can_table[] = {
425 	{ .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
426 	/* Note that only MPC5121 Rev. 2 (and later) is supported */
427 	{ .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
428 	{},
429 };
430 MODULE_DEVICE_TABLE(of, mpc5xxx_can_table);
431 
432 static struct platform_driver mpc5xxx_can_driver = {
433 	.driver = {
434 		.name = "mpc5xxx_can",
435 		.of_match_table = mpc5xxx_can_table,
436 	},
437 	.probe = mpc5xxx_can_probe,
438 	.remove = mpc5xxx_can_remove,
439 #ifdef CONFIG_PM
440 	.suspend = mpc5xxx_can_suspend,
441 	.resume = mpc5xxx_can_resume,
442 #endif
443 };
444 
445 module_platform_driver(mpc5xxx_can_driver);
446 
447 MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
448 MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
449 MODULE_LICENSE("GPL v2");
450