1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * CAN bus driver for the Freescale MPC5xxx embedded CPU.
4  *
5  * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
6  *                         Varma Electronics Oy
7  * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
8  * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de>
9  */
10 
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <linux/netdevice.h>
16 #include <linux/can/dev.h>
17 #include <linux/of_platform.h>
18 #include <sysdev/fsl_soc.h>
19 #include <linux/clk.h>
20 #include <linux/io.h>
21 #include <asm/mpc52xx.h>
22 
23 #include "mscan.h"
24 
25 #define DRV_NAME "mpc5xxx_can"
26 
27 struct mpc5xxx_can_data {
28 	unsigned int type;
29 	u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name,
30 			 int *mscan_clksrc);
31 	void (*put_clock)(struct platform_device *ofdev);
32 };
33 
34 #ifdef CONFIG_PPC_MPC52xx
35 static const struct of_device_id mpc52xx_cdm_ids[] = {
36 	{ .compatible = "fsl,mpc5200-cdm", },
37 	{}
38 };
39 
40 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
41 				 const char *clock_name, int *mscan_clksrc)
42 {
43 	unsigned int pvr;
44 	struct mpc52xx_cdm  __iomem *cdm;
45 	struct device_node *np_cdm;
46 	unsigned int freq;
47 	u32 val;
48 
49 	pvr = mfspr(SPRN_PVR);
50 
51 	/*
52 	 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
53 	 * (IP_CLK) can be selected as MSCAN clock source. According to
54 	 * the MPC5200 user's manual, the oscillator clock is the better
55 	 * choice as it has less jitter. For this reason, it is selected
56 	 * by default. Unfortunately, it can not be selected for the old
57 	 * MPC5200 Rev. A chips due to a hardware bug (check errata).
58 	 */
59 	if (clock_name && strcmp(clock_name, "ip") == 0)
60 		*mscan_clksrc = MSCAN_CLKSRC_BUS;
61 	else
62 		*mscan_clksrc = MSCAN_CLKSRC_XTAL;
63 
64 	freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
65 	if (!freq)
66 		return 0;
67 
68 	if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
69 		return freq;
70 
71 	/* Determine SYS_XTAL_IN frequency from the clock domain settings */
72 	np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
73 	if (!np_cdm) {
74 		dev_err(&ofdev->dev, "can't get clock node!\n");
75 		return 0;
76 	}
77 	cdm = of_iomap(np_cdm, 0);
78 	if (!cdm) {
79 		of_node_put(np_cdm);
80 		dev_err(&ofdev->dev, "can't map clock node!\n");
81 		return 0;
82 	}
83 
84 	if (in_8(&cdm->ipb_clk_sel) & 0x1)
85 		freq *= 2;
86 	val = in_be32(&cdm->rstcfg);
87 
88 	freq *= (val & (1 << 5)) ? 8 : 4;
89 	freq /= (val & (1 << 6)) ? 12 : 16;
90 
91 	of_node_put(np_cdm);
92 	iounmap(cdm);
93 
94 	return freq;
95 }
96 #else /* !CONFIG_PPC_MPC52xx */
97 static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
98 				 const char *clock_name, int *mscan_clksrc)
99 {
100 	return 0;
101 }
102 #endif /* CONFIG_PPC_MPC52xx */
103 
104 #ifdef CONFIG_PPC_MPC512x
105 static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
106 				 const char *clock_source, int *mscan_clksrc)
107 {
108 	struct device_node *np;
109 	u32 clockdiv;
110 	enum {
111 		CLK_FROM_AUTO,
112 		CLK_FROM_IPS,
113 		CLK_FROM_SYS,
114 		CLK_FROM_REF,
115 	} clk_from;
116 	struct clk *clk_in, *clk_can;
117 	unsigned long freq_calc;
118 	struct mscan_priv *priv;
119 	struct clk *clk_ipg;
120 
121 	/* the caller passed in the clock source spec that was read from
122 	 * the device tree, get the optional clock divider as well
123 	 */
124 	np = ofdev->dev.of_node;
125 	clockdiv = 1;
126 	of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
127 	dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
128 		clock_source ? clock_source : "<NULL>", clockdiv);
129 
130 	/* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
131 	 * get set, and the 'ips' clock is the input to the MSCAN
132 	 * component
133 	 *
134 	 * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
135 	 * bit needs to get cleared, an optional clock-divider may have
136 	 * been specified (the default value is 1), the appropriate
137 	 * MSCAN related MCLK is the input to the MSCAN component
138 	 *
139 	 * in the absence of a clock-source spec, first an optimal clock
140 	 * gets determined based on the 'sys' clock, if that fails the
141 	 * 'ref' clock is used
142 	 */
143 	clk_from = CLK_FROM_AUTO;
144 	if (clock_source) {
145 		/* interpret the device tree's spec for the clock source */
146 		if (!strcmp(clock_source, "ip"))
147 			clk_from = CLK_FROM_IPS;
148 		else if (!strcmp(clock_source, "sys"))
149 			clk_from = CLK_FROM_SYS;
150 		else if (!strcmp(clock_source, "ref"))
151 			clk_from = CLK_FROM_REF;
152 		else
153 			goto err_invalid;
154 		dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
155 	}
156 	if (clk_from == CLK_FROM_AUTO) {
157 		/* no spec so far, try the 'sys' clock; round to the
158 		 * next MHz and see if we can get a multiple of 16MHz
159 		 */
160 		dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
161 		clk_in = devm_clk_get(&ofdev->dev, "sys");
162 		if (IS_ERR(clk_in))
163 			goto err_notavail;
164 		freq_calc = clk_get_rate(clk_in);
165 		freq_calc +=  499999;
166 		freq_calc /= 1000000;
167 		freq_calc *= 1000000;
168 		if ((freq_calc % 16000000) == 0) {
169 			clk_from = CLK_FROM_SYS;
170 			clockdiv = freq_calc / 16000000;
171 			dev_dbg(&ofdev->dev,
172 				"clk fit, sys[%lu] div[%d] freq[%lu]\n",
173 				freq_calc, clockdiv, freq_calc / clockdiv);
174 		}
175 	}
176 	if (clk_from == CLK_FROM_AUTO) {
177 		/* no spec so far, use the 'ref' clock */
178 		dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
179 		clk_in = devm_clk_get(&ofdev->dev, "ref");
180 		if (IS_ERR(clk_in))
181 			goto err_notavail;
182 		clk_from = CLK_FROM_REF;
183 		freq_calc = clk_get_rate(clk_in);
184 		dev_dbg(&ofdev->dev,
185 			"clk fit, ref[%lu] (no div) freq[%lu]\n",
186 			freq_calc, freq_calc);
187 	}
188 
189 	/* select IPS or MCLK as the MSCAN input (returned to the caller),
190 	 * setup the MCLK mux source and rate if applicable, apply the
191 	 * optionally specified or derived above divider, and determine
192 	 * the actual resulting clock rate to return to the caller
193 	 */
194 	switch (clk_from) {
195 	case CLK_FROM_IPS:
196 		clk_can = devm_clk_get(&ofdev->dev, "ips");
197 		if (IS_ERR(clk_can))
198 			goto err_notavail;
199 		priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
200 		priv->clk_can = clk_can;
201 		freq_calc = clk_get_rate(clk_can);
202 		*mscan_clksrc = MSCAN_CLKSRC_IPS;
203 		dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
204 			*mscan_clksrc, freq_calc);
205 		break;
206 	case CLK_FROM_SYS:
207 	case CLK_FROM_REF:
208 		clk_can = devm_clk_get(&ofdev->dev, "mclk");
209 		if (IS_ERR(clk_can))
210 			goto err_notavail;
211 		priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
212 		priv->clk_can = clk_can;
213 		if (clk_from == CLK_FROM_SYS)
214 			clk_in = devm_clk_get(&ofdev->dev, "sys");
215 		if (clk_from == CLK_FROM_REF)
216 			clk_in = devm_clk_get(&ofdev->dev, "ref");
217 		if (IS_ERR(clk_in))
218 			goto err_notavail;
219 		clk_set_parent(clk_can, clk_in);
220 		freq_calc = clk_get_rate(clk_in);
221 		freq_calc /= clockdiv;
222 		clk_set_rate(clk_can, freq_calc);
223 		freq_calc = clk_get_rate(clk_can);
224 		*mscan_clksrc = MSCAN_CLKSRC_BUS;
225 		dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
226 			*mscan_clksrc, freq_calc);
227 		break;
228 	default:
229 		goto err_invalid;
230 	}
231 
232 	/* the above clk_can item is used for the bitrate, access to
233 	 * the peripheral's register set needs the clk_ipg item
234 	 */
235 	clk_ipg = devm_clk_get(&ofdev->dev, "ipg");
236 	if (IS_ERR(clk_ipg))
237 		goto err_notavail_ipg;
238 	if (clk_prepare_enable(clk_ipg))
239 		goto err_notavail_ipg;
240 	priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
241 	priv->clk_ipg = clk_ipg;
242 
243 	/* return the determined clock source rate */
244 	return freq_calc;
245 
246 err_invalid:
247 	dev_err(&ofdev->dev, "invalid clock source specification\n");
248 	/* clock source rate could not get determined */
249 	return 0;
250 
251 err_notavail:
252 	dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n");
253 	/* clock source rate could not get determined */
254 	return 0;
255 
256 err_notavail_ipg:
257 	dev_err(&ofdev->dev, "cannot acquire or setup register clock\n");
258 	/* clock source rate could not get determined */
259 	return 0;
260 }
261 
262 static void mpc512x_can_put_clock(struct platform_device *ofdev)
263 {
264 	struct mscan_priv *priv;
265 
266 	priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
267 	if (priv->clk_ipg)
268 		clk_disable_unprepare(priv->clk_ipg);
269 }
270 #else /* !CONFIG_PPC_MPC512x */
271 static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
272 				 const char *clock_name, int *mscan_clksrc)
273 {
274 	return 0;
275 }
276 #define mpc512x_can_put_clock NULL
277 #endif /* CONFIG_PPC_MPC512x */
278 
279 static const struct of_device_id mpc5xxx_can_table[];
280 static int mpc5xxx_can_probe(struct platform_device *ofdev)
281 {
282 	const struct of_device_id *match;
283 	const struct mpc5xxx_can_data *data;
284 	struct device_node *np = ofdev->dev.of_node;
285 	struct net_device *dev;
286 	struct mscan_priv *priv;
287 	void __iomem *base;
288 	const char *clock_name = NULL;
289 	int irq, mscan_clksrc = 0;
290 	int err = -ENOMEM;
291 
292 	match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
293 	if (!match)
294 		return -EINVAL;
295 	data = match->data;
296 
297 	base = of_iomap(np, 0);
298 	if (!base) {
299 		dev_err(&ofdev->dev, "couldn't ioremap\n");
300 		return err;
301 	}
302 
303 	irq = irq_of_parse_and_map(np, 0);
304 	if (!irq) {
305 		dev_err(&ofdev->dev, "no irq found\n");
306 		err = -ENODEV;
307 		goto exit_unmap_mem;
308 	}
309 
310 	dev = alloc_mscandev();
311 	if (!dev)
312 		goto exit_dispose_irq;
313 	platform_set_drvdata(ofdev, dev);
314 	SET_NETDEV_DEV(dev, &ofdev->dev);
315 
316 	priv = netdev_priv(dev);
317 	priv->reg_base = base;
318 	dev->irq = irq;
319 
320 	clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
321 
322 	BUG_ON(!data);
323 	priv->type = data->type;
324 	priv->can.clock.freq = data->get_clock(ofdev, clock_name,
325 					       &mscan_clksrc);
326 	if (!priv->can.clock.freq) {
327 		dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
328 		goto exit_free_mscan;
329 	}
330 
331 	err = register_mscandev(dev, mscan_clksrc);
332 	if (err) {
333 		dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
334 			DRV_NAME, err);
335 		goto exit_free_mscan;
336 	}
337 
338 	dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
339 		 priv->reg_base, dev->irq, priv->can.clock.freq);
340 
341 	return 0;
342 
343 exit_free_mscan:
344 	free_candev(dev);
345 exit_dispose_irq:
346 	irq_dispose_mapping(irq);
347 exit_unmap_mem:
348 	iounmap(base);
349 
350 	return err;
351 }
352 
353 static int mpc5xxx_can_remove(struct platform_device *ofdev)
354 {
355 	const struct of_device_id *match;
356 	const struct mpc5xxx_can_data *data;
357 	struct net_device *dev = platform_get_drvdata(ofdev);
358 	struct mscan_priv *priv = netdev_priv(dev);
359 
360 	match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
361 	data = match ? match->data : NULL;
362 
363 	unregister_mscandev(dev);
364 	if (data && data->put_clock)
365 		data->put_clock(ofdev);
366 	iounmap(priv->reg_base);
367 	irq_dispose_mapping(dev->irq);
368 	free_candev(dev);
369 
370 	return 0;
371 }
372 
373 #ifdef CONFIG_PM
374 static struct mscan_regs saved_regs;
375 static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state)
376 {
377 	struct net_device *dev = platform_get_drvdata(ofdev);
378 	struct mscan_priv *priv = netdev_priv(dev);
379 	struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
380 
381 	_memcpy_fromio(&saved_regs, regs, sizeof(*regs));
382 
383 	return 0;
384 }
385 
386 static int mpc5xxx_can_resume(struct platform_device *ofdev)
387 {
388 	struct net_device *dev = platform_get_drvdata(ofdev);
389 	struct mscan_priv *priv = netdev_priv(dev);
390 	struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
391 
392 	regs->canctl0 |= MSCAN_INITRQ;
393 	while (!(regs->canctl1 & MSCAN_INITAK))
394 		udelay(10);
395 
396 	regs->canctl1 = saved_regs.canctl1;
397 	regs->canbtr0 = saved_regs.canbtr0;
398 	regs->canbtr1 = saved_regs.canbtr1;
399 	regs->canidac = saved_regs.canidac;
400 
401 	/* restore masks, buffers etc. */
402 	_memcpy_toio(&regs->canidar1_0, (void *)&saved_regs.canidar1_0,
403 		     sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
404 
405 	regs->canctl0 &= ~MSCAN_INITRQ;
406 	regs->cantbsel = saved_regs.cantbsel;
407 	regs->canrier = saved_regs.canrier;
408 	regs->cantier = saved_regs.cantier;
409 	regs->canctl0 = saved_regs.canctl0;
410 
411 	return 0;
412 }
413 #endif
414 
415 static const struct mpc5xxx_can_data mpc5200_can_data = {
416 	.type = MSCAN_TYPE_MPC5200,
417 	.get_clock = mpc52xx_can_get_clock,
418 	/* .put_clock not applicable */
419 };
420 
421 static const struct mpc5xxx_can_data mpc5121_can_data = {
422 	.type = MSCAN_TYPE_MPC5121,
423 	.get_clock = mpc512x_can_get_clock,
424 	.put_clock = mpc512x_can_put_clock,
425 };
426 
427 static const struct of_device_id mpc5xxx_can_table[] = {
428 	{ .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
429 	/* Note that only MPC5121 Rev. 2 (and later) is supported */
430 	{ .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
431 	{},
432 };
433 MODULE_DEVICE_TABLE(of, mpc5xxx_can_table);
434 
435 static struct platform_driver mpc5xxx_can_driver = {
436 	.driver = {
437 		.name = "mpc5xxx_can",
438 		.of_match_table = mpc5xxx_can_table,
439 	},
440 	.probe = mpc5xxx_can_probe,
441 	.remove = mpc5xxx_can_remove,
442 #ifdef CONFIG_PM
443 	.suspend = mpc5xxx_can_suspend,
444 	.resume = mpc5xxx_can_resume,
445 #endif
446 };
447 
448 module_platform_driver(mpc5xxx_can_driver);
449 
450 MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
451 MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
452 MODULE_LICENSE("GPL v2");
453