1 // SPDX-License-Identifier: GPL-2.0 2 // SPI to CAN driver for the Texas Instruments TCAN4x5x 3 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/ 4 5 #include "tcan4x5x.h" 6 7 #define TCAN4X5X_EXT_CLK_DEF 40000000 8 9 #define TCAN4X5X_DEV_ID0 0x00 10 #define TCAN4X5X_DEV_ID1 0x04 11 #define TCAN4X5X_REV 0x08 12 #define TCAN4X5X_STATUS 0x0C 13 #define TCAN4X5X_ERROR_STATUS 0x10 14 #define TCAN4X5X_CONTROL 0x14 15 16 #define TCAN4X5X_CONFIG 0x800 17 #define TCAN4X5X_TS_PRESCALE 0x804 18 #define TCAN4X5X_TEST_REG 0x808 19 #define TCAN4X5X_INT_FLAGS 0x820 20 #define TCAN4X5X_MCAN_INT_REG 0x824 21 #define TCAN4X5X_INT_EN 0x830 22 23 /* Interrupt bits */ 24 #define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30) 25 #define TCAN4X5X_CANHCANL_INT_EN BIT(29) 26 #define TCAN4X5X_CANHBAT_INT_EN BIT(28) 27 #define TCAN4X5X_CANLGND_INT_EN BIT(27) 28 #define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26) 29 #define TCAN4X5X_CANBUSGND_INT_EN BIT(25) 30 #define TCAN4X5X_CANBUSBAT_INT_EN BIT(24) 31 #define TCAN4X5X_UVSUP_INT_EN BIT(22) 32 #define TCAN4X5X_UVIO_INT_EN BIT(21) 33 #define TCAN4X5X_TSD_INT_EN BIT(19) 34 #define TCAN4X5X_ECCERR_INT_EN BIT(16) 35 #define TCAN4X5X_CANINT_INT_EN BIT(15) 36 #define TCAN4X5X_LWU_INT_EN BIT(14) 37 #define TCAN4X5X_CANSLNT_INT_EN BIT(10) 38 #define TCAN4X5X_CANDOM_INT_EN BIT(8) 39 #define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5) 40 #define TCAN4X5X_BUS_FAULT BIT(4) 41 #define TCAN4X5X_MCAN_INT BIT(1) 42 #define TCAN4X5X_ENABLE_TCAN_INT \ 43 (TCAN4X5X_MCAN_INT | TCAN4X5X_BUS_FAULT | \ 44 TCAN4X5X_CANBUS_ERR_INT_EN | TCAN4X5X_CANINT_INT_EN) 45 46 /* MCAN Interrupt bits */ 47 #define TCAN4X5X_MCAN_IR_ARA BIT(29) 48 #define TCAN4X5X_MCAN_IR_PED BIT(28) 49 #define TCAN4X5X_MCAN_IR_PEA BIT(27) 50 #define TCAN4X5X_MCAN_IR_WD BIT(26) 51 #define TCAN4X5X_MCAN_IR_BO BIT(25) 52 #define TCAN4X5X_MCAN_IR_EW BIT(24) 53 #define TCAN4X5X_MCAN_IR_EP BIT(23) 54 #define TCAN4X5X_MCAN_IR_ELO BIT(22) 55 #define TCAN4X5X_MCAN_IR_BEU BIT(21) 56 #define TCAN4X5X_MCAN_IR_BEC BIT(20) 57 #define TCAN4X5X_MCAN_IR_DRX BIT(19) 58 #define TCAN4X5X_MCAN_IR_TOO BIT(18) 59 #define TCAN4X5X_MCAN_IR_MRAF BIT(17) 60 #define TCAN4X5X_MCAN_IR_TSW BIT(16) 61 #define TCAN4X5X_MCAN_IR_TEFL BIT(15) 62 #define TCAN4X5X_MCAN_IR_TEFF BIT(14) 63 #define TCAN4X5X_MCAN_IR_TEFW BIT(13) 64 #define TCAN4X5X_MCAN_IR_TEFN BIT(12) 65 #define TCAN4X5X_MCAN_IR_TFE BIT(11) 66 #define TCAN4X5X_MCAN_IR_TCF BIT(10) 67 #define TCAN4X5X_MCAN_IR_TC BIT(9) 68 #define TCAN4X5X_MCAN_IR_HPM BIT(8) 69 #define TCAN4X5X_MCAN_IR_RF1L BIT(7) 70 #define TCAN4X5X_MCAN_IR_RF1F BIT(6) 71 #define TCAN4X5X_MCAN_IR_RF1W BIT(5) 72 #define TCAN4X5X_MCAN_IR_RF1N BIT(4) 73 #define TCAN4X5X_MCAN_IR_RF0L BIT(3) 74 #define TCAN4X5X_MCAN_IR_RF0F BIT(2) 75 #define TCAN4X5X_MCAN_IR_RF0W BIT(1) 76 #define TCAN4X5X_MCAN_IR_RF0N BIT(0) 77 #define TCAN4X5X_ENABLE_MCAN_INT \ 78 (TCAN4X5X_MCAN_IR_TC | TCAN4X5X_MCAN_IR_RF0N | \ 79 TCAN4X5X_MCAN_IR_RF1N | TCAN4X5X_MCAN_IR_RF0F | \ 80 TCAN4X5X_MCAN_IR_RF1F) 81 82 #define TCAN4X5X_MRAM_START 0x8000 83 #define TCAN4X5X_MCAN_OFFSET 0x1000 84 85 #define TCAN4X5X_CLEAR_ALL_INT 0xffffffff 86 #define TCAN4X5X_SET_ALL_INT 0xffffffff 87 88 #define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6)) 89 #define TCAN4X5X_MODE_SLEEP 0x00 90 #define TCAN4X5X_MODE_STANDBY BIT(6) 91 #define TCAN4X5X_MODE_NORMAL BIT(7) 92 93 #define TCAN4X5X_DISABLE_WAKE_MSK (BIT(31) | BIT(30)) 94 #define TCAN4X5X_DISABLE_INH_MSK BIT(9) 95 96 #define TCAN4X5X_SW_RESET BIT(2) 97 98 #define TCAN4X5X_MCAN_CONFIGURED BIT(5) 99 #define TCAN4X5X_WATCHDOG_EN BIT(3) 100 #define TCAN4X5X_WD_60_MS_TIMER 0 101 #define TCAN4X5X_WD_600_MS_TIMER BIT(28) 102 #define TCAN4X5X_WD_3_S_TIMER BIT(29) 103 #define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29)) 104 105 static inline struct tcan4x5x_priv *cdev_to_priv(struct m_can_classdev *cdev) 106 { 107 return container_of(cdev, struct tcan4x5x_priv, cdev); 108 109 } 110 111 static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv) 112 { 113 int wake_state = 0; 114 115 if (priv->device_state_gpio) 116 wake_state = gpiod_get_value(priv->device_state_gpio); 117 118 if (priv->device_wake_gpio && wake_state) { 119 gpiod_set_value(priv->device_wake_gpio, 0); 120 usleep_range(5, 50); 121 gpiod_set_value(priv->device_wake_gpio, 1); 122 } 123 } 124 125 static int tcan4x5x_reset(struct tcan4x5x_priv *priv) 126 { 127 int ret = 0; 128 129 if (priv->reset_gpio) { 130 gpiod_set_value(priv->reset_gpio, 1); 131 132 /* tpulse_width minimum 30us */ 133 usleep_range(30, 100); 134 gpiod_set_value(priv->reset_gpio, 0); 135 } else { 136 ret = regmap_write(priv->regmap, TCAN4X5X_CONFIG, 137 TCAN4X5X_SW_RESET); 138 if (ret) 139 return ret; 140 } 141 142 usleep_range(700, 1000); 143 144 return ret; 145 } 146 147 static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg) 148 { 149 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 150 u32 val; 151 152 regmap_read(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, &val); 153 154 return val; 155 } 156 157 static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset) 158 { 159 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 160 u32 val; 161 162 regmap_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, &val); 163 164 return val; 165 } 166 167 static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val) 168 { 169 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 170 171 return regmap_write(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, val); 172 } 173 174 static int tcan4x5x_write_fifo(struct m_can_classdev *cdev, 175 int addr_offset, int val) 176 { 177 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 178 179 return regmap_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val); 180 } 181 182 static int tcan4x5x_power_enable(struct regulator *reg, int enable) 183 { 184 if (IS_ERR_OR_NULL(reg)) 185 return 0; 186 187 if (enable) 188 return regulator_enable(reg); 189 else 190 return regulator_disable(reg); 191 } 192 193 static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev, 194 int reg, int val) 195 { 196 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 197 198 return regmap_write(priv->regmap, reg, val); 199 } 200 201 static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev) 202 { 203 int ret; 204 205 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_STATUS, 206 TCAN4X5X_CLEAR_ALL_INT); 207 if (ret) 208 return ret; 209 210 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_MCAN_INT_REG, 211 TCAN4X5X_ENABLE_MCAN_INT); 212 if (ret) 213 return ret; 214 215 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_FLAGS, 216 TCAN4X5X_CLEAR_ALL_INT); 217 if (ret) 218 return ret; 219 220 return tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_ERROR_STATUS, 221 TCAN4X5X_CLEAR_ALL_INT); 222 } 223 224 static int tcan4x5x_init(struct m_can_classdev *cdev) 225 { 226 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 227 int ret; 228 229 tcan4x5x_check_wake(tcan4x5x); 230 231 ret = tcan4x5x_clear_interrupts(cdev); 232 if (ret) 233 return ret; 234 235 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_EN, 236 TCAN4X5X_ENABLE_TCAN_INT); 237 if (ret) 238 return ret; 239 240 /* Zero out the MCAN buffers */ 241 m_can_init_ram(cdev); 242 243 ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 244 TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL); 245 if (ret) 246 return ret; 247 248 return ret; 249 } 250 251 static int tcan4x5x_disable_wake(struct m_can_classdev *cdev) 252 { 253 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 254 255 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 256 TCAN4X5X_DISABLE_WAKE_MSK, 0x00); 257 } 258 259 static int tcan4x5x_disable_state(struct m_can_classdev *cdev) 260 { 261 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 262 263 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 264 TCAN4X5X_DISABLE_INH_MSK, 0x01); 265 } 266 267 static int tcan4x5x_get_gpios(struct m_can_classdev *cdev) 268 { 269 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 270 int ret; 271 272 tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake", 273 GPIOD_OUT_HIGH); 274 if (IS_ERR(tcan4x5x->device_wake_gpio)) { 275 if (PTR_ERR(tcan4x5x->device_wake_gpio) == -EPROBE_DEFER) 276 return -EPROBE_DEFER; 277 278 tcan4x5x_disable_wake(cdev); 279 } 280 281 tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset", 282 GPIOD_OUT_LOW); 283 if (IS_ERR(tcan4x5x->reset_gpio)) 284 tcan4x5x->reset_gpio = NULL; 285 286 ret = tcan4x5x_reset(tcan4x5x); 287 if (ret) 288 return ret; 289 290 tcan4x5x->device_state_gpio = devm_gpiod_get_optional(cdev->dev, 291 "device-state", 292 GPIOD_IN); 293 if (IS_ERR(tcan4x5x->device_state_gpio)) { 294 tcan4x5x->device_state_gpio = NULL; 295 tcan4x5x_disable_state(cdev); 296 } 297 298 return 0; 299 } 300 301 static struct m_can_ops tcan4x5x_ops = { 302 .init = tcan4x5x_init, 303 .read_reg = tcan4x5x_read_reg, 304 .write_reg = tcan4x5x_write_reg, 305 .write_fifo = tcan4x5x_write_fifo, 306 .read_fifo = tcan4x5x_read_fifo, 307 .clear_interrupts = tcan4x5x_clear_interrupts, 308 }; 309 310 static int tcan4x5x_can_probe(struct spi_device *spi) 311 { 312 struct tcan4x5x_priv *priv; 313 struct m_can_classdev *mcan_class; 314 int freq, ret; 315 316 mcan_class = m_can_class_allocate_dev(&spi->dev, 317 sizeof(struct tcan4x5x_priv)); 318 if (!mcan_class) 319 return -ENOMEM; 320 321 priv = cdev_to_priv(mcan_class); 322 323 priv->power = devm_regulator_get_optional(&spi->dev, "vsup"); 324 if (PTR_ERR(priv->power) == -EPROBE_DEFER) { 325 ret = -EPROBE_DEFER; 326 goto out_m_can_class_free_dev; 327 } else { 328 priv->power = NULL; 329 } 330 331 m_can_class_get_clocks(mcan_class); 332 if (IS_ERR(mcan_class->cclk)) { 333 dev_err(&spi->dev, "no CAN clock source defined\n"); 334 freq = TCAN4X5X_EXT_CLK_DEF; 335 } else { 336 freq = clk_get_rate(mcan_class->cclk); 337 } 338 339 /* Sanity check */ 340 if (freq < 20000000 || freq > TCAN4X5X_EXT_CLK_DEF) { 341 ret = -ERANGE; 342 goto out_m_can_class_free_dev; 343 } 344 345 priv->spi = spi; 346 347 mcan_class->pm_clock_support = 0; 348 mcan_class->can.clock.freq = freq; 349 mcan_class->dev = &spi->dev; 350 mcan_class->ops = &tcan4x5x_ops; 351 mcan_class->is_peripheral = true; 352 mcan_class->net->irq = spi->irq; 353 354 spi_set_drvdata(spi, priv); 355 356 /* Configure the SPI bus */ 357 spi->bits_per_word = 8; 358 ret = spi_setup(spi); 359 if (ret) 360 goto out_m_can_class_free_dev; 361 362 ret = tcan4x5x_regmap_init(priv); 363 if (ret) 364 goto out_m_can_class_free_dev; 365 366 ret = tcan4x5x_power_enable(priv->power, 1); 367 if (ret) 368 goto out_m_can_class_free_dev; 369 370 ret = tcan4x5x_get_gpios(mcan_class); 371 if (ret) 372 goto out_power; 373 374 ret = tcan4x5x_init(mcan_class); 375 if (ret) 376 goto out_power; 377 378 ret = m_can_class_register(mcan_class); 379 if (ret) 380 goto out_power; 381 382 netdev_info(mcan_class->net, "TCAN4X5X successfully initialized.\n"); 383 return 0; 384 385 out_power: 386 tcan4x5x_power_enable(priv->power, 0); 387 out_m_can_class_free_dev: 388 m_can_class_free_dev(mcan_class->net); 389 return ret; 390 } 391 392 static int tcan4x5x_can_remove(struct spi_device *spi) 393 { 394 struct tcan4x5x_priv *priv = spi_get_drvdata(spi); 395 396 m_can_class_unregister(&priv->cdev); 397 398 tcan4x5x_power_enable(priv->power, 0); 399 400 m_can_class_free_dev(priv->cdev.net); 401 402 return 0; 403 } 404 405 static const struct of_device_id tcan4x5x_of_match[] = { 406 { 407 .compatible = "ti,tcan4x5x", 408 }, { 409 /* sentinel */ 410 }, 411 }; 412 MODULE_DEVICE_TABLE(of, tcan4x5x_of_match); 413 414 static const struct spi_device_id tcan4x5x_id_table[] = { 415 { 416 .name = "tcan4x5x", 417 }, { 418 /* sentinel */ 419 }, 420 }; 421 MODULE_DEVICE_TABLE(spi, tcan4x5x_id_table); 422 423 static struct spi_driver tcan4x5x_can_driver = { 424 .driver = { 425 .name = KBUILD_MODNAME, 426 .of_match_table = tcan4x5x_of_match, 427 .pm = NULL, 428 }, 429 .id_table = tcan4x5x_id_table, 430 .probe = tcan4x5x_can_probe, 431 .remove = tcan4x5x_can_remove, 432 }; 433 module_spi_driver(tcan4x5x_can_driver); 434 435 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 436 MODULE_DESCRIPTION("Texas Instruments TCAN4x5x CAN driver"); 437 MODULE_LICENSE("GPL v2"); 438