1 // SPDX-License-Identifier: GPL-2.0 2 // SPI to CAN driver for the Texas Instruments TCAN4x5x 3 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/ 4 5 #include "tcan4x5x.h" 6 7 #define TCAN4X5X_EXT_CLK_DEF 40000000 8 9 #define TCAN4X5X_DEV_ID0 0x00 10 #define TCAN4X5X_DEV_ID1 0x04 11 #define TCAN4X5X_REV 0x08 12 #define TCAN4X5X_STATUS 0x0C 13 #define TCAN4X5X_ERROR_STATUS_MASK 0x10 14 #define TCAN4X5X_CONTROL 0x14 15 16 #define TCAN4X5X_CONFIG 0x800 17 #define TCAN4X5X_TS_PRESCALE 0x804 18 #define TCAN4X5X_TEST_REG 0x808 19 #define TCAN4X5X_INT_FLAGS 0x820 20 #define TCAN4X5X_MCAN_INT_REG 0x824 21 #define TCAN4X5X_INT_EN 0x830 22 23 /* Interrupt bits */ 24 #define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30) 25 #define TCAN4X5X_CANHCANL_INT_EN BIT(29) 26 #define TCAN4X5X_CANHBAT_INT_EN BIT(28) 27 #define TCAN4X5X_CANLGND_INT_EN BIT(27) 28 #define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26) 29 #define TCAN4X5X_CANBUSGND_INT_EN BIT(25) 30 #define TCAN4X5X_CANBUSBAT_INT_EN BIT(24) 31 #define TCAN4X5X_UVSUP_INT_EN BIT(22) 32 #define TCAN4X5X_UVIO_INT_EN BIT(21) 33 #define TCAN4X5X_TSD_INT_EN BIT(19) 34 #define TCAN4X5X_ECCERR_INT_EN BIT(16) 35 #define TCAN4X5X_CANINT_INT_EN BIT(15) 36 #define TCAN4X5X_LWU_INT_EN BIT(14) 37 #define TCAN4X5X_CANSLNT_INT_EN BIT(10) 38 #define TCAN4X5X_CANDOM_INT_EN BIT(8) 39 #define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5) 40 #define TCAN4X5X_BUS_FAULT BIT(4) 41 #define TCAN4X5X_MCAN_INT BIT(1) 42 #define TCAN4X5X_ENABLE_TCAN_INT \ 43 (TCAN4X5X_MCAN_INT | TCAN4X5X_BUS_FAULT | \ 44 TCAN4X5X_CANBUS_ERR_INT_EN | TCAN4X5X_CANINT_INT_EN) 45 46 /* MCAN Interrupt bits */ 47 #define TCAN4X5X_MCAN_IR_ARA BIT(29) 48 #define TCAN4X5X_MCAN_IR_PED BIT(28) 49 #define TCAN4X5X_MCAN_IR_PEA BIT(27) 50 #define TCAN4X5X_MCAN_IR_WD BIT(26) 51 #define TCAN4X5X_MCAN_IR_BO BIT(25) 52 #define TCAN4X5X_MCAN_IR_EW BIT(24) 53 #define TCAN4X5X_MCAN_IR_EP BIT(23) 54 #define TCAN4X5X_MCAN_IR_ELO BIT(22) 55 #define TCAN4X5X_MCAN_IR_BEU BIT(21) 56 #define TCAN4X5X_MCAN_IR_BEC BIT(20) 57 #define TCAN4X5X_MCAN_IR_DRX BIT(19) 58 #define TCAN4X5X_MCAN_IR_TOO BIT(18) 59 #define TCAN4X5X_MCAN_IR_MRAF BIT(17) 60 #define TCAN4X5X_MCAN_IR_TSW BIT(16) 61 #define TCAN4X5X_MCAN_IR_TEFL BIT(15) 62 #define TCAN4X5X_MCAN_IR_TEFF BIT(14) 63 #define TCAN4X5X_MCAN_IR_TEFW BIT(13) 64 #define TCAN4X5X_MCAN_IR_TEFN BIT(12) 65 #define TCAN4X5X_MCAN_IR_TFE BIT(11) 66 #define TCAN4X5X_MCAN_IR_TCF BIT(10) 67 #define TCAN4X5X_MCAN_IR_TC BIT(9) 68 #define TCAN4X5X_MCAN_IR_HPM BIT(8) 69 #define TCAN4X5X_MCAN_IR_RF1L BIT(7) 70 #define TCAN4X5X_MCAN_IR_RF1F BIT(6) 71 #define TCAN4X5X_MCAN_IR_RF1W BIT(5) 72 #define TCAN4X5X_MCAN_IR_RF1N BIT(4) 73 #define TCAN4X5X_MCAN_IR_RF0L BIT(3) 74 #define TCAN4X5X_MCAN_IR_RF0F BIT(2) 75 #define TCAN4X5X_MCAN_IR_RF0W BIT(1) 76 #define TCAN4X5X_MCAN_IR_RF0N BIT(0) 77 #define TCAN4X5X_ENABLE_MCAN_INT \ 78 (TCAN4X5X_MCAN_IR_TC | TCAN4X5X_MCAN_IR_RF0N | \ 79 TCAN4X5X_MCAN_IR_RF1N | TCAN4X5X_MCAN_IR_RF0F | \ 80 TCAN4X5X_MCAN_IR_RF1F) 81 82 #define TCAN4X5X_MRAM_START 0x8000 83 #define TCAN4X5X_MCAN_OFFSET 0x1000 84 85 #define TCAN4X5X_CLEAR_ALL_INT 0xffffffff 86 #define TCAN4X5X_SET_ALL_INT 0xffffffff 87 88 #define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6)) 89 #define TCAN4X5X_MODE_SLEEP 0x00 90 #define TCAN4X5X_MODE_STANDBY BIT(6) 91 #define TCAN4X5X_MODE_NORMAL BIT(7) 92 93 #define TCAN4X5X_DISABLE_WAKE_MSK (BIT(31) | BIT(30)) 94 #define TCAN4X5X_DISABLE_INH_MSK BIT(9) 95 96 #define TCAN4X5X_SW_RESET BIT(2) 97 98 #define TCAN4X5X_MCAN_CONFIGURED BIT(5) 99 #define TCAN4X5X_WATCHDOG_EN BIT(3) 100 #define TCAN4X5X_WD_60_MS_TIMER 0 101 #define TCAN4X5X_WD_600_MS_TIMER BIT(28) 102 #define TCAN4X5X_WD_3_S_TIMER BIT(29) 103 #define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29)) 104 105 static inline struct tcan4x5x_priv *cdev_to_priv(struct m_can_classdev *cdev) 106 { 107 return container_of(cdev, struct tcan4x5x_priv, cdev); 108 } 109 110 static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv) 111 { 112 int wake_state = 0; 113 114 if (priv->device_state_gpio) 115 wake_state = gpiod_get_value(priv->device_state_gpio); 116 117 if (priv->device_wake_gpio && wake_state) { 118 gpiod_set_value(priv->device_wake_gpio, 0); 119 usleep_range(5, 50); 120 gpiod_set_value(priv->device_wake_gpio, 1); 121 } 122 } 123 124 static int tcan4x5x_reset(struct tcan4x5x_priv *priv) 125 { 126 int ret = 0; 127 128 if (priv->reset_gpio) { 129 gpiod_set_value(priv->reset_gpio, 1); 130 131 /* tpulse_width minimum 30us */ 132 usleep_range(30, 100); 133 gpiod_set_value(priv->reset_gpio, 0); 134 } else { 135 ret = regmap_write(priv->regmap, TCAN4X5X_CONFIG, 136 TCAN4X5X_SW_RESET); 137 if (ret) 138 return ret; 139 } 140 141 usleep_range(700, 1000); 142 143 return ret; 144 } 145 146 static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg) 147 { 148 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 149 u32 val; 150 151 regmap_read(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, &val); 152 153 return val; 154 } 155 156 static int tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset, 157 void *val, size_t val_count) 158 { 159 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 160 161 return regmap_bulk_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val, val_count); 162 } 163 164 static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val) 165 { 166 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 167 168 return regmap_write(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, val); 169 } 170 171 static int tcan4x5x_write_fifo(struct m_can_classdev *cdev, 172 int addr_offset, const void *val, size_t val_count) 173 { 174 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 175 176 return regmap_bulk_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val, val_count); 177 } 178 179 static int tcan4x5x_power_enable(struct regulator *reg, int enable) 180 { 181 if (IS_ERR_OR_NULL(reg)) 182 return 0; 183 184 if (enable) 185 return regulator_enable(reg); 186 else 187 return regulator_disable(reg); 188 } 189 190 static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev, 191 int reg, int val) 192 { 193 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 194 195 return regmap_write(priv->regmap, reg, val); 196 } 197 198 static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev) 199 { 200 int ret; 201 202 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_STATUS, 203 TCAN4X5X_CLEAR_ALL_INT); 204 if (ret) 205 return ret; 206 207 return tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_FLAGS, 208 TCAN4X5X_CLEAR_ALL_INT); 209 } 210 211 static int tcan4x5x_init(struct m_can_classdev *cdev) 212 { 213 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 214 int ret; 215 216 tcan4x5x_check_wake(tcan4x5x); 217 218 ret = tcan4x5x_clear_interrupts(cdev); 219 if (ret) 220 return ret; 221 222 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_EN, 223 TCAN4X5X_ENABLE_TCAN_INT); 224 if (ret) 225 return ret; 226 227 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_ERROR_STATUS_MASK, 228 TCAN4X5X_CLEAR_ALL_INT); 229 if (ret) 230 return ret; 231 232 ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 233 TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL); 234 if (ret) 235 return ret; 236 237 return ret; 238 } 239 240 static int tcan4x5x_disable_wake(struct m_can_classdev *cdev) 241 { 242 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 243 244 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 245 TCAN4X5X_DISABLE_WAKE_MSK, 0x00); 246 } 247 248 static int tcan4x5x_disable_state(struct m_can_classdev *cdev) 249 { 250 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 251 252 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 253 TCAN4X5X_DISABLE_INH_MSK, 0x01); 254 } 255 256 static int tcan4x5x_get_gpios(struct m_can_classdev *cdev) 257 { 258 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 259 int ret; 260 261 tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake", 262 GPIOD_OUT_HIGH); 263 if (IS_ERR(tcan4x5x->device_wake_gpio)) { 264 if (PTR_ERR(tcan4x5x->device_wake_gpio) == -EPROBE_DEFER) 265 return -EPROBE_DEFER; 266 267 tcan4x5x_disable_wake(cdev); 268 } 269 270 tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset", 271 GPIOD_OUT_LOW); 272 if (IS_ERR(tcan4x5x->reset_gpio)) 273 tcan4x5x->reset_gpio = NULL; 274 275 ret = tcan4x5x_reset(tcan4x5x); 276 if (ret) 277 return ret; 278 279 tcan4x5x->device_state_gpio = devm_gpiod_get_optional(cdev->dev, 280 "device-state", 281 GPIOD_IN); 282 if (IS_ERR(tcan4x5x->device_state_gpio)) { 283 tcan4x5x->device_state_gpio = NULL; 284 tcan4x5x_disable_state(cdev); 285 } 286 287 return 0; 288 } 289 290 static struct m_can_ops tcan4x5x_ops = { 291 .init = tcan4x5x_init, 292 .read_reg = tcan4x5x_read_reg, 293 .write_reg = tcan4x5x_write_reg, 294 .write_fifo = tcan4x5x_write_fifo, 295 .read_fifo = tcan4x5x_read_fifo, 296 .clear_interrupts = tcan4x5x_clear_interrupts, 297 }; 298 299 static int tcan4x5x_can_probe(struct spi_device *spi) 300 { 301 struct tcan4x5x_priv *priv; 302 struct m_can_classdev *mcan_class; 303 int freq, ret; 304 305 mcan_class = m_can_class_allocate_dev(&spi->dev, 306 sizeof(struct tcan4x5x_priv)); 307 if (!mcan_class) 308 return -ENOMEM; 309 310 priv = cdev_to_priv(mcan_class); 311 312 priv->power = devm_regulator_get_optional(&spi->dev, "vsup"); 313 if (PTR_ERR(priv->power) == -EPROBE_DEFER) { 314 ret = -EPROBE_DEFER; 315 goto out_m_can_class_free_dev; 316 } else { 317 priv->power = NULL; 318 } 319 320 m_can_class_get_clocks(mcan_class); 321 if (IS_ERR(mcan_class->cclk)) { 322 dev_err(&spi->dev, "no CAN clock source defined\n"); 323 freq = TCAN4X5X_EXT_CLK_DEF; 324 } else { 325 freq = clk_get_rate(mcan_class->cclk); 326 } 327 328 /* Sanity check */ 329 if (freq < 20000000 || freq > TCAN4X5X_EXT_CLK_DEF) { 330 ret = -ERANGE; 331 goto out_m_can_class_free_dev; 332 } 333 334 priv->spi = spi; 335 336 mcan_class->pm_clock_support = 0; 337 mcan_class->can.clock.freq = freq; 338 mcan_class->dev = &spi->dev; 339 mcan_class->ops = &tcan4x5x_ops; 340 mcan_class->is_peripheral = true; 341 mcan_class->net->irq = spi->irq; 342 343 spi_set_drvdata(spi, priv); 344 345 /* Configure the SPI bus */ 346 spi->bits_per_word = 8; 347 ret = spi_setup(spi); 348 if (ret) 349 goto out_m_can_class_free_dev; 350 351 ret = tcan4x5x_regmap_init(priv); 352 if (ret) 353 goto out_m_can_class_free_dev; 354 355 ret = tcan4x5x_power_enable(priv->power, 1); 356 if (ret) 357 goto out_m_can_class_free_dev; 358 359 ret = tcan4x5x_get_gpios(mcan_class); 360 if (ret) 361 goto out_power; 362 363 ret = tcan4x5x_init(mcan_class); 364 if (ret) 365 goto out_power; 366 367 ret = m_can_class_register(mcan_class); 368 if (ret) 369 goto out_power; 370 371 netdev_info(mcan_class->net, "TCAN4X5X successfully initialized.\n"); 372 return 0; 373 374 out_power: 375 tcan4x5x_power_enable(priv->power, 0); 376 out_m_can_class_free_dev: 377 m_can_class_free_dev(mcan_class->net); 378 return ret; 379 } 380 381 static void tcan4x5x_can_remove(struct spi_device *spi) 382 { 383 struct tcan4x5x_priv *priv = spi_get_drvdata(spi); 384 385 m_can_class_unregister(&priv->cdev); 386 387 tcan4x5x_power_enable(priv->power, 0); 388 389 m_can_class_free_dev(priv->cdev.net); 390 } 391 392 static const struct of_device_id tcan4x5x_of_match[] = { 393 { 394 .compatible = "ti,tcan4x5x", 395 }, { 396 /* sentinel */ 397 }, 398 }; 399 MODULE_DEVICE_TABLE(of, tcan4x5x_of_match); 400 401 static const struct spi_device_id tcan4x5x_id_table[] = { 402 { 403 .name = "tcan4x5x", 404 }, { 405 /* sentinel */ 406 }, 407 }; 408 MODULE_DEVICE_TABLE(spi, tcan4x5x_id_table); 409 410 static struct spi_driver tcan4x5x_can_driver = { 411 .driver = { 412 .name = KBUILD_MODNAME, 413 .of_match_table = tcan4x5x_of_match, 414 .pm = NULL, 415 }, 416 .id_table = tcan4x5x_id_table, 417 .probe = tcan4x5x_can_probe, 418 .remove = tcan4x5x_can_remove, 419 }; 420 module_spi_driver(tcan4x5x_can_driver); 421 422 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 423 MODULE_DESCRIPTION("Texas Instruments TCAN4x5x CAN driver"); 424 MODULE_LICENSE("GPL v2"); 425