xref: /openbmc/linux/drivers/net/can/m_can/m_can.h (revision 84e00d9b)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* CAN bus driver for Bosch M_CAN controller
3  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4  */
5 
6 #ifndef _CAN_M_CAN_H_
7 #define _CAN_M_CAN_H_
8 
9 #include <linux/can/core.h>
10 #include <linux/can/dev.h>
11 #include <linux/can/rx-offload.h>
12 #include <linux/clk.h>
13 #include <linux/completion.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/freezer.h>
18 #include <linux/hrtimer.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/iopoll.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
25 #include <linux/of.h>
26 #include <linux/phy/phy.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/uaccess.h>
31 
32 /* m_can lec values */
33 enum m_can_lec_type {
34 	LEC_NO_ERROR = 0,
35 	LEC_STUFF_ERROR,
36 	LEC_FORM_ERROR,
37 	LEC_ACK_ERROR,
38 	LEC_BIT1_ERROR,
39 	LEC_BIT0_ERROR,
40 	LEC_CRC_ERROR,
41 	LEC_NO_CHANGE,
42 };
43 
44 enum m_can_mram_cfg {
45 	MRAM_SIDF = 0,
46 	MRAM_XIDF,
47 	MRAM_RXF0,
48 	MRAM_RXF1,
49 	MRAM_RXB,
50 	MRAM_TXE,
51 	MRAM_TXB,
52 	MRAM_CFG_NUM,
53 };
54 
55 /* address offset and element number for each FIFO/Buffer in the Message RAM */
56 struct mram_cfg {
57 	u16 off;
58 	u8  num;
59 };
60 
61 struct m_can_classdev;
62 struct m_can_ops {
63 	/* Device specific call backs */
64 	int (*clear_interrupts)(struct m_can_classdev *cdev);
65 	u32 (*read_reg)(struct m_can_classdev *cdev, int reg);
66 	int (*write_reg)(struct m_can_classdev *cdev, int reg, int val);
67 	int (*read_fifo)(struct m_can_classdev *cdev, int addr_offset, void *val, size_t val_count);
68 	int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset,
69 			  const void *val, size_t val_count);
70 	int (*init)(struct m_can_classdev *cdev);
71 };
72 
73 struct m_can_classdev {
74 	struct can_priv can;
75 	struct can_rx_offload offload;
76 	struct napi_struct napi;
77 	struct net_device *net;
78 	struct device *dev;
79 	struct clk *hclk;
80 	struct clk *cclk;
81 
82 	struct workqueue_struct *tx_wq;
83 	struct work_struct tx_work;
84 	struct sk_buff *tx_skb;
85 	struct phy *transceiver;
86 
87 	struct m_can_ops *ops;
88 
89 	int version;
90 	u32 irqstatus;
91 
92 	int pm_clock_support;
93 	int is_peripheral;
94 
95 	struct mram_cfg mcfg[MRAM_CFG_NUM];
96 
97 	struct hrtimer hrtimer;
98 };
99 
100 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv);
101 void m_can_class_free_dev(struct net_device *net);
102 int m_can_class_register(struct m_can_classdev *cdev);
103 void m_can_class_unregister(struct m_can_classdev *cdev);
104 int m_can_class_get_clocks(struct m_can_classdev *cdev);
105 int m_can_init_ram(struct m_can_classdev *priv);
106 
107 int m_can_class_suspend(struct device *dev);
108 int m_can_class_resume(struct device *dev);
109 #endif	/* _CAN_M_H_ */
110