1 // SPDX-License-Identifier: GPL-2.0 2 // CAN bus driver for Bosch M_CAN controller 3 // Copyright (C) 2014 Freescale Semiconductor, Inc. 4 // Dong Aisheng <b29396@freescale.com> 5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/ 6 7 /* Bosch M_CAN user manual can be obtained from: 8 * https://github.com/linux-can/can-doc/tree/master/m_can 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/iopoll.h> 22 #include <linux/can/dev.h> 23 #include <linux/pinctrl/consumer.h> 24 25 #include "m_can.h" 26 27 /* registers definition */ 28 enum m_can_reg { 29 M_CAN_CREL = 0x0, 30 M_CAN_ENDN = 0x4, 31 M_CAN_CUST = 0x8, 32 M_CAN_DBTP = 0xc, 33 M_CAN_TEST = 0x10, 34 M_CAN_RWD = 0x14, 35 M_CAN_CCCR = 0x18, 36 M_CAN_NBTP = 0x1c, 37 M_CAN_TSCC = 0x20, 38 M_CAN_TSCV = 0x24, 39 M_CAN_TOCC = 0x28, 40 M_CAN_TOCV = 0x2c, 41 M_CAN_ECR = 0x40, 42 M_CAN_PSR = 0x44, 43 /* TDCR Register only available for version >=3.1.x */ 44 M_CAN_TDCR = 0x48, 45 M_CAN_IR = 0x50, 46 M_CAN_IE = 0x54, 47 M_CAN_ILS = 0x58, 48 M_CAN_ILE = 0x5c, 49 M_CAN_GFC = 0x80, 50 M_CAN_SIDFC = 0x84, 51 M_CAN_XIDFC = 0x88, 52 M_CAN_XIDAM = 0x90, 53 M_CAN_HPMS = 0x94, 54 M_CAN_NDAT1 = 0x98, 55 M_CAN_NDAT2 = 0x9c, 56 M_CAN_RXF0C = 0xa0, 57 M_CAN_RXF0S = 0xa4, 58 M_CAN_RXF0A = 0xa8, 59 M_CAN_RXBC = 0xac, 60 M_CAN_RXF1C = 0xb0, 61 M_CAN_RXF1S = 0xb4, 62 M_CAN_RXF1A = 0xb8, 63 M_CAN_RXESC = 0xbc, 64 M_CAN_TXBC = 0xc0, 65 M_CAN_TXFQS = 0xc4, 66 M_CAN_TXESC = 0xc8, 67 M_CAN_TXBRP = 0xcc, 68 M_CAN_TXBAR = 0xd0, 69 M_CAN_TXBCR = 0xd4, 70 M_CAN_TXBTO = 0xd8, 71 M_CAN_TXBCF = 0xdc, 72 M_CAN_TXBTIE = 0xe0, 73 M_CAN_TXBCIE = 0xe4, 74 M_CAN_TXEFC = 0xf0, 75 M_CAN_TXEFS = 0xf4, 76 M_CAN_TXEFA = 0xf8, 77 }; 78 79 /* napi related */ 80 #define M_CAN_NAPI_WEIGHT 64 81 82 /* message ram configuration data length */ 83 #define MRAM_CFG_LEN 8 84 85 /* Core Release Register (CREL) */ 86 #define CREL_REL_SHIFT 28 87 #define CREL_REL_MASK (0xF << CREL_REL_SHIFT) 88 #define CREL_STEP_SHIFT 24 89 #define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT) 90 #define CREL_SUBSTEP_SHIFT 20 91 #define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT) 92 93 /* Data Bit Timing & Prescaler Register (DBTP) */ 94 #define DBTP_TDC BIT(23) 95 #define DBTP_DBRP_SHIFT 16 96 #define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT) 97 #define DBTP_DTSEG1_SHIFT 8 98 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT) 99 #define DBTP_DTSEG2_SHIFT 4 100 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT) 101 #define DBTP_DSJW_SHIFT 0 102 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT) 103 104 /* Transmitter Delay Compensation Register (TDCR) */ 105 #define TDCR_TDCO_SHIFT 8 106 #define TDCR_TDCO_MASK (0x7F << TDCR_TDCO_SHIFT) 107 #define TDCR_TDCF_SHIFT 0 108 #define TDCR_TDCF_MASK (0x7F << TDCR_TDCF_SHIFT) 109 110 /* Test Register (TEST) */ 111 #define TEST_LBCK BIT(4) 112 113 /* CC Control Register(CCCR) */ 114 #define CCCR_CMR_MASK 0x3 115 #define CCCR_CMR_SHIFT 10 116 #define CCCR_CMR_CANFD 0x1 117 #define CCCR_CMR_CANFD_BRS 0x2 118 #define CCCR_CMR_CAN 0x3 119 #define CCCR_CME_MASK 0x3 120 #define CCCR_CME_SHIFT 8 121 #define CCCR_CME_CAN 0 122 #define CCCR_CME_CANFD 0x1 123 #define CCCR_CME_CANFD_BRS 0x2 124 #define CCCR_TXP BIT(14) 125 #define CCCR_TEST BIT(7) 126 #define CCCR_DAR BIT(6) 127 #define CCCR_MON BIT(5) 128 #define CCCR_CSR BIT(4) 129 #define CCCR_CSA BIT(3) 130 #define CCCR_ASM BIT(2) 131 #define CCCR_CCE BIT(1) 132 #define CCCR_INIT BIT(0) 133 #define CCCR_CANFD 0x10 134 /* for version >=3.1.x */ 135 #define CCCR_EFBI BIT(13) 136 #define CCCR_PXHD BIT(12) 137 #define CCCR_BRSE BIT(9) 138 #define CCCR_FDOE BIT(8) 139 /* only for version >=3.2.x */ 140 #define CCCR_NISO BIT(15) 141 142 /* Nominal Bit Timing & Prescaler Register (NBTP) */ 143 #define NBTP_NSJW_SHIFT 25 144 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT) 145 #define NBTP_NBRP_SHIFT 16 146 #define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT) 147 #define NBTP_NTSEG1_SHIFT 8 148 #define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT) 149 #define NBTP_NTSEG2_SHIFT 0 150 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT) 151 152 /* Timestamp Counter Configuration Register (TSCC) */ 153 #define TSCC_TCP_MASK GENMASK(19, 16) 154 #define TSCC_TSS_MASK GENMASK(1, 0) 155 #define TSCC_TSS_DISABLE 0x0 156 #define TSCC_TSS_INTERNAL 0x1 157 #define TSCC_TSS_EXTERNAL 0x2 158 159 /* Timestamp Counter Value Register (TSCV) */ 160 #define TSCV_TSC_MASK GENMASK(15, 0) 161 162 /* Error Counter Register(ECR) */ 163 #define ECR_RP BIT(15) 164 #define ECR_REC_SHIFT 8 165 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT) 166 #define ECR_TEC_SHIFT 0 167 #define ECR_TEC_MASK 0xff 168 169 /* Protocol Status Register(PSR) */ 170 #define PSR_BO BIT(7) 171 #define PSR_EW BIT(6) 172 #define PSR_EP BIT(5) 173 #define PSR_LEC_MASK 0x7 174 175 /* Interrupt Register(IR) */ 176 #define IR_ALL_INT 0xffffffff 177 178 /* Renamed bits for versions > 3.1.x */ 179 #define IR_ARA BIT(29) 180 #define IR_PED BIT(28) 181 #define IR_PEA BIT(27) 182 183 /* Bits for version 3.0.x */ 184 #define IR_STE BIT(31) 185 #define IR_FOE BIT(30) 186 #define IR_ACKE BIT(29) 187 #define IR_BE BIT(28) 188 #define IR_CRCE BIT(27) 189 #define IR_WDI BIT(26) 190 #define IR_BO BIT(25) 191 #define IR_EW BIT(24) 192 #define IR_EP BIT(23) 193 #define IR_ELO BIT(22) 194 #define IR_BEU BIT(21) 195 #define IR_BEC BIT(20) 196 #define IR_DRX BIT(19) 197 #define IR_TOO BIT(18) 198 #define IR_MRAF BIT(17) 199 #define IR_TSW BIT(16) 200 #define IR_TEFL BIT(15) 201 #define IR_TEFF BIT(14) 202 #define IR_TEFW BIT(13) 203 #define IR_TEFN BIT(12) 204 #define IR_TFE BIT(11) 205 #define IR_TCF BIT(10) 206 #define IR_TC BIT(9) 207 #define IR_HPM BIT(8) 208 #define IR_RF1L BIT(7) 209 #define IR_RF1F BIT(6) 210 #define IR_RF1W BIT(5) 211 #define IR_RF1N BIT(4) 212 #define IR_RF0L BIT(3) 213 #define IR_RF0F BIT(2) 214 #define IR_RF0W BIT(1) 215 #define IR_RF0N BIT(0) 216 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) 217 218 /* Interrupts for version 3.0.x */ 219 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) 220 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \ 221 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 222 IR_RF1L | IR_RF0L) 223 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X) 224 /* Interrupts for version >= 3.1.x */ 225 #define IR_ERR_LEC_31X (IR_PED | IR_PEA) 226 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \ 227 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 228 IR_RF1L | IR_RF0L) 229 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X) 230 231 /* Interrupt Line Select (ILS) */ 232 #define ILS_ALL_INT0 0x0 233 #define ILS_ALL_INT1 0xFFFFFFFF 234 235 /* Interrupt Line Enable (ILE) */ 236 #define ILE_EINT1 BIT(1) 237 #define ILE_EINT0 BIT(0) 238 239 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ 240 #define RXFC_FWM_SHIFT 24 241 #define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT) 242 #define RXFC_FS_SHIFT 16 243 #define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT) 244 245 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ 246 #define RXFS_RFL BIT(25) 247 #define RXFS_FF BIT(24) 248 #define RXFS_FPI_SHIFT 16 249 #define RXFS_FPI_MASK 0x3f0000 250 #define RXFS_FGI_SHIFT 8 251 #define RXFS_FGI_MASK 0x3f00 252 #define RXFS_FFL_MASK 0x7f 253 254 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ 255 #define M_CAN_RXESC_8BYTES 0x0 256 #define M_CAN_RXESC_64BYTES 0x777 257 258 /* Tx Buffer Configuration(TXBC) */ 259 #define TXBC_NDTB_SHIFT 16 260 #define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT) 261 #define TXBC_TFQS_SHIFT 24 262 #define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT) 263 264 /* Tx FIFO/Queue Status (TXFQS) */ 265 #define TXFQS_TFQF BIT(21) 266 #define TXFQS_TFQPI_SHIFT 16 267 #define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT) 268 #define TXFQS_TFGI_SHIFT 8 269 #define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT) 270 #define TXFQS_TFFL_SHIFT 0 271 #define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT) 272 273 /* Tx Buffer Element Size Configuration(TXESC) */ 274 #define TXESC_TBDS_8BYTES 0x0 275 #define TXESC_TBDS_64BYTES 0x7 276 277 /* Tx Event FIFO Configuration (TXEFC) */ 278 #define TXEFC_EFS_SHIFT 16 279 #define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT) 280 281 /* Tx Event FIFO Status (TXEFS) */ 282 #define TXEFS_TEFL BIT(25) 283 #define TXEFS_EFF BIT(24) 284 #define TXEFS_EFGI_SHIFT 8 285 #define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT) 286 #define TXEFS_EFFL_SHIFT 0 287 #define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT) 288 289 /* Tx Event FIFO Acknowledge (TXEFA) */ 290 #define TXEFA_EFAI_SHIFT 0 291 #define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT) 292 293 /* Message RAM Configuration (in bytes) */ 294 #define SIDF_ELEMENT_SIZE 4 295 #define XIDF_ELEMENT_SIZE 8 296 #define RXF0_ELEMENT_SIZE 72 297 #define RXF1_ELEMENT_SIZE 72 298 #define RXB_ELEMENT_SIZE 72 299 #define TXE_ELEMENT_SIZE 8 300 #define TXB_ELEMENT_SIZE 72 301 302 /* Message RAM Elements */ 303 #define M_CAN_FIFO_ID 0x0 304 #define M_CAN_FIFO_DLC 0x4 305 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2)) 306 307 /* Rx Buffer Element */ 308 /* R0 */ 309 #define RX_BUF_ESI BIT(31) 310 #define RX_BUF_XTD BIT(30) 311 #define RX_BUF_RTR BIT(29) 312 /* R1 */ 313 #define RX_BUF_ANMF BIT(31) 314 #define RX_BUF_FDF BIT(21) 315 #define RX_BUF_BRS BIT(20) 316 #define RX_BUF_RXTS_MASK GENMASK(15, 0) 317 318 /* Tx Buffer Element */ 319 /* T0 */ 320 #define TX_BUF_ESI BIT(31) 321 #define TX_BUF_XTD BIT(30) 322 #define TX_BUF_RTR BIT(29) 323 /* T1 */ 324 #define TX_BUF_EFC BIT(23) 325 #define TX_BUF_FDF BIT(21) 326 #define TX_BUF_BRS BIT(20) 327 #define TX_BUF_MM_SHIFT 24 328 #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT) 329 330 /* Tx event FIFO Element */ 331 /* E1 */ 332 #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT 333 #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT) 334 #define TX_EVENT_TXTS_MASK GENMASK(15, 0) 335 336 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) 337 { 338 return cdev->ops->read_reg(cdev, reg); 339 } 340 341 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, 342 u32 val) 343 { 344 cdev->ops->write_reg(cdev, reg, val); 345 } 346 347 static u32 m_can_fifo_read(struct m_can_classdev *cdev, 348 u32 fgi, unsigned int offset) 349 { 350 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + 351 offset; 352 353 return cdev->ops->read_fifo(cdev, addr_offset); 354 } 355 356 static void m_can_fifo_write(struct m_can_classdev *cdev, 357 u32 fpi, unsigned int offset, u32 val) 358 { 359 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + 360 offset; 361 362 cdev->ops->write_fifo(cdev, addr_offset, val); 363 } 364 365 static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev, 366 u32 fpi, u32 val) 367 { 368 cdev->ops->write_fifo(cdev, fpi, val); 369 } 370 371 static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset) 372 { 373 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + 374 offset; 375 376 return cdev->ops->read_fifo(cdev, addr_offset); 377 } 378 379 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev) 380 { 381 return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF); 382 } 383 384 static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable) 385 { 386 u32 cccr = m_can_read(cdev, M_CAN_CCCR); 387 u32 timeout = 10; 388 u32 val = 0; 389 390 /* Clear the Clock stop request if it was set */ 391 if (cccr & CCCR_CSR) 392 cccr &= ~CCCR_CSR; 393 394 if (enable) { 395 /* enable m_can configuration */ 396 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT); 397 udelay(5); 398 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ 399 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); 400 } else { 401 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); 402 } 403 404 /* there's a delay for module initialization */ 405 if (enable) 406 val = CCCR_INIT | CCCR_CCE; 407 408 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { 409 if (timeout == 0) { 410 netdev_warn(cdev->net, "Failed to init module\n"); 411 return; 412 } 413 timeout--; 414 udelay(1); 415 } 416 } 417 418 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev) 419 { 420 /* Only interrupt line 0 is used in this driver */ 421 m_can_write(cdev, M_CAN_ILE, ILE_EINT0); 422 } 423 424 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev) 425 { 426 m_can_write(cdev, M_CAN_ILE, 0x0); 427 } 428 429 /* Retrieve internal timestamp counter from TSCV.TSC, and shift it to 32-bit 430 * width. 431 */ 432 static u32 m_can_get_timestamp(struct m_can_classdev *cdev) 433 { 434 u32 tscv; 435 u32 tsc; 436 437 tscv = m_can_read(cdev, M_CAN_TSCV); 438 tsc = FIELD_GET(TSCV_TSC_MASK, tscv); 439 440 return (tsc << 16); 441 } 442 443 static void m_can_clean(struct net_device *net) 444 { 445 struct m_can_classdev *cdev = netdev_priv(net); 446 447 if (cdev->tx_skb) { 448 int putidx = 0; 449 450 net->stats.tx_errors++; 451 if (cdev->version > 30) 452 putidx = ((m_can_read(cdev, M_CAN_TXFQS) & 453 TXFQS_TFQPI_MASK) >> TXFQS_TFQPI_SHIFT); 454 455 can_free_echo_skb(cdev->net, putidx, NULL); 456 cdev->tx_skb = NULL; 457 } 458 } 459 460 /* For peripherals, pass skb to rx-offload, which will push skb from 461 * napi. For non-peripherals, RX is done in napi already, so push 462 * directly. timestamp is used to ensure good skb ordering in 463 * rx-offload and is ignored for non-peripherals. 464 */ 465 static void m_can_receive_skb(struct m_can_classdev *cdev, 466 struct sk_buff *skb, 467 u32 timestamp) 468 { 469 if (cdev->is_peripheral) { 470 struct net_device_stats *stats = &cdev->net->stats; 471 int err; 472 473 err = can_rx_offload_queue_sorted(&cdev->offload, skb, 474 timestamp); 475 if (err) 476 stats->rx_fifo_errors++; 477 } else { 478 netif_receive_skb(skb); 479 } 480 } 481 482 static void m_can_read_fifo(struct net_device *dev, u32 rxfs) 483 { 484 struct net_device_stats *stats = &dev->stats; 485 struct m_can_classdev *cdev = netdev_priv(dev); 486 struct canfd_frame *cf; 487 struct sk_buff *skb; 488 u32 id, fgi, dlc; 489 u32 timestamp = 0; 490 int i; 491 492 /* calculate the fifo get index for where to read data */ 493 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT; 494 dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC); 495 if (dlc & RX_BUF_FDF) 496 skb = alloc_canfd_skb(dev, &cf); 497 else 498 skb = alloc_can_skb(dev, (struct can_frame **)&cf); 499 if (!skb) { 500 stats->rx_dropped++; 501 return; 502 } 503 504 if (dlc & RX_BUF_FDF) 505 cf->len = can_fd_dlc2len((dlc >> 16) & 0x0F); 506 else 507 cf->len = can_cc_dlc2len((dlc >> 16) & 0x0F); 508 509 id = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID); 510 if (id & RX_BUF_XTD) 511 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 512 else 513 cf->can_id = (id >> 18) & CAN_SFF_MASK; 514 515 if (id & RX_BUF_ESI) { 516 cf->flags |= CANFD_ESI; 517 netdev_dbg(dev, "ESI Error\n"); 518 } 519 520 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) { 521 cf->can_id |= CAN_RTR_FLAG; 522 } else { 523 if (dlc & RX_BUF_BRS) 524 cf->flags |= CANFD_BRS; 525 526 for (i = 0; i < cf->len; i += 4) 527 *(u32 *)(cf->data + i) = 528 m_can_fifo_read(cdev, fgi, 529 M_CAN_FIFO_DATA(i / 4)); 530 } 531 532 /* acknowledge rx fifo 0 */ 533 m_can_write(cdev, M_CAN_RXF0A, fgi); 534 535 stats->rx_packets++; 536 stats->rx_bytes += cf->len; 537 538 timestamp = FIELD_GET(RX_BUF_RXTS_MASK, dlc); 539 540 m_can_receive_skb(cdev, skb, timestamp); 541 } 542 543 static int m_can_do_rx_poll(struct net_device *dev, int quota) 544 { 545 struct m_can_classdev *cdev = netdev_priv(dev); 546 u32 pkts = 0; 547 u32 rxfs; 548 549 rxfs = m_can_read(cdev, M_CAN_RXF0S); 550 if (!(rxfs & RXFS_FFL_MASK)) { 551 netdev_dbg(dev, "no messages in fifo0\n"); 552 return 0; 553 } 554 555 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) { 556 m_can_read_fifo(dev, rxfs); 557 558 quota--; 559 pkts++; 560 rxfs = m_can_read(cdev, M_CAN_RXF0S); 561 } 562 563 if (pkts) 564 can_led_event(dev, CAN_LED_EVENT_RX); 565 566 return pkts; 567 } 568 569 static int m_can_handle_lost_msg(struct net_device *dev) 570 { 571 struct m_can_classdev *cdev = netdev_priv(dev); 572 struct net_device_stats *stats = &dev->stats; 573 struct sk_buff *skb; 574 struct can_frame *frame; 575 u32 timestamp = 0; 576 577 netdev_err(dev, "msg lost in rxf0\n"); 578 579 stats->rx_errors++; 580 stats->rx_over_errors++; 581 582 skb = alloc_can_err_skb(dev, &frame); 583 if (unlikely(!skb)) 584 return 0; 585 586 frame->can_id |= CAN_ERR_CRTL; 587 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 588 589 if (cdev->is_peripheral) 590 timestamp = m_can_get_timestamp(cdev); 591 592 m_can_receive_skb(cdev, skb, timestamp); 593 594 return 1; 595 } 596 597 static int m_can_handle_lec_err(struct net_device *dev, 598 enum m_can_lec_type lec_type) 599 { 600 struct m_can_classdev *cdev = netdev_priv(dev); 601 struct net_device_stats *stats = &dev->stats; 602 struct can_frame *cf; 603 struct sk_buff *skb; 604 u32 timestamp = 0; 605 606 cdev->can.can_stats.bus_error++; 607 stats->rx_errors++; 608 609 /* propagate the error condition to the CAN stack */ 610 skb = alloc_can_err_skb(dev, &cf); 611 if (unlikely(!skb)) 612 return 0; 613 614 /* check for 'last error code' which tells us the 615 * type of the last error to occur on the CAN bus 616 */ 617 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 618 619 switch (lec_type) { 620 case LEC_STUFF_ERROR: 621 netdev_dbg(dev, "stuff error\n"); 622 cf->data[2] |= CAN_ERR_PROT_STUFF; 623 break; 624 case LEC_FORM_ERROR: 625 netdev_dbg(dev, "form error\n"); 626 cf->data[2] |= CAN_ERR_PROT_FORM; 627 break; 628 case LEC_ACK_ERROR: 629 netdev_dbg(dev, "ack error\n"); 630 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 631 break; 632 case LEC_BIT1_ERROR: 633 netdev_dbg(dev, "bit1 error\n"); 634 cf->data[2] |= CAN_ERR_PROT_BIT1; 635 break; 636 case LEC_BIT0_ERROR: 637 netdev_dbg(dev, "bit0 error\n"); 638 cf->data[2] |= CAN_ERR_PROT_BIT0; 639 break; 640 case LEC_CRC_ERROR: 641 netdev_dbg(dev, "CRC error\n"); 642 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 643 break; 644 default: 645 break; 646 } 647 648 stats->rx_packets++; 649 stats->rx_bytes += cf->len; 650 651 if (cdev->is_peripheral) 652 timestamp = m_can_get_timestamp(cdev); 653 654 m_can_receive_skb(cdev, skb, timestamp); 655 656 return 1; 657 } 658 659 static int __m_can_get_berr_counter(const struct net_device *dev, 660 struct can_berr_counter *bec) 661 { 662 struct m_can_classdev *cdev = netdev_priv(dev); 663 unsigned int ecr; 664 665 ecr = m_can_read(cdev, M_CAN_ECR); 666 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT; 667 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT; 668 669 return 0; 670 } 671 672 static int m_can_clk_start(struct m_can_classdev *cdev) 673 { 674 if (cdev->pm_clock_support == 0) 675 return 0; 676 677 return pm_runtime_resume_and_get(cdev->dev); 678 } 679 680 static void m_can_clk_stop(struct m_can_classdev *cdev) 681 { 682 if (cdev->pm_clock_support) 683 pm_runtime_put_sync(cdev->dev); 684 } 685 686 static int m_can_get_berr_counter(const struct net_device *dev, 687 struct can_berr_counter *bec) 688 { 689 struct m_can_classdev *cdev = netdev_priv(dev); 690 int err; 691 692 err = m_can_clk_start(cdev); 693 if (err) 694 return err; 695 696 __m_can_get_berr_counter(dev, bec); 697 698 m_can_clk_stop(cdev); 699 700 return 0; 701 } 702 703 static int m_can_handle_state_change(struct net_device *dev, 704 enum can_state new_state) 705 { 706 struct m_can_classdev *cdev = netdev_priv(dev); 707 struct net_device_stats *stats = &dev->stats; 708 struct can_frame *cf; 709 struct sk_buff *skb; 710 struct can_berr_counter bec; 711 unsigned int ecr; 712 u32 timestamp = 0; 713 714 switch (new_state) { 715 case CAN_STATE_ERROR_WARNING: 716 /* error warning state */ 717 cdev->can.can_stats.error_warning++; 718 cdev->can.state = CAN_STATE_ERROR_WARNING; 719 break; 720 case CAN_STATE_ERROR_PASSIVE: 721 /* error passive state */ 722 cdev->can.can_stats.error_passive++; 723 cdev->can.state = CAN_STATE_ERROR_PASSIVE; 724 break; 725 case CAN_STATE_BUS_OFF: 726 /* bus-off state */ 727 cdev->can.state = CAN_STATE_BUS_OFF; 728 m_can_disable_all_interrupts(cdev); 729 cdev->can.can_stats.bus_off++; 730 can_bus_off(dev); 731 break; 732 default: 733 break; 734 } 735 736 /* propagate the error condition to the CAN stack */ 737 skb = alloc_can_err_skb(dev, &cf); 738 if (unlikely(!skb)) 739 return 0; 740 741 __m_can_get_berr_counter(dev, &bec); 742 743 switch (new_state) { 744 case CAN_STATE_ERROR_WARNING: 745 /* error warning state */ 746 cf->can_id |= CAN_ERR_CRTL; 747 cf->data[1] = (bec.txerr > bec.rxerr) ? 748 CAN_ERR_CRTL_TX_WARNING : 749 CAN_ERR_CRTL_RX_WARNING; 750 cf->data[6] = bec.txerr; 751 cf->data[7] = bec.rxerr; 752 break; 753 case CAN_STATE_ERROR_PASSIVE: 754 /* error passive state */ 755 cf->can_id |= CAN_ERR_CRTL; 756 ecr = m_can_read(cdev, M_CAN_ECR); 757 if (ecr & ECR_RP) 758 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 759 if (bec.txerr > 127) 760 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 761 cf->data[6] = bec.txerr; 762 cf->data[7] = bec.rxerr; 763 break; 764 case CAN_STATE_BUS_OFF: 765 /* bus-off state */ 766 cf->can_id |= CAN_ERR_BUSOFF; 767 break; 768 default: 769 break; 770 } 771 772 stats->rx_packets++; 773 stats->rx_bytes += cf->len; 774 775 if (cdev->is_peripheral) 776 timestamp = m_can_get_timestamp(cdev); 777 778 m_can_receive_skb(cdev, skb, timestamp); 779 780 return 1; 781 } 782 783 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) 784 { 785 struct m_can_classdev *cdev = netdev_priv(dev); 786 int work_done = 0; 787 788 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { 789 netdev_dbg(dev, "entered error warning state\n"); 790 work_done += m_can_handle_state_change(dev, 791 CAN_STATE_ERROR_WARNING); 792 } 793 794 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { 795 netdev_dbg(dev, "entered error passive state\n"); 796 work_done += m_can_handle_state_change(dev, 797 CAN_STATE_ERROR_PASSIVE); 798 } 799 800 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { 801 netdev_dbg(dev, "entered error bus off state\n"); 802 work_done += m_can_handle_state_change(dev, 803 CAN_STATE_BUS_OFF); 804 } 805 806 return work_done; 807 } 808 809 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) 810 { 811 if (irqstatus & IR_WDI) 812 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); 813 if (irqstatus & IR_ELO) 814 netdev_err(dev, "Error Logging Overflow\n"); 815 if (irqstatus & IR_BEU) 816 netdev_err(dev, "Bit Error Uncorrected\n"); 817 if (irqstatus & IR_BEC) 818 netdev_err(dev, "Bit Error Corrected\n"); 819 if (irqstatus & IR_TOO) 820 netdev_err(dev, "Timeout reached\n"); 821 if (irqstatus & IR_MRAF) 822 netdev_err(dev, "Message RAM access failure occurred\n"); 823 } 824 825 static inline bool is_lec_err(u32 psr) 826 { 827 psr &= LEC_UNUSED; 828 829 return psr && (psr != LEC_UNUSED); 830 } 831 832 static inline bool m_can_is_protocol_err(u32 irqstatus) 833 { 834 return irqstatus & IR_ERR_LEC_31X; 835 } 836 837 static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus) 838 { 839 struct net_device_stats *stats = &dev->stats; 840 struct m_can_classdev *cdev = netdev_priv(dev); 841 struct can_frame *cf; 842 struct sk_buff *skb; 843 u32 timestamp = 0; 844 845 /* propagate the error condition to the CAN stack */ 846 skb = alloc_can_err_skb(dev, &cf); 847 848 /* update tx error stats since there is protocol error */ 849 stats->tx_errors++; 850 851 /* update arbitration lost status */ 852 if (cdev->version >= 31 && (irqstatus & IR_PEA)) { 853 netdev_dbg(dev, "Protocol error in Arbitration fail\n"); 854 cdev->can.can_stats.arbitration_lost++; 855 if (skb) { 856 cf->can_id |= CAN_ERR_LOSTARB; 857 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC; 858 } 859 } 860 861 if (unlikely(!skb)) { 862 netdev_dbg(dev, "allocation of skb failed\n"); 863 return 0; 864 } 865 866 if (cdev->is_peripheral) 867 timestamp = m_can_get_timestamp(cdev); 868 869 m_can_receive_skb(cdev, skb, timestamp); 870 871 return 1; 872 } 873 874 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, 875 u32 psr) 876 { 877 struct m_can_classdev *cdev = netdev_priv(dev); 878 int work_done = 0; 879 880 if (irqstatus & IR_RF0L) 881 work_done += m_can_handle_lost_msg(dev); 882 883 /* handle lec errors on the bus */ 884 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 885 is_lec_err(psr)) 886 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED); 887 888 /* handle protocol errors in arbitration phase */ 889 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 890 m_can_is_protocol_err(irqstatus)) 891 work_done += m_can_handle_protocol_error(dev, irqstatus); 892 893 /* other unproccessed error interrupts */ 894 m_can_handle_other_err(dev, irqstatus); 895 896 return work_done; 897 } 898 899 static int m_can_rx_handler(struct net_device *dev, int quota) 900 { 901 struct m_can_classdev *cdev = netdev_priv(dev); 902 int work_done = 0; 903 u32 irqstatus, psr; 904 905 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR); 906 if (!irqstatus) 907 goto end; 908 909 /* Errata workaround for issue "Needless activation of MRAF irq" 910 * During frame reception while the MCAN is in Error Passive state 911 * and the Receive Error Counter has the value MCAN_ECR.REC = 127, 912 * it may happen that MCAN_IR.MRAF is set although there was no 913 * Message RAM access failure. 914 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated 915 * The Message RAM Access Failure interrupt routine needs to check 916 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127. 917 * In this case, reset MCAN_IR.MRAF. No further action is required. 918 */ 919 if (cdev->version <= 31 && irqstatus & IR_MRAF && 920 m_can_read(cdev, M_CAN_ECR) & ECR_RP) { 921 struct can_berr_counter bec; 922 923 __m_can_get_berr_counter(dev, &bec); 924 if (bec.rxerr == 127) { 925 m_can_write(cdev, M_CAN_IR, IR_MRAF); 926 irqstatus &= ~IR_MRAF; 927 } 928 } 929 930 psr = m_can_read(cdev, M_CAN_PSR); 931 932 if (irqstatus & IR_ERR_STATE) 933 work_done += m_can_handle_state_errors(dev, psr); 934 935 if (irqstatus & IR_ERR_BUS_30X) 936 work_done += m_can_handle_bus_errors(dev, irqstatus, psr); 937 938 if (irqstatus & IR_RF0N) 939 work_done += m_can_do_rx_poll(dev, (quota - work_done)); 940 end: 941 return work_done; 942 } 943 944 static int m_can_rx_peripheral(struct net_device *dev) 945 { 946 struct m_can_classdev *cdev = netdev_priv(dev); 947 948 m_can_rx_handler(dev, M_CAN_NAPI_WEIGHT); 949 950 m_can_enable_all_interrupts(cdev); 951 952 return 0; 953 } 954 955 static int m_can_poll(struct napi_struct *napi, int quota) 956 { 957 struct net_device *dev = napi->dev; 958 struct m_can_classdev *cdev = netdev_priv(dev); 959 int work_done; 960 961 work_done = m_can_rx_handler(dev, quota); 962 if (work_done < quota) { 963 napi_complete_done(napi, work_done); 964 m_can_enable_all_interrupts(cdev); 965 } 966 967 return work_done; 968 } 969 970 /* Echo tx skb and update net stats. Peripherals use rx-offload for 971 * echo. timestamp is used for peripherals to ensure correct ordering 972 * by rx-offload, and is ignored for non-peripherals. 973 */ 974 static void m_can_tx_update_stats(struct m_can_classdev *cdev, 975 unsigned int msg_mark, 976 u32 timestamp) 977 { 978 struct net_device *dev = cdev->net; 979 struct net_device_stats *stats = &dev->stats; 980 981 if (cdev->is_peripheral) 982 stats->tx_bytes += 983 can_rx_offload_get_echo_skb(&cdev->offload, 984 msg_mark, 985 timestamp, 986 NULL); 987 else 988 stats->tx_bytes += can_get_echo_skb(dev, msg_mark, NULL); 989 990 stats->tx_packets++; 991 } 992 993 static void m_can_echo_tx_event(struct net_device *dev) 994 { 995 u32 txe_count = 0; 996 u32 m_can_txefs; 997 u32 fgi = 0; 998 int i = 0; 999 unsigned int msg_mark; 1000 1001 struct m_can_classdev *cdev = netdev_priv(dev); 1002 1003 /* read tx event fifo status */ 1004 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); 1005 1006 /* Get Tx Event fifo element count */ 1007 txe_count = (m_can_txefs & TXEFS_EFFL_MASK) >> TXEFS_EFFL_SHIFT; 1008 1009 /* Get and process all sent elements */ 1010 for (i = 0; i < txe_count; i++) { 1011 u32 txe, timestamp = 0; 1012 1013 /* retrieve get index */ 1014 fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK) >> 1015 TXEFS_EFGI_SHIFT; 1016 1017 /* get message marker, timestamp */ 1018 txe = m_can_txe_fifo_read(cdev, fgi, 4); 1019 msg_mark = (txe & TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT; 1020 timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe); 1021 1022 /* ack txe element */ 1023 m_can_write(cdev, M_CAN_TXEFA, (TXEFA_EFAI_MASK & 1024 (fgi << TXEFA_EFAI_SHIFT))); 1025 1026 /* update stats */ 1027 m_can_tx_update_stats(cdev, msg_mark, timestamp); 1028 } 1029 } 1030 1031 static irqreturn_t m_can_isr(int irq, void *dev_id) 1032 { 1033 struct net_device *dev = (struct net_device *)dev_id; 1034 struct m_can_classdev *cdev = netdev_priv(dev); 1035 u32 ir; 1036 1037 if (pm_runtime_suspended(cdev->dev)) 1038 return IRQ_NONE; 1039 ir = m_can_read(cdev, M_CAN_IR); 1040 if (!ir) 1041 return IRQ_NONE; 1042 1043 /* ACK all irqs */ 1044 if (ir & IR_ALL_INT) 1045 m_can_write(cdev, M_CAN_IR, ir); 1046 1047 if (cdev->ops->clear_interrupts) 1048 cdev->ops->clear_interrupts(cdev); 1049 1050 /* schedule NAPI in case of 1051 * - rx IRQ 1052 * - state change IRQ 1053 * - bus error IRQ and bus error reporting 1054 */ 1055 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) { 1056 cdev->irqstatus = ir; 1057 m_can_disable_all_interrupts(cdev); 1058 if (!cdev->is_peripheral) 1059 napi_schedule(&cdev->napi); 1060 else 1061 m_can_rx_peripheral(dev); 1062 } 1063 1064 if (cdev->version == 30) { 1065 if (ir & IR_TC) { 1066 /* Transmission Complete Interrupt*/ 1067 u32 timestamp = 0; 1068 1069 if (cdev->is_peripheral) 1070 timestamp = m_can_get_timestamp(cdev); 1071 m_can_tx_update_stats(cdev, 0, timestamp); 1072 1073 can_led_event(dev, CAN_LED_EVENT_TX); 1074 netif_wake_queue(dev); 1075 } 1076 } else { 1077 if (ir & IR_TEFN) { 1078 /* New TX FIFO Element arrived */ 1079 m_can_echo_tx_event(dev); 1080 can_led_event(dev, CAN_LED_EVENT_TX); 1081 if (netif_queue_stopped(dev) && 1082 !m_can_tx_fifo_full(cdev)) 1083 netif_wake_queue(dev); 1084 } 1085 } 1086 1087 return IRQ_HANDLED; 1088 } 1089 1090 static const struct can_bittiming_const m_can_bittiming_const_30X = { 1091 .name = KBUILD_MODNAME, 1092 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1093 .tseg1_max = 64, 1094 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1095 .tseg2_max = 16, 1096 .sjw_max = 16, 1097 .brp_min = 1, 1098 .brp_max = 1024, 1099 .brp_inc = 1, 1100 }; 1101 1102 static const struct can_bittiming_const m_can_data_bittiming_const_30X = { 1103 .name = KBUILD_MODNAME, 1104 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1105 .tseg1_max = 16, 1106 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1107 .tseg2_max = 8, 1108 .sjw_max = 4, 1109 .brp_min = 1, 1110 .brp_max = 32, 1111 .brp_inc = 1, 1112 }; 1113 1114 static const struct can_bittiming_const m_can_bittiming_const_31X = { 1115 .name = KBUILD_MODNAME, 1116 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1117 .tseg1_max = 256, 1118 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */ 1119 .tseg2_max = 128, 1120 .sjw_max = 128, 1121 .brp_min = 1, 1122 .brp_max = 512, 1123 .brp_inc = 1, 1124 }; 1125 1126 static const struct can_bittiming_const m_can_data_bittiming_const_31X = { 1127 .name = KBUILD_MODNAME, 1128 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */ 1129 .tseg1_max = 32, 1130 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1131 .tseg2_max = 16, 1132 .sjw_max = 16, 1133 .brp_min = 1, 1134 .brp_max = 32, 1135 .brp_inc = 1, 1136 }; 1137 1138 static int m_can_set_bittiming(struct net_device *dev) 1139 { 1140 struct m_can_classdev *cdev = netdev_priv(dev); 1141 const struct can_bittiming *bt = &cdev->can.bittiming; 1142 const struct can_bittiming *dbt = &cdev->can.data_bittiming; 1143 u16 brp, sjw, tseg1, tseg2; 1144 u32 reg_btp; 1145 1146 brp = bt->brp - 1; 1147 sjw = bt->sjw - 1; 1148 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 1149 tseg2 = bt->phase_seg2 - 1; 1150 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) | 1151 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT); 1152 m_can_write(cdev, M_CAN_NBTP, reg_btp); 1153 1154 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1155 reg_btp = 0; 1156 brp = dbt->brp - 1; 1157 sjw = dbt->sjw - 1; 1158 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; 1159 tseg2 = dbt->phase_seg2 - 1; 1160 1161 /* TDC is only needed for bitrates beyond 2.5 MBit/s. 1162 * This is mentioned in the "Bit Time Requirements for CAN FD" 1163 * paper presented at the International CAN Conference 2013 1164 */ 1165 if (dbt->bitrate > 2500000) { 1166 u32 tdco, ssp; 1167 1168 /* Use the same value of secondary sampling point 1169 * as the data sampling point 1170 */ 1171 ssp = dbt->sample_point; 1172 1173 /* Equation based on Bosch's M_CAN User Manual's 1174 * Transmitter Delay Compensation Section 1175 */ 1176 tdco = (cdev->can.clock.freq / 1000) * 1177 ssp / dbt->bitrate; 1178 1179 /* Max valid TDCO value is 127 */ 1180 if (tdco > 127) { 1181 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n", 1182 tdco); 1183 tdco = 127; 1184 } 1185 1186 reg_btp |= DBTP_TDC; 1187 m_can_write(cdev, M_CAN_TDCR, 1188 tdco << TDCR_TDCO_SHIFT); 1189 } 1190 1191 reg_btp |= (brp << DBTP_DBRP_SHIFT) | 1192 (sjw << DBTP_DSJW_SHIFT) | 1193 (tseg1 << DBTP_DTSEG1_SHIFT) | 1194 (tseg2 << DBTP_DTSEG2_SHIFT); 1195 1196 m_can_write(cdev, M_CAN_DBTP, reg_btp); 1197 } 1198 1199 return 0; 1200 } 1201 1202 /* Configure M_CAN chip: 1203 * - set rx buffer/fifo element size 1204 * - configure rx fifo 1205 * - accept non-matching frame into fifo 0 1206 * - configure tx buffer 1207 * - >= v3.1.x: TX FIFO is used 1208 * - configure mode 1209 * - setup bittiming 1210 * - configure timestamp generation 1211 */ 1212 static void m_can_chip_config(struct net_device *dev) 1213 { 1214 struct m_can_classdev *cdev = netdev_priv(dev); 1215 u32 cccr, test; 1216 1217 m_can_config_endisable(cdev, true); 1218 1219 /* RX Buffer/FIFO Element Size 64 bytes data field */ 1220 m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES); 1221 1222 /* Accept Non-matching Frames Into FIFO 0 */ 1223 m_can_write(cdev, M_CAN_GFC, 0x0); 1224 1225 if (cdev->version == 30) { 1226 /* only support one Tx Buffer currently */ 1227 m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) | 1228 cdev->mcfg[MRAM_TXB].off); 1229 } else { 1230 /* TX FIFO is used for newer IP Core versions */ 1231 m_can_write(cdev, M_CAN_TXBC, 1232 (cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) | 1233 (cdev->mcfg[MRAM_TXB].off)); 1234 } 1235 1236 /* support 64 bytes payload */ 1237 m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES); 1238 1239 /* TX Event FIFO */ 1240 if (cdev->version == 30) { 1241 m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) | 1242 cdev->mcfg[MRAM_TXE].off); 1243 } else { 1244 /* Full TX Event FIFO is used */ 1245 m_can_write(cdev, M_CAN_TXEFC, 1246 ((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT) 1247 & TXEFC_EFS_MASK) | 1248 cdev->mcfg[MRAM_TXE].off); 1249 } 1250 1251 /* rx fifo configuration, blocking mode, fifo size 1 */ 1252 m_can_write(cdev, M_CAN_RXF0C, 1253 (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) | 1254 cdev->mcfg[MRAM_RXF0].off); 1255 1256 m_can_write(cdev, M_CAN_RXF1C, 1257 (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) | 1258 cdev->mcfg[MRAM_RXF1].off); 1259 1260 cccr = m_can_read(cdev, M_CAN_CCCR); 1261 test = m_can_read(cdev, M_CAN_TEST); 1262 test &= ~TEST_LBCK; 1263 if (cdev->version == 30) { 1264 /* Version 3.0.x */ 1265 1266 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR | 1267 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | 1268 (CCCR_CME_MASK << CCCR_CME_SHIFT)); 1269 1270 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1271 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT; 1272 1273 } else { 1274 /* Version 3.1.x or 3.2.x */ 1275 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE | 1276 CCCR_NISO | CCCR_DAR); 1277 1278 /* Only 3.2.x has NISO Bit implemented */ 1279 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 1280 cccr |= CCCR_NISO; 1281 1282 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1283 cccr |= (CCCR_BRSE | CCCR_FDOE); 1284 } 1285 1286 /* Loopback Mode */ 1287 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1288 cccr |= CCCR_TEST | CCCR_MON; 1289 test |= TEST_LBCK; 1290 } 1291 1292 /* Enable Monitoring (all versions) */ 1293 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1294 cccr |= CCCR_MON; 1295 1296 /* Disable Auto Retransmission (all versions) */ 1297 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 1298 cccr |= CCCR_DAR; 1299 1300 /* Write config */ 1301 m_can_write(cdev, M_CAN_CCCR, cccr); 1302 m_can_write(cdev, M_CAN_TEST, test); 1303 1304 /* Enable interrupts */ 1305 m_can_write(cdev, M_CAN_IR, IR_ALL_INT); 1306 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1307 if (cdev->version == 30) 1308 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & 1309 ~(IR_ERR_LEC_30X)); 1310 else 1311 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & 1312 ~(IR_ERR_LEC_31X)); 1313 else 1314 m_can_write(cdev, M_CAN_IE, IR_ALL_INT); 1315 1316 /* route all interrupts to INT0 */ 1317 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); 1318 1319 /* set bittiming params */ 1320 m_can_set_bittiming(dev); 1321 1322 /* enable internal timestamp generation, with a prescalar of 16. The 1323 * prescalar is applied to the nominal bit timing */ 1324 m_can_write(cdev, M_CAN_TSCC, FIELD_PREP(TSCC_TCP_MASK, 0xf)); 1325 1326 m_can_config_endisable(cdev, false); 1327 1328 if (cdev->ops->init) 1329 cdev->ops->init(cdev); 1330 } 1331 1332 static void m_can_start(struct net_device *dev) 1333 { 1334 struct m_can_classdev *cdev = netdev_priv(dev); 1335 1336 /* basic m_can configuration */ 1337 m_can_chip_config(dev); 1338 1339 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 1340 1341 m_can_enable_all_interrupts(cdev); 1342 } 1343 1344 static int m_can_set_mode(struct net_device *dev, enum can_mode mode) 1345 { 1346 switch (mode) { 1347 case CAN_MODE_START: 1348 m_can_clean(dev); 1349 m_can_start(dev); 1350 netif_wake_queue(dev); 1351 break; 1352 default: 1353 return -EOPNOTSUPP; 1354 } 1355 1356 return 0; 1357 } 1358 1359 /* Checks core release number of M_CAN 1360 * returns 0 if an unsupported device is detected 1361 * else it returns the release and step coded as: 1362 * return value = 10 * <release> + 1 * <step> 1363 */ 1364 static int m_can_check_core_release(struct m_can_classdev *cdev) 1365 { 1366 u32 crel_reg; 1367 u8 rel; 1368 u8 step; 1369 int res; 1370 1371 /* Read Core Release Version and split into version number 1372 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; 1373 */ 1374 crel_reg = m_can_read(cdev, M_CAN_CREL); 1375 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT); 1376 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT); 1377 1378 if (rel == 3) { 1379 /* M_CAN v3.x.y: create return value */ 1380 res = 30 + step; 1381 } else { 1382 /* Unsupported M_CAN version */ 1383 res = 0; 1384 } 1385 1386 return res; 1387 } 1388 1389 /* Selectable Non ISO support only in version 3.2.x 1390 * This function checks if the bit is writable. 1391 */ 1392 static bool m_can_niso_supported(struct m_can_classdev *cdev) 1393 { 1394 u32 cccr_reg, cccr_poll = 0; 1395 int niso_timeout = -ETIMEDOUT; 1396 int i; 1397 1398 m_can_config_endisable(cdev, true); 1399 cccr_reg = m_can_read(cdev, M_CAN_CCCR); 1400 cccr_reg |= CCCR_NISO; 1401 m_can_write(cdev, M_CAN_CCCR, cccr_reg); 1402 1403 for (i = 0; i <= 10; i++) { 1404 cccr_poll = m_can_read(cdev, M_CAN_CCCR); 1405 if (cccr_poll == cccr_reg) { 1406 niso_timeout = 0; 1407 break; 1408 } 1409 1410 usleep_range(1, 5); 1411 } 1412 1413 /* Clear NISO */ 1414 cccr_reg &= ~(CCCR_NISO); 1415 m_can_write(cdev, M_CAN_CCCR, cccr_reg); 1416 1417 m_can_config_endisable(cdev, false); 1418 1419 /* return false if time out (-ETIMEDOUT), else return true */ 1420 return !niso_timeout; 1421 } 1422 1423 static int m_can_dev_setup(struct m_can_classdev *cdev) 1424 { 1425 struct net_device *dev = cdev->net; 1426 int m_can_version; 1427 1428 m_can_version = m_can_check_core_release(cdev); 1429 /* return if unsupported version */ 1430 if (!m_can_version) { 1431 dev_err(cdev->dev, "Unsupported version number: %2d", 1432 m_can_version); 1433 return -EINVAL; 1434 } 1435 1436 if (!cdev->is_peripheral) 1437 netif_napi_add(dev, &cdev->napi, 1438 m_can_poll, M_CAN_NAPI_WEIGHT); 1439 1440 /* Shared properties of all M_CAN versions */ 1441 cdev->version = m_can_version; 1442 cdev->can.do_set_mode = m_can_set_mode; 1443 cdev->can.do_get_berr_counter = m_can_get_berr_counter; 1444 1445 /* Set M_CAN supported operations */ 1446 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1447 CAN_CTRLMODE_LISTENONLY | 1448 CAN_CTRLMODE_BERR_REPORTING | 1449 CAN_CTRLMODE_FD | 1450 CAN_CTRLMODE_ONE_SHOT; 1451 1452 /* Set properties depending on M_CAN version */ 1453 switch (cdev->version) { 1454 case 30: 1455 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ 1456 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1457 cdev->can.bittiming_const = cdev->bit_timing ? 1458 cdev->bit_timing : &m_can_bittiming_const_30X; 1459 1460 cdev->can.data_bittiming_const = cdev->data_timing ? 1461 cdev->data_timing : 1462 &m_can_data_bittiming_const_30X; 1463 break; 1464 case 31: 1465 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ 1466 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1467 cdev->can.bittiming_const = cdev->bit_timing ? 1468 cdev->bit_timing : &m_can_bittiming_const_31X; 1469 1470 cdev->can.data_bittiming_const = cdev->data_timing ? 1471 cdev->data_timing : 1472 &m_can_data_bittiming_const_31X; 1473 break; 1474 case 32: 1475 case 33: 1476 /* Support both MCAN version v3.2.x and v3.3.0 */ 1477 cdev->can.bittiming_const = cdev->bit_timing ? 1478 cdev->bit_timing : &m_can_bittiming_const_31X; 1479 1480 cdev->can.data_bittiming_const = cdev->data_timing ? 1481 cdev->data_timing : 1482 &m_can_data_bittiming_const_31X; 1483 1484 cdev->can.ctrlmode_supported |= 1485 (m_can_niso_supported(cdev) ? 1486 CAN_CTRLMODE_FD_NON_ISO : 0); 1487 break; 1488 default: 1489 dev_err(cdev->dev, "Unsupported version number: %2d", 1490 cdev->version); 1491 return -EINVAL; 1492 } 1493 1494 if (cdev->ops->init) 1495 cdev->ops->init(cdev); 1496 1497 return 0; 1498 } 1499 1500 static void m_can_stop(struct net_device *dev) 1501 { 1502 struct m_can_classdev *cdev = netdev_priv(dev); 1503 1504 /* disable all interrupts */ 1505 m_can_disable_all_interrupts(cdev); 1506 1507 /* Set init mode to disengage from the network */ 1508 m_can_config_endisable(cdev, true); 1509 1510 /* set the state as STOPPED */ 1511 cdev->can.state = CAN_STATE_STOPPED; 1512 } 1513 1514 static int m_can_close(struct net_device *dev) 1515 { 1516 struct m_can_classdev *cdev = netdev_priv(dev); 1517 1518 netif_stop_queue(dev); 1519 1520 if (!cdev->is_peripheral) 1521 napi_disable(&cdev->napi); 1522 1523 m_can_stop(dev); 1524 m_can_clk_stop(cdev); 1525 free_irq(dev->irq, dev); 1526 1527 if (cdev->is_peripheral) { 1528 cdev->tx_skb = NULL; 1529 destroy_workqueue(cdev->tx_wq); 1530 cdev->tx_wq = NULL; 1531 } 1532 1533 if (cdev->is_peripheral) 1534 can_rx_offload_disable(&cdev->offload); 1535 1536 close_candev(dev); 1537 can_led_event(dev, CAN_LED_EVENT_STOP); 1538 1539 return 0; 1540 } 1541 1542 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx) 1543 { 1544 struct m_can_classdev *cdev = netdev_priv(dev); 1545 /*get wrap around for loopback skb index */ 1546 unsigned int wrap = cdev->can.echo_skb_max; 1547 int next_idx; 1548 1549 /* calculate next index */ 1550 next_idx = (++putidx >= wrap ? 0 : putidx); 1551 1552 /* check if occupied */ 1553 return !!cdev->can.echo_skb[next_idx]; 1554 } 1555 1556 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) 1557 { 1558 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data; 1559 struct net_device *dev = cdev->net; 1560 struct sk_buff *skb = cdev->tx_skb; 1561 u32 id, cccr, fdflags; 1562 int i; 1563 int putidx; 1564 1565 cdev->tx_skb = NULL; 1566 1567 /* Generate ID field for TX buffer Element */ 1568 /* Common to all supported M_CAN versions */ 1569 if (cf->can_id & CAN_EFF_FLAG) { 1570 id = cf->can_id & CAN_EFF_MASK; 1571 id |= TX_BUF_XTD; 1572 } else { 1573 id = ((cf->can_id & CAN_SFF_MASK) << 18); 1574 } 1575 1576 if (cf->can_id & CAN_RTR_FLAG) 1577 id |= TX_BUF_RTR; 1578 1579 if (cdev->version == 30) { 1580 netif_stop_queue(dev); 1581 1582 /* message ram configuration */ 1583 m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, id); 1584 m_can_fifo_write(cdev, 0, M_CAN_FIFO_DLC, 1585 can_fd_len2dlc(cf->len) << 16); 1586 1587 for (i = 0; i < cf->len; i += 4) 1588 m_can_fifo_write(cdev, 0, 1589 M_CAN_FIFO_DATA(i / 4), 1590 *(u32 *)(cf->data + i)); 1591 1592 can_put_echo_skb(skb, dev, 0, 0); 1593 1594 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1595 cccr = m_can_read(cdev, M_CAN_CCCR); 1596 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT); 1597 if (can_is_canfd_skb(skb)) { 1598 if (cf->flags & CANFD_BRS) 1599 cccr |= CCCR_CMR_CANFD_BRS << 1600 CCCR_CMR_SHIFT; 1601 else 1602 cccr |= CCCR_CMR_CANFD << 1603 CCCR_CMR_SHIFT; 1604 } else { 1605 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT; 1606 } 1607 m_can_write(cdev, M_CAN_CCCR, cccr); 1608 } 1609 m_can_write(cdev, M_CAN_TXBTIE, 0x1); 1610 m_can_write(cdev, M_CAN_TXBAR, 0x1); 1611 /* End of xmit function for version 3.0.x */ 1612 } else { 1613 /* Transmit routine for version >= v3.1.x */ 1614 1615 /* Check if FIFO full */ 1616 if (m_can_tx_fifo_full(cdev)) { 1617 /* This shouldn't happen */ 1618 netif_stop_queue(dev); 1619 netdev_warn(dev, 1620 "TX queue active although FIFO is full."); 1621 1622 if (cdev->is_peripheral) { 1623 kfree_skb(skb); 1624 dev->stats.tx_dropped++; 1625 return NETDEV_TX_OK; 1626 } else { 1627 return NETDEV_TX_BUSY; 1628 } 1629 } 1630 1631 /* get put index for frame */ 1632 putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK) 1633 >> TXFQS_TFQPI_SHIFT); 1634 /* Write ID Field to FIFO Element */ 1635 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id); 1636 1637 /* get CAN FD configuration of frame */ 1638 fdflags = 0; 1639 if (can_is_canfd_skb(skb)) { 1640 fdflags |= TX_BUF_FDF; 1641 if (cf->flags & CANFD_BRS) 1642 fdflags |= TX_BUF_BRS; 1643 } 1644 1645 /* Construct DLC Field. Also contains CAN-FD configuration 1646 * use put index of fifo as message marker 1647 * it is used in TX interrupt for 1648 * sending the correct echo frame 1649 */ 1650 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC, 1651 ((putidx << TX_BUF_MM_SHIFT) & 1652 TX_BUF_MM_MASK) | 1653 (can_fd_len2dlc(cf->len) << 16) | 1654 fdflags | TX_BUF_EFC); 1655 1656 for (i = 0; i < cf->len; i += 4) 1657 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA(i / 4), 1658 *(u32 *)(cf->data + i)); 1659 1660 /* Push loopback echo. 1661 * Will be looped back on TX interrupt based on message marker 1662 */ 1663 can_put_echo_skb(skb, dev, putidx, 0); 1664 1665 /* Enable TX FIFO element to start transfer */ 1666 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx)); 1667 1668 /* stop network queue if fifo full */ 1669 if (m_can_tx_fifo_full(cdev) || 1670 m_can_next_echo_skb_occupied(dev, putidx)) 1671 netif_stop_queue(dev); 1672 } 1673 1674 return NETDEV_TX_OK; 1675 } 1676 1677 static void m_can_tx_work_queue(struct work_struct *ws) 1678 { 1679 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev, 1680 tx_work); 1681 1682 m_can_tx_handler(cdev); 1683 } 1684 1685 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, 1686 struct net_device *dev) 1687 { 1688 struct m_can_classdev *cdev = netdev_priv(dev); 1689 1690 if (can_dropped_invalid_skb(dev, skb)) 1691 return NETDEV_TX_OK; 1692 1693 if (cdev->is_peripheral) { 1694 if (cdev->tx_skb) { 1695 netdev_err(dev, "hard_xmit called while tx busy\n"); 1696 return NETDEV_TX_BUSY; 1697 } 1698 1699 if (cdev->can.state == CAN_STATE_BUS_OFF) { 1700 m_can_clean(dev); 1701 } else { 1702 /* Need to stop the queue to avoid numerous requests 1703 * from being sent. Suggested improvement is to create 1704 * a queueing mechanism that will queue the skbs and 1705 * process them in order. 1706 */ 1707 cdev->tx_skb = skb; 1708 netif_stop_queue(cdev->net); 1709 queue_work(cdev->tx_wq, &cdev->tx_work); 1710 } 1711 } else { 1712 cdev->tx_skb = skb; 1713 return m_can_tx_handler(cdev); 1714 } 1715 1716 return NETDEV_TX_OK; 1717 } 1718 1719 static int m_can_open(struct net_device *dev) 1720 { 1721 struct m_can_classdev *cdev = netdev_priv(dev); 1722 int err; 1723 1724 err = m_can_clk_start(cdev); 1725 if (err) 1726 return err; 1727 1728 /* open the can device */ 1729 err = open_candev(dev); 1730 if (err) { 1731 netdev_err(dev, "failed to open can device\n"); 1732 goto exit_disable_clks; 1733 } 1734 1735 if (cdev->is_peripheral) 1736 can_rx_offload_enable(&cdev->offload); 1737 1738 /* register interrupt handler */ 1739 if (cdev->is_peripheral) { 1740 cdev->tx_skb = NULL; 1741 cdev->tx_wq = alloc_workqueue("mcan_wq", 1742 WQ_FREEZABLE | WQ_MEM_RECLAIM, 0); 1743 if (!cdev->tx_wq) { 1744 err = -ENOMEM; 1745 goto out_wq_fail; 1746 } 1747 1748 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue); 1749 1750 err = request_threaded_irq(dev->irq, NULL, m_can_isr, 1751 IRQF_ONESHOT, 1752 dev->name, dev); 1753 } else { 1754 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, 1755 dev); 1756 } 1757 1758 if (err < 0) { 1759 netdev_err(dev, "failed to request interrupt\n"); 1760 goto exit_irq_fail; 1761 } 1762 1763 /* start the m_can controller */ 1764 m_can_start(dev); 1765 1766 can_led_event(dev, CAN_LED_EVENT_OPEN); 1767 1768 if (!cdev->is_peripheral) 1769 napi_enable(&cdev->napi); 1770 1771 netif_start_queue(dev); 1772 1773 return 0; 1774 1775 exit_irq_fail: 1776 if (cdev->is_peripheral) 1777 destroy_workqueue(cdev->tx_wq); 1778 out_wq_fail: 1779 if (cdev->is_peripheral) 1780 can_rx_offload_disable(&cdev->offload); 1781 close_candev(dev); 1782 exit_disable_clks: 1783 m_can_clk_stop(cdev); 1784 return err; 1785 } 1786 1787 static const struct net_device_ops m_can_netdev_ops = { 1788 .ndo_open = m_can_open, 1789 .ndo_stop = m_can_close, 1790 .ndo_start_xmit = m_can_start_xmit, 1791 .ndo_change_mtu = can_change_mtu, 1792 }; 1793 1794 static int register_m_can_dev(struct net_device *dev) 1795 { 1796 dev->flags |= IFF_ECHO; /* we support local echo */ 1797 dev->netdev_ops = &m_can_netdev_ops; 1798 1799 return register_candev(dev); 1800 } 1801 1802 static void m_can_of_parse_mram(struct m_can_classdev *cdev, 1803 const u32 *mram_config_vals) 1804 { 1805 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; 1806 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; 1807 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + 1808 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; 1809 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; 1810 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + 1811 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; 1812 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & 1813 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1814 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + 1815 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; 1816 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & 1817 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1818 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + 1819 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; 1820 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; 1821 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + 1822 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; 1823 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; 1824 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + 1825 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; 1826 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & 1827 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT); 1828 1829 dev_dbg(cdev->dev, 1830 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", 1831 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num, 1832 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num, 1833 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num, 1834 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num, 1835 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num, 1836 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num, 1837 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num); 1838 } 1839 1840 void m_can_init_ram(struct m_can_classdev *cdev) 1841 { 1842 int end, i, start; 1843 1844 /* initialize the entire Message RAM in use to avoid possible 1845 * ECC/parity checksum errors when reading an uninitialized buffer 1846 */ 1847 start = cdev->mcfg[MRAM_SIDF].off; 1848 end = cdev->mcfg[MRAM_TXB].off + 1849 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 1850 1851 for (i = start; i < end; i += 4) 1852 m_can_fifo_write_no_off(cdev, i, 0x0); 1853 } 1854 EXPORT_SYMBOL_GPL(m_can_init_ram); 1855 1856 int m_can_class_get_clocks(struct m_can_classdev *cdev) 1857 { 1858 int ret = 0; 1859 1860 cdev->hclk = devm_clk_get(cdev->dev, "hclk"); 1861 cdev->cclk = devm_clk_get(cdev->dev, "cclk"); 1862 1863 if (IS_ERR(cdev->cclk)) { 1864 dev_err(cdev->dev, "no clock found\n"); 1865 ret = -ENODEV; 1866 } 1867 1868 return ret; 1869 } 1870 EXPORT_SYMBOL_GPL(m_can_class_get_clocks); 1871 1872 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, 1873 int sizeof_priv) 1874 { 1875 struct m_can_classdev *class_dev = NULL; 1876 u32 mram_config_vals[MRAM_CFG_LEN]; 1877 struct net_device *net_dev; 1878 u32 tx_fifo_size; 1879 int ret; 1880 1881 ret = fwnode_property_read_u32_array(dev_fwnode(dev), 1882 "bosch,mram-cfg", 1883 mram_config_vals, 1884 sizeof(mram_config_vals) / 4); 1885 if (ret) { 1886 dev_err(dev, "Could not get Message RAM configuration."); 1887 goto out; 1888 } 1889 1890 /* Get TX FIFO size 1891 * Defines the total amount of echo buffers for loopback 1892 */ 1893 tx_fifo_size = mram_config_vals[7]; 1894 1895 /* allocate the m_can device */ 1896 net_dev = alloc_candev(sizeof_priv, tx_fifo_size); 1897 if (!net_dev) { 1898 dev_err(dev, "Failed to allocate CAN device"); 1899 goto out; 1900 } 1901 1902 class_dev = netdev_priv(net_dev); 1903 class_dev->net = net_dev; 1904 class_dev->dev = dev; 1905 SET_NETDEV_DEV(net_dev, dev); 1906 1907 m_can_of_parse_mram(class_dev, mram_config_vals); 1908 out: 1909 return class_dev; 1910 } 1911 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev); 1912 1913 void m_can_class_free_dev(struct net_device *net) 1914 { 1915 free_candev(net); 1916 } 1917 EXPORT_SYMBOL_GPL(m_can_class_free_dev); 1918 1919 int m_can_class_register(struct m_can_classdev *cdev) 1920 { 1921 int ret; 1922 1923 if (cdev->pm_clock_support) { 1924 ret = m_can_clk_start(cdev); 1925 if (ret) 1926 return ret; 1927 } 1928 1929 if (cdev->is_peripheral) { 1930 ret = can_rx_offload_add_manual(cdev->net, &cdev->offload, 1931 M_CAN_NAPI_WEIGHT); 1932 if (ret) 1933 goto clk_disable; 1934 } 1935 1936 ret = m_can_dev_setup(cdev); 1937 if (ret) 1938 goto rx_offload_del; 1939 1940 ret = register_m_can_dev(cdev->net); 1941 if (ret) { 1942 dev_err(cdev->dev, "registering %s failed (err=%d)\n", 1943 cdev->net->name, ret); 1944 goto rx_offload_del; 1945 } 1946 1947 devm_can_led_init(cdev->net); 1948 1949 of_can_transceiver(cdev->net); 1950 1951 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n", 1952 KBUILD_MODNAME, cdev->net->irq, cdev->version); 1953 1954 /* Probe finished 1955 * Stop clocks. They will be reactivated once the M_CAN device is opened 1956 */ 1957 m_can_clk_stop(cdev); 1958 1959 return 0; 1960 1961 rx_offload_del: 1962 if (cdev->is_peripheral) 1963 can_rx_offload_del(&cdev->offload); 1964 clk_disable: 1965 m_can_clk_stop(cdev); 1966 1967 return ret; 1968 } 1969 EXPORT_SYMBOL_GPL(m_can_class_register); 1970 1971 void m_can_class_unregister(struct m_can_classdev *cdev) 1972 { 1973 if (cdev->is_peripheral) 1974 can_rx_offload_del(&cdev->offload); 1975 unregister_candev(cdev->net); 1976 } 1977 EXPORT_SYMBOL_GPL(m_can_class_unregister); 1978 1979 int m_can_class_suspend(struct device *dev) 1980 { 1981 struct m_can_classdev *cdev = dev_get_drvdata(dev); 1982 struct net_device *ndev = cdev->net; 1983 1984 if (netif_running(ndev)) { 1985 netif_stop_queue(ndev); 1986 netif_device_detach(ndev); 1987 m_can_stop(ndev); 1988 m_can_clk_stop(cdev); 1989 } 1990 1991 pinctrl_pm_select_sleep_state(dev); 1992 1993 cdev->can.state = CAN_STATE_SLEEPING; 1994 1995 return 0; 1996 } 1997 EXPORT_SYMBOL_GPL(m_can_class_suspend); 1998 1999 int m_can_class_resume(struct device *dev) 2000 { 2001 struct m_can_classdev *cdev = dev_get_drvdata(dev); 2002 struct net_device *ndev = cdev->net; 2003 2004 pinctrl_pm_select_default_state(dev); 2005 2006 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 2007 2008 if (netif_running(ndev)) { 2009 int ret; 2010 2011 ret = m_can_clk_start(cdev); 2012 if (ret) 2013 return ret; 2014 2015 m_can_init_ram(cdev); 2016 m_can_start(ndev); 2017 netif_device_attach(ndev); 2018 netif_start_queue(ndev); 2019 } 2020 2021 return 0; 2022 } 2023 EXPORT_SYMBOL_GPL(m_can_class_resume); 2024 2025 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); 2026 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 2027 MODULE_LICENSE("GPL v2"); 2028 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); 2029