1 // SPDX-License-Identifier: GPL-2.0 2 // CAN bus driver for Bosch M_CAN controller 3 // Copyright (C) 2014 Freescale Semiconductor, Inc. 4 // Dong Aisheng <b29396@freescale.com> 5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/ 6 7 /* Bosch M_CAN user manual can be obtained from: 8 * https://github.com/linux-can/can-doc/tree/master/m_can 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/iopoll.h> 21 #include <linux/can/dev.h> 22 #include <linux/pinctrl/consumer.h> 23 24 #include "m_can.h" 25 26 /* registers definition */ 27 enum m_can_reg { 28 M_CAN_CREL = 0x0, 29 M_CAN_ENDN = 0x4, 30 M_CAN_CUST = 0x8, 31 M_CAN_DBTP = 0xc, 32 M_CAN_TEST = 0x10, 33 M_CAN_RWD = 0x14, 34 M_CAN_CCCR = 0x18, 35 M_CAN_NBTP = 0x1c, 36 M_CAN_TSCC = 0x20, 37 M_CAN_TSCV = 0x24, 38 M_CAN_TOCC = 0x28, 39 M_CAN_TOCV = 0x2c, 40 M_CAN_ECR = 0x40, 41 M_CAN_PSR = 0x44, 42 /* TDCR Register only available for version >=3.1.x */ 43 M_CAN_TDCR = 0x48, 44 M_CAN_IR = 0x50, 45 M_CAN_IE = 0x54, 46 M_CAN_ILS = 0x58, 47 M_CAN_ILE = 0x5c, 48 M_CAN_GFC = 0x80, 49 M_CAN_SIDFC = 0x84, 50 M_CAN_XIDFC = 0x88, 51 M_CAN_XIDAM = 0x90, 52 M_CAN_HPMS = 0x94, 53 M_CAN_NDAT1 = 0x98, 54 M_CAN_NDAT2 = 0x9c, 55 M_CAN_RXF0C = 0xa0, 56 M_CAN_RXF0S = 0xa4, 57 M_CAN_RXF0A = 0xa8, 58 M_CAN_RXBC = 0xac, 59 M_CAN_RXF1C = 0xb0, 60 M_CAN_RXF1S = 0xb4, 61 M_CAN_RXF1A = 0xb8, 62 M_CAN_RXESC = 0xbc, 63 M_CAN_TXBC = 0xc0, 64 M_CAN_TXFQS = 0xc4, 65 M_CAN_TXESC = 0xc8, 66 M_CAN_TXBRP = 0xcc, 67 M_CAN_TXBAR = 0xd0, 68 M_CAN_TXBCR = 0xd4, 69 M_CAN_TXBTO = 0xd8, 70 M_CAN_TXBCF = 0xdc, 71 M_CAN_TXBTIE = 0xe0, 72 M_CAN_TXBCIE = 0xe4, 73 M_CAN_TXEFC = 0xf0, 74 M_CAN_TXEFS = 0xf4, 75 M_CAN_TXEFA = 0xf8, 76 }; 77 78 /* napi related */ 79 #define M_CAN_NAPI_WEIGHT 64 80 81 /* message ram configuration data length */ 82 #define MRAM_CFG_LEN 8 83 84 /* Core Release Register (CREL) */ 85 #define CREL_REL_SHIFT 28 86 #define CREL_REL_MASK (0xF << CREL_REL_SHIFT) 87 #define CREL_STEP_SHIFT 24 88 #define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT) 89 #define CREL_SUBSTEP_SHIFT 20 90 #define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT) 91 92 /* Data Bit Timing & Prescaler Register (DBTP) */ 93 #define DBTP_TDC BIT(23) 94 #define DBTP_DBRP_SHIFT 16 95 #define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT) 96 #define DBTP_DTSEG1_SHIFT 8 97 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT) 98 #define DBTP_DTSEG2_SHIFT 4 99 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT) 100 #define DBTP_DSJW_SHIFT 0 101 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT) 102 103 /* Transmitter Delay Compensation Register (TDCR) */ 104 #define TDCR_TDCO_SHIFT 8 105 #define TDCR_TDCO_MASK (0x7F << TDCR_TDCO_SHIFT) 106 #define TDCR_TDCF_SHIFT 0 107 #define TDCR_TDCF_MASK (0x7F << TDCR_TDCF_SHIFT) 108 109 /* Test Register (TEST) */ 110 #define TEST_LBCK BIT(4) 111 112 /* CC Control Register(CCCR) */ 113 #define CCCR_CMR_MASK 0x3 114 #define CCCR_CMR_SHIFT 10 115 #define CCCR_CMR_CANFD 0x1 116 #define CCCR_CMR_CANFD_BRS 0x2 117 #define CCCR_CMR_CAN 0x3 118 #define CCCR_CME_MASK 0x3 119 #define CCCR_CME_SHIFT 8 120 #define CCCR_CME_CAN 0 121 #define CCCR_CME_CANFD 0x1 122 #define CCCR_CME_CANFD_BRS 0x2 123 #define CCCR_TXP BIT(14) 124 #define CCCR_TEST BIT(7) 125 #define CCCR_DAR BIT(6) 126 #define CCCR_MON BIT(5) 127 #define CCCR_CSR BIT(4) 128 #define CCCR_CSA BIT(3) 129 #define CCCR_ASM BIT(2) 130 #define CCCR_CCE BIT(1) 131 #define CCCR_INIT BIT(0) 132 #define CCCR_CANFD 0x10 133 /* for version >=3.1.x */ 134 #define CCCR_EFBI BIT(13) 135 #define CCCR_PXHD BIT(12) 136 #define CCCR_BRSE BIT(9) 137 #define CCCR_FDOE BIT(8) 138 /* only for version >=3.2.x */ 139 #define CCCR_NISO BIT(15) 140 141 /* Nominal Bit Timing & Prescaler Register (NBTP) */ 142 #define NBTP_NSJW_SHIFT 25 143 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT) 144 #define NBTP_NBRP_SHIFT 16 145 #define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT) 146 #define NBTP_NTSEG1_SHIFT 8 147 #define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT) 148 #define NBTP_NTSEG2_SHIFT 0 149 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT) 150 151 /* Error Counter Register(ECR) */ 152 #define ECR_RP BIT(15) 153 #define ECR_REC_SHIFT 8 154 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT) 155 #define ECR_TEC_SHIFT 0 156 #define ECR_TEC_MASK 0xff 157 158 /* Protocol Status Register(PSR) */ 159 #define PSR_BO BIT(7) 160 #define PSR_EW BIT(6) 161 #define PSR_EP BIT(5) 162 #define PSR_LEC_MASK 0x7 163 164 /* Interrupt Register(IR) */ 165 #define IR_ALL_INT 0xffffffff 166 167 /* Renamed bits for versions > 3.1.x */ 168 #define IR_ARA BIT(29) 169 #define IR_PED BIT(28) 170 #define IR_PEA BIT(27) 171 172 /* Bits for version 3.0.x */ 173 #define IR_STE BIT(31) 174 #define IR_FOE BIT(30) 175 #define IR_ACKE BIT(29) 176 #define IR_BE BIT(28) 177 #define IR_CRCE BIT(27) 178 #define IR_WDI BIT(26) 179 #define IR_BO BIT(25) 180 #define IR_EW BIT(24) 181 #define IR_EP BIT(23) 182 #define IR_ELO BIT(22) 183 #define IR_BEU BIT(21) 184 #define IR_BEC BIT(20) 185 #define IR_DRX BIT(19) 186 #define IR_TOO BIT(18) 187 #define IR_MRAF BIT(17) 188 #define IR_TSW BIT(16) 189 #define IR_TEFL BIT(15) 190 #define IR_TEFF BIT(14) 191 #define IR_TEFW BIT(13) 192 #define IR_TEFN BIT(12) 193 #define IR_TFE BIT(11) 194 #define IR_TCF BIT(10) 195 #define IR_TC BIT(9) 196 #define IR_HPM BIT(8) 197 #define IR_RF1L BIT(7) 198 #define IR_RF1F BIT(6) 199 #define IR_RF1W BIT(5) 200 #define IR_RF1N BIT(4) 201 #define IR_RF0L BIT(3) 202 #define IR_RF0F BIT(2) 203 #define IR_RF0W BIT(1) 204 #define IR_RF0N BIT(0) 205 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) 206 207 /* Interrupts for version 3.0.x */ 208 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) 209 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \ 210 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 211 IR_RF1L | IR_RF0L) 212 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X) 213 /* Interrupts for version >= 3.1.x */ 214 #define IR_ERR_LEC_31X (IR_PED | IR_PEA) 215 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \ 216 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 217 IR_RF1L | IR_RF0L) 218 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X) 219 220 /* Interrupt Line Select (ILS) */ 221 #define ILS_ALL_INT0 0x0 222 #define ILS_ALL_INT1 0xFFFFFFFF 223 224 /* Interrupt Line Enable (ILE) */ 225 #define ILE_EINT1 BIT(1) 226 #define ILE_EINT0 BIT(0) 227 228 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ 229 #define RXFC_FWM_SHIFT 24 230 #define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT) 231 #define RXFC_FS_SHIFT 16 232 #define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT) 233 234 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ 235 #define RXFS_RFL BIT(25) 236 #define RXFS_FF BIT(24) 237 #define RXFS_FPI_SHIFT 16 238 #define RXFS_FPI_MASK 0x3f0000 239 #define RXFS_FGI_SHIFT 8 240 #define RXFS_FGI_MASK 0x3f00 241 #define RXFS_FFL_MASK 0x7f 242 243 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ 244 #define M_CAN_RXESC_8BYTES 0x0 245 #define M_CAN_RXESC_64BYTES 0x777 246 247 /* Tx Buffer Configuration(TXBC) */ 248 #define TXBC_NDTB_SHIFT 16 249 #define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT) 250 #define TXBC_TFQS_SHIFT 24 251 #define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT) 252 253 /* Tx FIFO/Queue Status (TXFQS) */ 254 #define TXFQS_TFQF BIT(21) 255 #define TXFQS_TFQPI_SHIFT 16 256 #define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT) 257 #define TXFQS_TFGI_SHIFT 8 258 #define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT) 259 #define TXFQS_TFFL_SHIFT 0 260 #define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT) 261 262 /* Tx Buffer Element Size Configuration(TXESC) */ 263 #define TXESC_TBDS_8BYTES 0x0 264 #define TXESC_TBDS_64BYTES 0x7 265 266 /* Tx Event FIFO Configuration (TXEFC) */ 267 #define TXEFC_EFS_SHIFT 16 268 #define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT) 269 270 /* Tx Event FIFO Status (TXEFS) */ 271 #define TXEFS_TEFL BIT(25) 272 #define TXEFS_EFF BIT(24) 273 #define TXEFS_EFGI_SHIFT 8 274 #define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT) 275 #define TXEFS_EFFL_SHIFT 0 276 #define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT) 277 278 /* Tx Event FIFO Acknowledge (TXEFA) */ 279 #define TXEFA_EFAI_SHIFT 0 280 #define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT) 281 282 /* Message RAM Configuration (in bytes) */ 283 #define SIDF_ELEMENT_SIZE 4 284 #define XIDF_ELEMENT_SIZE 8 285 #define RXF0_ELEMENT_SIZE 72 286 #define RXF1_ELEMENT_SIZE 72 287 #define RXB_ELEMENT_SIZE 72 288 #define TXE_ELEMENT_SIZE 8 289 #define TXB_ELEMENT_SIZE 72 290 291 /* Message RAM Elements */ 292 #define M_CAN_FIFO_ID 0x0 293 #define M_CAN_FIFO_DLC 0x4 294 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2)) 295 296 /* Rx Buffer Element */ 297 /* R0 */ 298 #define RX_BUF_ESI BIT(31) 299 #define RX_BUF_XTD BIT(30) 300 #define RX_BUF_RTR BIT(29) 301 /* R1 */ 302 #define RX_BUF_ANMF BIT(31) 303 #define RX_BUF_FDF BIT(21) 304 #define RX_BUF_BRS BIT(20) 305 306 /* Tx Buffer Element */ 307 /* T0 */ 308 #define TX_BUF_ESI BIT(31) 309 #define TX_BUF_XTD BIT(30) 310 #define TX_BUF_RTR BIT(29) 311 /* T1 */ 312 #define TX_BUF_EFC BIT(23) 313 #define TX_BUF_FDF BIT(21) 314 #define TX_BUF_BRS BIT(20) 315 #define TX_BUF_MM_SHIFT 24 316 #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT) 317 318 /* Tx event FIFO Element */ 319 /* E1 */ 320 #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT 321 #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT) 322 323 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) 324 { 325 return cdev->ops->read_reg(cdev, reg); 326 } 327 328 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, 329 u32 val) 330 { 331 cdev->ops->write_reg(cdev, reg, val); 332 } 333 334 static u32 m_can_fifo_read(struct m_can_classdev *cdev, 335 u32 fgi, unsigned int offset) 336 { 337 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + 338 offset; 339 340 return cdev->ops->read_fifo(cdev, addr_offset); 341 } 342 343 static void m_can_fifo_write(struct m_can_classdev *cdev, 344 u32 fpi, unsigned int offset, u32 val) 345 { 346 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + 347 offset; 348 349 cdev->ops->write_fifo(cdev, addr_offset, val); 350 } 351 352 static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev, 353 u32 fpi, u32 val) 354 { 355 cdev->ops->write_fifo(cdev, fpi, val); 356 } 357 358 static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset) 359 { 360 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + 361 offset; 362 363 return cdev->ops->read_fifo(cdev, addr_offset); 364 } 365 366 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev) 367 { 368 return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF); 369 } 370 371 static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable) 372 { 373 u32 cccr = m_can_read(cdev, M_CAN_CCCR); 374 u32 timeout = 10; 375 u32 val = 0; 376 377 /* Clear the Clock stop request if it was set */ 378 if (cccr & CCCR_CSR) 379 cccr &= ~CCCR_CSR; 380 381 if (enable) { 382 /* enable m_can configuration */ 383 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT); 384 udelay(5); 385 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ 386 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); 387 } else { 388 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); 389 } 390 391 /* there's a delay for module initialization */ 392 if (enable) 393 val = CCCR_INIT | CCCR_CCE; 394 395 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { 396 if (timeout == 0) { 397 netdev_warn(cdev->net, "Failed to init module\n"); 398 return; 399 } 400 timeout--; 401 udelay(1); 402 } 403 } 404 405 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev) 406 { 407 /* Only interrupt line 0 is used in this driver */ 408 m_can_write(cdev, M_CAN_ILE, ILE_EINT0); 409 } 410 411 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev) 412 { 413 m_can_write(cdev, M_CAN_ILE, 0x0); 414 } 415 416 static void m_can_clean(struct net_device *net) 417 { 418 struct m_can_classdev *cdev = netdev_priv(net); 419 420 if (cdev->tx_skb) { 421 int putidx = 0; 422 423 net->stats.tx_errors++; 424 if (cdev->version > 30) 425 putidx = ((m_can_read(cdev, M_CAN_TXFQS) & 426 TXFQS_TFQPI_MASK) >> TXFQS_TFQPI_SHIFT); 427 428 can_free_echo_skb(cdev->net, putidx); 429 cdev->tx_skb = NULL; 430 } 431 } 432 433 static void m_can_read_fifo(struct net_device *dev, u32 rxfs) 434 { 435 struct net_device_stats *stats = &dev->stats; 436 struct m_can_classdev *cdev = netdev_priv(dev); 437 struct canfd_frame *cf; 438 struct sk_buff *skb; 439 u32 id, fgi, dlc; 440 int i; 441 442 /* calculate the fifo get index for where to read data */ 443 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT; 444 dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC); 445 if (dlc & RX_BUF_FDF) 446 skb = alloc_canfd_skb(dev, &cf); 447 else 448 skb = alloc_can_skb(dev, (struct can_frame **)&cf); 449 if (!skb) { 450 stats->rx_dropped++; 451 return; 452 } 453 454 if (dlc & RX_BUF_FDF) 455 cf->len = can_fd_dlc2len((dlc >> 16) & 0x0F); 456 else 457 cf->len = can_cc_dlc2len((dlc >> 16) & 0x0F); 458 459 id = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID); 460 if (id & RX_BUF_XTD) 461 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 462 else 463 cf->can_id = (id >> 18) & CAN_SFF_MASK; 464 465 if (id & RX_BUF_ESI) { 466 cf->flags |= CANFD_ESI; 467 netdev_dbg(dev, "ESI Error\n"); 468 } 469 470 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) { 471 cf->can_id |= CAN_RTR_FLAG; 472 } else { 473 if (dlc & RX_BUF_BRS) 474 cf->flags |= CANFD_BRS; 475 476 for (i = 0; i < cf->len; i += 4) 477 *(u32 *)(cf->data + i) = 478 m_can_fifo_read(cdev, fgi, 479 M_CAN_FIFO_DATA(i / 4)); 480 } 481 482 /* acknowledge rx fifo 0 */ 483 m_can_write(cdev, M_CAN_RXF0A, fgi); 484 485 stats->rx_packets++; 486 stats->rx_bytes += cf->len; 487 488 netif_receive_skb(skb); 489 } 490 491 static int m_can_do_rx_poll(struct net_device *dev, int quota) 492 { 493 struct m_can_classdev *cdev = netdev_priv(dev); 494 u32 pkts = 0; 495 u32 rxfs; 496 497 rxfs = m_can_read(cdev, M_CAN_RXF0S); 498 if (!(rxfs & RXFS_FFL_MASK)) { 499 netdev_dbg(dev, "no messages in fifo0\n"); 500 return 0; 501 } 502 503 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) { 504 m_can_read_fifo(dev, rxfs); 505 506 quota--; 507 pkts++; 508 rxfs = m_can_read(cdev, M_CAN_RXF0S); 509 } 510 511 if (pkts) 512 can_led_event(dev, CAN_LED_EVENT_RX); 513 514 return pkts; 515 } 516 517 static int m_can_handle_lost_msg(struct net_device *dev) 518 { 519 struct net_device_stats *stats = &dev->stats; 520 struct sk_buff *skb; 521 struct can_frame *frame; 522 523 netdev_err(dev, "msg lost in rxf0\n"); 524 525 stats->rx_errors++; 526 stats->rx_over_errors++; 527 528 skb = alloc_can_err_skb(dev, &frame); 529 if (unlikely(!skb)) 530 return 0; 531 532 frame->can_id |= CAN_ERR_CRTL; 533 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 534 535 netif_receive_skb(skb); 536 537 return 1; 538 } 539 540 static int m_can_handle_lec_err(struct net_device *dev, 541 enum m_can_lec_type lec_type) 542 { 543 struct m_can_classdev *cdev = netdev_priv(dev); 544 struct net_device_stats *stats = &dev->stats; 545 struct can_frame *cf; 546 struct sk_buff *skb; 547 548 cdev->can.can_stats.bus_error++; 549 stats->rx_errors++; 550 551 /* propagate the error condition to the CAN stack */ 552 skb = alloc_can_err_skb(dev, &cf); 553 if (unlikely(!skb)) 554 return 0; 555 556 /* check for 'last error code' which tells us the 557 * type of the last error to occur on the CAN bus 558 */ 559 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 560 561 switch (lec_type) { 562 case LEC_STUFF_ERROR: 563 netdev_dbg(dev, "stuff error\n"); 564 cf->data[2] |= CAN_ERR_PROT_STUFF; 565 break; 566 case LEC_FORM_ERROR: 567 netdev_dbg(dev, "form error\n"); 568 cf->data[2] |= CAN_ERR_PROT_FORM; 569 break; 570 case LEC_ACK_ERROR: 571 netdev_dbg(dev, "ack error\n"); 572 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 573 break; 574 case LEC_BIT1_ERROR: 575 netdev_dbg(dev, "bit1 error\n"); 576 cf->data[2] |= CAN_ERR_PROT_BIT1; 577 break; 578 case LEC_BIT0_ERROR: 579 netdev_dbg(dev, "bit0 error\n"); 580 cf->data[2] |= CAN_ERR_PROT_BIT0; 581 break; 582 case LEC_CRC_ERROR: 583 netdev_dbg(dev, "CRC error\n"); 584 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 585 break; 586 default: 587 break; 588 } 589 590 stats->rx_packets++; 591 stats->rx_bytes += cf->len; 592 netif_receive_skb(skb); 593 594 return 1; 595 } 596 597 static int __m_can_get_berr_counter(const struct net_device *dev, 598 struct can_berr_counter *bec) 599 { 600 struct m_can_classdev *cdev = netdev_priv(dev); 601 unsigned int ecr; 602 603 ecr = m_can_read(cdev, M_CAN_ECR); 604 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT; 605 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT; 606 607 return 0; 608 } 609 610 static int m_can_clk_start(struct m_can_classdev *cdev) 611 { 612 if (cdev->pm_clock_support == 0) 613 return 0; 614 615 return pm_runtime_resume_and_get(cdev->dev); 616 } 617 618 static void m_can_clk_stop(struct m_can_classdev *cdev) 619 { 620 if (cdev->pm_clock_support) 621 pm_runtime_put_sync(cdev->dev); 622 } 623 624 static int m_can_get_berr_counter(const struct net_device *dev, 625 struct can_berr_counter *bec) 626 { 627 struct m_can_classdev *cdev = netdev_priv(dev); 628 int err; 629 630 err = m_can_clk_start(cdev); 631 if (err) 632 return err; 633 634 __m_can_get_berr_counter(dev, bec); 635 636 m_can_clk_stop(cdev); 637 638 return 0; 639 } 640 641 static int m_can_handle_state_change(struct net_device *dev, 642 enum can_state new_state) 643 { 644 struct m_can_classdev *cdev = netdev_priv(dev); 645 struct net_device_stats *stats = &dev->stats; 646 struct can_frame *cf; 647 struct sk_buff *skb; 648 struct can_berr_counter bec; 649 unsigned int ecr; 650 651 switch (new_state) { 652 case CAN_STATE_ERROR_WARNING: 653 /* error warning state */ 654 cdev->can.can_stats.error_warning++; 655 cdev->can.state = CAN_STATE_ERROR_WARNING; 656 break; 657 case CAN_STATE_ERROR_PASSIVE: 658 /* error passive state */ 659 cdev->can.can_stats.error_passive++; 660 cdev->can.state = CAN_STATE_ERROR_PASSIVE; 661 break; 662 case CAN_STATE_BUS_OFF: 663 /* bus-off state */ 664 cdev->can.state = CAN_STATE_BUS_OFF; 665 m_can_disable_all_interrupts(cdev); 666 cdev->can.can_stats.bus_off++; 667 can_bus_off(dev); 668 break; 669 default: 670 break; 671 } 672 673 /* propagate the error condition to the CAN stack */ 674 skb = alloc_can_err_skb(dev, &cf); 675 if (unlikely(!skb)) 676 return 0; 677 678 __m_can_get_berr_counter(dev, &bec); 679 680 switch (new_state) { 681 case CAN_STATE_ERROR_WARNING: 682 /* error warning state */ 683 cf->can_id |= CAN_ERR_CRTL; 684 cf->data[1] = (bec.txerr > bec.rxerr) ? 685 CAN_ERR_CRTL_TX_WARNING : 686 CAN_ERR_CRTL_RX_WARNING; 687 cf->data[6] = bec.txerr; 688 cf->data[7] = bec.rxerr; 689 break; 690 case CAN_STATE_ERROR_PASSIVE: 691 /* error passive state */ 692 cf->can_id |= CAN_ERR_CRTL; 693 ecr = m_can_read(cdev, M_CAN_ECR); 694 if (ecr & ECR_RP) 695 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 696 if (bec.txerr > 127) 697 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 698 cf->data[6] = bec.txerr; 699 cf->data[7] = bec.rxerr; 700 break; 701 case CAN_STATE_BUS_OFF: 702 /* bus-off state */ 703 cf->can_id |= CAN_ERR_BUSOFF; 704 break; 705 default: 706 break; 707 } 708 709 stats->rx_packets++; 710 stats->rx_bytes += cf->len; 711 netif_receive_skb(skb); 712 713 return 1; 714 } 715 716 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) 717 { 718 struct m_can_classdev *cdev = netdev_priv(dev); 719 int work_done = 0; 720 721 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { 722 netdev_dbg(dev, "entered error warning state\n"); 723 work_done += m_can_handle_state_change(dev, 724 CAN_STATE_ERROR_WARNING); 725 } 726 727 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { 728 netdev_dbg(dev, "entered error passive state\n"); 729 work_done += m_can_handle_state_change(dev, 730 CAN_STATE_ERROR_PASSIVE); 731 } 732 733 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { 734 netdev_dbg(dev, "entered error bus off state\n"); 735 work_done += m_can_handle_state_change(dev, 736 CAN_STATE_BUS_OFF); 737 } 738 739 return work_done; 740 } 741 742 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) 743 { 744 if (irqstatus & IR_WDI) 745 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); 746 if (irqstatus & IR_ELO) 747 netdev_err(dev, "Error Logging Overflow\n"); 748 if (irqstatus & IR_BEU) 749 netdev_err(dev, "Bit Error Uncorrected\n"); 750 if (irqstatus & IR_BEC) 751 netdev_err(dev, "Bit Error Corrected\n"); 752 if (irqstatus & IR_TOO) 753 netdev_err(dev, "Timeout reached\n"); 754 if (irqstatus & IR_MRAF) 755 netdev_err(dev, "Message RAM access failure occurred\n"); 756 } 757 758 static inline bool is_lec_err(u32 psr) 759 { 760 psr &= LEC_UNUSED; 761 762 return psr && (psr != LEC_UNUSED); 763 } 764 765 static inline bool m_can_is_protocol_err(u32 irqstatus) 766 { 767 return irqstatus & IR_ERR_LEC_31X; 768 } 769 770 static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus) 771 { 772 struct net_device_stats *stats = &dev->stats; 773 struct m_can_classdev *cdev = netdev_priv(dev); 774 struct can_frame *cf; 775 struct sk_buff *skb; 776 777 /* propagate the error condition to the CAN stack */ 778 skb = alloc_can_err_skb(dev, &cf); 779 780 /* update tx error stats since there is protocol error */ 781 stats->tx_errors++; 782 783 /* update arbitration lost status */ 784 if (cdev->version >= 31 && (irqstatus & IR_PEA)) { 785 netdev_dbg(dev, "Protocol error in Arbitration fail\n"); 786 cdev->can.can_stats.arbitration_lost++; 787 if (skb) { 788 cf->can_id |= CAN_ERR_LOSTARB; 789 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC; 790 } 791 } 792 793 if (unlikely(!skb)) { 794 netdev_dbg(dev, "allocation of skb failed\n"); 795 return 0; 796 } 797 netif_receive_skb(skb); 798 799 return 1; 800 } 801 802 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, 803 u32 psr) 804 { 805 struct m_can_classdev *cdev = netdev_priv(dev); 806 int work_done = 0; 807 808 if (irqstatus & IR_RF0L) 809 work_done += m_can_handle_lost_msg(dev); 810 811 /* handle lec errors on the bus */ 812 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 813 is_lec_err(psr)) 814 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED); 815 816 /* handle protocol errors in arbitration phase */ 817 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 818 m_can_is_protocol_err(irqstatus)) 819 work_done += m_can_handle_protocol_error(dev, irqstatus); 820 821 /* other unproccessed error interrupts */ 822 m_can_handle_other_err(dev, irqstatus); 823 824 return work_done; 825 } 826 827 static int m_can_rx_handler(struct net_device *dev, int quota) 828 { 829 struct m_can_classdev *cdev = netdev_priv(dev); 830 int work_done = 0; 831 u32 irqstatus, psr; 832 833 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR); 834 if (!irqstatus) 835 goto end; 836 837 /* Errata workaround for issue "Needless activation of MRAF irq" 838 * During frame reception while the MCAN is in Error Passive state 839 * and the Receive Error Counter has the value MCAN_ECR.REC = 127, 840 * it may happen that MCAN_IR.MRAF is set although there was no 841 * Message RAM access failure. 842 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated 843 * The Message RAM Access Failure interrupt routine needs to check 844 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127. 845 * In this case, reset MCAN_IR.MRAF. No further action is required. 846 */ 847 if (cdev->version <= 31 && irqstatus & IR_MRAF && 848 m_can_read(cdev, M_CAN_ECR) & ECR_RP) { 849 struct can_berr_counter bec; 850 851 __m_can_get_berr_counter(dev, &bec); 852 if (bec.rxerr == 127) { 853 m_can_write(cdev, M_CAN_IR, IR_MRAF); 854 irqstatus &= ~IR_MRAF; 855 } 856 } 857 858 psr = m_can_read(cdev, M_CAN_PSR); 859 860 if (irqstatus & IR_ERR_STATE) 861 work_done += m_can_handle_state_errors(dev, psr); 862 863 if (irqstatus & IR_ERR_BUS_30X) 864 work_done += m_can_handle_bus_errors(dev, irqstatus, psr); 865 866 if (irqstatus & IR_RF0N) 867 work_done += m_can_do_rx_poll(dev, (quota - work_done)); 868 end: 869 return work_done; 870 } 871 872 static int m_can_rx_peripheral(struct net_device *dev) 873 { 874 struct m_can_classdev *cdev = netdev_priv(dev); 875 876 m_can_rx_handler(dev, M_CAN_NAPI_WEIGHT); 877 878 m_can_enable_all_interrupts(cdev); 879 880 return 0; 881 } 882 883 static int m_can_poll(struct napi_struct *napi, int quota) 884 { 885 struct net_device *dev = napi->dev; 886 struct m_can_classdev *cdev = netdev_priv(dev); 887 int work_done; 888 889 work_done = m_can_rx_handler(dev, quota); 890 if (work_done < quota) { 891 napi_complete_done(napi, work_done); 892 m_can_enable_all_interrupts(cdev); 893 } 894 895 return work_done; 896 } 897 898 static void m_can_echo_tx_event(struct net_device *dev) 899 { 900 u32 txe_count = 0; 901 u32 m_can_txefs; 902 u32 fgi = 0; 903 int i = 0; 904 unsigned int msg_mark; 905 906 struct m_can_classdev *cdev = netdev_priv(dev); 907 struct net_device_stats *stats = &dev->stats; 908 909 /* read tx event fifo status */ 910 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); 911 912 /* Get Tx Event fifo element count */ 913 txe_count = (m_can_txefs & TXEFS_EFFL_MASK) >> TXEFS_EFFL_SHIFT; 914 915 /* Get and process all sent elements */ 916 for (i = 0; i < txe_count; i++) { 917 /* retrieve get index */ 918 fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK) >> 919 TXEFS_EFGI_SHIFT; 920 921 /* get message marker */ 922 msg_mark = (m_can_txe_fifo_read(cdev, fgi, 4) & 923 TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT; 924 925 /* ack txe element */ 926 m_can_write(cdev, M_CAN_TXEFA, (TXEFA_EFAI_MASK & 927 (fgi << TXEFA_EFAI_SHIFT))); 928 929 /* update stats */ 930 stats->tx_bytes += can_get_echo_skb(dev, msg_mark, NULL); 931 stats->tx_packets++; 932 } 933 } 934 935 static irqreturn_t m_can_isr(int irq, void *dev_id) 936 { 937 struct net_device *dev = (struct net_device *)dev_id; 938 struct m_can_classdev *cdev = netdev_priv(dev); 939 struct net_device_stats *stats = &dev->stats; 940 u32 ir; 941 942 if (pm_runtime_suspended(cdev->dev)) 943 return IRQ_NONE; 944 ir = m_can_read(cdev, M_CAN_IR); 945 if (!ir) 946 return IRQ_NONE; 947 948 /* ACK all irqs */ 949 if (ir & IR_ALL_INT) 950 m_can_write(cdev, M_CAN_IR, ir); 951 952 if (cdev->ops->clear_interrupts) 953 cdev->ops->clear_interrupts(cdev); 954 955 /* schedule NAPI in case of 956 * - rx IRQ 957 * - state change IRQ 958 * - bus error IRQ and bus error reporting 959 */ 960 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) { 961 cdev->irqstatus = ir; 962 m_can_disable_all_interrupts(cdev); 963 if (!cdev->is_peripheral) 964 napi_schedule(&cdev->napi); 965 else 966 m_can_rx_peripheral(dev); 967 } 968 969 if (cdev->version == 30) { 970 if (ir & IR_TC) { 971 /* Transmission Complete Interrupt*/ 972 stats->tx_bytes += can_get_echo_skb(dev, 0, NULL); 973 stats->tx_packets++; 974 can_led_event(dev, CAN_LED_EVENT_TX); 975 netif_wake_queue(dev); 976 } 977 } else { 978 if (ir & IR_TEFN) { 979 /* New TX FIFO Element arrived */ 980 m_can_echo_tx_event(dev); 981 can_led_event(dev, CAN_LED_EVENT_TX); 982 if (netif_queue_stopped(dev) && 983 !m_can_tx_fifo_full(cdev)) 984 netif_wake_queue(dev); 985 } 986 } 987 988 return IRQ_HANDLED; 989 } 990 991 static const struct can_bittiming_const m_can_bittiming_const_30X = { 992 .name = KBUILD_MODNAME, 993 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 994 .tseg1_max = 64, 995 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 996 .tseg2_max = 16, 997 .sjw_max = 16, 998 .brp_min = 1, 999 .brp_max = 1024, 1000 .brp_inc = 1, 1001 }; 1002 1003 static const struct can_bittiming_const m_can_data_bittiming_const_30X = { 1004 .name = KBUILD_MODNAME, 1005 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1006 .tseg1_max = 16, 1007 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1008 .tseg2_max = 8, 1009 .sjw_max = 4, 1010 .brp_min = 1, 1011 .brp_max = 32, 1012 .brp_inc = 1, 1013 }; 1014 1015 static const struct can_bittiming_const m_can_bittiming_const_31X = { 1016 .name = KBUILD_MODNAME, 1017 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1018 .tseg1_max = 256, 1019 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */ 1020 .tseg2_max = 128, 1021 .sjw_max = 128, 1022 .brp_min = 1, 1023 .brp_max = 512, 1024 .brp_inc = 1, 1025 }; 1026 1027 static const struct can_bittiming_const m_can_data_bittiming_const_31X = { 1028 .name = KBUILD_MODNAME, 1029 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */ 1030 .tseg1_max = 32, 1031 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1032 .tseg2_max = 16, 1033 .sjw_max = 16, 1034 .brp_min = 1, 1035 .brp_max = 32, 1036 .brp_inc = 1, 1037 }; 1038 1039 static int m_can_set_bittiming(struct net_device *dev) 1040 { 1041 struct m_can_classdev *cdev = netdev_priv(dev); 1042 const struct can_bittiming *bt = &cdev->can.bittiming; 1043 const struct can_bittiming *dbt = &cdev->can.data_bittiming; 1044 u16 brp, sjw, tseg1, tseg2; 1045 u32 reg_btp; 1046 1047 brp = bt->brp - 1; 1048 sjw = bt->sjw - 1; 1049 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 1050 tseg2 = bt->phase_seg2 - 1; 1051 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) | 1052 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT); 1053 m_can_write(cdev, M_CAN_NBTP, reg_btp); 1054 1055 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1056 reg_btp = 0; 1057 brp = dbt->brp - 1; 1058 sjw = dbt->sjw - 1; 1059 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; 1060 tseg2 = dbt->phase_seg2 - 1; 1061 1062 /* TDC is only needed for bitrates beyond 2.5 MBit/s. 1063 * This is mentioned in the "Bit Time Requirements for CAN FD" 1064 * paper presented at the International CAN Conference 2013 1065 */ 1066 if (dbt->bitrate > 2500000) { 1067 u32 tdco, ssp; 1068 1069 /* Use the same value of secondary sampling point 1070 * as the data sampling point 1071 */ 1072 ssp = dbt->sample_point; 1073 1074 /* Equation based on Bosch's M_CAN User Manual's 1075 * Transmitter Delay Compensation Section 1076 */ 1077 tdco = (cdev->can.clock.freq / 1000) * 1078 ssp / dbt->bitrate; 1079 1080 /* Max valid TDCO value is 127 */ 1081 if (tdco > 127) { 1082 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n", 1083 tdco); 1084 tdco = 127; 1085 } 1086 1087 reg_btp |= DBTP_TDC; 1088 m_can_write(cdev, M_CAN_TDCR, 1089 tdco << TDCR_TDCO_SHIFT); 1090 } 1091 1092 reg_btp |= (brp << DBTP_DBRP_SHIFT) | 1093 (sjw << DBTP_DSJW_SHIFT) | 1094 (tseg1 << DBTP_DTSEG1_SHIFT) | 1095 (tseg2 << DBTP_DTSEG2_SHIFT); 1096 1097 m_can_write(cdev, M_CAN_DBTP, reg_btp); 1098 } 1099 1100 return 0; 1101 } 1102 1103 /* Configure M_CAN chip: 1104 * - set rx buffer/fifo element size 1105 * - configure rx fifo 1106 * - accept non-matching frame into fifo 0 1107 * - configure tx buffer 1108 * - >= v3.1.x: TX FIFO is used 1109 * - configure mode 1110 * - setup bittiming 1111 */ 1112 static void m_can_chip_config(struct net_device *dev) 1113 { 1114 struct m_can_classdev *cdev = netdev_priv(dev); 1115 u32 cccr, test; 1116 1117 m_can_config_endisable(cdev, true); 1118 1119 /* RX Buffer/FIFO Element Size 64 bytes data field */ 1120 m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES); 1121 1122 /* Accept Non-matching Frames Into FIFO 0 */ 1123 m_can_write(cdev, M_CAN_GFC, 0x0); 1124 1125 if (cdev->version == 30) { 1126 /* only support one Tx Buffer currently */ 1127 m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) | 1128 cdev->mcfg[MRAM_TXB].off); 1129 } else { 1130 /* TX FIFO is used for newer IP Core versions */ 1131 m_can_write(cdev, M_CAN_TXBC, 1132 (cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) | 1133 (cdev->mcfg[MRAM_TXB].off)); 1134 } 1135 1136 /* support 64 bytes payload */ 1137 m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES); 1138 1139 /* TX Event FIFO */ 1140 if (cdev->version == 30) { 1141 m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) | 1142 cdev->mcfg[MRAM_TXE].off); 1143 } else { 1144 /* Full TX Event FIFO is used */ 1145 m_can_write(cdev, M_CAN_TXEFC, 1146 ((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT) 1147 & TXEFC_EFS_MASK) | 1148 cdev->mcfg[MRAM_TXE].off); 1149 } 1150 1151 /* rx fifo configuration, blocking mode, fifo size 1 */ 1152 m_can_write(cdev, M_CAN_RXF0C, 1153 (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) | 1154 cdev->mcfg[MRAM_RXF0].off); 1155 1156 m_can_write(cdev, M_CAN_RXF1C, 1157 (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) | 1158 cdev->mcfg[MRAM_RXF1].off); 1159 1160 cccr = m_can_read(cdev, M_CAN_CCCR); 1161 test = m_can_read(cdev, M_CAN_TEST); 1162 test &= ~TEST_LBCK; 1163 if (cdev->version == 30) { 1164 /* Version 3.0.x */ 1165 1166 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR | 1167 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | 1168 (CCCR_CME_MASK << CCCR_CME_SHIFT)); 1169 1170 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1171 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT; 1172 1173 } else { 1174 /* Version 3.1.x or 3.2.x */ 1175 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE | 1176 CCCR_NISO | CCCR_DAR); 1177 1178 /* Only 3.2.x has NISO Bit implemented */ 1179 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 1180 cccr |= CCCR_NISO; 1181 1182 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1183 cccr |= (CCCR_BRSE | CCCR_FDOE); 1184 } 1185 1186 /* Loopback Mode */ 1187 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1188 cccr |= CCCR_TEST | CCCR_MON; 1189 test |= TEST_LBCK; 1190 } 1191 1192 /* Enable Monitoring (all versions) */ 1193 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1194 cccr |= CCCR_MON; 1195 1196 /* Disable Auto Retransmission (all versions) */ 1197 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 1198 cccr |= CCCR_DAR; 1199 1200 /* Write config */ 1201 m_can_write(cdev, M_CAN_CCCR, cccr); 1202 m_can_write(cdev, M_CAN_TEST, test); 1203 1204 /* Enable interrupts */ 1205 m_can_write(cdev, M_CAN_IR, IR_ALL_INT); 1206 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1207 if (cdev->version == 30) 1208 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & 1209 ~(IR_ERR_LEC_30X)); 1210 else 1211 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & 1212 ~(IR_ERR_LEC_31X)); 1213 else 1214 m_can_write(cdev, M_CAN_IE, IR_ALL_INT); 1215 1216 /* route all interrupts to INT0 */ 1217 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); 1218 1219 /* set bittiming params */ 1220 m_can_set_bittiming(dev); 1221 1222 m_can_config_endisable(cdev, false); 1223 1224 if (cdev->ops->init) 1225 cdev->ops->init(cdev); 1226 } 1227 1228 static void m_can_start(struct net_device *dev) 1229 { 1230 struct m_can_classdev *cdev = netdev_priv(dev); 1231 1232 /* basic m_can configuration */ 1233 m_can_chip_config(dev); 1234 1235 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 1236 1237 m_can_enable_all_interrupts(cdev); 1238 } 1239 1240 static int m_can_set_mode(struct net_device *dev, enum can_mode mode) 1241 { 1242 switch (mode) { 1243 case CAN_MODE_START: 1244 m_can_clean(dev); 1245 m_can_start(dev); 1246 netif_wake_queue(dev); 1247 break; 1248 default: 1249 return -EOPNOTSUPP; 1250 } 1251 1252 return 0; 1253 } 1254 1255 /* Checks core release number of M_CAN 1256 * returns 0 if an unsupported device is detected 1257 * else it returns the release and step coded as: 1258 * return value = 10 * <release> + 1 * <step> 1259 */ 1260 static int m_can_check_core_release(struct m_can_classdev *cdev) 1261 { 1262 u32 crel_reg; 1263 u8 rel; 1264 u8 step; 1265 int res; 1266 1267 /* Read Core Release Version and split into version number 1268 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; 1269 */ 1270 crel_reg = m_can_read(cdev, M_CAN_CREL); 1271 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT); 1272 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT); 1273 1274 if (rel == 3) { 1275 /* M_CAN v3.x.y: create return value */ 1276 res = 30 + step; 1277 } else { 1278 /* Unsupported M_CAN version */ 1279 res = 0; 1280 } 1281 1282 return res; 1283 } 1284 1285 /* Selectable Non ISO support only in version 3.2.x 1286 * This function checks if the bit is writable. 1287 */ 1288 static bool m_can_niso_supported(struct m_can_classdev *cdev) 1289 { 1290 u32 cccr_reg, cccr_poll = 0; 1291 int niso_timeout = -ETIMEDOUT; 1292 int i; 1293 1294 m_can_config_endisable(cdev, true); 1295 cccr_reg = m_can_read(cdev, M_CAN_CCCR); 1296 cccr_reg |= CCCR_NISO; 1297 m_can_write(cdev, M_CAN_CCCR, cccr_reg); 1298 1299 for (i = 0; i <= 10; i++) { 1300 cccr_poll = m_can_read(cdev, M_CAN_CCCR); 1301 if (cccr_poll == cccr_reg) { 1302 niso_timeout = 0; 1303 break; 1304 } 1305 1306 usleep_range(1, 5); 1307 } 1308 1309 /* Clear NISO */ 1310 cccr_reg &= ~(CCCR_NISO); 1311 m_can_write(cdev, M_CAN_CCCR, cccr_reg); 1312 1313 m_can_config_endisable(cdev, false); 1314 1315 /* return false if time out (-ETIMEDOUT), else return true */ 1316 return !niso_timeout; 1317 } 1318 1319 static int m_can_dev_setup(struct m_can_classdev *cdev) 1320 { 1321 struct net_device *dev = cdev->net; 1322 int m_can_version; 1323 1324 m_can_version = m_can_check_core_release(cdev); 1325 /* return if unsupported version */ 1326 if (!m_can_version) { 1327 dev_err(cdev->dev, "Unsupported version number: %2d", 1328 m_can_version); 1329 return -EINVAL; 1330 } 1331 1332 if (!cdev->is_peripheral) 1333 netif_napi_add(dev, &cdev->napi, 1334 m_can_poll, M_CAN_NAPI_WEIGHT); 1335 1336 /* Shared properties of all M_CAN versions */ 1337 cdev->version = m_can_version; 1338 cdev->can.do_set_mode = m_can_set_mode; 1339 cdev->can.do_get_berr_counter = m_can_get_berr_counter; 1340 1341 /* Set M_CAN supported operations */ 1342 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1343 CAN_CTRLMODE_LISTENONLY | 1344 CAN_CTRLMODE_BERR_REPORTING | 1345 CAN_CTRLMODE_FD | 1346 CAN_CTRLMODE_ONE_SHOT; 1347 1348 /* Set properties depending on M_CAN version */ 1349 switch (cdev->version) { 1350 case 30: 1351 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ 1352 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1353 cdev->can.bittiming_const = cdev->bit_timing ? 1354 cdev->bit_timing : &m_can_bittiming_const_30X; 1355 1356 cdev->can.data_bittiming_const = cdev->data_timing ? 1357 cdev->data_timing : 1358 &m_can_data_bittiming_const_30X; 1359 break; 1360 case 31: 1361 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ 1362 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1363 cdev->can.bittiming_const = cdev->bit_timing ? 1364 cdev->bit_timing : &m_can_bittiming_const_31X; 1365 1366 cdev->can.data_bittiming_const = cdev->data_timing ? 1367 cdev->data_timing : 1368 &m_can_data_bittiming_const_31X; 1369 break; 1370 case 32: 1371 case 33: 1372 /* Support both MCAN version v3.2.x and v3.3.0 */ 1373 cdev->can.bittiming_const = cdev->bit_timing ? 1374 cdev->bit_timing : &m_can_bittiming_const_31X; 1375 1376 cdev->can.data_bittiming_const = cdev->data_timing ? 1377 cdev->data_timing : 1378 &m_can_data_bittiming_const_31X; 1379 1380 cdev->can.ctrlmode_supported |= 1381 (m_can_niso_supported(cdev) ? 1382 CAN_CTRLMODE_FD_NON_ISO : 0); 1383 break; 1384 default: 1385 dev_err(cdev->dev, "Unsupported version number: %2d", 1386 cdev->version); 1387 return -EINVAL; 1388 } 1389 1390 if (cdev->ops->init) 1391 cdev->ops->init(cdev); 1392 1393 return 0; 1394 } 1395 1396 static void m_can_stop(struct net_device *dev) 1397 { 1398 struct m_can_classdev *cdev = netdev_priv(dev); 1399 1400 /* disable all interrupts */ 1401 m_can_disable_all_interrupts(cdev); 1402 1403 /* Set init mode to disengage from the network */ 1404 m_can_config_endisable(cdev, true); 1405 1406 /* set the state as STOPPED */ 1407 cdev->can.state = CAN_STATE_STOPPED; 1408 } 1409 1410 static int m_can_close(struct net_device *dev) 1411 { 1412 struct m_can_classdev *cdev = netdev_priv(dev); 1413 1414 netif_stop_queue(dev); 1415 1416 if (!cdev->is_peripheral) 1417 napi_disable(&cdev->napi); 1418 1419 m_can_stop(dev); 1420 m_can_clk_stop(cdev); 1421 free_irq(dev->irq, dev); 1422 1423 if (cdev->is_peripheral) { 1424 cdev->tx_skb = NULL; 1425 destroy_workqueue(cdev->tx_wq); 1426 cdev->tx_wq = NULL; 1427 } 1428 1429 close_candev(dev); 1430 can_led_event(dev, CAN_LED_EVENT_STOP); 1431 1432 return 0; 1433 } 1434 1435 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx) 1436 { 1437 struct m_can_classdev *cdev = netdev_priv(dev); 1438 /*get wrap around for loopback skb index */ 1439 unsigned int wrap = cdev->can.echo_skb_max; 1440 int next_idx; 1441 1442 /* calculate next index */ 1443 next_idx = (++putidx >= wrap ? 0 : putidx); 1444 1445 /* check if occupied */ 1446 return !!cdev->can.echo_skb[next_idx]; 1447 } 1448 1449 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) 1450 { 1451 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data; 1452 struct net_device *dev = cdev->net; 1453 struct sk_buff *skb = cdev->tx_skb; 1454 u32 id, cccr, fdflags; 1455 int i; 1456 int putidx; 1457 1458 /* Generate ID field for TX buffer Element */ 1459 /* Common to all supported M_CAN versions */ 1460 if (cf->can_id & CAN_EFF_FLAG) { 1461 id = cf->can_id & CAN_EFF_MASK; 1462 id |= TX_BUF_XTD; 1463 } else { 1464 id = ((cf->can_id & CAN_SFF_MASK) << 18); 1465 } 1466 1467 if (cf->can_id & CAN_RTR_FLAG) 1468 id |= TX_BUF_RTR; 1469 1470 if (cdev->version == 30) { 1471 netif_stop_queue(dev); 1472 1473 /* message ram configuration */ 1474 m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, id); 1475 m_can_fifo_write(cdev, 0, M_CAN_FIFO_DLC, 1476 can_fd_len2dlc(cf->len) << 16); 1477 1478 for (i = 0; i < cf->len; i += 4) 1479 m_can_fifo_write(cdev, 0, 1480 M_CAN_FIFO_DATA(i / 4), 1481 *(u32 *)(cf->data + i)); 1482 1483 can_put_echo_skb(skb, dev, 0, 0); 1484 1485 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1486 cccr = m_can_read(cdev, M_CAN_CCCR); 1487 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT); 1488 if (can_is_canfd_skb(skb)) { 1489 if (cf->flags & CANFD_BRS) 1490 cccr |= CCCR_CMR_CANFD_BRS << 1491 CCCR_CMR_SHIFT; 1492 else 1493 cccr |= CCCR_CMR_CANFD << 1494 CCCR_CMR_SHIFT; 1495 } else { 1496 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT; 1497 } 1498 m_can_write(cdev, M_CAN_CCCR, cccr); 1499 } 1500 m_can_write(cdev, M_CAN_TXBTIE, 0x1); 1501 m_can_write(cdev, M_CAN_TXBAR, 0x1); 1502 /* End of xmit function for version 3.0.x */ 1503 } else { 1504 /* Transmit routine for version >= v3.1.x */ 1505 1506 /* Check if FIFO full */ 1507 if (m_can_tx_fifo_full(cdev)) { 1508 /* This shouldn't happen */ 1509 netif_stop_queue(dev); 1510 netdev_warn(dev, 1511 "TX queue active although FIFO is full."); 1512 1513 if (cdev->is_peripheral) { 1514 kfree_skb(skb); 1515 dev->stats.tx_dropped++; 1516 return NETDEV_TX_OK; 1517 } else { 1518 return NETDEV_TX_BUSY; 1519 } 1520 } 1521 1522 /* get put index for frame */ 1523 putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK) 1524 >> TXFQS_TFQPI_SHIFT); 1525 /* Write ID Field to FIFO Element */ 1526 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id); 1527 1528 /* get CAN FD configuration of frame */ 1529 fdflags = 0; 1530 if (can_is_canfd_skb(skb)) { 1531 fdflags |= TX_BUF_FDF; 1532 if (cf->flags & CANFD_BRS) 1533 fdflags |= TX_BUF_BRS; 1534 } 1535 1536 /* Construct DLC Field. Also contains CAN-FD configuration 1537 * use put index of fifo as message marker 1538 * it is used in TX interrupt for 1539 * sending the correct echo frame 1540 */ 1541 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC, 1542 ((putidx << TX_BUF_MM_SHIFT) & 1543 TX_BUF_MM_MASK) | 1544 (can_fd_len2dlc(cf->len) << 16) | 1545 fdflags | TX_BUF_EFC); 1546 1547 for (i = 0; i < cf->len; i += 4) 1548 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA(i / 4), 1549 *(u32 *)(cf->data + i)); 1550 1551 /* Push loopback echo. 1552 * Will be looped back on TX interrupt based on message marker 1553 */ 1554 can_put_echo_skb(skb, dev, putidx, 0); 1555 1556 /* Enable TX FIFO element to start transfer */ 1557 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx)); 1558 1559 /* stop network queue if fifo full */ 1560 if (m_can_tx_fifo_full(cdev) || 1561 m_can_next_echo_skb_occupied(dev, putidx)) 1562 netif_stop_queue(dev); 1563 } 1564 1565 return NETDEV_TX_OK; 1566 } 1567 1568 static void m_can_tx_work_queue(struct work_struct *ws) 1569 { 1570 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev, 1571 tx_work); 1572 1573 m_can_tx_handler(cdev); 1574 cdev->tx_skb = NULL; 1575 } 1576 1577 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, 1578 struct net_device *dev) 1579 { 1580 struct m_can_classdev *cdev = netdev_priv(dev); 1581 1582 if (can_dropped_invalid_skb(dev, skb)) 1583 return NETDEV_TX_OK; 1584 1585 if (cdev->is_peripheral) { 1586 if (cdev->tx_skb) { 1587 netdev_err(dev, "hard_xmit called while tx busy\n"); 1588 return NETDEV_TX_BUSY; 1589 } 1590 1591 if (cdev->can.state == CAN_STATE_BUS_OFF) { 1592 m_can_clean(dev); 1593 } else { 1594 /* Need to stop the queue to avoid numerous requests 1595 * from being sent. Suggested improvement is to create 1596 * a queueing mechanism that will queue the skbs and 1597 * process them in order. 1598 */ 1599 cdev->tx_skb = skb; 1600 netif_stop_queue(cdev->net); 1601 queue_work(cdev->tx_wq, &cdev->tx_work); 1602 } 1603 } else { 1604 cdev->tx_skb = skb; 1605 return m_can_tx_handler(cdev); 1606 } 1607 1608 return NETDEV_TX_OK; 1609 } 1610 1611 static int m_can_open(struct net_device *dev) 1612 { 1613 struct m_can_classdev *cdev = netdev_priv(dev); 1614 int err; 1615 1616 err = m_can_clk_start(cdev); 1617 if (err) 1618 return err; 1619 1620 /* open the can device */ 1621 err = open_candev(dev); 1622 if (err) { 1623 netdev_err(dev, "failed to open can device\n"); 1624 goto exit_disable_clks; 1625 } 1626 1627 /* register interrupt handler */ 1628 if (cdev->is_peripheral) { 1629 cdev->tx_skb = NULL; 1630 cdev->tx_wq = alloc_workqueue("mcan_wq", 1631 WQ_FREEZABLE | WQ_MEM_RECLAIM, 0); 1632 if (!cdev->tx_wq) { 1633 err = -ENOMEM; 1634 goto out_wq_fail; 1635 } 1636 1637 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue); 1638 1639 err = request_threaded_irq(dev->irq, NULL, m_can_isr, 1640 IRQF_ONESHOT, 1641 dev->name, dev); 1642 } else { 1643 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, 1644 dev); 1645 } 1646 1647 if (err < 0) { 1648 netdev_err(dev, "failed to request interrupt\n"); 1649 goto exit_irq_fail; 1650 } 1651 1652 /* start the m_can controller */ 1653 m_can_start(dev); 1654 1655 can_led_event(dev, CAN_LED_EVENT_OPEN); 1656 1657 if (!cdev->is_peripheral) 1658 napi_enable(&cdev->napi); 1659 1660 netif_start_queue(dev); 1661 1662 return 0; 1663 1664 exit_irq_fail: 1665 if (cdev->is_peripheral) 1666 destroy_workqueue(cdev->tx_wq); 1667 out_wq_fail: 1668 close_candev(dev); 1669 exit_disable_clks: 1670 m_can_clk_stop(cdev); 1671 return err; 1672 } 1673 1674 static const struct net_device_ops m_can_netdev_ops = { 1675 .ndo_open = m_can_open, 1676 .ndo_stop = m_can_close, 1677 .ndo_start_xmit = m_can_start_xmit, 1678 .ndo_change_mtu = can_change_mtu, 1679 }; 1680 1681 static int register_m_can_dev(struct net_device *dev) 1682 { 1683 dev->flags |= IFF_ECHO; /* we support local echo */ 1684 dev->netdev_ops = &m_can_netdev_ops; 1685 1686 return register_candev(dev); 1687 } 1688 1689 static void m_can_of_parse_mram(struct m_can_classdev *cdev, 1690 const u32 *mram_config_vals) 1691 { 1692 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; 1693 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; 1694 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + 1695 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; 1696 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; 1697 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + 1698 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; 1699 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & 1700 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1701 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + 1702 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; 1703 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & 1704 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1705 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + 1706 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; 1707 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; 1708 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + 1709 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; 1710 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; 1711 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + 1712 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; 1713 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & 1714 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT); 1715 1716 dev_dbg(cdev->dev, 1717 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", 1718 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num, 1719 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num, 1720 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num, 1721 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num, 1722 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num, 1723 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num, 1724 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num); 1725 } 1726 1727 void m_can_init_ram(struct m_can_classdev *cdev) 1728 { 1729 int end, i, start; 1730 1731 /* initialize the entire Message RAM in use to avoid possible 1732 * ECC/parity checksum errors when reading an uninitialized buffer 1733 */ 1734 start = cdev->mcfg[MRAM_SIDF].off; 1735 end = cdev->mcfg[MRAM_TXB].off + 1736 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 1737 1738 for (i = start; i < end; i += 4) 1739 m_can_fifo_write_no_off(cdev, i, 0x0); 1740 } 1741 EXPORT_SYMBOL_GPL(m_can_init_ram); 1742 1743 int m_can_class_get_clocks(struct m_can_classdev *cdev) 1744 { 1745 int ret = 0; 1746 1747 cdev->hclk = devm_clk_get(cdev->dev, "hclk"); 1748 cdev->cclk = devm_clk_get(cdev->dev, "cclk"); 1749 1750 if (IS_ERR(cdev->cclk)) { 1751 dev_err(cdev->dev, "no clock found\n"); 1752 ret = -ENODEV; 1753 } 1754 1755 return ret; 1756 } 1757 EXPORT_SYMBOL_GPL(m_can_class_get_clocks); 1758 1759 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, 1760 int sizeof_priv) 1761 { 1762 struct m_can_classdev *class_dev = NULL; 1763 u32 mram_config_vals[MRAM_CFG_LEN]; 1764 struct net_device *net_dev; 1765 u32 tx_fifo_size; 1766 int ret; 1767 1768 ret = fwnode_property_read_u32_array(dev_fwnode(dev), 1769 "bosch,mram-cfg", 1770 mram_config_vals, 1771 sizeof(mram_config_vals) / 4); 1772 if (ret) { 1773 dev_err(dev, "Could not get Message RAM configuration."); 1774 goto out; 1775 } 1776 1777 /* Get TX FIFO size 1778 * Defines the total amount of echo buffers for loopback 1779 */ 1780 tx_fifo_size = mram_config_vals[7]; 1781 1782 /* allocate the m_can device */ 1783 net_dev = alloc_candev(sizeof_priv, tx_fifo_size); 1784 if (!net_dev) { 1785 dev_err(dev, "Failed to allocate CAN device"); 1786 goto out; 1787 } 1788 1789 class_dev = netdev_priv(net_dev); 1790 if (!class_dev) { 1791 dev_err(dev, "Failed to init netdev cdevate"); 1792 goto out; 1793 } 1794 1795 class_dev->net = net_dev; 1796 class_dev->dev = dev; 1797 SET_NETDEV_DEV(net_dev, dev); 1798 1799 m_can_of_parse_mram(class_dev, mram_config_vals); 1800 out: 1801 return class_dev; 1802 } 1803 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev); 1804 1805 void m_can_class_free_dev(struct net_device *net) 1806 { 1807 free_candev(net); 1808 } 1809 EXPORT_SYMBOL_GPL(m_can_class_free_dev); 1810 1811 int m_can_class_register(struct m_can_classdev *cdev) 1812 { 1813 int ret; 1814 1815 if (cdev->pm_clock_support) { 1816 ret = m_can_clk_start(cdev); 1817 if (ret) 1818 return ret; 1819 } 1820 1821 ret = m_can_dev_setup(cdev); 1822 if (ret) 1823 goto clk_disable; 1824 1825 ret = register_m_can_dev(cdev->net); 1826 if (ret) { 1827 dev_err(cdev->dev, "registering %s failed (err=%d)\n", 1828 cdev->net->name, ret); 1829 goto clk_disable; 1830 } 1831 1832 devm_can_led_init(cdev->net); 1833 1834 of_can_transceiver(cdev->net); 1835 1836 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n", 1837 KBUILD_MODNAME, cdev->net->irq, cdev->version); 1838 1839 /* Probe finished 1840 * Stop clocks. They will be reactivated once the M_CAN device is opened 1841 */ 1842 clk_disable: 1843 m_can_clk_stop(cdev); 1844 1845 return ret; 1846 } 1847 EXPORT_SYMBOL_GPL(m_can_class_register); 1848 1849 void m_can_class_unregister(struct m_can_classdev *cdev) 1850 { 1851 unregister_candev(cdev->net); 1852 } 1853 EXPORT_SYMBOL_GPL(m_can_class_unregister); 1854 1855 int m_can_class_suspend(struct device *dev) 1856 { 1857 struct m_can_classdev *cdev = dev_get_drvdata(dev); 1858 struct net_device *ndev = cdev->net; 1859 1860 if (netif_running(ndev)) { 1861 netif_stop_queue(ndev); 1862 netif_device_detach(ndev); 1863 m_can_stop(ndev); 1864 m_can_clk_stop(cdev); 1865 } 1866 1867 pinctrl_pm_select_sleep_state(dev); 1868 1869 cdev->can.state = CAN_STATE_SLEEPING; 1870 1871 return 0; 1872 } 1873 EXPORT_SYMBOL_GPL(m_can_class_suspend); 1874 1875 int m_can_class_resume(struct device *dev) 1876 { 1877 struct m_can_classdev *cdev = dev_get_drvdata(dev); 1878 struct net_device *ndev = cdev->net; 1879 1880 pinctrl_pm_select_default_state(dev); 1881 1882 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 1883 1884 if (netif_running(ndev)) { 1885 int ret; 1886 1887 ret = m_can_clk_start(cdev); 1888 if (ret) 1889 return ret; 1890 1891 m_can_init_ram(cdev); 1892 m_can_start(ndev); 1893 netif_device_attach(ndev); 1894 netif_start_queue(ndev); 1895 } 1896 1897 return 0; 1898 } 1899 EXPORT_SYMBOL_GPL(m_can_class_resume); 1900 1901 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); 1902 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 1903 MODULE_LICENSE("GPL v2"); 1904 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); 1905