1 /* 2 * CAN bus driver for Bosch M_CAN controller 3 * 4 * Copyright (C) 2014 Freescale Semiconductor, Inc. 5 * Dong Aisheng <b29396@freescale.com> 6 * 7 * Bosch M_CAN user manual can be obtained from: 8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/ 9 * mcan_users_manual_v302.pdf 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/netdevice.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/platform_device.h> 26 #include <linux/iopoll.h> 27 #include <linux/can/dev.h> 28 29 /* napi related */ 30 #define M_CAN_NAPI_WEIGHT 64 31 32 /* message ram configuration data length */ 33 #define MRAM_CFG_LEN 8 34 35 /* registers definition */ 36 enum m_can_reg { 37 M_CAN_CREL = 0x0, 38 M_CAN_ENDN = 0x4, 39 M_CAN_CUST = 0x8, 40 M_CAN_DBTP = 0xc, 41 M_CAN_TEST = 0x10, 42 M_CAN_RWD = 0x14, 43 M_CAN_CCCR = 0x18, 44 M_CAN_NBTP = 0x1c, 45 M_CAN_TSCC = 0x20, 46 M_CAN_TSCV = 0x24, 47 M_CAN_TOCC = 0x28, 48 M_CAN_TOCV = 0x2c, 49 M_CAN_ECR = 0x40, 50 M_CAN_PSR = 0x44, 51 /* TDCR Register only available for version >=3.1.x */ 52 M_CAN_TDCR = 0x48, 53 M_CAN_IR = 0x50, 54 M_CAN_IE = 0x54, 55 M_CAN_ILS = 0x58, 56 M_CAN_ILE = 0x5c, 57 M_CAN_GFC = 0x80, 58 M_CAN_SIDFC = 0x84, 59 M_CAN_XIDFC = 0x88, 60 M_CAN_XIDAM = 0x90, 61 M_CAN_HPMS = 0x94, 62 M_CAN_NDAT1 = 0x98, 63 M_CAN_NDAT2 = 0x9c, 64 M_CAN_RXF0C = 0xa0, 65 M_CAN_RXF0S = 0xa4, 66 M_CAN_RXF0A = 0xa8, 67 M_CAN_RXBC = 0xac, 68 M_CAN_RXF1C = 0xb0, 69 M_CAN_RXF1S = 0xb4, 70 M_CAN_RXF1A = 0xb8, 71 M_CAN_RXESC = 0xbc, 72 M_CAN_TXBC = 0xc0, 73 M_CAN_TXFQS = 0xc4, 74 M_CAN_TXESC = 0xc8, 75 M_CAN_TXBRP = 0xcc, 76 M_CAN_TXBAR = 0xd0, 77 M_CAN_TXBCR = 0xd4, 78 M_CAN_TXBTO = 0xd8, 79 M_CAN_TXBCF = 0xdc, 80 M_CAN_TXBTIE = 0xe0, 81 M_CAN_TXBCIE = 0xe4, 82 M_CAN_TXEFC = 0xf0, 83 M_CAN_TXEFS = 0xf4, 84 M_CAN_TXEFA = 0xf8, 85 }; 86 87 /* m_can lec values */ 88 enum m_can_lec_type { 89 LEC_NO_ERROR = 0, 90 LEC_STUFF_ERROR, 91 LEC_FORM_ERROR, 92 LEC_ACK_ERROR, 93 LEC_BIT1_ERROR, 94 LEC_BIT0_ERROR, 95 LEC_CRC_ERROR, 96 LEC_UNUSED, 97 }; 98 99 enum m_can_mram_cfg { 100 MRAM_SIDF = 0, 101 MRAM_XIDF, 102 MRAM_RXF0, 103 MRAM_RXF1, 104 MRAM_RXB, 105 MRAM_TXE, 106 MRAM_TXB, 107 MRAM_CFG_NUM, 108 }; 109 110 /* Core Release Register (CREL) */ 111 #define CREL_REL_SHIFT 28 112 #define CREL_REL_MASK (0xF << CREL_REL_SHIFT) 113 #define CREL_STEP_SHIFT 24 114 #define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT) 115 #define CREL_SUBSTEP_SHIFT 20 116 #define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT) 117 118 /* Data Bit Timing & Prescaler Register (DBTP) */ 119 #define DBTP_TDC BIT(23) 120 #define DBTP_DBRP_SHIFT 16 121 #define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT) 122 #define DBTP_DTSEG1_SHIFT 8 123 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT) 124 #define DBTP_DTSEG2_SHIFT 4 125 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT) 126 #define DBTP_DSJW_SHIFT 0 127 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT) 128 129 /* Test Register (TEST) */ 130 #define TEST_LBCK BIT(4) 131 132 /* CC Control Register(CCCR) */ 133 #define CCCR_CMR_MASK 0x3 134 #define CCCR_CMR_SHIFT 10 135 #define CCCR_CMR_CANFD 0x1 136 #define CCCR_CMR_CANFD_BRS 0x2 137 #define CCCR_CMR_CAN 0x3 138 #define CCCR_CME_MASK 0x3 139 #define CCCR_CME_SHIFT 8 140 #define CCCR_CME_CAN 0 141 #define CCCR_CME_CANFD 0x1 142 #define CCCR_CME_CANFD_BRS 0x2 143 #define CCCR_TXP BIT(14) 144 #define CCCR_TEST BIT(7) 145 #define CCCR_MON BIT(5) 146 #define CCCR_CSR BIT(4) 147 #define CCCR_CSA BIT(3) 148 #define CCCR_ASM BIT(2) 149 #define CCCR_CCE BIT(1) 150 #define CCCR_INIT BIT(0) 151 #define CCCR_CANFD 0x10 152 /* for version >=3.1.x */ 153 #define CCCR_EFBI BIT(13) 154 #define CCCR_PXHD BIT(12) 155 #define CCCR_BRSE BIT(9) 156 #define CCCR_FDOE BIT(8) 157 /* only for version >=3.2.x */ 158 #define CCCR_NISO BIT(15) 159 160 /* Nominal Bit Timing & Prescaler Register (NBTP) */ 161 #define NBTP_NSJW_SHIFT 25 162 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT) 163 #define NBTP_NBRP_SHIFT 16 164 #define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT) 165 #define NBTP_NTSEG1_SHIFT 8 166 #define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT) 167 #define NBTP_NTSEG2_SHIFT 0 168 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT) 169 170 /* Error Counter Register(ECR) */ 171 #define ECR_RP BIT(15) 172 #define ECR_REC_SHIFT 8 173 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT) 174 #define ECR_TEC_SHIFT 0 175 #define ECR_TEC_MASK 0xff 176 177 /* Protocol Status Register(PSR) */ 178 #define PSR_BO BIT(7) 179 #define PSR_EW BIT(6) 180 #define PSR_EP BIT(5) 181 #define PSR_LEC_MASK 0x7 182 183 /* Interrupt Register(IR) */ 184 #define IR_ALL_INT 0xffffffff 185 186 /* Renamed bits for versions > 3.1.x */ 187 #define IR_ARA BIT(29) 188 #define IR_PED BIT(28) 189 #define IR_PEA BIT(27) 190 191 /* Bits for version 3.0.x */ 192 #define IR_STE BIT(31) 193 #define IR_FOE BIT(30) 194 #define IR_ACKE BIT(29) 195 #define IR_BE BIT(28) 196 #define IR_CRCE BIT(27) 197 #define IR_WDI BIT(26) 198 #define IR_BO BIT(25) 199 #define IR_EW BIT(24) 200 #define IR_EP BIT(23) 201 #define IR_ELO BIT(22) 202 #define IR_BEU BIT(21) 203 #define IR_BEC BIT(20) 204 #define IR_DRX BIT(19) 205 #define IR_TOO BIT(18) 206 #define IR_MRAF BIT(17) 207 #define IR_TSW BIT(16) 208 #define IR_TEFL BIT(15) 209 #define IR_TEFF BIT(14) 210 #define IR_TEFW BIT(13) 211 #define IR_TEFN BIT(12) 212 #define IR_TFE BIT(11) 213 #define IR_TCF BIT(10) 214 #define IR_TC BIT(9) 215 #define IR_HPM BIT(8) 216 #define IR_RF1L BIT(7) 217 #define IR_RF1F BIT(6) 218 #define IR_RF1W BIT(5) 219 #define IR_RF1N BIT(4) 220 #define IR_RF0L BIT(3) 221 #define IR_RF0F BIT(2) 222 #define IR_RF0W BIT(1) 223 #define IR_RF0N BIT(0) 224 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) 225 226 /* Interrupts for version 3.0.x */ 227 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) 228 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \ 229 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 230 IR_RF1L | IR_RF0L) 231 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X) 232 /* Interrupts for version >= 3.1.x */ 233 #define IR_ERR_LEC_31X (IR_PED | IR_PEA) 234 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \ 235 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 236 IR_RF1L | IR_RF0L) 237 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X) 238 239 /* Interrupt Line Select (ILS) */ 240 #define ILS_ALL_INT0 0x0 241 #define ILS_ALL_INT1 0xFFFFFFFF 242 243 /* Interrupt Line Enable (ILE) */ 244 #define ILE_EINT1 BIT(1) 245 #define ILE_EINT0 BIT(0) 246 247 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ 248 #define RXFC_FWM_SHIFT 24 249 #define RXFC_FWM_MASK (0x7f < RXFC_FWM_SHIFT) 250 #define RXFC_FS_SHIFT 16 251 #define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT) 252 253 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ 254 #define RXFS_RFL BIT(25) 255 #define RXFS_FF BIT(24) 256 #define RXFS_FPI_SHIFT 16 257 #define RXFS_FPI_MASK 0x3f0000 258 #define RXFS_FGI_SHIFT 8 259 #define RXFS_FGI_MASK 0x3f00 260 #define RXFS_FFL_MASK 0x7f 261 262 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ 263 #define M_CAN_RXESC_8BYTES 0x0 264 #define M_CAN_RXESC_64BYTES 0x777 265 266 /* Tx Buffer Configuration(TXBC) */ 267 #define TXBC_NDTB_SHIFT 16 268 #define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT) 269 #define TXBC_TFQS_SHIFT 24 270 #define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT) 271 272 /* Tx FIFO/Queue Status (TXFQS) */ 273 #define TXFQS_TFQF BIT(21) 274 #define TXFQS_TFQPI_SHIFT 16 275 #define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT) 276 #define TXFQS_TFGI_SHIFT 8 277 #define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT) 278 #define TXFQS_TFFL_SHIFT 0 279 #define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT) 280 281 /* Tx Buffer Element Size Configuration(TXESC) */ 282 #define TXESC_TBDS_8BYTES 0x0 283 #define TXESC_TBDS_64BYTES 0x7 284 285 /* Tx Event FIFO Configuration (TXEFC) */ 286 #define TXEFC_EFS_SHIFT 16 287 #define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT) 288 289 /* Tx Event FIFO Status (TXEFS) */ 290 #define TXEFS_TEFL BIT(25) 291 #define TXEFS_EFF BIT(24) 292 #define TXEFS_EFGI_SHIFT 8 293 #define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT) 294 #define TXEFS_EFFL_SHIFT 0 295 #define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT) 296 297 /* Tx Event FIFO Acknowledge (TXEFA) */ 298 #define TXEFA_EFAI_SHIFT 0 299 #define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT) 300 301 /* Message RAM Configuration (in bytes) */ 302 #define SIDF_ELEMENT_SIZE 4 303 #define XIDF_ELEMENT_SIZE 8 304 #define RXF0_ELEMENT_SIZE 72 305 #define RXF1_ELEMENT_SIZE 72 306 #define RXB_ELEMENT_SIZE 72 307 #define TXE_ELEMENT_SIZE 8 308 #define TXB_ELEMENT_SIZE 72 309 310 /* Message RAM Elements */ 311 #define M_CAN_FIFO_ID 0x0 312 #define M_CAN_FIFO_DLC 0x4 313 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2)) 314 315 /* Rx Buffer Element */ 316 /* R0 */ 317 #define RX_BUF_ESI BIT(31) 318 #define RX_BUF_XTD BIT(30) 319 #define RX_BUF_RTR BIT(29) 320 /* R1 */ 321 #define RX_BUF_ANMF BIT(31) 322 #define RX_BUF_FDF BIT(21) 323 #define RX_BUF_BRS BIT(20) 324 325 /* Tx Buffer Element */ 326 /* T0 */ 327 #define TX_BUF_ESI BIT(31) 328 #define TX_BUF_XTD BIT(30) 329 #define TX_BUF_RTR BIT(29) 330 /* T1 */ 331 #define TX_BUF_EFC BIT(23) 332 #define TX_BUF_FDF BIT(21) 333 #define TX_BUF_BRS BIT(20) 334 #define TX_BUF_MM_SHIFT 24 335 #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT) 336 337 /* Tx event FIFO Element */ 338 /* E1 */ 339 #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT 340 #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT) 341 342 /* address offset and element number for each FIFO/Buffer in the Message RAM */ 343 struct mram_cfg { 344 u16 off; 345 u8 num; 346 }; 347 348 /* m_can private data structure */ 349 struct m_can_priv { 350 struct can_priv can; /* must be the first member */ 351 struct napi_struct napi; 352 struct net_device *dev; 353 struct device *device; 354 struct clk *hclk; 355 struct clk *cclk; 356 void __iomem *base; 357 u32 irqstatus; 358 int version; 359 360 /* message ram configuration */ 361 void __iomem *mram_base; 362 struct mram_cfg mcfg[MRAM_CFG_NUM]; 363 }; 364 365 static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg) 366 { 367 return readl(priv->base + reg); 368 } 369 370 static inline void m_can_write(const struct m_can_priv *priv, 371 enum m_can_reg reg, u32 val) 372 { 373 writel(val, priv->base + reg); 374 } 375 376 static inline u32 m_can_fifo_read(const struct m_can_priv *priv, 377 u32 fgi, unsigned int offset) 378 { 379 return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off + 380 fgi * RXF0_ELEMENT_SIZE + offset); 381 } 382 383 static inline void m_can_fifo_write(const struct m_can_priv *priv, 384 u32 fpi, unsigned int offset, u32 val) 385 { 386 writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off + 387 fpi * TXB_ELEMENT_SIZE + offset); 388 } 389 390 static inline u32 m_can_txe_fifo_read(const struct m_can_priv *priv, 391 u32 fgi, 392 u32 offset) { 393 return readl(priv->mram_base + priv->mcfg[MRAM_TXE].off + 394 fgi * TXE_ELEMENT_SIZE + offset); 395 } 396 397 static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv) 398 { 399 return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF); 400 } 401 402 static inline void m_can_config_endisable(const struct m_can_priv *priv, 403 bool enable) 404 { 405 u32 cccr = m_can_read(priv, M_CAN_CCCR); 406 u32 timeout = 10; 407 u32 val = 0; 408 409 if (enable) { 410 /* enable m_can configuration */ 411 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT); 412 udelay(5); 413 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ 414 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); 415 } else { 416 m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); 417 } 418 419 /* there's a delay for module initialization */ 420 if (enable) 421 val = CCCR_INIT | CCCR_CCE; 422 423 while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { 424 if (timeout == 0) { 425 netdev_warn(priv->dev, "Failed to init module\n"); 426 return; 427 } 428 timeout--; 429 udelay(1); 430 } 431 } 432 433 static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv) 434 { 435 /* Only interrupt line 0 is used in this driver */ 436 m_can_write(priv, M_CAN_ILE, ILE_EINT0); 437 } 438 439 static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv) 440 { 441 m_can_write(priv, M_CAN_ILE, 0x0); 442 } 443 444 static void m_can_read_fifo(struct net_device *dev, u32 rxfs) 445 { 446 struct net_device_stats *stats = &dev->stats; 447 struct m_can_priv *priv = netdev_priv(dev); 448 struct canfd_frame *cf; 449 struct sk_buff *skb; 450 u32 id, fgi, dlc; 451 int i; 452 453 /* calculate the fifo get index for where to read data */ 454 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT; 455 dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC); 456 if (dlc & RX_BUF_FDF) 457 skb = alloc_canfd_skb(dev, &cf); 458 else 459 skb = alloc_can_skb(dev, (struct can_frame **)&cf); 460 if (!skb) { 461 stats->rx_dropped++; 462 return; 463 } 464 465 if (dlc & RX_BUF_FDF) 466 cf->len = can_dlc2len((dlc >> 16) & 0x0F); 467 else 468 cf->len = get_can_dlc((dlc >> 16) & 0x0F); 469 470 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID); 471 if (id & RX_BUF_XTD) 472 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 473 else 474 cf->can_id = (id >> 18) & CAN_SFF_MASK; 475 476 if (id & RX_BUF_ESI) { 477 cf->flags |= CANFD_ESI; 478 netdev_dbg(dev, "ESI Error\n"); 479 } 480 481 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) { 482 cf->can_id |= CAN_RTR_FLAG; 483 } else { 484 if (dlc & RX_BUF_BRS) 485 cf->flags |= CANFD_BRS; 486 487 for (i = 0; i < cf->len; i += 4) 488 *(u32 *)(cf->data + i) = 489 m_can_fifo_read(priv, fgi, 490 M_CAN_FIFO_DATA(i / 4)); 491 } 492 493 /* acknowledge rx fifo 0 */ 494 m_can_write(priv, M_CAN_RXF0A, fgi); 495 496 stats->rx_packets++; 497 stats->rx_bytes += cf->len; 498 499 netif_receive_skb(skb); 500 } 501 502 static int m_can_do_rx_poll(struct net_device *dev, int quota) 503 { 504 struct m_can_priv *priv = netdev_priv(dev); 505 u32 pkts = 0; 506 u32 rxfs; 507 508 rxfs = m_can_read(priv, M_CAN_RXF0S); 509 if (!(rxfs & RXFS_FFL_MASK)) { 510 netdev_dbg(dev, "no messages in fifo0\n"); 511 return 0; 512 } 513 514 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) { 515 if (rxfs & RXFS_RFL) 516 netdev_warn(dev, "Rx FIFO 0 Message Lost\n"); 517 518 m_can_read_fifo(dev, rxfs); 519 520 quota--; 521 pkts++; 522 rxfs = m_can_read(priv, M_CAN_RXF0S); 523 } 524 525 if (pkts) 526 can_led_event(dev, CAN_LED_EVENT_RX); 527 528 return pkts; 529 } 530 531 static int m_can_handle_lost_msg(struct net_device *dev) 532 { 533 struct net_device_stats *stats = &dev->stats; 534 struct sk_buff *skb; 535 struct can_frame *frame; 536 537 netdev_err(dev, "msg lost in rxf0\n"); 538 539 stats->rx_errors++; 540 stats->rx_over_errors++; 541 542 skb = alloc_can_err_skb(dev, &frame); 543 if (unlikely(!skb)) 544 return 0; 545 546 frame->can_id |= CAN_ERR_CRTL; 547 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 548 549 netif_receive_skb(skb); 550 551 return 1; 552 } 553 554 static int m_can_handle_lec_err(struct net_device *dev, 555 enum m_can_lec_type lec_type) 556 { 557 struct m_can_priv *priv = netdev_priv(dev); 558 struct net_device_stats *stats = &dev->stats; 559 struct can_frame *cf; 560 struct sk_buff *skb; 561 562 priv->can.can_stats.bus_error++; 563 stats->rx_errors++; 564 565 /* propagate the error condition to the CAN stack */ 566 skb = alloc_can_err_skb(dev, &cf); 567 if (unlikely(!skb)) 568 return 0; 569 570 /* check for 'last error code' which tells us the 571 * type of the last error to occur on the CAN bus 572 */ 573 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 574 575 switch (lec_type) { 576 case LEC_STUFF_ERROR: 577 netdev_dbg(dev, "stuff error\n"); 578 cf->data[2] |= CAN_ERR_PROT_STUFF; 579 break; 580 case LEC_FORM_ERROR: 581 netdev_dbg(dev, "form error\n"); 582 cf->data[2] |= CAN_ERR_PROT_FORM; 583 break; 584 case LEC_ACK_ERROR: 585 netdev_dbg(dev, "ack error\n"); 586 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 587 break; 588 case LEC_BIT1_ERROR: 589 netdev_dbg(dev, "bit1 error\n"); 590 cf->data[2] |= CAN_ERR_PROT_BIT1; 591 break; 592 case LEC_BIT0_ERROR: 593 netdev_dbg(dev, "bit0 error\n"); 594 cf->data[2] |= CAN_ERR_PROT_BIT0; 595 break; 596 case LEC_CRC_ERROR: 597 netdev_dbg(dev, "CRC error\n"); 598 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 599 break; 600 default: 601 break; 602 } 603 604 stats->rx_packets++; 605 stats->rx_bytes += cf->can_dlc; 606 netif_receive_skb(skb); 607 608 return 1; 609 } 610 611 static int __m_can_get_berr_counter(const struct net_device *dev, 612 struct can_berr_counter *bec) 613 { 614 struct m_can_priv *priv = netdev_priv(dev); 615 unsigned int ecr; 616 617 ecr = m_can_read(priv, M_CAN_ECR); 618 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT; 619 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT; 620 621 return 0; 622 } 623 624 static int m_can_get_berr_counter(const struct net_device *dev, 625 struct can_berr_counter *bec) 626 { 627 struct m_can_priv *priv = netdev_priv(dev); 628 int err; 629 630 err = clk_prepare_enable(priv->hclk); 631 if (err) 632 return err; 633 634 err = clk_prepare_enable(priv->cclk); 635 if (err) { 636 clk_disable_unprepare(priv->hclk); 637 return err; 638 } 639 640 __m_can_get_berr_counter(dev, bec); 641 642 clk_disable_unprepare(priv->cclk); 643 clk_disable_unprepare(priv->hclk); 644 645 return 0; 646 } 647 648 static int m_can_handle_state_change(struct net_device *dev, 649 enum can_state new_state) 650 { 651 struct m_can_priv *priv = netdev_priv(dev); 652 struct net_device_stats *stats = &dev->stats; 653 struct can_frame *cf; 654 struct sk_buff *skb; 655 struct can_berr_counter bec; 656 unsigned int ecr; 657 658 switch (new_state) { 659 case CAN_STATE_ERROR_ACTIVE: 660 /* error warning state */ 661 priv->can.can_stats.error_warning++; 662 priv->can.state = CAN_STATE_ERROR_WARNING; 663 break; 664 case CAN_STATE_ERROR_PASSIVE: 665 /* error passive state */ 666 priv->can.can_stats.error_passive++; 667 priv->can.state = CAN_STATE_ERROR_PASSIVE; 668 break; 669 case CAN_STATE_BUS_OFF: 670 /* bus-off state */ 671 priv->can.state = CAN_STATE_BUS_OFF; 672 m_can_disable_all_interrupts(priv); 673 priv->can.can_stats.bus_off++; 674 can_bus_off(dev); 675 break; 676 default: 677 break; 678 } 679 680 /* propagate the error condition to the CAN stack */ 681 skb = alloc_can_err_skb(dev, &cf); 682 if (unlikely(!skb)) 683 return 0; 684 685 __m_can_get_berr_counter(dev, &bec); 686 687 switch (new_state) { 688 case CAN_STATE_ERROR_ACTIVE: 689 /* error warning state */ 690 cf->can_id |= CAN_ERR_CRTL; 691 cf->data[1] = (bec.txerr > bec.rxerr) ? 692 CAN_ERR_CRTL_TX_WARNING : 693 CAN_ERR_CRTL_RX_WARNING; 694 cf->data[6] = bec.txerr; 695 cf->data[7] = bec.rxerr; 696 break; 697 case CAN_STATE_ERROR_PASSIVE: 698 /* error passive state */ 699 cf->can_id |= CAN_ERR_CRTL; 700 ecr = m_can_read(priv, M_CAN_ECR); 701 if (ecr & ECR_RP) 702 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 703 if (bec.txerr > 127) 704 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 705 cf->data[6] = bec.txerr; 706 cf->data[7] = bec.rxerr; 707 break; 708 case CAN_STATE_BUS_OFF: 709 /* bus-off state */ 710 cf->can_id |= CAN_ERR_BUSOFF; 711 break; 712 default: 713 break; 714 } 715 716 stats->rx_packets++; 717 stats->rx_bytes += cf->can_dlc; 718 netif_receive_skb(skb); 719 720 return 1; 721 } 722 723 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) 724 { 725 struct m_can_priv *priv = netdev_priv(dev); 726 int work_done = 0; 727 728 if ((psr & PSR_EW) && 729 (priv->can.state != CAN_STATE_ERROR_WARNING)) { 730 netdev_dbg(dev, "entered error warning state\n"); 731 work_done += m_can_handle_state_change(dev, 732 CAN_STATE_ERROR_WARNING); 733 } 734 735 if ((psr & PSR_EP) && 736 (priv->can.state != CAN_STATE_ERROR_PASSIVE)) { 737 netdev_dbg(dev, "entered error passive state\n"); 738 work_done += m_can_handle_state_change(dev, 739 CAN_STATE_ERROR_PASSIVE); 740 } 741 742 if ((psr & PSR_BO) && 743 (priv->can.state != CAN_STATE_BUS_OFF)) { 744 netdev_dbg(dev, "entered error bus off state\n"); 745 work_done += m_can_handle_state_change(dev, 746 CAN_STATE_BUS_OFF); 747 } 748 749 return work_done; 750 } 751 752 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) 753 { 754 if (irqstatus & IR_WDI) 755 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); 756 if (irqstatus & IR_ELO) 757 netdev_err(dev, "Error Logging Overflow\n"); 758 if (irqstatus & IR_BEU) 759 netdev_err(dev, "Bit Error Uncorrected\n"); 760 if (irqstatus & IR_BEC) 761 netdev_err(dev, "Bit Error Corrected\n"); 762 if (irqstatus & IR_TOO) 763 netdev_err(dev, "Timeout reached\n"); 764 if (irqstatus & IR_MRAF) 765 netdev_err(dev, "Message RAM access failure occurred\n"); 766 } 767 768 static inline bool is_lec_err(u32 psr) 769 { 770 psr &= LEC_UNUSED; 771 772 return psr && (psr != LEC_UNUSED); 773 } 774 775 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, 776 u32 psr) 777 { 778 struct m_can_priv *priv = netdev_priv(dev); 779 int work_done = 0; 780 781 if (irqstatus & IR_RF0L) 782 work_done += m_can_handle_lost_msg(dev); 783 784 /* handle lec errors on the bus */ 785 if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 786 is_lec_err(psr)) 787 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED); 788 789 /* other unproccessed error interrupts */ 790 m_can_handle_other_err(dev, irqstatus); 791 792 return work_done; 793 } 794 795 static int m_can_poll(struct napi_struct *napi, int quota) 796 { 797 struct net_device *dev = napi->dev; 798 struct m_can_priv *priv = netdev_priv(dev); 799 int work_done = 0; 800 u32 irqstatus, psr; 801 802 irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR); 803 if (!irqstatus) 804 goto end; 805 806 psr = m_can_read(priv, M_CAN_PSR); 807 if (irqstatus & IR_ERR_STATE) 808 work_done += m_can_handle_state_errors(dev, psr); 809 810 if (irqstatus & IR_ERR_BUS_30X) 811 work_done += m_can_handle_bus_errors(dev, irqstatus, psr); 812 813 if (irqstatus & IR_RF0N) 814 work_done += m_can_do_rx_poll(dev, (quota - work_done)); 815 816 if (work_done < quota) { 817 napi_complete_done(napi, work_done); 818 m_can_enable_all_interrupts(priv); 819 } 820 821 end: 822 return work_done; 823 } 824 825 static void m_can_echo_tx_event(struct net_device *dev) 826 { 827 u32 txe_count = 0; 828 u32 m_can_txefs; 829 u32 fgi = 0; 830 int i = 0; 831 unsigned int msg_mark; 832 833 struct m_can_priv *priv = netdev_priv(dev); 834 struct net_device_stats *stats = &dev->stats; 835 836 /* read tx event fifo status */ 837 m_can_txefs = m_can_read(priv, M_CAN_TXEFS); 838 839 /* Get Tx Event fifo element count */ 840 txe_count = (m_can_txefs & TXEFS_EFFL_MASK) 841 >> TXEFS_EFFL_SHIFT; 842 843 /* Get and process all sent elements */ 844 for (i = 0; i < txe_count; i++) { 845 /* retrieve get index */ 846 fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK) 847 >> TXEFS_EFGI_SHIFT; 848 849 /* get message marker */ 850 msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) & 851 TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT; 852 853 /* ack txe element */ 854 m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK & 855 (fgi << TXEFA_EFAI_SHIFT))); 856 857 /* update stats */ 858 stats->tx_bytes += can_get_echo_skb(dev, msg_mark); 859 stats->tx_packets++; 860 } 861 } 862 863 static irqreturn_t m_can_isr(int irq, void *dev_id) 864 { 865 struct net_device *dev = (struct net_device *)dev_id; 866 struct m_can_priv *priv = netdev_priv(dev); 867 struct net_device_stats *stats = &dev->stats; 868 u32 ir; 869 870 ir = m_can_read(priv, M_CAN_IR); 871 if (!ir) 872 return IRQ_NONE; 873 874 /* ACK all irqs */ 875 if (ir & IR_ALL_INT) 876 m_can_write(priv, M_CAN_IR, ir); 877 878 /* schedule NAPI in case of 879 * - rx IRQ 880 * - state change IRQ 881 * - bus error IRQ and bus error reporting 882 */ 883 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) { 884 priv->irqstatus = ir; 885 m_can_disable_all_interrupts(priv); 886 napi_schedule(&priv->napi); 887 } 888 889 if (priv->version == 30) { 890 if (ir & IR_TC) { 891 /* Transmission Complete Interrupt*/ 892 stats->tx_bytes += can_get_echo_skb(dev, 0); 893 stats->tx_packets++; 894 can_led_event(dev, CAN_LED_EVENT_TX); 895 netif_wake_queue(dev); 896 } 897 } else { 898 if (ir & IR_TEFN) { 899 /* New TX FIFO Element arrived */ 900 m_can_echo_tx_event(dev); 901 can_led_event(dev, CAN_LED_EVENT_TX); 902 if (netif_queue_stopped(dev) && 903 !m_can_tx_fifo_full(priv)) 904 netif_wake_queue(dev); 905 } 906 } 907 908 return IRQ_HANDLED; 909 } 910 911 static const struct can_bittiming_const m_can_bittiming_const_30X = { 912 .name = KBUILD_MODNAME, 913 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 914 .tseg1_max = 64, 915 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 916 .tseg2_max = 16, 917 .sjw_max = 16, 918 .brp_min = 1, 919 .brp_max = 1024, 920 .brp_inc = 1, 921 }; 922 923 static const struct can_bittiming_const m_can_data_bittiming_const_30X = { 924 .name = KBUILD_MODNAME, 925 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 926 .tseg1_max = 16, 927 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 928 .tseg2_max = 8, 929 .sjw_max = 4, 930 .brp_min = 1, 931 .brp_max = 32, 932 .brp_inc = 1, 933 }; 934 935 static const struct can_bittiming_const m_can_bittiming_const_31X = { 936 .name = KBUILD_MODNAME, 937 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 938 .tseg1_max = 256, 939 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 940 .tseg2_max = 128, 941 .sjw_max = 128, 942 .brp_min = 1, 943 .brp_max = 512, 944 .brp_inc = 1, 945 }; 946 947 static const struct can_bittiming_const m_can_data_bittiming_const_31X = { 948 .name = KBUILD_MODNAME, 949 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */ 950 .tseg1_max = 32, 951 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 952 .tseg2_max = 16, 953 .sjw_max = 16, 954 .brp_min = 1, 955 .brp_max = 32, 956 .brp_inc = 1, 957 }; 958 959 static int m_can_set_bittiming(struct net_device *dev) 960 { 961 struct m_can_priv *priv = netdev_priv(dev); 962 const struct can_bittiming *bt = &priv->can.bittiming; 963 const struct can_bittiming *dbt = &priv->can.data_bittiming; 964 u16 brp, sjw, tseg1, tseg2; 965 u32 reg_btp; 966 967 brp = bt->brp - 1; 968 sjw = bt->sjw - 1; 969 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 970 tseg2 = bt->phase_seg2 - 1; 971 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) | 972 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT); 973 m_can_write(priv, M_CAN_NBTP, reg_btp); 974 975 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 976 brp = dbt->brp - 1; 977 sjw = dbt->sjw - 1; 978 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; 979 tseg2 = dbt->phase_seg2 - 1; 980 reg_btp = (brp << DBTP_DBRP_SHIFT) | (sjw << DBTP_DSJW_SHIFT) | 981 (tseg1 << DBTP_DTSEG1_SHIFT) | 982 (tseg2 << DBTP_DTSEG2_SHIFT); 983 m_can_write(priv, M_CAN_DBTP, reg_btp); 984 } 985 986 return 0; 987 } 988 989 /* Configure M_CAN chip: 990 * - set rx buffer/fifo element size 991 * - configure rx fifo 992 * - accept non-matching frame into fifo 0 993 * - configure tx buffer 994 * - >= v3.1.x: TX FIFO is used 995 * - configure mode 996 * - setup bittiming 997 */ 998 static void m_can_chip_config(struct net_device *dev) 999 { 1000 struct m_can_priv *priv = netdev_priv(dev); 1001 u32 cccr, test; 1002 1003 m_can_config_endisable(priv, true); 1004 1005 /* RX Buffer/FIFO Element Size 64 bytes data field */ 1006 m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_64BYTES); 1007 1008 /* Accept Non-matching Frames Into FIFO 0 */ 1009 m_can_write(priv, M_CAN_GFC, 0x0); 1010 1011 if (priv->version == 30) { 1012 /* only support one Tx Buffer currently */ 1013 m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) | 1014 priv->mcfg[MRAM_TXB].off); 1015 } else { 1016 /* TX FIFO is used for newer IP Core versions */ 1017 m_can_write(priv, M_CAN_TXBC, 1018 (priv->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) | 1019 (priv->mcfg[MRAM_TXB].off)); 1020 } 1021 1022 /* support 64 bytes payload */ 1023 m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES); 1024 1025 /* TX Event FIFO */ 1026 if (priv->version == 30) { 1027 m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) | 1028 priv->mcfg[MRAM_TXE].off); 1029 } else { 1030 /* Full TX Event FIFO is used */ 1031 m_can_write(priv, M_CAN_TXEFC, 1032 ((priv->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT) 1033 & TXEFC_EFS_MASK) | 1034 priv->mcfg[MRAM_TXE].off); 1035 } 1036 1037 /* rx fifo configuration, blocking mode, fifo size 1 */ 1038 m_can_write(priv, M_CAN_RXF0C, 1039 (priv->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) | 1040 priv->mcfg[MRAM_RXF0].off); 1041 1042 m_can_write(priv, M_CAN_RXF1C, 1043 (priv->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) | 1044 priv->mcfg[MRAM_RXF1].off); 1045 1046 cccr = m_can_read(priv, M_CAN_CCCR); 1047 test = m_can_read(priv, M_CAN_TEST); 1048 test &= ~TEST_LBCK; 1049 if (priv->version == 30) { 1050 /* Version 3.0.x */ 1051 1052 cccr &= ~(CCCR_TEST | CCCR_MON | 1053 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | 1054 (CCCR_CME_MASK << CCCR_CME_SHIFT)); 1055 1056 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1057 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT; 1058 1059 } else { 1060 /* Version 3.1.x or 3.2.x */ 1061 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE); 1062 1063 /* Only 3.2.x has NISO Bit implemented */ 1064 if (priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 1065 cccr |= CCCR_NISO; 1066 1067 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1068 cccr |= (CCCR_BRSE | CCCR_FDOE); 1069 } 1070 1071 /* Loopback Mode */ 1072 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1073 cccr |= CCCR_TEST | CCCR_MON; 1074 test |= TEST_LBCK; 1075 } 1076 1077 /* Enable Monitoring (all versions) */ 1078 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1079 cccr |= CCCR_MON; 1080 1081 /* Write config */ 1082 m_can_write(priv, M_CAN_CCCR, cccr); 1083 m_can_write(priv, M_CAN_TEST, test); 1084 1085 /* Enable interrupts */ 1086 m_can_write(priv, M_CAN_IR, IR_ALL_INT); 1087 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1088 if (priv->version == 30) 1089 m_can_write(priv, M_CAN_IE, IR_ALL_INT & 1090 ~(IR_ERR_LEC_30X)); 1091 else 1092 m_can_write(priv, M_CAN_IE, IR_ALL_INT & 1093 ~(IR_ERR_LEC_31X)); 1094 else 1095 m_can_write(priv, M_CAN_IE, IR_ALL_INT); 1096 1097 /* route all interrupts to INT0 */ 1098 m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0); 1099 1100 /* set bittiming params */ 1101 m_can_set_bittiming(dev); 1102 1103 m_can_config_endisable(priv, false); 1104 } 1105 1106 static void m_can_start(struct net_device *dev) 1107 { 1108 struct m_can_priv *priv = netdev_priv(dev); 1109 1110 /* basic m_can configuration */ 1111 m_can_chip_config(dev); 1112 1113 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1114 1115 m_can_enable_all_interrupts(priv); 1116 } 1117 1118 static int m_can_set_mode(struct net_device *dev, enum can_mode mode) 1119 { 1120 switch (mode) { 1121 case CAN_MODE_START: 1122 m_can_start(dev); 1123 netif_wake_queue(dev); 1124 break; 1125 default: 1126 return -EOPNOTSUPP; 1127 } 1128 1129 return 0; 1130 } 1131 1132 static void free_m_can_dev(struct net_device *dev) 1133 { 1134 free_candev(dev); 1135 } 1136 1137 /* Checks core release number of M_CAN 1138 * returns 0 if an unsupported device is detected 1139 * else it returns the release and step coded as: 1140 * return value = 10 * <release> + 1 * <step> 1141 */ 1142 static int m_can_check_core_release(void __iomem *m_can_base) 1143 { 1144 u32 crel_reg; 1145 u8 rel; 1146 u8 step; 1147 int res; 1148 struct m_can_priv temp_priv = { 1149 .base = m_can_base 1150 }; 1151 1152 /* Read Core Release Version and split into version number 1153 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; 1154 */ 1155 crel_reg = m_can_read(&temp_priv, M_CAN_CREL); 1156 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT); 1157 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT); 1158 1159 if (rel == 3) { 1160 /* M_CAN v3.x.y: create return value */ 1161 res = 30 + step; 1162 } else { 1163 /* Unsupported M_CAN version */ 1164 res = 0; 1165 } 1166 1167 return res; 1168 } 1169 1170 /* Selectable Non ISO support only in version 3.2.x 1171 * This function checks if the bit is writable. 1172 */ 1173 static bool m_can_niso_supported(const struct m_can_priv *priv) 1174 { 1175 u32 cccr_reg, cccr_poll; 1176 int niso_timeout; 1177 1178 m_can_config_endisable(priv, true); 1179 cccr_reg = m_can_read(priv, M_CAN_CCCR); 1180 cccr_reg |= CCCR_NISO; 1181 m_can_write(priv, M_CAN_CCCR, cccr_reg); 1182 1183 niso_timeout = readl_poll_timeout((priv->base + M_CAN_CCCR), cccr_poll, 1184 (cccr_poll == cccr_reg), 0, 10); 1185 1186 /* Clear NISO */ 1187 cccr_reg &= ~(CCCR_NISO); 1188 m_can_write(priv, M_CAN_CCCR, cccr_reg); 1189 1190 m_can_config_endisable(priv, false); 1191 1192 /* return false if time out (-ETIMEDOUT), else return true */ 1193 return !niso_timeout; 1194 } 1195 1196 static struct net_device *alloc_m_can_dev(struct platform_device *pdev, 1197 void __iomem *addr, u32 tx_fifo_size) 1198 { 1199 struct net_device *dev; 1200 struct m_can_priv *priv; 1201 int m_can_version; 1202 unsigned int echo_buffer_count; 1203 1204 m_can_version = m_can_check_core_release(addr); 1205 /* return if unsupported version */ 1206 if (!m_can_version) { 1207 dev = NULL; 1208 goto return_dev; 1209 } 1210 1211 /* If version < 3.1.x, then only one echo buffer is used */ 1212 echo_buffer_count = ((m_can_version == 30) 1213 ? 1U 1214 : (unsigned int)tx_fifo_size); 1215 1216 dev = alloc_candev(sizeof(*priv), echo_buffer_count); 1217 if (!dev) { 1218 dev = NULL; 1219 goto return_dev; 1220 } 1221 priv = netdev_priv(dev); 1222 netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT); 1223 1224 /* Shared properties of all M_CAN versions */ 1225 priv->version = m_can_version; 1226 priv->dev = dev; 1227 priv->base = addr; 1228 priv->can.do_set_mode = m_can_set_mode; 1229 priv->can.do_get_berr_counter = m_can_get_berr_counter; 1230 1231 /* Set M_CAN supported operations */ 1232 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1233 CAN_CTRLMODE_LISTENONLY | 1234 CAN_CTRLMODE_BERR_REPORTING | 1235 CAN_CTRLMODE_FD; 1236 1237 /* Set properties depending on M_CAN version */ 1238 switch (priv->version) { 1239 case 30: 1240 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ 1241 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1242 priv->can.bittiming_const = &m_can_bittiming_const_30X; 1243 priv->can.data_bittiming_const = 1244 &m_can_data_bittiming_const_30X; 1245 break; 1246 case 31: 1247 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ 1248 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1249 priv->can.bittiming_const = &m_can_bittiming_const_31X; 1250 priv->can.data_bittiming_const = 1251 &m_can_data_bittiming_const_31X; 1252 break; 1253 case 32: 1254 priv->can.bittiming_const = &m_can_bittiming_const_31X; 1255 priv->can.data_bittiming_const = 1256 &m_can_data_bittiming_const_31X; 1257 priv->can.ctrlmode_supported |= (m_can_niso_supported(priv) 1258 ? CAN_CTRLMODE_FD_NON_ISO 1259 : 0); 1260 break; 1261 default: 1262 /* Unsupported device: free candev */ 1263 free_m_can_dev(dev); 1264 dev_err(&pdev->dev, "Unsupported version number: %2d", 1265 priv->version); 1266 dev = NULL; 1267 break; 1268 } 1269 1270 return_dev: 1271 return dev; 1272 } 1273 1274 static int m_can_open(struct net_device *dev) 1275 { 1276 struct m_can_priv *priv = netdev_priv(dev); 1277 int err; 1278 1279 err = clk_prepare_enable(priv->hclk); 1280 if (err) 1281 return err; 1282 1283 err = clk_prepare_enable(priv->cclk); 1284 if (err) 1285 goto exit_disable_hclk; 1286 1287 /* open the can device */ 1288 err = open_candev(dev); 1289 if (err) { 1290 netdev_err(dev, "failed to open can device\n"); 1291 goto exit_disable_cclk; 1292 } 1293 1294 /* register interrupt handler */ 1295 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, 1296 dev); 1297 if (err < 0) { 1298 netdev_err(dev, "failed to request interrupt\n"); 1299 goto exit_irq_fail; 1300 } 1301 1302 /* start the m_can controller */ 1303 m_can_start(dev); 1304 1305 can_led_event(dev, CAN_LED_EVENT_OPEN); 1306 napi_enable(&priv->napi); 1307 netif_start_queue(dev); 1308 1309 return 0; 1310 1311 exit_irq_fail: 1312 close_candev(dev); 1313 exit_disable_cclk: 1314 clk_disable_unprepare(priv->cclk); 1315 exit_disable_hclk: 1316 clk_disable_unprepare(priv->hclk); 1317 return err; 1318 } 1319 1320 static void m_can_stop(struct net_device *dev) 1321 { 1322 struct m_can_priv *priv = netdev_priv(dev); 1323 1324 /* disable all interrupts */ 1325 m_can_disable_all_interrupts(priv); 1326 1327 clk_disable_unprepare(priv->hclk); 1328 clk_disable_unprepare(priv->cclk); 1329 1330 /* set the state as STOPPED */ 1331 priv->can.state = CAN_STATE_STOPPED; 1332 } 1333 1334 static int m_can_close(struct net_device *dev) 1335 { 1336 struct m_can_priv *priv = netdev_priv(dev); 1337 1338 netif_stop_queue(dev); 1339 napi_disable(&priv->napi); 1340 m_can_stop(dev); 1341 free_irq(dev->irq, dev); 1342 close_candev(dev); 1343 can_led_event(dev, CAN_LED_EVENT_STOP); 1344 1345 return 0; 1346 } 1347 1348 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx) 1349 { 1350 struct m_can_priv *priv = netdev_priv(dev); 1351 /*get wrap around for loopback skb index */ 1352 unsigned int wrap = priv->can.echo_skb_max; 1353 int next_idx; 1354 1355 /* calculate next index */ 1356 next_idx = (++putidx >= wrap ? 0 : putidx); 1357 1358 /* check if occupied */ 1359 return !!priv->can.echo_skb[next_idx]; 1360 } 1361 1362 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, 1363 struct net_device *dev) 1364 { 1365 struct m_can_priv *priv = netdev_priv(dev); 1366 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 1367 u32 id, cccr, fdflags; 1368 int i; 1369 int putidx; 1370 1371 if (can_dropped_invalid_skb(dev, skb)) 1372 return NETDEV_TX_OK; 1373 1374 /* Generate ID field for TX buffer Element */ 1375 /* Common to all supported M_CAN versions */ 1376 if (cf->can_id & CAN_EFF_FLAG) { 1377 id = cf->can_id & CAN_EFF_MASK; 1378 id |= TX_BUF_XTD; 1379 } else { 1380 id = ((cf->can_id & CAN_SFF_MASK) << 18); 1381 } 1382 1383 if (cf->can_id & CAN_RTR_FLAG) 1384 id |= TX_BUF_RTR; 1385 1386 if (priv->version == 30) { 1387 netif_stop_queue(dev); 1388 1389 /* message ram configuration */ 1390 m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id); 1391 m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, 1392 can_len2dlc(cf->len) << 16); 1393 1394 for (i = 0; i < cf->len; i += 4) 1395 m_can_fifo_write(priv, 0, 1396 M_CAN_FIFO_DATA(i / 4), 1397 *(u32 *)(cf->data + i)); 1398 1399 can_put_echo_skb(skb, dev, 0); 1400 1401 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1402 cccr = m_can_read(priv, M_CAN_CCCR); 1403 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT); 1404 if (can_is_canfd_skb(skb)) { 1405 if (cf->flags & CANFD_BRS) 1406 cccr |= CCCR_CMR_CANFD_BRS << 1407 CCCR_CMR_SHIFT; 1408 else 1409 cccr |= CCCR_CMR_CANFD << 1410 CCCR_CMR_SHIFT; 1411 } else { 1412 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT; 1413 } 1414 m_can_write(priv, M_CAN_CCCR, cccr); 1415 } 1416 m_can_write(priv, M_CAN_TXBTIE, 0x1); 1417 m_can_write(priv, M_CAN_TXBAR, 0x1); 1418 /* End of xmit function for version 3.0.x */ 1419 } else { 1420 /* Transmit routine for version >= v3.1.x */ 1421 1422 /* Check if FIFO full */ 1423 if (m_can_tx_fifo_full(priv)) { 1424 /* This shouldn't happen */ 1425 netif_stop_queue(dev); 1426 netdev_warn(dev, 1427 "TX queue active although FIFO is full."); 1428 return NETDEV_TX_BUSY; 1429 } 1430 1431 /* get put index for frame */ 1432 putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK) 1433 >> TXFQS_TFQPI_SHIFT); 1434 /* Write ID Field to FIFO Element */ 1435 m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id); 1436 1437 /* get CAN FD configuration of frame */ 1438 fdflags = 0; 1439 if (can_is_canfd_skb(skb)) { 1440 fdflags |= TX_BUF_FDF; 1441 if (cf->flags & CANFD_BRS) 1442 fdflags |= TX_BUF_BRS; 1443 } 1444 1445 /* Construct DLC Field. Also contains CAN-FD configuration 1446 * use put index of fifo as message marker 1447 * it is used in TX interrupt for 1448 * sending the correct echo frame 1449 */ 1450 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC, 1451 ((putidx << TX_BUF_MM_SHIFT) & 1452 TX_BUF_MM_MASK) | 1453 (can_len2dlc(cf->len) << 16) | 1454 fdflags | TX_BUF_EFC); 1455 1456 for (i = 0; i < cf->len; i += 4) 1457 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4), 1458 *(u32 *)(cf->data + i)); 1459 1460 /* Push loopback echo. 1461 * Will be looped back on TX interrupt based on message marker 1462 */ 1463 can_put_echo_skb(skb, dev, putidx); 1464 1465 /* Enable TX FIFO element to start transfer */ 1466 m_can_write(priv, M_CAN_TXBAR, (1 << putidx)); 1467 1468 /* stop network queue if fifo full */ 1469 if (m_can_tx_fifo_full(priv) || 1470 m_can_next_echo_skb_occupied(dev, putidx)) 1471 netif_stop_queue(dev); 1472 } 1473 1474 return NETDEV_TX_OK; 1475 } 1476 1477 static const struct net_device_ops m_can_netdev_ops = { 1478 .ndo_open = m_can_open, 1479 .ndo_stop = m_can_close, 1480 .ndo_start_xmit = m_can_start_xmit, 1481 .ndo_change_mtu = can_change_mtu, 1482 }; 1483 1484 static int register_m_can_dev(struct net_device *dev) 1485 { 1486 dev->flags |= IFF_ECHO; /* we support local echo */ 1487 dev->netdev_ops = &m_can_netdev_ops; 1488 1489 return register_candev(dev); 1490 } 1491 1492 static void m_can_of_parse_mram(struct m_can_priv *priv, 1493 const u32 *mram_config_vals) 1494 { 1495 int i, start, end; 1496 1497 priv->mcfg[MRAM_SIDF].off = mram_config_vals[0]; 1498 priv->mcfg[MRAM_SIDF].num = mram_config_vals[1]; 1499 priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off + 1500 priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; 1501 priv->mcfg[MRAM_XIDF].num = mram_config_vals[2]; 1502 priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off + 1503 priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; 1504 priv->mcfg[MRAM_RXF0].num = mram_config_vals[3] & 1505 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1506 priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off + 1507 priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; 1508 priv->mcfg[MRAM_RXF1].num = mram_config_vals[4] & 1509 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1510 priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off + 1511 priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; 1512 priv->mcfg[MRAM_RXB].num = mram_config_vals[5]; 1513 priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off + 1514 priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; 1515 priv->mcfg[MRAM_TXE].num = mram_config_vals[6]; 1516 priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off + 1517 priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; 1518 priv->mcfg[MRAM_TXB].num = mram_config_vals[7] & 1519 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT); 1520 1521 dev_dbg(priv->device, 1522 "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", 1523 priv->mram_base, 1524 priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num, 1525 priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num, 1526 priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num, 1527 priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num, 1528 priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num, 1529 priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num, 1530 priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num); 1531 1532 /* initialize the entire Message RAM in use to avoid possible 1533 * ECC/parity checksum errors when reading an uninitialized buffer 1534 */ 1535 start = priv->mcfg[MRAM_SIDF].off; 1536 end = priv->mcfg[MRAM_TXB].off + 1537 priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 1538 for (i = start; i < end; i += 4) 1539 writel(0x0, priv->mram_base + i); 1540 1541 } 1542 1543 static int m_can_plat_probe(struct platform_device *pdev) 1544 { 1545 struct net_device *dev; 1546 struct m_can_priv *priv; 1547 struct resource *res; 1548 void __iomem *addr; 1549 void __iomem *mram_addr; 1550 struct clk *hclk, *cclk; 1551 int irq, ret; 1552 struct device_node *np; 1553 u32 mram_config_vals[MRAM_CFG_LEN]; 1554 u32 tx_fifo_size; 1555 1556 np = pdev->dev.of_node; 1557 1558 hclk = devm_clk_get(&pdev->dev, "hclk"); 1559 cclk = devm_clk_get(&pdev->dev, "cclk"); 1560 1561 if (IS_ERR(hclk) || IS_ERR(cclk)) { 1562 dev_err(&pdev->dev, "no clock found\n"); 1563 ret = -ENODEV; 1564 goto failed_ret; 1565 } 1566 1567 /* Enable clocks. Necessary to read Core Release in order to determine 1568 * M_CAN version 1569 */ 1570 ret = clk_prepare_enable(hclk); 1571 if (ret) 1572 goto disable_hclk_ret; 1573 1574 ret = clk_prepare_enable(cclk); 1575 if (ret) 1576 goto disable_cclk_ret; 1577 1578 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can"); 1579 addr = devm_ioremap_resource(&pdev->dev, res); 1580 irq = platform_get_irq_byname(pdev, "int0"); 1581 1582 if (IS_ERR(addr) || irq < 0) { 1583 ret = -EINVAL; 1584 goto disable_cclk_ret; 1585 } 1586 1587 /* message ram could be shared */ 1588 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram"); 1589 if (!res) { 1590 ret = -ENODEV; 1591 goto disable_cclk_ret; 1592 } 1593 1594 mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1595 if (!mram_addr) { 1596 ret = -ENOMEM; 1597 goto disable_cclk_ret; 1598 } 1599 1600 /* get message ram configuration */ 1601 ret = of_property_read_u32_array(np, "bosch,mram-cfg", 1602 mram_config_vals, 1603 sizeof(mram_config_vals) / 4); 1604 if (ret) { 1605 dev_err(&pdev->dev, "Could not get Message RAM configuration."); 1606 goto disable_cclk_ret; 1607 } 1608 1609 /* Get TX FIFO size 1610 * Defines the total amount of echo buffers for loopback 1611 */ 1612 tx_fifo_size = mram_config_vals[7]; 1613 1614 /* allocate the m_can device */ 1615 dev = alloc_m_can_dev(pdev, addr, tx_fifo_size); 1616 if (!dev) { 1617 ret = -ENOMEM; 1618 goto disable_cclk_ret; 1619 } 1620 priv = netdev_priv(dev); 1621 dev->irq = irq; 1622 priv->device = &pdev->dev; 1623 priv->hclk = hclk; 1624 priv->cclk = cclk; 1625 priv->can.clock.freq = clk_get_rate(cclk); 1626 priv->mram_base = mram_addr; 1627 1628 m_can_of_parse_mram(priv, mram_config_vals); 1629 1630 platform_set_drvdata(pdev, dev); 1631 SET_NETDEV_DEV(dev, &pdev->dev); 1632 1633 ret = register_m_can_dev(dev); 1634 if (ret) { 1635 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 1636 KBUILD_MODNAME, ret); 1637 goto failed_free_dev; 1638 } 1639 1640 devm_can_led_init(dev); 1641 1642 dev_info(&pdev->dev, "%s device registered (irq=%d, version=%d)\n", 1643 KBUILD_MODNAME, dev->irq, priv->version); 1644 1645 /* Probe finished 1646 * Stop clocks. They will be reactivated once the M_CAN device is opened 1647 */ 1648 1649 goto disable_cclk_ret; 1650 1651 failed_free_dev: 1652 free_m_can_dev(dev); 1653 disable_cclk_ret: 1654 clk_disable_unprepare(cclk); 1655 disable_hclk_ret: 1656 clk_disable_unprepare(hclk); 1657 failed_ret: 1658 return ret; 1659 } 1660 1661 static __maybe_unused int m_can_suspend(struct device *dev) 1662 { 1663 struct net_device *ndev = dev_get_drvdata(dev); 1664 struct m_can_priv *priv = netdev_priv(ndev); 1665 1666 if (netif_running(ndev)) { 1667 netif_stop_queue(ndev); 1668 netif_device_detach(ndev); 1669 } 1670 1671 /* TODO: enter low power */ 1672 1673 priv->can.state = CAN_STATE_SLEEPING; 1674 1675 return 0; 1676 } 1677 1678 static __maybe_unused int m_can_resume(struct device *dev) 1679 { 1680 struct net_device *ndev = dev_get_drvdata(dev); 1681 struct m_can_priv *priv = netdev_priv(ndev); 1682 1683 /* TODO: exit low power */ 1684 1685 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1686 1687 if (netif_running(ndev)) { 1688 netif_device_attach(ndev); 1689 netif_start_queue(ndev); 1690 } 1691 1692 return 0; 1693 } 1694 1695 static void unregister_m_can_dev(struct net_device *dev) 1696 { 1697 unregister_candev(dev); 1698 } 1699 1700 static int m_can_plat_remove(struct platform_device *pdev) 1701 { 1702 struct net_device *dev = platform_get_drvdata(pdev); 1703 1704 unregister_m_can_dev(dev); 1705 platform_set_drvdata(pdev, NULL); 1706 1707 free_m_can_dev(dev); 1708 1709 return 0; 1710 } 1711 1712 static const struct dev_pm_ops m_can_pmops = { 1713 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume) 1714 }; 1715 1716 static const struct of_device_id m_can_of_table[] = { 1717 { .compatible = "bosch,m_can", .data = NULL }, 1718 { /* sentinel */ }, 1719 }; 1720 MODULE_DEVICE_TABLE(of, m_can_of_table); 1721 1722 static struct platform_driver m_can_plat_driver = { 1723 .driver = { 1724 .name = KBUILD_MODNAME, 1725 .of_match_table = m_can_of_table, 1726 .pm = &m_can_pmops, 1727 }, 1728 .probe = m_can_plat_probe, 1729 .remove = m_can_plat_remove, 1730 }; 1731 1732 module_platform_driver(m_can_plat_driver); 1733 1734 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); 1735 MODULE_LICENSE("GPL v2"); 1736 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); 1737