1 /* 2 * CAN bus driver for Bosch M_CAN controller 3 * 4 * Copyright (C) 2014 Freescale Semiconductor, Inc. 5 * Dong Aisheng <b29396@freescale.com> 6 * 7 * Bosch M_CAN user manual can be obtained from: 8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/ 9 * mcan_users_manual_v302.pdf 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/netdevice.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/iopoll.h> 28 #include <linux/can/dev.h> 29 #include <linux/pinctrl/consumer.h> 30 31 /* napi related */ 32 #define M_CAN_NAPI_WEIGHT 64 33 34 /* message ram configuration data length */ 35 #define MRAM_CFG_LEN 8 36 37 /* registers definition */ 38 enum m_can_reg { 39 M_CAN_CREL = 0x0, 40 M_CAN_ENDN = 0x4, 41 M_CAN_CUST = 0x8, 42 M_CAN_DBTP = 0xc, 43 M_CAN_TEST = 0x10, 44 M_CAN_RWD = 0x14, 45 M_CAN_CCCR = 0x18, 46 M_CAN_NBTP = 0x1c, 47 M_CAN_TSCC = 0x20, 48 M_CAN_TSCV = 0x24, 49 M_CAN_TOCC = 0x28, 50 M_CAN_TOCV = 0x2c, 51 M_CAN_ECR = 0x40, 52 M_CAN_PSR = 0x44, 53 /* TDCR Register only available for version >=3.1.x */ 54 M_CAN_TDCR = 0x48, 55 M_CAN_IR = 0x50, 56 M_CAN_IE = 0x54, 57 M_CAN_ILS = 0x58, 58 M_CAN_ILE = 0x5c, 59 M_CAN_GFC = 0x80, 60 M_CAN_SIDFC = 0x84, 61 M_CAN_XIDFC = 0x88, 62 M_CAN_XIDAM = 0x90, 63 M_CAN_HPMS = 0x94, 64 M_CAN_NDAT1 = 0x98, 65 M_CAN_NDAT2 = 0x9c, 66 M_CAN_RXF0C = 0xa0, 67 M_CAN_RXF0S = 0xa4, 68 M_CAN_RXF0A = 0xa8, 69 M_CAN_RXBC = 0xac, 70 M_CAN_RXF1C = 0xb0, 71 M_CAN_RXF1S = 0xb4, 72 M_CAN_RXF1A = 0xb8, 73 M_CAN_RXESC = 0xbc, 74 M_CAN_TXBC = 0xc0, 75 M_CAN_TXFQS = 0xc4, 76 M_CAN_TXESC = 0xc8, 77 M_CAN_TXBRP = 0xcc, 78 M_CAN_TXBAR = 0xd0, 79 M_CAN_TXBCR = 0xd4, 80 M_CAN_TXBTO = 0xd8, 81 M_CAN_TXBCF = 0xdc, 82 M_CAN_TXBTIE = 0xe0, 83 M_CAN_TXBCIE = 0xe4, 84 M_CAN_TXEFC = 0xf0, 85 M_CAN_TXEFS = 0xf4, 86 M_CAN_TXEFA = 0xf8, 87 }; 88 89 /* m_can lec values */ 90 enum m_can_lec_type { 91 LEC_NO_ERROR = 0, 92 LEC_STUFF_ERROR, 93 LEC_FORM_ERROR, 94 LEC_ACK_ERROR, 95 LEC_BIT1_ERROR, 96 LEC_BIT0_ERROR, 97 LEC_CRC_ERROR, 98 LEC_UNUSED, 99 }; 100 101 enum m_can_mram_cfg { 102 MRAM_SIDF = 0, 103 MRAM_XIDF, 104 MRAM_RXF0, 105 MRAM_RXF1, 106 MRAM_RXB, 107 MRAM_TXE, 108 MRAM_TXB, 109 MRAM_CFG_NUM, 110 }; 111 112 /* Core Release Register (CREL) */ 113 #define CREL_REL_SHIFT 28 114 #define CREL_REL_MASK (0xF << CREL_REL_SHIFT) 115 #define CREL_STEP_SHIFT 24 116 #define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT) 117 #define CREL_SUBSTEP_SHIFT 20 118 #define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT) 119 120 /* Data Bit Timing & Prescaler Register (DBTP) */ 121 #define DBTP_TDC BIT(23) 122 #define DBTP_DBRP_SHIFT 16 123 #define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT) 124 #define DBTP_DTSEG1_SHIFT 8 125 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT) 126 #define DBTP_DTSEG2_SHIFT 4 127 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT) 128 #define DBTP_DSJW_SHIFT 0 129 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT) 130 131 /* Transmitter Delay Compensation Register (TDCR) */ 132 #define TDCR_TDCO_SHIFT 8 133 #define TDCR_TDCO_MASK (0x7F << TDCR_TDCO_SHIFT) 134 #define TDCR_TDCF_SHIFT 0 135 #define TDCR_TDCF_MASK (0x7F << TDCR_TDCF_SHIFT) 136 137 /* Test Register (TEST) */ 138 #define TEST_LBCK BIT(4) 139 140 /* CC Control Register(CCCR) */ 141 #define CCCR_CMR_MASK 0x3 142 #define CCCR_CMR_SHIFT 10 143 #define CCCR_CMR_CANFD 0x1 144 #define CCCR_CMR_CANFD_BRS 0x2 145 #define CCCR_CMR_CAN 0x3 146 #define CCCR_CME_MASK 0x3 147 #define CCCR_CME_SHIFT 8 148 #define CCCR_CME_CAN 0 149 #define CCCR_CME_CANFD 0x1 150 #define CCCR_CME_CANFD_BRS 0x2 151 #define CCCR_TXP BIT(14) 152 #define CCCR_TEST BIT(7) 153 #define CCCR_MON BIT(5) 154 #define CCCR_CSR BIT(4) 155 #define CCCR_CSA BIT(3) 156 #define CCCR_ASM BIT(2) 157 #define CCCR_CCE BIT(1) 158 #define CCCR_INIT BIT(0) 159 #define CCCR_CANFD 0x10 160 /* for version >=3.1.x */ 161 #define CCCR_EFBI BIT(13) 162 #define CCCR_PXHD BIT(12) 163 #define CCCR_BRSE BIT(9) 164 #define CCCR_FDOE BIT(8) 165 /* only for version >=3.2.x */ 166 #define CCCR_NISO BIT(15) 167 168 /* Nominal Bit Timing & Prescaler Register (NBTP) */ 169 #define NBTP_NSJW_SHIFT 25 170 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT) 171 #define NBTP_NBRP_SHIFT 16 172 #define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT) 173 #define NBTP_NTSEG1_SHIFT 8 174 #define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT) 175 #define NBTP_NTSEG2_SHIFT 0 176 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT) 177 178 /* Error Counter Register(ECR) */ 179 #define ECR_RP BIT(15) 180 #define ECR_REC_SHIFT 8 181 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT) 182 #define ECR_TEC_SHIFT 0 183 #define ECR_TEC_MASK 0xff 184 185 /* Protocol Status Register(PSR) */ 186 #define PSR_BO BIT(7) 187 #define PSR_EW BIT(6) 188 #define PSR_EP BIT(5) 189 #define PSR_LEC_MASK 0x7 190 191 /* Interrupt Register(IR) */ 192 #define IR_ALL_INT 0xffffffff 193 194 /* Renamed bits for versions > 3.1.x */ 195 #define IR_ARA BIT(29) 196 #define IR_PED BIT(28) 197 #define IR_PEA BIT(27) 198 199 /* Bits for version 3.0.x */ 200 #define IR_STE BIT(31) 201 #define IR_FOE BIT(30) 202 #define IR_ACKE BIT(29) 203 #define IR_BE BIT(28) 204 #define IR_CRCE BIT(27) 205 #define IR_WDI BIT(26) 206 #define IR_BO BIT(25) 207 #define IR_EW BIT(24) 208 #define IR_EP BIT(23) 209 #define IR_ELO BIT(22) 210 #define IR_BEU BIT(21) 211 #define IR_BEC BIT(20) 212 #define IR_DRX BIT(19) 213 #define IR_TOO BIT(18) 214 #define IR_MRAF BIT(17) 215 #define IR_TSW BIT(16) 216 #define IR_TEFL BIT(15) 217 #define IR_TEFF BIT(14) 218 #define IR_TEFW BIT(13) 219 #define IR_TEFN BIT(12) 220 #define IR_TFE BIT(11) 221 #define IR_TCF BIT(10) 222 #define IR_TC BIT(9) 223 #define IR_HPM BIT(8) 224 #define IR_RF1L BIT(7) 225 #define IR_RF1F BIT(6) 226 #define IR_RF1W BIT(5) 227 #define IR_RF1N BIT(4) 228 #define IR_RF0L BIT(3) 229 #define IR_RF0F BIT(2) 230 #define IR_RF0W BIT(1) 231 #define IR_RF0N BIT(0) 232 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) 233 234 /* Interrupts for version 3.0.x */ 235 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) 236 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \ 237 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 238 IR_RF1L | IR_RF0L) 239 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X) 240 /* Interrupts for version >= 3.1.x */ 241 #define IR_ERR_LEC_31X (IR_PED | IR_PEA) 242 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \ 243 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 244 IR_RF1L | IR_RF0L) 245 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X) 246 247 /* Interrupt Line Select (ILS) */ 248 #define ILS_ALL_INT0 0x0 249 #define ILS_ALL_INT1 0xFFFFFFFF 250 251 /* Interrupt Line Enable (ILE) */ 252 #define ILE_EINT1 BIT(1) 253 #define ILE_EINT0 BIT(0) 254 255 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ 256 #define RXFC_FWM_SHIFT 24 257 #define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT) 258 #define RXFC_FS_SHIFT 16 259 #define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT) 260 261 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ 262 #define RXFS_RFL BIT(25) 263 #define RXFS_FF BIT(24) 264 #define RXFS_FPI_SHIFT 16 265 #define RXFS_FPI_MASK 0x3f0000 266 #define RXFS_FGI_SHIFT 8 267 #define RXFS_FGI_MASK 0x3f00 268 #define RXFS_FFL_MASK 0x7f 269 270 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ 271 #define M_CAN_RXESC_8BYTES 0x0 272 #define M_CAN_RXESC_64BYTES 0x777 273 274 /* Tx Buffer Configuration(TXBC) */ 275 #define TXBC_NDTB_SHIFT 16 276 #define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT) 277 #define TXBC_TFQS_SHIFT 24 278 #define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT) 279 280 /* Tx FIFO/Queue Status (TXFQS) */ 281 #define TXFQS_TFQF BIT(21) 282 #define TXFQS_TFQPI_SHIFT 16 283 #define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT) 284 #define TXFQS_TFGI_SHIFT 8 285 #define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT) 286 #define TXFQS_TFFL_SHIFT 0 287 #define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT) 288 289 /* Tx Buffer Element Size Configuration(TXESC) */ 290 #define TXESC_TBDS_8BYTES 0x0 291 #define TXESC_TBDS_64BYTES 0x7 292 293 /* Tx Event FIFO Configuration (TXEFC) */ 294 #define TXEFC_EFS_SHIFT 16 295 #define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT) 296 297 /* Tx Event FIFO Status (TXEFS) */ 298 #define TXEFS_TEFL BIT(25) 299 #define TXEFS_EFF BIT(24) 300 #define TXEFS_EFGI_SHIFT 8 301 #define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT) 302 #define TXEFS_EFFL_SHIFT 0 303 #define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT) 304 305 /* Tx Event FIFO Acknowledge (TXEFA) */ 306 #define TXEFA_EFAI_SHIFT 0 307 #define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT) 308 309 /* Message RAM Configuration (in bytes) */ 310 #define SIDF_ELEMENT_SIZE 4 311 #define XIDF_ELEMENT_SIZE 8 312 #define RXF0_ELEMENT_SIZE 72 313 #define RXF1_ELEMENT_SIZE 72 314 #define RXB_ELEMENT_SIZE 72 315 #define TXE_ELEMENT_SIZE 8 316 #define TXB_ELEMENT_SIZE 72 317 318 /* Message RAM Elements */ 319 #define M_CAN_FIFO_ID 0x0 320 #define M_CAN_FIFO_DLC 0x4 321 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2)) 322 323 /* Rx Buffer Element */ 324 /* R0 */ 325 #define RX_BUF_ESI BIT(31) 326 #define RX_BUF_XTD BIT(30) 327 #define RX_BUF_RTR BIT(29) 328 /* R1 */ 329 #define RX_BUF_ANMF BIT(31) 330 #define RX_BUF_FDF BIT(21) 331 #define RX_BUF_BRS BIT(20) 332 333 /* Tx Buffer Element */ 334 /* T0 */ 335 #define TX_BUF_ESI BIT(31) 336 #define TX_BUF_XTD BIT(30) 337 #define TX_BUF_RTR BIT(29) 338 /* T1 */ 339 #define TX_BUF_EFC BIT(23) 340 #define TX_BUF_FDF BIT(21) 341 #define TX_BUF_BRS BIT(20) 342 #define TX_BUF_MM_SHIFT 24 343 #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT) 344 345 /* Tx event FIFO Element */ 346 /* E1 */ 347 #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT 348 #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT) 349 350 /* address offset and element number for each FIFO/Buffer in the Message RAM */ 351 struct mram_cfg { 352 u16 off; 353 u8 num; 354 }; 355 356 /* m_can private data structure */ 357 struct m_can_priv { 358 struct can_priv can; /* must be the first member */ 359 struct napi_struct napi; 360 struct net_device *dev; 361 struct device *device; 362 struct clk *hclk; 363 struct clk *cclk; 364 void __iomem *base; 365 u32 irqstatus; 366 int version; 367 368 /* message ram configuration */ 369 void __iomem *mram_base; 370 struct mram_cfg mcfg[MRAM_CFG_NUM]; 371 }; 372 373 static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg) 374 { 375 return readl(priv->base + reg); 376 } 377 378 static inline void m_can_write(const struct m_can_priv *priv, 379 enum m_can_reg reg, u32 val) 380 { 381 writel(val, priv->base + reg); 382 } 383 384 static inline u32 m_can_fifo_read(const struct m_can_priv *priv, 385 u32 fgi, unsigned int offset) 386 { 387 return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off + 388 fgi * RXF0_ELEMENT_SIZE + offset); 389 } 390 391 static inline void m_can_fifo_write(const struct m_can_priv *priv, 392 u32 fpi, unsigned int offset, u32 val) 393 { 394 writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off + 395 fpi * TXB_ELEMENT_SIZE + offset); 396 } 397 398 static inline u32 m_can_txe_fifo_read(const struct m_can_priv *priv, 399 u32 fgi, 400 u32 offset) { 401 return readl(priv->mram_base + priv->mcfg[MRAM_TXE].off + 402 fgi * TXE_ELEMENT_SIZE + offset); 403 } 404 405 static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv) 406 { 407 return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF); 408 } 409 410 static inline void m_can_config_endisable(const struct m_can_priv *priv, 411 bool enable) 412 { 413 u32 cccr = m_can_read(priv, M_CAN_CCCR); 414 u32 timeout = 10; 415 u32 val = 0; 416 417 if (enable) { 418 /* enable m_can configuration */ 419 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT); 420 udelay(5); 421 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ 422 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); 423 } else { 424 m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); 425 } 426 427 /* there's a delay for module initialization */ 428 if (enable) 429 val = CCCR_INIT | CCCR_CCE; 430 431 while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { 432 if (timeout == 0) { 433 netdev_warn(priv->dev, "Failed to init module\n"); 434 return; 435 } 436 timeout--; 437 udelay(1); 438 } 439 } 440 441 static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv) 442 { 443 /* Only interrupt line 0 is used in this driver */ 444 m_can_write(priv, M_CAN_ILE, ILE_EINT0); 445 } 446 447 static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv) 448 { 449 m_can_write(priv, M_CAN_ILE, 0x0); 450 } 451 452 static void m_can_read_fifo(struct net_device *dev, u32 rxfs) 453 { 454 struct net_device_stats *stats = &dev->stats; 455 struct m_can_priv *priv = netdev_priv(dev); 456 struct canfd_frame *cf; 457 struct sk_buff *skb; 458 u32 id, fgi, dlc; 459 int i; 460 461 /* calculate the fifo get index for where to read data */ 462 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT; 463 dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC); 464 if (dlc & RX_BUF_FDF) 465 skb = alloc_canfd_skb(dev, &cf); 466 else 467 skb = alloc_can_skb(dev, (struct can_frame **)&cf); 468 if (!skb) { 469 stats->rx_dropped++; 470 return; 471 } 472 473 if (dlc & RX_BUF_FDF) 474 cf->len = can_dlc2len((dlc >> 16) & 0x0F); 475 else 476 cf->len = get_can_dlc((dlc >> 16) & 0x0F); 477 478 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID); 479 if (id & RX_BUF_XTD) 480 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 481 else 482 cf->can_id = (id >> 18) & CAN_SFF_MASK; 483 484 if (id & RX_BUF_ESI) { 485 cf->flags |= CANFD_ESI; 486 netdev_dbg(dev, "ESI Error\n"); 487 } 488 489 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) { 490 cf->can_id |= CAN_RTR_FLAG; 491 } else { 492 if (dlc & RX_BUF_BRS) 493 cf->flags |= CANFD_BRS; 494 495 for (i = 0; i < cf->len; i += 4) 496 *(u32 *)(cf->data + i) = 497 m_can_fifo_read(priv, fgi, 498 M_CAN_FIFO_DATA(i / 4)); 499 } 500 501 /* acknowledge rx fifo 0 */ 502 m_can_write(priv, M_CAN_RXF0A, fgi); 503 504 stats->rx_packets++; 505 stats->rx_bytes += cf->len; 506 507 netif_receive_skb(skb); 508 } 509 510 static int m_can_do_rx_poll(struct net_device *dev, int quota) 511 { 512 struct m_can_priv *priv = netdev_priv(dev); 513 u32 pkts = 0; 514 u32 rxfs; 515 516 rxfs = m_can_read(priv, M_CAN_RXF0S); 517 if (!(rxfs & RXFS_FFL_MASK)) { 518 netdev_dbg(dev, "no messages in fifo0\n"); 519 return 0; 520 } 521 522 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) { 523 if (rxfs & RXFS_RFL) 524 netdev_warn(dev, "Rx FIFO 0 Message Lost\n"); 525 526 m_can_read_fifo(dev, rxfs); 527 528 quota--; 529 pkts++; 530 rxfs = m_can_read(priv, M_CAN_RXF0S); 531 } 532 533 if (pkts) 534 can_led_event(dev, CAN_LED_EVENT_RX); 535 536 return pkts; 537 } 538 539 static int m_can_handle_lost_msg(struct net_device *dev) 540 { 541 struct net_device_stats *stats = &dev->stats; 542 struct sk_buff *skb; 543 struct can_frame *frame; 544 545 netdev_err(dev, "msg lost in rxf0\n"); 546 547 stats->rx_errors++; 548 stats->rx_over_errors++; 549 550 skb = alloc_can_err_skb(dev, &frame); 551 if (unlikely(!skb)) 552 return 0; 553 554 frame->can_id |= CAN_ERR_CRTL; 555 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 556 557 netif_receive_skb(skb); 558 559 return 1; 560 } 561 562 static int m_can_handle_lec_err(struct net_device *dev, 563 enum m_can_lec_type lec_type) 564 { 565 struct m_can_priv *priv = netdev_priv(dev); 566 struct net_device_stats *stats = &dev->stats; 567 struct can_frame *cf; 568 struct sk_buff *skb; 569 570 priv->can.can_stats.bus_error++; 571 stats->rx_errors++; 572 573 /* propagate the error condition to the CAN stack */ 574 skb = alloc_can_err_skb(dev, &cf); 575 if (unlikely(!skb)) 576 return 0; 577 578 /* check for 'last error code' which tells us the 579 * type of the last error to occur on the CAN bus 580 */ 581 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 582 583 switch (lec_type) { 584 case LEC_STUFF_ERROR: 585 netdev_dbg(dev, "stuff error\n"); 586 cf->data[2] |= CAN_ERR_PROT_STUFF; 587 break; 588 case LEC_FORM_ERROR: 589 netdev_dbg(dev, "form error\n"); 590 cf->data[2] |= CAN_ERR_PROT_FORM; 591 break; 592 case LEC_ACK_ERROR: 593 netdev_dbg(dev, "ack error\n"); 594 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 595 break; 596 case LEC_BIT1_ERROR: 597 netdev_dbg(dev, "bit1 error\n"); 598 cf->data[2] |= CAN_ERR_PROT_BIT1; 599 break; 600 case LEC_BIT0_ERROR: 601 netdev_dbg(dev, "bit0 error\n"); 602 cf->data[2] |= CAN_ERR_PROT_BIT0; 603 break; 604 case LEC_CRC_ERROR: 605 netdev_dbg(dev, "CRC error\n"); 606 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 607 break; 608 default: 609 break; 610 } 611 612 stats->rx_packets++; 613 stats->rx_bytes += cf->can_dlc; 614 netif_receive_skb(skb); 615 616 return 1; 617 } 618 619 static int __m_can_get_berr_counter(const struct net_device *dev, 620 struct can_berr_counter *bec) 621 { 622 struct m_can_priv *priv = netdev_priv(dev); 623 unsigned int ecr; 624 625 ecr = m_can_read(priv, M_CAN_ECR); 626 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT; 627 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT; 628 629 return 0; 630 } 631 632 static int m_can_clk_start(struct m_can_priv *priv) 633 { 634 int err; 635 636 err = pm_runtime_get_sync(priv->device); 637 if (err) 638 pm_runtime_put_noidle(priv->device); 639 640 return err; 641 } 642 643 static void m_can_clk_stop(struct m_can_priv *priv) 644 { 645 pm_runtime_put_sync(priv->device); 646 } 647 648 static int m_can_get_berr_counter(const struct net_device *dev, 649 struct can_berr_counter *bec) 650 { 651 struct m_can_priv *priv = netdev_priv(dev); 652 int err; 653 654 err = m_can_clk_start(priv); 655 if (err) 656 return err; 657 658 __m_can_get_berr_counter(dev, bec); 659 660 m_can_clk_stop(priv); 661 662 return 0; 663 } 664 665 static int m_can_handle_state_change(struct net_device *dev, 666 enum can_state new_state) 667 { 668 struct m_can_priv *priv = netdev_priv(dev); 669 struct net_device_stats *stats = &dev->stats; 670 struct can_frame *cf; 671 struct sk_buff *skb; 672 struct can_berr_counter bec; 673 unsigned int ecr; 674 675 switch (new_state) { 676 case CAN_STATE_ERROR_ACTIVE: 677 /* error warning state */ 678 priv->can.can_stats.error_warning++; 679 priv->can.state = CAN_STATE_ERROR_WARNING; 680 break; 681 case CAN_STATE_ERROR_PASSIVE: 682 /* error passive state */ 683 priv->can.can_stats.error_passive++; 684 priv->can.state = CAN_STATE_ERROR_PASSIVE; 685 break; 686 case CAN_STATE_BUS_OFF: 687 /* bus-off state */ 688 priv->can.state = CAN_STATE_BUS_OFF; 689 m_can_disable_all_interrupts(priv); 690 priv->can.can_stats.bus_off++; 691 can_bus_off(dev); 692 break; 693 default: 694 break; 695 } 696 697 /* propagate the error condition to the CAN stack */ 698 skb = alloc_can_err_skb(dev, &cf); 699 if (unlikely(!skb)) 700 return 0; 701 702 __m_can_get_berr_counter(dev, &bec); 703 704 switch (new_state) { 705 case CAN_STATE_ERROR_ACTIVE: 706 /* error warning state */ 707 cf->can_id |= CAN_ERR_CRTL; 708 cf->data[1] = (bec.txerr > bec.rxerr) ? 709 CAN_ERR_CRTL_TX_WARNING : 710 CAN_ERR_CRTL_RX_WARNING; 711 cf->data[6] = bec.txerr; 712 cf->data[7] = bec.rxerr; 713 break; 714 case CAN_STATE_ERROR_PASSIVE: 715 /* error passive state */ 716 cf->can_id |= CAN_ERR_CRTL; 717 ecr = m_can_read(priv, M_CAN_ECR); 718 if (ecr & ECR_RP) 719 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 720 if (bec.txerr > 127) 721 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 722 cf->data[6] = bec.txerr; 723 cf->data[7] = bec.rxerr; 724 break; 725 case CAN_STATE_BUS_OFF: 726 /* bus-off state */ 727 cf->can_id |= CAN_ERR_BUSOFF; 728 break; 729 default: 730 break; 731 } 732 733 stats->rx_packets++; 734 stats->rx_bytes += cf->can_dlc; 735 netif_receive_skb(skb); 736 737 return 1; 738 } 739 740 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) 741 { 742 struct m_can_priv *priv = netdev_priv(dev); 743 int work_done = 0; 744 745 if ((psr & PSR_EW) && 746 (priv->can.state != CAN_STATE_ERROR_WARNING)) { 747 netdev_dbg(dev, "entered error warning state\n"); 748 work_done += m_can_handle_state_change(dev, 749 CAN_STATE_ERROR_WARNING); 750 } 751 752 if ((psr & PSR_EP) && 753 (priv->can.state != CAN_STATE_ERROR_PASSIVE)) { 754 netdev_dbg(dev, "entered error passive state\n"); 755 work_done += m_can_handle_state_change(dev, 756 CAN_STATE_ERROR_PASSIVE); 757 } 758 759 if ((psr & PSR_BO) && 760 (priv->can.state != CAN_STATE_BUS_OFF)) { 761 netdev_dbg(dev, "entered error bus off state\n"); 762 work_done += m_can_handle_state_change(dev, 763 CAN_STATE_BUS_OFF); 764 } 765 766 return work_done; 767 } 768 769 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) 770 { 771 if (irqstatus & IR_WDI) 772 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); 773 if (irqstatus & IR_ELO) 774 netdev_err(dev, "Error Logging Overflow\n"); 775 if (irqstatus & IR_BEU) 776 netdev_err(dev, "Bit Error Uncorrected\n"); 777 if (irqstatus & IR_BEC) 778 netdev_err(dev, "Bit Error Corrected\n"); 779 if (irqstatus & IR_TOO) 780 netdev_err(dev, "Timeout reached\n"); 781 if (irqstatus & IR_MRAF) 782 netdev_err(dev, "Message RAM access failure occurred\n"); 783 } 784 785 static inline bool is_lec_err(u32 psr) 786 { 787 psr &= LEC_UNUSED; 788 789 return psr && (psr != LEC_UNUSED); 790 } 791 792 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, 793 u32 psr) 794 { 795 struct m_can_priv *priv = netdev_priv(dev); 796 int work_done = 0; 797 798 if (irqstatus & IR_RF0L) 799 work_done += m_can_handle_lost_msg(dev); 800 801 /* handle lec errors on the bus */ 802 if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 803 is_lec_err(psr)) 804 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED); 805 806 /* other unproccessed error interrupts */ 807 m_can_handle_other_err(dev, irqstatus); 808 809 return work_done; 810 } 811 812 static int m_can_poll(struct napi_struct *napi, int quota) 813 { 814 struct net_device *dev = napi->dev; 815 struct m_can_priv *priv = netdev_priv(dev); 816 int work_done = 0; 817 u32 irqstatus, psr; 818 819 irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR); 820 if (!irqstatus) 821 goto end; 822 823 psr = m_can_read(priv, M_CAN_PSR); 824 if (irqstatus & IR_ERR_STATE) 825 work_done += m_can_handle_state_errors(dev, psr); 826 827 if (irqstatus & IR_ERR_BUS_30X) 828 work_done += m_can_handle_bus_errors(dev, irqstatus, psr); 829 830 if (irqstatus & IR_RF0N) 831 work_done += m_can_do_rx_poll(dev, (quota - work_done)); 832 833 if (work_done < quota) { 834 napi_complete_done(napi, work_done); 835 m_can_enable_all_interrupts(priv); 836 } 837 838 end: 839 return work_done; 840 } 841 842 static void m_can_echo_tx_event(struct net_device *dev) 843 { 844 u32 txe_count = 0; 845 u32 m_can_txefs; 846 u32 fgi = 0; 847 int i = 0; 848 unsigned int msg_mark; 849 850 struct m_can_priv *priv = netdev_priv(dev); 851 struct net_device_stats *stats = &dev->stats; 852 853 /* read tx event fifo status */ 854 m_can_txefs = m_can_read(priv, M_CAN_TXEFS); 855 856 /* Get Tx Event fifo element count */ 857 txe_count = (m_can_txefs & TXEFS_EFFL_MASK) 858 >> TXEFS_EFFL_SHIFT; 859 860 /* Get and process all sent elements */ 861 for (i = 0; i < txe_count; i++) { 862 /* retrieve get index */ 863 fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK) 864 >> TXEFS_EFGI_SHIFT; 865 866 /* get message marker */ 867 msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) & 868 TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT; 869 870 /* ack txe element */ 871 m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK & 872 (fgi << TXEFA_EFAI_SHIFT))); 873 874 /* update stats */ 875 stats->tx_bytes += can_get_echo_skb(dev, msg_mark); 876 stats->tx_packets++; 877 } 878 } 879 880 static irqreturn_t m_can_isr(int irq, void *dev_id) 881 { 882 struct net_device *dev = (struct net_device *)dev_id; 883 struct m_can_priv *priv = netdev_priv(dev); 884 struct net_device_stats *stats = &dev->stats; 885 u32 ir; 886 887 ir = m_can_read(priv, M_CAN_IR); 888 if (!ir) 889 return IRQ_NONE; 890 891 /* ACK all irqs */ 892 if (ir & IR_ALL_INT) 893 m_can_write(priv, M_CAN_IR, ir); 894 895 /* schedule NAPI in case of 896 * - rx IRQ 897 * - state change IRQ 898 * - bus error IRQ and bus error reporting 899 */ 900 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) { 901 priv->irqstatus = ir; 902 m_can_disable_all_interrupts(priv); 903 napi_schedule(&priv->napi); 904 } 905 906 if (priv->version == 30) { 907 if (ir & IR_TC) { 908 /* Transmission Complete Interrupt*/ 909 stats->tx_bytes += can_get_echo_skb(dev, 0); 910 stats->tx_packets++; 911 can_led_event(dev, CAN_LED_EVENT_TX); 912 netif_wake_queue(dev); 913 } 914 } else { 915 if (ir & IR_TEFN) { 916 /* New TX FIFO Element arrived */ 917 m_can_echo_tx_event(dev); 918 can_led_event(dev, CAN_LED_EVENT_TX); 919 if (netif_queue_stopped(dev) && 920 !m_can_tx_fifo_full(priv)) 921 netif_wake_queue(dev); 922 } 923 } 924 925 return IRQ_HANDLED; 926 } 927 928 static const struct can_bittiming_const m_can_bittiming_const_30X = { 929 .name = KBUILD_MODNAME, 930 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 931 .tseg1_max = 64, 932 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 933 .tseg2_max = 16, 934 .sjw_max = 16, 935 .brp_min = 1, 936 .brp_max = 1024, 937 .brp_inc = 1, 938 }; 939 940 static const struct can_bittiming_const m_can_data_bittiming_const_30X = { 941 .name = KBUILD_MODNAME, 942 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 943 .tseg1_max = 16, 944 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 945 .tseg2_max = 8, 946 .sjw_max = 4, 947 .brp_min = 1, 948 .brp_max = 32, 949 .brp_inc = 1, 950 }; 951 952 static const struct can_bittiming_const m_can_bittiming_const_31X = { 953 .name = KBUILD_MODNAME, 954 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 955 .tseg1_max = 256, 956 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 957 .tseg2_max = 128, 958 .sjw_max = 128, 959 .brp_min = 1, 960 .brp_max = 512, 961 .brp_inc = 1, 962 }; 963 964 static const struct can_bittiming_const m_can_data_bittiming_const_31X = { 965 .name = KBUILD_MODNAME, 966 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */ 967 .tseg1_max = 32, 968 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 969 .tseg2_max = 16, 970 .sjw_max = 16, 971 .brp_min = 1, 972 .brp_max = 32, 973 .brp_inc = 1, 974 }; 975 976 static int m_can_set_bittiming(struct net_device *dev) 977 { 978 struct m_can_priv *priv = netdev_priv(dev); 979 const struct can_bittiming *bt = &priv->can.bittiming; 980 const struct can_bittiming *dbt = &priv->can.data_bittiming; 981 u16 brp, sjw, tseg1, tseg2; 982 u32 reg_btp; 983 984 brp = bt->brp - 1; 985 sjw = bt->sjw - 1; 986 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 987 tseg2 = bt->phase_seg2 - 1; 988 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) | 989 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT); 990 m_can_write(priv, M_CAN_NBTP, reg_btp); 991 992 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 993 reg_btp = 0; 994 brp = dbt->brp - 1; 995 sjw = dbt->sjw - 1; 996 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; 997 tseg2 = dbt->phase_seg2 - 1; 998 999 /* TDC is only needed for bitrates beyond 2.5 MBit/s. 1000 * This is mentioned in the "Bit Time Requirements for CAN FD" 1001 * paper presented at the International CAN Conference 2013 1002 */ 1003 if (dbt->bitrate > 2500000) { 1004 u32 tdco, ssp; 1005 1006 /* Use the same value of secondary sampling point 1007 * as the data sampling point 1008 */ 1009 ssp = dbt->sample_point; 1010 1011 /* Equation based on Bosch's M_CAN User Manual's 1012 * Transmitter Delay Compensation Section 1013 */ 1014 tdco = (priv->can.clock.freq / 1000) * 1015 ssp / dbt->bitrate; 1016 1017 /* Max valid TDCO value is 127 */ 1018 if (tdco > 127) { 1019 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n", 1020 tdco); 1021 tdco = 127; 1022 } 1023 1024 reg_btp |= DBTP_TDC; 1025 m_can_write(priv, M_CAN_TDCR, 1026 tdco << TDCR_TDCO_SHIFT); 1027 } 1028 1029 reg_btp |= (brp << DBTP_DBRP_SHIFT) | 1030 (sjw << DBTP_DSJW_SHIFT) | 1031 (tseg1 << DBTP_DTSEG1_SHIFT) | 1032 (tseg2 << DBTP_DTSEG2_SHIFT); 1033 1034 m_can_write(priv, M_CAN_DBTP, reg_btp); 1035 } 1036 1037 return 0; 1038 } 1039 1040 /* Configure M_CAN chip: 1041 * - set rx buffer/fifo element size 1042 * - configure rx fifo 1043 * - accept non-matching frame into fifo 0 1044 * - configure tx buffer 1045 * - >= v3.1.x: TX FIFO is used 1046 * - configure mode 1047 * - setup bittiming 1048 */ 1049 static void m_can_chip_config(struct net_device *dev) 1050 { 1051 struct m_can_priv *priv = netdev_priv(dev); 1052 u32 cccr, test; 1053 1054 m_can_config_endisable(priv, true); 1055 1056 /* RX Buffer/FIFO Element Size 64 bytes data field */ 1057 m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_64BYTES); 1058 1059 /* Accept Non-matching Frames Into FIFO 0 */ 1060 m_can_write(priv, M_CAN_GFC, 0x0); 1061 1062 if (priv->version == 30) { 1063 /* only support one Tx Buffer currently */ 1064 m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) | 1065 priv->mcfg[MRAM_TXB].off); 1066 } else { 1067 /* TX FIFO is used for newer IP Core versions */ 1068 m_can_write(priv, M_CAN_TXBC, 1069 (priv->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) | 1070 (priv->mcfg[MRAM_TXB].off)); 1071 } 1072 1073 /* support 64 bytes payload */ 1074 m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES); 1075 1076 /* TX Event FIFO */ 1077 if (priv->version == 30) { 1078 m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) | 1079 priv->mcfg[MRAM_TXE].off); 1080 } else { 1081 /* Full TX Event FIFO is used */ 1082 m_can_write(priv, M_CAN_TXEFC, 1083 ((priv->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT) 1084 & TXEFC_EFS_MASK) | 1085 priv->mcfg[MRAM_TXE].off); 1086 } 1087 1088 /* rx fifo configuration, blocking mode, fifo size 1 */ 1089 m_can_write(priv, M_CAN_RXF0C, 1090 (priv->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) | 1091 priv->mcfg[MRAM_RXF0].off); 1092 1093 m_can_write(priv, M_CAN_RXF1C, 1094 (priv->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) | 1095 priv->mcfg[MRAM_RXF1].off); 1096 1097 cccr = m_can_read(priv, M_CAN_CCCR); 1098 test = m_can_read(priv, M_CAN_TEST); 1099 test &= ~TEST_LBCK; 1100 if (priv->version == 30) { 1101 /* Version 3.0.x */ 1102 1103 cccr &= ~(CCCR_TEST | CCCR_MON | 1104 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | 1105 (CCCR_CME_MASK << CCCR_CME_SHIFT)); 1106 1107 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1108 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT; 1109 1110 } else { 1111 /* Version 3.1.x or 3.2.x */ 1112 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE); 1113 1114 /* Only 3.2.x has NISO Bit implemented */ 1115 if (priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 1116 cccr |= CCCR_NISO; 1117 1118 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1119 cccr |= (CCCR_BRSE | CCCR_FDOE); 1120 } 1121 1122 /* Loopback Mode */ 1123 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1124 cccr |= CCCR_TEST | CCCR_MON; 1125 test |= TEST_LBCK; 1126 } 1127 1128 /* Enable Monitoring (all versions) */ 1129 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1130 cccr |= CCCR_MON; 1131 1132 /* Write config */ 1133 m_can_write(priv, M_CAN_CCCR, cccr); 1134 m_can_write(priv, M_CAN_TEST, test); 1135 1136 /* Enable interrupts */ 1137 m_can_write(priv, M_CAN_IR, IR_ALL_INT); 1138 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1139 if (priv->version == 30) 1140 m_can_write(priv, M_CAN_IE, IR_ALL_INT & 1141 ~(IR_ERR_LEC_30X)); 1142 else 1143 m_can_write(priv, M_CAN_IE, IR_ALL_INT & 1144 ~(IR_ERR_LEC_31X)); 1145 else 1146 m_can_write(priv, M_CAN_IE, IR_ALL_INT); 1147 1148 /* route all interrupts to INT0 */ 1149 m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0); 1150 1151 /* set bittiming params */ 1152 m_can_set_bittiming(dev); 1153 1154 m_can_config_endisable(priv, false); 1155 } 1156 1157 static void m_can_start(struct net_device *dev) 1158 { 1159 struct m_can_priv *priv = netdev_priv(dev); 1160 1161 /* basic m_can configuration */ 1162 m_can_chip_config(dev); 1163 1164 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1165 1166 m_can_enable_all_interrupts(priv); 1167 } 1168 1169 static int m_can_set_mode(struct net_device *dev, enum can_mode mode) 1170 { 1171 switch (mode) { 1172 case CAN_MODE_START: 1173 m_can_start(dev); 1174 netif_wake_queue(dev); 1175 break; 1176 default: 1177 return -EOPNOTSUPP; 1178 } 1179 1180 return 0; 1181 } 1182 1183 /* Checks core release number of M_CAN 1184 * returns 0 if an unsupported device is detected 1185 * else it returns the release and step coded as: 1186 * return value = 10 * <release> + 1 * <step> 1187 */ 1188 static int m_can_check_core_release(void __iomem *m_can_base) 1189 { 1190 u32 crel_reg; 1191 u8 rel; 1192 u8 step; 1193 int res; 1194 struct m_can_priv temp_priv = { 1195 .base = m_can_base 1196 }; 1197 1198 /* Read Core Release Version and split into version number 1199 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; 1200 */ 1201 crel_reg = m_can_read(&temp_priv, M_CAN_CREL); 1202 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT); 1203 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT); 1204 1205 if (rel == 3) { 1206 /* M_CAN v3.x.y: create return value */ 1207 res = 30 + step; 1208 } else { 1209 /* Unsupported M_CAN version */ 1210 res = 0; 1211 } 1212 1213 return res; 1214 } 1215 1216 /* Selectable Non ISO support only in version 3.2.x 1217 * This function checks if the bit is writable. 1218 */ 1219 static bool m_can_niso_supported(const struct m_can_priv *priv) 1220 { 1221 u32 cccr_reg, cccr_poll; 1222 int niso_timeout; 1223 1224 m_can_config_endisable(priv, true); 1225 cccr_reg = m_can_read(priv, M_CAN_CCCR); 1226 cccr_reg |= CCCR_NISO; 1227 m_can_write(priv, M_CAN_CCCR, cccr_reg); 1228 1229 niso_timeout = readl_poll_timeout((priv->base + M_CAN_CCCR), cccr_poll, 1230 (cccr_poll == cccr_reg), 0, 10); 1231 1232 /* Clear NISO */ 1233 cccr_reg &= ~(CCCR_NISO); 1234 m_can_write(priv, M_CAN_CCCR, cccr_reg); 1235 1236 m_can_config_endisable(priv, false); 1237 1238 /* return false if time out (-ETIMEDOUT), else return true */ 1239 return !niso_timeout; 1240 } 1241 1242 static int m_can_dev_setup(struct platform_device *pdev, struct net_device *dev, 1243 void __iomem *addr) 1244 { 1245 struct m_can_priv *priv; 1246 int m_can_version; 1247 1248 m_can_version = m_can_check_core_release(addr); 1249 /* return if unsupported version */ 1250 if (!m_can_version) { 1251 dev_err(&pdev->dev, "Unsupported version number: %2d", 1252 m_can_version); 1253 return -EINVAL; 1254 } 1255 1256 priv = netdev_priv(dev); 1257 netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT); 1258 1259 /* Shared properties of all M_CAN versions */ 1260 priv->version = m_can_version; 1261 priv->dev = dev; 1262 priv->base = addr; 1263 priv->can.do_set_mode = m_can_set_mode; 1264 priv->can.do_get_berr_counter = m_can_get_berr_counter; 1265 1266 /* Set M_CAN supported operations */ 1267 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1268 CAN_CTRLMODE_LISTENONLY | 1269 CAN_CTRLMODE_BERR_REPORTING | 1270 CAN_CTRLMODE_FD; 1271 1272 /* Set properties depending on M_CAN version */ 1273 switch (priv->version) { 1274 case 30: 1275 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ 1276 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1277 priv->can.bittiming_const = &m_can_bittiming_const_30X; 1278 priv->can.data_bittiming_const = 1279 &m_can_data_bittiming_const_30X; 1280 break; 1281 case 31: 1282 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ 1283 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1284 priv->can.bittiming_const = &m_can_bittiming_const_31X; 1285 priv->can.data_bittiming_const = 1286 &m_can_data_bittiming_const_31X; 1287 break; 1288 case 32: 1289 priv->can.bittiming_const = &m_can_bittiming_const_31X; 1290 priv->can.data_bittiming_const = 1291 &m_can_data_bittiming_const_31X; 1292 priv->can.ctrlmode_supported |= (m_can_niso_supported(priv) 1293 ? CAN_CTRLMODE_FD_NON_ISO 1294 : 0); 1295 break; 1296 default: 1297 dev_err(&pdev->dev, "Unsupported version number: %2d", 1298 priv->version); 1299 return -EINVAL; 1300 } 1301 1302 return 0; 1303 } 1304 1305 static int m_can_open(struct net_device *dev) 1306 { 1307 struct m_can_priv *priv = netdev_priv(dev); 1308 int err; 1309 1310 err = m_can_clk_start(priv); 1311 if (err) 1312 return err; 1313 1314 /* open the can device */ 1315 err = open_candev(dev); 1316 if (err) { 1317 netdev_err(dev, "failed to open can device\n"); 1318 goto exit_disable_clks; 1319 } 1320 1321 /* register interrupt handler */ 1322 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, 1323 dev); 1324 if (err < 0) { 1325 netdev_err(dev, "failed to request interrupt\n"); 1326 goto exit_irq_fail; 1327 } 1328 1329 /* start the m_can controller */ 1330 m_can_start(dev); 1331 1332 can_led_event(dev, CAN_LED_EVENT_OPEN); 1333 napi_enable(&priv->napi); 1334 netif_start_queue(dev); 1335 1336 return 0; 1337 1338 exit_irq_fail: 1339 close_candev(dev); 1340 exit_disable_clks: 1341 m_can_clk_stop(priv); 1342 return err; 1343 } 1344 1345 static void m_can_stop(struct net_device *dev) 1346 { 1347 struct m_can_priv *priv = netdev_priv(dev); 1348 1349 /* disable all interrupts */ 1350 m_can_disable_all_interrupts(priv); 1351 1352 /* set the state as STOPPED */ 1353 priv->can.state = CAN_STATE_STOPPED; 1354 } 1355 1356 static int m_can_close(struct net_device *dev) 1357 { 1358 struct m_can_priv *priv = netdev_priv(dev); 1359 1360 netif_stop_queue(dev); 1361 napi_disable(&priv->napi); 1362 m_can_stop(dev); 1363 m_can_clk_stop(priv); 1364 free_irq(dev->irq, dev); 1365 close_candev(dev); 1366 can_led_event(dev, CAN_LED_EVENT_STOP); 1367 1368 return 0; 1369 } 1370 1371 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx) 1372 { 1373 struct m_can_priv *priv = netdev_priv(dev); 1374 /*get wrap around for loopback skb index */ 1375 unsigned int wrap = priv->can.echo_skb_max; 1376 int next_idx; 1377 1378 /* calculate next index */ 1379 next_idx = (++putidx >= wrap ? 0 : putidx); 1380 1381 /* check if occupied */ 1382 return !!priv->can.echo_skb[next_idx]; 1383 } 1384 1385 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, 1386 struct net_device *dev) 1387 { 1388 struct m_can_priv *priv = netdev_priv(dev); 1389 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 1390 u32 id, cccr, fdflags; 1391 int i; 1392 int putidx; 1393 1394 if (can_dropped_invalid_skb(dev, skb)) 1395 return NETDEV_TX_OK; 1396 1397 /* Generate ID field for TX buffer Element */ 1398 /* Common to all supported M_CAN versions */ 1399 if (cf->can_id & CAN_EFF_FLAG) { 1400 id = cf->can_id & CAN_EFF_MASK; 1401 id |= TX_BUF_XTD; 1402 } else { 1403 id = ((cf->can_id & CAN_SFF_MASK) << 18); 1404 } 1405 1406 if (cf->can_id & CAN_RTR_FLAG) 1407 id |= TX_BUF_RTR; 1408 1409 if (priv->version == 30) { 1410 netif_stop_queue(dev); 1411 1412 /* message ram configuration */ 1413 m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id); 1414 m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, 1415 can_len2dlc(cf->len) << 16); 1416 1417 for (i = 0; i < cf->len; i += 4) 1418 m_can_fifo_write(priv, 0, 1419 M_CAN_FIFO_DATA(i / 4), 1420 *(u32 *)(cf->data + i)); 1421 1422 can_put_echo_skb(skb, dev, 0); 1423 1424 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1425 cccr = m_can_read(priv, M_CAN_CCCR); 1426 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT); 1427 if (can_is_canfd_skb(skb)) { 1428 if (cf->flags & CANFD_BRS) 1429 cccr |= CCCR_CMR_CANFD_BRS << 1430 CCCR_CMR_SHIFT; 1431 else 1432 cccr |= CCCR_CMR_CANFD << 1433 CCCR_CMR_SHIFT; 1434 } else { 1435 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT; 1436 } 1437 m_can_write(priv, M_CAN_CCCR, cccr); 1438 } 1439 m_can_write(priv, M_CAN_TXBTIE, 0x1); 1440 m_can_write(priv, M_CAN_TXBAR, 0x1); 1441 /* End of xmit function for version 3.0.x */ 1442 } else { 1443 /* Transmit routine for version >= v3.1.x */ 1444 1445 /* Check if FIFO full */ 1446 if (m_can_tx_fifo_full(priv)) { 1447 /* This shouldn't happen */ 1448 netif_stop_queue(dev); 1449 netdev_warn(dev, 1450 "TX queue active although FIFO is full."); 1451 return NETDEV_TX_BUSY; 1452 } 1453 1454 /* get put index for frame */ 1455 putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK) 1456 >> TXFQS_TFQPI_SHIFT); 1457 /* Write ID Field to FIFO Element */ 1458 m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id); 1459 1460 /* get CAN FD configuration of frame */ 1461 fdflags = 0; 1462 if (can_is_canfd_skb(skb)) { 1463 fdflags |= TX_BUF_FDF; 1464 if (cf->flags & CANFD_BRS) 1465 fdflags |= TX_BUF_BRS; 1466 } 1467 1468 /* Construct DLC Field. Also contains CAN-FD configuration 1469 * use put index of fifo as message marker 1470 * it is used in TX interrupt for 1471 * sending the correct echo frame 1472 */ 1473 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC, 1474 ((putidx << TX_BUF_MM_SHIFT) & 1475 TX_BUF_MM_MASK) | 1476 (can_len2dlc(cf->len) << 16) | 1477 fdflags | TX_BUF_EFC); 1478 1479 for (i = 0; i < cf->len; i += 4) 1480 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4), 1481 *(u32 *)(cf->data + i)); 1482 1483 /* Push loopback echo. 1484 * Will be looped back on TX interrupt based on message marker 1485 */ 1486 can_put_echo_skb(skb, dev, putidx); 1487 1488 /* Enable TX FIFO element to start transfer */ 1489 m_can_write(priv, M_CAN_TXBAR, (1 << putidx)); 1490 1491 /* stop network queue if fifo full */ 1492 if (m_can_tx_fifo_full(priv) || 1493 m_can_next_echo_skb_occupied(dev, putidx)) 1494 netif_stop_queue(dev); 1495 } 1496 1497 return NETDEV_TX_OK; 1498 } 1499 1500 static const struct net_device_ops m_can_netdev_ops = { 1501 .ndo_open = m_can_open, 1502 .ndo_stop = m_can_close, 1503 .ndo_start_xmit = m_can_start_xmit, 1504 .ndo_change_mtu = can_change_mtu, 1505 }; 1506 1507 static int register_m_can_dev(struct net_device *dev) 1508 { 1509 dev->flags |= IFF_ECHO; /* we support local echo */ 1510 dev->netdev_ops = &m_can_netdev_ops; 1511 1512 return register_candev(dev); 1513 } 1514 1515 static void m_can_init_ram(struct m_can_priv *priv) 1516 { 1517 int end, i, start; 1518 1519 /* initialize the entire Message RAM in use to avoid possible 1520 * ECC/parity checksum errors when reading an uninitialized buffer 1521 */ 1522 start = priv->mcfg[MRAM_SIDF].off; 1523 end = priv->mcfg[MRAM_TXB].off + 1524 priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 1525 for (i = start; i < end; i += 4) 1526 writel(0x0, priv->mram_base + i); 1527 } 1528 1529 static void m_can_of_parse_mram(struct m_can_priv *priv, 1530 const u32 *mram_config_vals) 1531 { 1532 priv->mcfg[MRAM_SIDF].off = mram_config_vals[0]; 1533 priv->mcfg[MRAM_SIDF].num = mram_config_vals[1]; 1534 priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off + 1535 priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; 1536 priv->mcfg[MRAM_XIDF].num = mram_config_vals[2]; 1537 priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off + 1538 priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; 1539 priv->mcfg[MRAM_RXF0].num = mram_config_vals[3] & 1540 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1541 priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off + 1542 priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; 1543 priv->mcfg[MRAM_RXF1].num = mram_config_vals[4] & 1544 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1545 priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off + 1546 priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; 1547 priv->mcfg[MRAM_RXB].num = mram_config_vals[5]; 1548 priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off + 1549 priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; 1550 priv->mcfg[MRAM_TXE].num = mram_config_vals[6]; 1551 priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off + 1552 priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; 1553 priv->mcfg[MRAM_TXB].num = mram_config_vals[7] & 1554 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT); 1555 1556 dev_dbg(priv->device, 1557 "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", 1558 priv->mram_base, 1559 priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num, 1560 priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num, 1561 priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num, 1562 priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num, 1563 priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num, 1564 priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num, 1565 priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num); 1566 1567 m_can_init_ram(priv); 1568 } 1569 1570 static int m_can_plat_probe(struct platform_device *pdev) 1571 { 1572 struct net_device *dev; 1573 struct m_can_priv *priv; 1574 struct resource *res; 1575 void __iomem *addr; 1576 void __iomem *mram_addr; 1577 struct clk *hclk, *cclk; 1578 int irq, ret; 1579 struct device_node *np; 1580 u32 mram_config_vals[MRAM_CFG_LEN]; 1581 u32 tx_fifo_size; 1582 1583 np = pdev->dev.of_node; 1584 1585 hclk = devm_clk_get(&pdev->dev, "hclk"); 1586 cclk = devm_clk_get(&pdev->dev, "cclk"); 1587 1588 if (IS_ERR(hclk) || IS_ERR(cclk)) { 1589 dev_err(&pdev->dev, "no clock found\n"); 1590 ret = -ENODEV; 1591 goto failed_ret; 1592 } 1593 1594 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can"); 1595 addr = devm_ioremap_resource(&pdev->dev, res); 1596 irq = platform_get_irq_byname(pdev, "int0"); 1597 1598 if (IS_ERR(addr) || irq < 0) { 1599 ret = -EINVAL; 1600 goto failed_ret; 1601 } 1602 1603 /* message ram could be shared */ 1604 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram"); 1605 if (!res) { 1606 ret = -ENODEV; 1607 goto failed_ret; 1608 } 1609 1610 mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1611 if (!mram_addr) { 1612 ret = -ENOMEM; 1613 goto failed_ret; 1614 } 1615 1616 /* get message ram configuration */ 1617 ret = of_property_read_u32_array(np, "bosch,mram-cfg", 1618 mram_config_vals, 1619 sizeof(mram_config_vals) / 4); 1620 if (ret) { 1621 dev_err(&pdev->dev, "Could not get Message RAM configuration."); 1622 goto failed_ret; 1623 } 1624 1625 /* Get TX FIFO size 1626 * Defines the total amount of echo buffers for loopback 1627 */ 1628 tx_fifo_size = mram_config_vals[7]; 1629 1630 /* allocate the m_can device */ 1631 dev = alloc_candev(sizeof(*priv), tx_fifo_size); 1632 if (!dev) { 1633 ret = -ENOMEM; 1634 goto failed_ret; 1635 } 1636 1637 priv = netdev_priv(dev); 1638 dev->irq = irq; 1639 priv->device = &pdev->dev; 1640 priv->hclk = hclk; 1641 priv->cclk = cclk; 1642 priv->can.clock.freq = clk_get_rate(cclk); 1643 priv->mram_base = mram_addr; 1644 1645 m_can_of_parse_mram(priv, mram_config_vals); 1646 1647 platform_set_drvdata(pdev, dev); 1648 SET_NETDEV_DEV(dev, &pdev->dev); 1649 1650 /* Enable clocks. Necessary to read Core Release in order to determine 1651 * M_CAN version 1652 */ 1653 pm_runtime_enable(&pdev->dev); 1654 ret = m_can_clk_start(priv); 1655 if (ret) 1656 goto pm_runtime_fail; 1657 1658 ret = m_can_dev_setup(pdev, dev, addr); 1659 if (ret) 1660 goto clk_disable; 1661 1662 ret = register_m_can_dev(dev); 1663 if (ret) { 1664 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 1665 KBUILD_MODNAME, ret); 1666 goto clk_disable; 1667 } 1668 1669 devm_can_led_init(dev); 1670 1671 of_can_transceiver(dev); 1672 1673 dev_info(&pdev->dev, "%s device registered (irq=%d, version=%d)\n", 1674 KBUILD_MODNAME, dev->irq, priv->version); 1675 1676 /* Probe finished 1677 * Stop clocks. They will be reactivated once the M_CAN device is opened 1678 */ 1679 clk_disable: 1680 m_can_clk_stop(priv); 1681 pm_runtime_fail: 1682 if (ret) { 1683 pm_runtime_disable(&pdev->dev); 1684 free_candev(dev); 1685 } 1686 failed_ret: 1687 return ret; 1688 } 1689 1690 /* TODO: runtime PM with power down or sleep mode */ 1691 1692 static __maybe_unused int m_can_suspend(struct device *dev) 1693 { 1694 struct net_device *ndev = dev_get_drvdata(dev); 1695 struct m_can_priv *priv = netdev_priv(ndev); 1696 1697 if (netif_running(ndev)) { 1698 netif_stop_queue(ndev); 1699 netif_device_detach(ndev); 1700 m_can_stop(ndev); 1701 m_can_clk_stop(priv); 1702 } 1703 1704 pinctrl_pm_select_sleep_state(dev); 1705 1706 priv->can.state = CAN_STATE_SLEEPING; 1707 1708 return 0; 1709 } 1710 1711 static __maybe_unused int m_can_resume(struct device *dev) 1712 { 1713 struct net_device *ndev = dev_get_drvdata(dev); 1714 struct m_can_priv *priv = netdev_priv(ndev); 1715 1716 pinctrl_pm_select_default_state(dev); 1717 1718 m_can_init_ram(priv); 1719 1720 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1721 1722 if (netif_running(ndev)) { 1723 int ret; 1724 1725 ret = m_can_clk_start(priv); 1726 if (ret) 1727 return ret; 1728 1729 m_can_start(ndev); 1730 netif_device_attach(ndev); 1731 netif_start_queue(ndev); 1732 } 1733 1734 return 0; 1735 } 1736 1737 static void unregister_m_can_dev(struct net_device *dev) 1738 { 1739 unregister_candev(dev); 1740 } 1741 1742 static int m_can_plat_remove(struct platform_device *pdev) 1743 { 1744 struct net_device *dev = platform_get_drvdata(pdev); 1745 1746 unregister_m_can_dev(dev); 1747 1748 pm_runtime_disable(&pdev->dev); 1749 1750 platform_set_drvdata(pdev, NULL); 1751 1752 free_candev(dev); 1753 1754 return 0; 1755 } 1756 1757 static int __maybe_unused m_can_runtime_suspend(struct device *dev) 1758 { 1759 struct net_device *ndev = dev_get_drvdata(dev); 1760 struct m_can_priv *priv = netdev_priv(ndev); 1761 1762 clk_disable_unprepare(priv->cclk); 1763 clk_disable_unprepare(priv->hclk); 1764 1765 return 0; 1766 } 1767 1768 static int __maybe_unused m_can_runtime_resume(struct device *dev) 1769 { 1770 struct net_device *ndev = dev_get_drvdata(dev); 1771 struct m_can_priv *priv = netdev_priv(ndev); 1772 int err; 1773 1774 err = clk_prepare_enable(priv->hclk); 1775 if (err) 1776 return err; 1777 1778 err = clk_prepare_enable(priv->cclk); 1779 if (err) 1780 clk_disable_unprepare(priv->hclk); 1781 1782 return err; 1783 } 1784 1785 static const struct dev_pm_ops m_can_pmops = { 1786 SET_RUNTIME_PM_OPS(m_can_runtime_suspend, 1787 m_can_runtime_resume, NULL) 1788 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume) 1789 }; 1790 1791 static const struct of_device_id m_can_of_table[] = { 1792 { .compatible = "bosch,m_can", .data = NULL }, 1793 { /* sentinel */ }, 1794 }; 1795 MODULE_DEVICE_TABLE(of, m_can_of_table); 1796 1797 static struct platform_driver m_can_plat_driver = { 1798 .driver = { 1799 .name = KBUILD_MODNAME, 1800 .of_match_table = m_can_of_table, 1801 .pm = &m_can_pmops, 1802 }, 1803 .probe = m_can_plat_probe, 1804 .remove = m_can_plat_remove, 1805 }; 1806 1807 module_platform_driver(m_can_plat_driver); 1808 1809 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); 1810 MODULE_LICENSE("GPL v2"); 1811 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); 1812