1 /* 2 * CAN bus driver for Bosch M_CAN controller 3 * 4 * Copyright (C) 2014 Freescale Semiconductor, Inc. 5 * Dong Aisheng <b29396@freescale.com> 6 * 7 * Bosch M_CAN user manual can be obtained from: 8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/ 9 * mcan_users_manual_v302.pdf 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/netdevice.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/platform_device.h> 26 27 #include <linux/can/dev.h> 28 29 /* napi related */ 30 #define M_CAN_NAPI_WEIGHT 64 31 32 /* message ram configuration data length */ 33 #define MRAM_CFG_LEN 8 34 35 /* registers definition */ 36 enum m_can_reg { 37 M_CAN_CREL = 0x0, 38 M_CAN_ENDN = 0x4, 39 M_CAN_CUST = 0x8, 40 M_CAN_FBTP = 0xc, 41 M_CAN_TEST = 0x10, 42 M_CAN_RWD = 0x14, 43 M_CAN_CCCR = 0x18, 44 M_CAN_BTP = 0x1c, 45 M_CAN_TSCC = 0x20, 46 M_CAN_TSCV = 0x24, 47 M_CAN_TOCC = 0x28, 48 M_CAN_TOCV = 0x2c, 49 M_CAN_ECR = 0x40, 50 M_CAN_PSR = 0x44, 51 M_CAN_IR = 0x50, 52 M_CAN_IE = 0x54, 53 M_CAN_ILS = 0x58, 54 M_CAN_ILE = 0x5c, 55 M_CAN_GFC = 0x80, 56 M_CAN_SIDFC = 0x84, 57 M_CAN_XIDFC = 0x88, 58 M_CAN_XIDAM = 0x90, 59 M_CAN_HPMS = 0x94, 60 M_CAN_NDAT1 = 0x98, 61 M_CAN_NDAT2 = 0x9c, 62 M_CAN_RXF0C = 0xa0, 63 M_CAN_RXF0S = 0xa4, 64 M_CAN_RXF0A = 0xa8, 65 M_CAN_RXBC = 0xac, 66 M_CAN_RXF1C = 0xb0, 67 M_CAN_RXF1S = 0xb4, 68 M_CAN_RXF1A = 0xb8, 69 M_CAN_RXESC = 0xbc, 70 M_CAN_TXBC = 0xc0, 71 M_CAN_TXFQS = 0xc4, 72 M_CAN_TXESC = 0xc8, 73 M_CAN_TXBRP = 0xcc, 74 M_CAN_TXBAR = 0xd0, 75 M_CAN_TXBCR = 0xd4, 76 M_CAN_TXBTO = 0xd8, 77 M_CAN_TXBCF = 0xdc, 78 M_CAN_TXBTIE = 0xe0, 79 M_CAN_TXBCIE = 0xe4, 80 M_CAN_TXEFC = 0xf0, 81 M_CAN_TXEFS = 0xf4, 82 M_CAN_TXEFA = 0xf8, 83 }; 84 85 /* m_can lec values */ 86 enum m_can_lec_type { 87 LEC_NO_ERROR = 0, 88 LEC_STUFF_ERROR, 89 LEC_FORM_ERROR, 90 LEC_ACK_ERROR, 91 LEC_BIT1_ERROR, 92 LEC_BIT0_ERROR, 93 LEC_CRC_ERROR, 94 LEC_UNUSED, 95 }; 96 97 enum m_can_mram_cfg { 98 MRAM_SIDF = 0, 99 MRAM_XIDF, 100 MRAM_RXF0, 101 MRAM_RXF1, 102 MRAM_RXB, 103 MRAM_TXE, 104 MRAM_TXB, 105 MRAM_CFG_NUM, 106 }; 107 108 /* Test Register (TEST) */ 109 #define TEST_LBCK BIT(4) 110 111 /* CC Control Register(CCCR) */ 112 #define CCCR_TEST BIT(7) 113 #define CCCR_MON BIT(5) 114 #define CCCR_CCE BIT(1) 115 #define CCCR_INIT BIT(0) 116 117 /* Bit Timing & Prescaler Register (BTP) */ 118 #define BTR_BRP_MASK 0x3ff 119 #define BTR_BRP_SHIFT 16 120 #define BTR_TSEG1_SHIFT 8 121 #define BTR_TSEG1_MASK (0x3f << BTR_TSEG1_SHIFT) 122 #define BTR_TSEG2_SHIFT 4 123 #define BTR_TSEG2_MASK (0xf << BTR_TSEG2_SHIFT) 124 #define BTR_SJW_SHIFT 0 125 #define BTR_SJW_MASK 0xf 126 127 /* Error Counter Register(ECR) */ 128 #define ECR_RP BIT(15) 129 #define ECR_REC_SHIFT 8 130 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT) 131 #define ECR_TEC_SHIFT 0 132 #define ECR_TEC_MASK 0xff 133 134 /* Protocol Status Register(PSR) */ 135 #define PSR_BO BIT(7) 136 #define PSR_EW BIT(6) 137 #define PSR_EP BIT(5) 138 #define PSR_LEC_MASK 0x7 139 140 /* Interrupt Register(IR) */ 141 #define IR_ALL_INT 0xffffffff 142 #define IR_STE BIT(31) 143 #define IR_FOE BIT(30) 144 #define IR_ACKE BIT(29) 145 #define IR_BE BIT(28) 146 #define IR_CRCE BIT(27) 147 #define IR_WDI BIT(26) 148 #define IR_BO BIT(25) 149 #define IR_EW BIT(24) 150 #define IR_EP BIT(23) 151 #define IR_ELO BIT(22) 152 #define IR_BEU BIT(21) 153 #define IR_BEC BIT(20) 154 #define IR_DRX BIT(19) 155 #define IR_TOO BIT(18) 156 #define IR_MRAF BIT(17) 157 #define IR_TSW BIT(16) 158 #define IR_TEFL BIT(15) 159 #define IR_TEFF BIT(14) 160 #define IR_TEFW BIT(13) 161 #define IR_TEFN BIT(12) 162 #define IR_TFE BIT(11) 163 #define IR_TCF BIT(10) 164 #define IR_TC BIT(9) 165 #define IR_HPM BIT(8) 166 #define IR_RF1L BIT(7) 167 #define IR_RF1F BIT(6) 168 #define IR_RF1W BIT(5) 169 #define IR_RF1N BIT(4) 170 #define IR_RF0L BIT(3) 171 #define IR_RF0F BIT(2) 172 #define IR_RF0W BIT(1) 173 #define IR_RF0N BIT(0) 174 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) 175 #define IR_ERR_LEC (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) 176 #define IR_ERR_BUS (IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | \ 177 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 178 IR_RF1L | IR_RF0L) 179 #define IR_ERR_ALL (IR_ERR_STATE | IR_ERR_BUS) 180 181 /* Interrupt Line Select (ILS) */ 182 #define ILS_ALL_INT0 0x0 183 #define ILS_ALL_INT1 0xFFFFFFFF 184 185 /* Interrupt Line Enable (ILE) */ 186 #define ILE_EINT0 BIT(0) 187 #define ILE_EINT1 BIT(1) 188 189 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ 190 #define RXFC_FWM_OFF 24 191 #define RXFC_FWM_MASK 0x7f 192 #define RXFC_FWM_1 (1 << RXFC_FWM_OFF) 193 #define RXFC_FS_OFF 16 194 #define RXFC_FS_MASK 0x7f 195 196 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ 197 #define RXFS_RFL BIT(25) 198 #define RXFS_FF BIT(24) 199 #define RXFS_FPI_OFF 16 200 #define RXFS_FPI_MASK 0x3f0000 201 #define RXFS_FGI_OFF 8 202 #define RXFS_FGI_MASK 0x3f00 203 #define RXFS_FFL_MASK 0x7f 204 205 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ 206 #define M_CAN_RXESC_8BYTES 0x0 207 208 /* Tx Buffer Configuration(TXBC) */ 209 #define TXBC_NDTB_OFF 16 210 #define TXBC_NDTB_MASK 0x3f 211 212 /* Tx Buffer Element Size Configuration(TXESC) */ 213 #define TXESC_TBDS_8BYTES 0x0 214 215 /* Tx Event FIFO Con.guration (TXEFC) */ 216 #define TXEFC_EFS_OFF 16 217 #define TXEFC_EFS_MASK 0x3f 218 219 /* Message RAM Configuration (in bytes) */ 220 #define SIDF_ELEMENT_SIZE 4 221 #define XIDF_ELEMENT_SIZE 8 222 #define RXF0_ELEMENT_SIZE 16 223 #define RXF1_ELEMENT_SIZE 16 224 #define RXB_ELEMENT_SIZE 16 225 #define TXE_ELEMENT_SIZE 8 226 #define TXB_ELEMENT_SIZE 16 227 228 /* Message RAM Elements */ 229 #define M_CAN_FIFO_ID 0x0 230 #define M_CAN_FIFO_DLC 0x4 231 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2)) 232 233 /* Rx Buffer Element */ 234 #define RX_BUF_ESI BIT(31) 235 #define RX_BUF_XTD BIT(30) 236 #define RX_BUF_RTR BIT(29) 237 238 /* Tx Buffer Element */ 239 #define TX_BUF_XTD BIT(30) 240 #define TX_BUF_RTR BIT(29) 241 242 /* address offset and element number for each FIFO/Buffer in the Message RAM */ 243 struct mram_cfg { 244 u16 off; 245 u8 num; 246 }; 247 248 /* m_can private data structure */ 249 struct m_can_priv { 250 struct can_priv can; /* must be the first member */ 251 struct napi_struct napi; 252 struct net_device *dev; 253 struct device *device; 254 struct clk *hclk; 255 struct clk *cclk; 256 void __iomem *base; 257 u32 irqstatus; 258 259 /* message ram configuration */ 260 void __iomem *mram_base; 261 struct mram_cfg mcfg[MRAM_CFG_NUM]; 262 }; 263 264 static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg) 265 { 266 return readl(priv->base + reg); 267 } 268 269 static inline void m_can_write(const struct m_can_priv *priv, 270 enum m_can_reg reg, u32 val) 271 { 272 writel(val, priv->base + reg); 273 } 274 275 static inline u32 m_can_fifo_read(const struct m_can_priv *priv, 276 u32 fgi, unsigned int offset) 277 { 278 return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off + 279 fgi * RXF0_ELEMENT_SIZE + offset); 280 } 281 282 static inline void m_can_fifo_write(const struct m_can_priv *priv, 283 u32 fpi, unsigned int offset, u32 val) 284 { 285 return writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off + 286 fpi * TXB_ELEMENT_SIZE + offset); 287 } 288 289 static inline void m_can_config_endisable(const struct m_can_priv *priv, 290 bool enable) 291 { 292 u32 cccr = m_can_read(priv, M_CAN_CCCR); 293 u32 timeout = 10; 294 u32 val = 0; 295 296 if (enable) { 297 /* enable m_can configuration */ 298 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT); 299 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ 300 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); 301 } else { 302 m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); 303 } 304 305 /* there's a delay for module initialization */ 306 if (enable) 307 val = CCCR_INIT | CCCR_CCE; 308 309 while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { 310 if (timeout == 0) { 311 netdev_warn(priv->dev, "Failed to init module\n"); 312 return; 313 } 314 timeout--; 315 udelay(1); 316 } 317 } 318 319 static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv) 320 { 321 m_can_write(priv, M_CAN_ILE, ILE_EINT0 | ILE_EINT1); 322 } 323 324 static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv) 325 { 326 m_can_write(priv, M_CAN_ILE, 0x0); 327 } 328 329 static void m_can_read_fifo(const struct net_device *dev, struct can_frame *cf, 330 u32 rxfs) 331 { 332 struct m_can_priv *priv = netdev_priv(dev); 333 u32 id, fgi; 334 335 /* calculate the fifo get index for where to read data */ 336 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF; 337 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID); 338 if (id & RX_BUF_XTD) 339 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 340 else 341 cf->can_id = (id >> 18) & CAN_SFF_MASK; 342 343 if (id & RX_BUF_RTR) { 344 cf->can_id |= CAN_RTR_FLAG; 345 } else { 346 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC); 347 cf->can_dlc = get_can_dlc((id >> 16) & 0x0F); 348 *(u32 *)(cf->data + 0) = m_can_fifo_read(priv, fgi, 349 M_CAN_FIFO_DATA(0)); 350 *(u32 *)(cf->data + 4) = m_can_fifo_read(priv, fgi, 351 M_CAN_FIFO_DATA(1)); 352 } 353 354 /* acknowledge rx fifo 0 */ 355 m_can_write(priv, M_CAN_RXF0A, fgi); 356 } 357 358 static int m_can_do_rx_poll(struct net_device *dev, int quota) 359 { 360 struct m_can_priv *priv = netdev_priv(dev); 361 struct net_device_stats *stats = &dev->stats; 362 struct sk_buff *skb; 363 struct can_frame *frame; 364 u32 pkts = 0; 365 u32 rxfs; 366 367 rxfs = m_can_read(priv, M_CAN_RXF0S); 368 if (!(rxfs & RXFS_FFL_MASK)) { 369 netdev_dbg(dev, "no messages in fifo0\n"); 370 return 0; 371 } 372 373 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) { 374 if (rxfs & RXFS_RFL) 375 netdev_warn(dev, "Rx FIFO 0 Message Lost\n"); 376 377 skb = alloc_can_skb(dev, &frame); 378 if (!skb) { 379 stats->rx_dropped++; 380 return pkts; 381 } 382 383 m_can_read_fifo(dev, frame, rxfs); 384 385 stats->rx_packets++; 386 stats->rx_bytes += frame->can_dlc; 387 388 netif_receive_skb(skb); 389 390 quota--; 391 pkts++; 392 rxfs = m_can_read(priv, M_CAN_RXF0S); 393 } 394 395 if (pkts) 396 can_led_event(dev, CAN_LED_EVENT_RX); 397 398 return pkts; 399 } 400 401 static int m_can_handle_lost_msg(struct net_device *dev) 402 { 403 struct net_device_stats *stats = &dev->stats; 404 struct sk_buff *skb; 405 struct can_frame *frame; 406 407 netdev_err(dev, "msg lost in rxf0\n"); 408 409 stats->rx_errors++; 410 stats->rx_over_errors++; 411 412 skb = alloc_can_err_skb(dev, &frame); 413 if (unlikely(!skb)) 414 return 0; 415 416 frame->can_id |= CAN_ERR_CRTL; 417 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 418 419 netif_receive_skb(skb); 420 421 return 1; 422 } 423 424 static int m_can_handle_lec_err(struct net_device *dev, 425 enum m_can_lec_type lec_type) 426 { 427 struct m_can_priv *priv = netdev_priv(dev); 428 struct net_device_stats *stats = &dev->stats; 429 struct can_frame *cf; 430 struct sk_buff *skb; 431 432 priv->can.can_stats.bus_error++; 433 stats->rx_errors++; 434 435 /* propagate the error condition to the CAN stack */ 436 skb = alloc_can_err_skb(dev, &cf); 437 if (unlikely(!skb)) 438 return 0; 439 440 /* check for 'last error code' which tells us the 441 * type of the last error to occur on the CAN bus 442 */ 443 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 444 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 445 446 switch (lec_type) { 447 case LEC_STUFF_ERROR: 448 netdev_dbg(dev, "stuff error\n"); 449 cf->data[2] |= CAN_ERR_PROT_STUFF; 450 break; 451 case LEC_FORM_ERROR: 452 netdev_dbg(dev, "form error\n"); 453 cf->data[2] |= CAN_ERR_PROT_FORM; 454 break; 455 case LEC_ACK_ERROR: 456 netdev_dbg(dev, "ack error\n"); 457 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 458 CAN_ERR_PROT_LOC_ACK_DEL); 459 break; 460 case LEC_BIT1_ERROR: 461 netdev_dbg(dev, "bit1 error\n"); 462 cf->data[2] |= CAN_ERR_PROT_BIT1; 463 break; 464 case LEC_BIT0_ERROR: 465 netdev_dbg(dev, "bit0 error\n"); 466 cf->data[2] |= CAN_ERR_PROT_BIT0; 467 break; 468 case LEC_CRC_ERROR: 469 netdev_dbg(dev, "CRC error\n"); 470 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 471 CAN_ERR_PROT_LOC_CRC_DEL); 472 break; 473 default: 474 break; 475 } 476 477 stats->rx_packets++; 478 stats->rx_bytes += cf->can_dlc; 479 netif_receive_skb(skb); 480 481 return 1; 482 } 483 484 static int m_can_get_berr_counter(const struct net_device *dev, 485 struct can_berr_counter *bec) 486 { 487 struct m_can_priv *priv = netdev_priv(dev); 488 unsigned int ecr; 489 int err; 490 491 err = clk_prepare_enable(priv->hclk); 492 if (err) 493 return err; 494 495 err = clk_prepare_enable(priv->cclk); 496 if (err) { 497 clk_disable_unprepare(priv->hclk); 498 return err; 499 } 500 501 ecr = m_can_read(priv, M_CAN_ECR); 502 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT; 503 bec->txerr = ecr & ECR_TEC_MASK; 504 505 clk_disable_unprepare(priv->cclk); 506 clk_disable_unprepare(priv->hclk); 507 508 return 0; 509 } 510 511 static int m_can_handle_state_change(struct net_device *dev, 512 enum can_state new_state) 513 { 514 struct m_can_priv *priv = netdev_priv(dev); 515 struct net_device_stats *stats = &dev->stats; 516 struct can_frame *cf; 517 struct sk_buff *skb; 518 struct can_berr_counter bec; 519 unsigned int ecr; 520 521 switch (new_state) { 522 case CAN_STATE_ERROR_ACTIVE: 523 /* error warning state */ 524 priv->can.can_stats.error_warning++; 525 priv->can.state = CAN_STATE_ERROR_WARNING; 526 break; 527 case CAN_STATE_ERROR_PASSIVE: 528 /* error passive state */ 529 priv->can.can_stats.error_passive++; 530 priv->can.state = CAN_STATE_ERROR_PASSIVE; 531 break; 532 case CAN_STATE_BUS_OFF: 533 /* bus-off state */ 534 priv->can.state = CAN_STATE_BUS_OFF; 535 m_can_disable_all_interrupts(priv); 536 can_bus_off(dev); 537 break; 538 default: 539 break; 540 } 541 542 /* propagate the error condition to the CAN stack */ 543 skb = alloc_can_err_skb(dev, &cf); 544 if (unlikely(!skb)) 545 return 0; 546 547 m_can_get_berr_counter(dev, &bec); 548 549 switch (new_state) { 550 case CAN_STATE_ERROR_ACTIVE: 551 /* error warning state */ 552 cf->can_id |= CAN_ERR_CRTL; 553 cf->data[1] = (bec.txerr > bec.rxerr) ? 554 CAN_ERR_CRTL_TX_WARNING : 555 CAN_ERR_CRTL_RX_WARNING; 556 cf->data[6] = bec.txerr; 557 cf->data[7] = bec.rxerr; 558 break; 559 case CAN_STATE_ERROR_PASSIVE: 560 /* error passive state */ 561 cf->can_id |= CAN_ERR_CRTL; 562 ecr = m_can_read(priv, M_CAN_ECR); 563 if (ecr & ECR_RP) 564 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 565 if (bec.txerr > 127) 566 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 567 cf->data[6] = bec.txerr; 568 cf->data[7] = bec.rxerr; 569 break; 570 case CAN_STATE_BUS_OFF: 571 /* bus-off state */ 572 cf->can_id |= CAN_ERR_BUSOFF; 573 break; 574 default: 575 break; 576 } 577 578 stats->rx_packets++; 579 stats->rx_bytes += cf->can_dlc; 580 netif_receive_skb(skb); 581 582 return 1; 583 } 584 585 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) 586 { 587 struct m_can_priv *priv = netdev_priv(dev); 588 int work_done = 0; 589 590 if ((psr & PSR_EW) && 591 (priv->can.state != CAN_STATE_ERROR_WARNING)) { 592 netdev_dbg(dev, "entered error warning state\n"); 593 work_done += m_can_handle_state_change(dev, 594 CAN_STATE_ERROR_WARNING); 595 } 596 597 if ((psr & PSR_EP) && 598 (priv->can.state != CAN_STATE_ERROR_PASSIVE)) { 599 netdev_dbg(dev, "entered error warning state\n"); 600 work_done += m_can_handle_state_change(dev, 601 CAN_STATE_ERROR_PASSIVE); 602 } 603 604 if ((psr & PSR_BO) && 605 (priv->can.state != CAN_STATE_BUS_OFF)) { 606 netdev_dbg(dev, "entered error warning state\n"); 607 work_done += m_can_handle_state_change(dev, 608 CAN_STATE_BUS_OFF); 609 } 610 611 return work_done; 612 } 613 614 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) 615 { 616 if (irqstatus & IR_WDI) 617 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); 618 if (irqstatus & IR_BEU) 619 netdev_err(dev, "Error Logging Overflow\n"); 620 if (irqstatus & IR_BEU) 621 netdev_err(dev, "Bit Error Uncorrected\n"); 622 if (irqstatus & IR_BEC) 623 netdev_err(dev, "Bit Error Corrected\n"); 624 if (irqstatus & IR_TOO) 625 netdev_err(dev, "Timeout reached\n"); 626 if (irqstatus & IR_MRAF) 627 netdev_err(dev, "Message RAM access failure occurred\n"); 628 } 629 630 static inline bool is_lec_err(u32 psr) 631 { 632 psr &= LEC_UNUSED; 633 634 return psr && (psr != LEC_UNUSED); 635 } 636 637 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, 638 u32 psr) 639 { 640 struct m_can_priv *priv = netdev_priv(dev); 641 int work_done = 0; 642 643 if (irqstatus & IR_RF0L) 644 work_done += m_can_handle_lost_msg(dev); 645 646 /* handle lec errors on the bus */ 647 if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 648 is_lec_err(psr)) 649 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED); 650 651 /* other unproccessed error interrupts */ 652 m_can_handle_other_err(dev, irqstatus); 653 654 return work_done; 655 } 656 657 static int m_can_poll(struct napi_struct *napi, int quota) 658 { 659 struct net_device *dev = napi->dev; 660 struct m_can_priv *priv = netdev_priv(dev); 661 int work_done = 0; 662 u32 irqstatus, psr; 663 664 irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR); 665 if (!irqstatus) 666 goto end; 667 668 psr = m_can_read(priv, M_CAN_PSR); 669 if (irqstatus & IR_ERR_STATE) 670 work_done += m_can_handle_state_errors(dev, psr); 671 672 if (irqstatus & IR_ERR_BUS) 673 work_done += m_can_handle_bus_errors(dev, irqstatus, psr); 674 675 if (irqstatus & IR_RF0N) 676 work_done += m_can_do_rx_poll(dev, (quota - work_done)); 677 678 if (work_done < quota) { 679 napi_complete(napi); 680 m_can_enable_all_interrupts(priv); 681 } 682 683 end: 684 return work_done; 685 } 686 687 static irqreturn_t m_can_isr(int irq, void *dev_id) 688 { 689 struct net_device *dev = (struct net_device *)dev_id; 690 struct m_can_priv *priv = netdev_priv(dev); 691 struct net_device_stats *stats = &dev->stats; 692 u32 ir; 693 694 ir = m_can_read(priv, M_CAN_IR); 695 if (!ir) 696 return IRQ_NONE; 697 698 /* ACK all irqs */ 699 if (ir & IR_ALL_INT) 700 m_can_write(priv, M_CAN_IR, ir); 701 702 /* schedule NAPI in case of 703 * - rx IRQ 704 * - state change IRQ 705 * - bus error IRQ and bus error reporting 706 */ 707 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) { 708 priv->irqstatus = ir; 709 m_can_disable_all_interrupts(priv); 710 napi_schedule(&priv->napi); 711 } 712 713 /* transmission complete interrupt */ 714 if (ir & IR_TC) { 715 stats->tx_bytes += can_get_echo_skb(dev, 0); 716 stats->tx_packets++; 717 can_led_event(dev, CAN_LED_EVENT_TX); 718 netif_wake_queue(dev); 719 } 720 721 return IRQ_HANDLED; 722 } 723 724 static const struct can_bittiming_const m_can_bittiming_const = { 725 .name = KBUILD_MODNAME, 726 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 727 .tseg1_max = 64, 728 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 729 .tseg2_max = 16, 730 .sjw_max = 16, 731 .brp_min = 1, 732 .brp_max = 1024, 733 .brp_inc = 1, 734 }; 735 736 static int m_can_set_bittiming(struct net_device *dev) 737 { 738 struct m_can_priv *priv = netdev_priv(dev); 739 const struct can_bittiming *bt = &priv->can.bittiming; 740 u16 brp, sjw, tseg1, tseg2; 741 u32 reg_btp; 742 743 brp = bt->brp - 1; 744 sjw = bt->sjw - 1; 745 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 746 tseg2 = bt->phase_seg2 - 1; 747 reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) | 748 (tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT); 749 m_can_write(priv, M_CAN_BTP, reg_btp); 750 netdev_dbg(dev, "setting BTP 0x%x\n", reg_btp); 751 752 return 0; 753 } 754 755 /* Configure M_CAN chip: 756 * - set rx buffer/fifo element size 757 * - configure rx fifo 758 * - accept non-matching frame into fifo 0 759 * - configure tx buffer 760 * - configure mode 761 * - setup bittiming 762 */ 763 static void m_can_chip_config(struct net_device *dev) 764 { 765 struct m_can_priv *priv = netdev_priv(dev); 766 u32 cccr, test; 767 768 m_can_config_endisable(priv, true); 769 770 /* RX Buffer/FIFO Element Size 8 bytes data field */ 771 m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_8BYTES); 772 773 /* Accept Non-matching Frames Into FIFO 0 */ 774 m_can_write(priv, M_CAN_GFC, 0x0); 775 776 /* only support one Tx Buffer currently */ 777 m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) | 778 priv->mcfg[MRAM_TXB].off); 779 780 /* only support 8 bytes firstly */ 781 m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_8BYTES); 782 783 m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) | 784 priv->mcfg[MRAM_TXE].off); 785 786 /* rx fifo configuration, blocking mode, fifo size 1 */ 787 m_can_write(priv, M_CAN_RXF0C, 788 (priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) | 789 RXFC_FWM_1 | priv->mcfg[MRAM_RXF0].off); 790 791 m_can_write(priv, M_CAN_RXF1C, 792 (priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) | 793 RXFC_FWM_1 | priv->mcfg[MRAM_RXF1].off); 794 795 cccr = m_can_read(priv, M_CAN_CCCR); 796 cccr &= ~(CCCR_TEST | CCCR_MON); 797 test = m_can_read(priv, M_CAN_TEST); 798 test &= ~TEST_LBCK; 799 800 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 801 cccr |= CCCR_MON; 802 803 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 804 cccr |= CCCR_TEST; 805 test |= TEST_LBCK; 806 } 807 808 m_can_write(priv, M_CAN_CCCR, cccr); 809 m_can_write(priv, M_CAN_TEST, test); 810 811 /* enable interrupts */ 812 m_can_write(priv, M_CAN_IR, IR_ALL_INT); 813 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 814 m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC); 815 else 816 m_can_write(priv, M_CAN_IE, IR_ALL_INT); 817 818 /* route all interrupts to INT0 */ 819 m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0); 820 821 /* set bittiming params */ 822 m_can_set_bittiming(dev); 823 824 m_can_config_endisable(priv, false); 825 } 826 827 static void m_can_start(struct net_device *dev) 828 { 829 struct m_can_priv *priv = netdev_priv(dev); 830 831 /* basic m_can configuration */ 832 m_can_chip_config(dev); 833 834 priv->can.state = CAN_STATE_ERROR_ACTIVE; 835 836 m_can_enable_all_interrupts(priv); 837 } 838 839 static int m_can_set_mode(struct net_device *dev, enum can_mode mode) 840 { 841 switch (mode) { 842 case CAN_MODE_START: 843 m_can_start(dev); 844 netif_wake_queue(dev); 845 break; 846 default: 847 return -EOPNOTSUPP; 848 } 849 850 return 0; 851 } 852 853 static void free_m_can_dev(struct net_device *dev) 854 { 855 free_candev(dev); 856 } 857 858 static struct net_device *alloc_m_can_dev(void) 859 { 860 struct net_device *dev; 861 struct m_can_priv *priv; 862 863 dev = alloc_candev(sizeof(*priv), 1); 864 if (!dev) 865 return NULL; 866 867 priv = netdev_priv(dev); 868 netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT); 869 870 priv->dev = dev; 871 priv->can.bittiming_const = &m_can_bittiming_const; 872 priv->can.do_set_mode = m_can_set_mode; 873 priv->can.do_get_berr_counter = m_can_get_berr_counter; 874 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 875 CAN_CTRLMODE_LISTENONLY | 876 CAN_CTRLMODE_BERR_REPORTING; 877 878 return dev; 879 } 880 881 static int m_can_open(struct net_device *dev) 882 { 883 struct m_can_priv *priv = netdev_priv(dev); 884 int err; 885 886 err = clk_prepare_enable(priv->hclk); 887 if (err) 888 return err; 889 890 err = clk_prepare_enable(priv->cclk); 891 if (err) 892 goto exit_disable_hclk; 893 894 /* open the can device */ 895 err = open_candev(dev); 896 if (err) { 897 netdev_err(dev, "failed to open can device\n"); 898 goto exit_disable_cclk; 899 } 900 901 /* register interrupt handler */ 902 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, 903 dev); 904 if (err < 0) { 905 netdev_err(dev, "failed to request interrupt\n"); 906 goto exit_irq_fail; 907 } 908 909 /* start the m_can controller */ 910 m_can_start(dev); 911 912 can_led_event(dev, CAN_LED_EVENT_OPEN); 913 napi_enable(&priv->napi); 914 netif_start_queue(dev); 915 916 return 0; 917 918 exit_irq_fail: 919 close_candev(dev); 920 exit_disable_cclk: 921 clk_disable_unprepare(priv->cclk); 922 exit_disable_hclk: 923 clk_disable_unprepare(priv->hclk); 924 return err; 925 } 926 927 static void m_can_stop(struct net_device *dev) 928 { 929 struct m_can_priv *priv = netdev_priv(dev); 930 931 /* disable all interrupts */ 932 m_can_disable_all_interrupts(priv); 933 934 clk_disable_unprepare(priv->hclk); 935 clk_disable_unprepare(priv->cclk); 936 937 /* set the state as STOPPED */ 938 priv->can.state = CAN_STATE_STOPPED; 939 } 940 941 static int m_can_close(struct net_device *dev) 942 { 943 struct m_can_priv *priv = netdev_priv(dev); 944 945 netif_stop_queue(dev); 946 napi_disable(&priv->napi); 947 m_can_stop(dev); 948 free_irq(dev->irq, dev); 949 close_candev(dev); 950 can_led_event(dev, CAN_LED_EVENT_STOP); 951 952 return 0; 953 } 954 955 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, 956 struct net_device *dev) 957 { 958 struct m_can_priv *priv = netdev_priv(dev); 959 struct can_frame *cf = (struct can_frame *)skb->data; 960 u32 id; 961 962 if (can_dropped_invalid_skb(dev, skb)) 963 return NETDEV_TX_OK; 964 965 netif_stop_queue(dev); 966 967 if (cf->can_id & CAN_EFF_FLAG) { 968 id = cf->can_id & CAN_EFF_MASK; 969 id |= TX_BUF_XTD; 970 } else { 971 id = ((cf->can_id & CAN_SFF_MASK) << 18); 972 } 973 974 if (cf->can_id & CAN_RTR_FLAG) 975 id |= TX_BUF_RTR; 976 977 /* message ram configuration */ 978 m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id); 979 m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, cf->can_dlc << 16); 980 m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(0), *(u32 *)(cf->data + 0)); 981 m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(1), *(u32 *)(cf->data + 4)); 982 can_put_echo_skb(skb, dev, 0); 983 984 /* enable first TX buffer to start transfer */ 985 m_can_write(priv, M_CAN_TXBTIE, 0x1); 986 m_can_write(priv, M_CAN_TXBAR, 0x1); 987 988 return NETDEV_TX_OK; 989 } 990 991 static const struct net_device_ops m_can_netdev_ops = { 992 .ndo_open = m_can_open, 993 .ndo_stop = m_can_close, 994 .ndo_start_xmit = m_can_start_xmit, 995 }; 996 997 static int register_m_can_dev(struct net_device *dev) 998 { 999 dev->flags |= IFF_ECHO; /* we support local echo */ 1000 dev->netdev_ops = &m_can_netdev_ops; 1001 1002 return register_candev(dev); 1003 } 1004 1005 static int m_can_of_parse_mram(struct platform_device *pdev, 1006 struct m_can_priv *priv) 1007 { 1008 struct device_node *np = pdev->dev.of_node; 1009 struct resource *res; 1010 void __iomem *addr; 1011 u32 out_val[MRAM_CFG_LEN]; 1012 int ret; 1013 1014 /* message ram could be shared */ 1015 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram"); 1016 if (!res) 1017 return -ENODEV; 1018 1019 addr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1020 if (!addr) 1021 return -ENOMEM; 1022 1023 /* get message ram configuration */ 1024 ret = of_property_read_u32_array(np, "bosch,mram-cfg", 1025 out_val, sizeof(out_val) / 4); 1026 if (ret) { 1027 dev_err(&pdev->dev, "can not get message ram configuration\n"); 1028 return -ENODEV; 1029 } 1030 1031 priv->mram_base = addr; 1032 priv->mcfg[MRAM_SIDF].off = out_val[0]; 1033 priv->mcfg[MRAM_SIDF].num = out_val[1]; 1034 priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off + 1035 priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; 1036 priv->mcfg[MRAM_XIDF].num = out_val[2]; 1037 priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off + 1038 priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; 1039 priv->mcfg[MRAM_RXF0].num = out_val[3] & RXFC_FS_MASK; 1040 priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off + 1041 priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; 1042 priv->mcfg[MRAM_RXF1].num = out_val[4] & RXFC_FS_MASK; 1043 priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off + 1044 priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; 1045 priv->mcfg[MRAM_RXB].num = out_val[5]; 1046 priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off + 1047 priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; 1048 priv->mcfg[MRAM_TXE].num = out_val[6]; 1049 priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off + 1050 priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; 1051 priv->mcfg[MRAM_TXB].num = out_val[7] & TXBC_NDTB_MASK; 1052 1053 dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", 1054 priv->mram_base, 1055 priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num, 1056 priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num, 1057 priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num, 1058 priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num, 1059 priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num, 1060 priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num, 1061 priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num); 1062 1063 return 0; 1064 } 1065 1066 static int m_can_plat_probe(struct platform_device *pdev) 1067 { 1068 struct net_device *dev; 1069 struct m_can_priv *priv; 1070 struct resource *res; 1071 void __iomem *addr; 1072 struct clk *hclk, *cclk; 1073 int irq, ret; 1074 1075 hclk = devm_clk_get(&pdev->dev, "hclk"); 1076 cclk = devm_clk_get(&pdev->dev, "cclk"); 1077 if (IS_ERR(hclk) || IS_ERR(cclk)) { 1078 dev_err(&pdev->dev, "no clock find\n"); 1079 return -ENODEV; 1080 } 1081 1082 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can"); 1083 addr = devm_ioremap_resource(&pdev->dev, res); 1084 irq = platform_get_irq_byname(pdev, "int0"); 1085 if (IS_ERR(addr) || irq < 0) 1086 return -EINVAL; 1087 1088 /* allocate the m_can device */ 1089 dev = alloc_m_can_dev(); 1090 if (!dev) 1091 return -ENOMEM; 1092 1093 priv = netdev_priv(dev); 1094 dev->irq = irq; 1095 priv->base = addr; 1096 priv->device = &pdev->dev; 1097 priv->hclk = hclk; 1098 priv->cclk = cclk; 1099 priv->can.clock.freq = clk_get_rate(cclk); 1100 1101 ret = m_can_of_parse_mram(pdev, priv); 1102 if (ret) 1103 goto failed_free_dev; 1104 1105 platform_set_drvdata(pdev, dev); 1106 SET_NETDEV_DEV(dev, &pdev->dev); 1107 1108 ret = register_m_can_dev(dev); 1109 if (ret) { 1110 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 1111 KBUILD_MODNAME, ret); 1112 goto failed_free_dev; 1113 } 1114 1115 devm_can_led_init(dev); 1116 1117 dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n", 1118 KBUILD_MODNAME, priv->base, dev->irq); 1119 1120 return 0; 1121 1122 failed_free_dev: 1123 free_m_can_dev(dev); 1124 return ret; 1125 } 1126 1127 static __maybe_unused int m_can_suspend(struct device *dev) 1128 { 1129 struct net_device *ndev = dev_get_drvdata(dev); 1130 struct m_can_priv *priv = netdev_priv(ndev); 1131 1132 if (netif_running(ndev)) { 1133 netif_stop_queue(ndev); 1134 netif_device_detach(ndev); 1135 } 1136 1137 /* TODO: enter low power */ 1138 1139 priv->can.state = CAN_STATE_SLEEPING; 1140 1141 return 0; 1142 } 1143 1144 static __maybe_unused int m_can_resume(struct device *dev) 1145 { 1146 struct net_device *ndev = dev_get_drvdata(dev); 1147 struct m_can_priv *priv = netdev_priv(ndev); 1148 1149 /* TODO: exit low power */ 1150 1151 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1152 1153 if (netif_running(ndev)) { 1154 netif_device_attach(ndev); 1155 netif_start_queue(ndev); 1156 } 1157 1158 return 0; 1159 } 1160 1161 static void unregister_m_can_dev(struct net_device *dev) 1162 { 1163 unregister_candev(dev); 1164 } 1165 1166 static int m_can_plat_remove(struct platform_device *pdev) 1167 { 1168 struct net_device *dev = platform_get_drvdata(pdev); 1169 1170 unregister_m_can_dev(dev); 1171 platform_set_drvdata(pdev, NULL); 1172 1173 free_m_can_dev(dev); 1174 1175 return 0; 1176 } 1177 1178 static const struct dev_pm_ops m_can_pmops = { 1179 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume) 1180 }; 1181 1182 static const struct of_device_id m_can_of_table[] = { 1183 { .compatible = "bosch,m_can", .data = NULL }, 1184 { /* sentinel */ }, 1185 }; 1186 MODULE_DEVICE_TABLE(of, m_can_of_table); 1187 1188 static struct platform_driver m_can_plat_driver = { 1189 .driver = { 1190 .name = KBUILD_MODNAME, 1191 .of_match_table = m_can_of_table, 1192 .pm = &m_can_pmops, 1193 }, 1194 .probe = m_can_plat_probe, 1195 .remove = m_can_plat_remove, 1196 }; 1197 1198 module_platform_driver(m_can_plat_driver); 1199 1200 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); 1201 MODULE_LICENSE("GPL v2"); 1202 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); 1203