1 /* 2 * CAN bus driver for Bosch M_CAN controller 3 * 4 * Copyright (C) 2014 Freescale Semiconductor, Inc. 5 * Dong Aisheng <b29396@freescale.com> 6 * 7 * Bosch M_CAN user manual can be obtained from: 8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/ 9 * mcan_users_manual_v302.pdf 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/netdevice.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/platform_device.h> 26 #include <linux/iopoll.h> 27 #include <linux/can/dev.h> 28 29 /* napi related */ 30 #define M_CAN_NAPI_WEIGHT 64 31 32 /* message ram configuration data length */ 33 #define MRAM_CFG_LEN 8 34 35 /* registers definition */ 36 enum m_can_reg { 37 M_CAN_CREL = 0x0, 38 M_CAN_ENDN = 0x4, 39 M_CAN_CUST = 0x8, 40 M_CAN_DBTP = 0xc, 41 M_CAN_TEST = 0x10, 42 M_CAN_RWD = 0x14, 43 M_CAN_CCCR = 0x18, 44 M_CAN_NBTP = 0x1c, 45 M_CAN_TSCC = 0x20, 46 M_CAN_TSCV = 0x24, 47 M_CAN_TOCC = 0x28, 48 M_CAN_TOCV = 0x2c, 49 M_CAN_ECR = 0x40, 50 M_CAN_PSR = 0x44, 51 /* TDCR Register only available for version >=3.1.x */ 52 M_CAN_TDCR = 0x48, 53 M_CAN_IR = 0x50, 54 M_CAN_IE = 0x54, 55 M_CAN_ILS = 0x58, 56 M_CAN_ILE = 0x5c, 57 M_CAN_GFC = 0x80, 58 M_CAN_SIDFC = 0x84, 59 M_CAN_XIDFC = 0x88, 60 M_CAN_XIDAM = 0x90, 61 M_CAN_HPMS = 0x94, 62 M_CAN_NDAT1 = 0x98, 63 M_CAN_NDAT2 = 0x9c, 64 M_CAN_RXF0C = 0xa0, 65 M_CAN_RXF0S = 0xa4, 66 M_CAN_RXF0A = 0xa8, 67 M_CAN_RXBC = 0xac, 68 M_CAN_RXF1C = 0xb0, 69 M_CAN_RXF1S = 0xb4, 70 M_CAN_RXF1A = 0xb8, 71 M_CAN_RXESC = 0xbc, 72 M_CAN_TXBC = 0xc0, 73 M_CAN_TXFQS = 0xc4, 74 M_CAN_TXESC = 0xc8, 75 M_CAN_TXBRP = 0xcc, 76 M_CAN_TXBAR = 0xd0, 77 M_CAN_TXBCR = 0xd4, 78 M_CAN_TXBTO = 0xd8, 79 M_CAN_TXBCF = 0xdc, 80 M_CAN_TXBTIE = 0xe0, 81 M_CAN_TXBCIE = 0xe4, 82 M_CAN_TXEFC = 0xf0, 83 M_CAN_TXEFS = 0xf4, 84 M_CAN_TXEFA = 0xf8, 85 }; 86 87 /* m_can lec values */ 88 enum m_can_lec_type { 89 LEC_NO_ERROR = 0, 90 LEC_STUFF_ERROR, 91 LEC_FORM_ERROR, 92 LEC_ACK_ERROR, 93 LEC_BIT1_ERROR, 94 LEC_BIT0_ERROR, 95 LEC_CRC_ERROR, 96 LEC_UNUSED, 97 }; 98 99 enum m_can_mram_cfg { 100 MRAM_SIDF = 0, 101 MRAM_XIDF, 102 MRAM_RXF0, 103 MRAM_RXF1, 104 MRAM_RXB, 105 MRAM_TXE, 106 MRAM_TXB, 107 MRAM_CFG_NUM, 108 }; 109 110 /* Core Release Register (CREL) */ 111 #define CREL_REL_SHIFT 28 112 #define CREL_REL_MASK (0xF << CREL_REL_SHIFT) 113 #define CREL_STEP_SHIFT 24 114 #define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT) 115 #define CREL_SUBSTEP_SHIFT 20 116 #define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT) 117 118 /* Data Bit Timing & Prescaler Register (DBTP) */ 119 #define DBTP_TDC BIT(23) 120 #define DBTP_DBRP_SHIFT 16 121 #define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT) 122 #define DBTP_DTSEG1_SHIFT 8 123 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT) 124 #define DBTP_DTSEG2_SHIFT 4 125 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT) 126 #define DBTP_DSJW_SHIFT 0 127 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT) 128 129 /* Test Register (TEST) */ 130 #define TEST_LBCK BIT(4) 131 132 /* CC Control Register(CCCR) */ 133 #define CCCR_CMR_MASK 0x3 134 #define CCCR_CMR_SHIFT 10 135 #define CCCR_CMR_CANFD 0x1 136 #define CCCR_CMR_CANFD_BRS 0x2 137 #define CCCR_CMR_CAN 0x3 138 #define CCCR_CME_MASK 0x3 139 #define CCCR_CME_SHIFT 8 140 #define CCCR_CME_CAN 0 141 #define CCCR_CME_CANFD 0x1 142 #define CCCR_CME_CANFD_BRS 0x2 143 #define CCCR_TXP BIT(14) 144 #define CCCR_TEST BIT(7) 145 #define CCCR_MON BIT(5) 146 #define CCCR_CSR BIT(4) 147 #define CCCR_CSA BIT(3) 148 #define CCCR_ASM BIT(2) 149 #define CCCR_CCE BIT(1) 150 #define CCCR_INIT BIT(0) 151 #define CCCR_CANFD 0x10 152 /* for version >=3.1.x */ 153 #define CCCR_EFBI BIT(13) 154 #define CCCR_PXHD BIT(12) 155 #define CCCR_BRSE BIT(9) 156 #define CCCR_FDOE BIT(8) 157 /* only for version >=3.2.x */ 158 #define CCCR_NISO BIT(15) 159 160 /* Nominal Bit Timing & Prescaler Register (NBTP) */ 161 #define NBTP_NSJW_SHIFT 25 162 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT) 163 #define NBTP_NBRP_SHIFT 16 164 #define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT) 165 #define NBTP_NTSEG1_SHIFT 8 166 #define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT) 167 #define NBTP_NTSEG2_SHIFT 0 168 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT) 169 170 /* Error Counter Register(ECR) */ 171 #define ECR_RP BIT(15) 172 #define ECR_REC_SHIFT 8 173 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT) 174 #define ECR_TEC_SHIFT 0 175 #define ECR_TEC_MASK 0xff 176 177 /* Protocol Status Register(PSR) */ 178 #define PSR_BO BIT(7) 179 #define PSR_EW BIT(6) 180 #define PSR_EP BIT(5) 181 #define PSR_LEC_MASK 0x7 182 183 /* Interrupt Register(IR) */ 184 #define IR_ALL_INT 0xffffffff 185 186 /* Renamed bits for versions > 3.1.x */ 187 #define IR_ARA BIT(29) 188 #define IR_PED BIT(28) 189 #define IR_PEA BIT(27) 190 191 /* Bits for version 3.0.x */ 192 #define IR_STE BIT(31) 193 #define IR_FOE BIT(30) 194 #define IR_ACKE BIT(29) 195 #define IR_BE BIT(28) 196 #define IR_CRCE BIT(27) 197 #define IR_WDI BIT(26) 198 #define IR_BO BIT(25) 199 #define IR_EW BIT(24) 200 #define IR_EP BIT(23) 201 #define IR_ELO BIT(22) 202 #define IR_BEU BIT(21) 203 #define IR_BEC BIT(20) 204 #define IR_DRX BIT(19) 205 #define IR_TOO BIT(18) 206 #define IR_MRAF BIT(17) 207 #define IR_TSW BIT(16) 208 #define IR_TEFL BIT(15) 209 #define IR_TEFF BIT(14) 210 #define IR_TEFW BIT(13) 211 #define IR_TEFN BIT(12) 212 #define IR_TFE BIT(11) 213 #define IR_TCF BIT(10) 214 #define IR_TC BIT(9) 215 #define IR_HPM BIT(8) 216 #define IR_RF1L BIT(7) 217 #define IR_RF1F BIT(6) 218 #define IR_RF1W BIT(5) 219 #define IR_RF1N BIT(4) 220 #define IR_RF0L BIT(3) 221 #define IR_RF0F BIT(2) 222 #define IR_RF0W BIT(1) 223 #define IR_RF0N BIT(0) 224 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) 225 226 /* Interrupts for version 3.0.x */ 227 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) 228 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \ 229 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 230 IR_RF1L | IR_RF0L) 231 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X) 232 /* Interrupts for version >= 3.1.x */ 233 #define IR_ERR_LEC_31X (IR_PED | IR_PEA) 234 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \ 235 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 236 IR_RF1L | IR_RF0L) 237 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X) 238 239 /* Interrupt Line Select (ILS) */ 240 #define ILS_ALL_INT0 0x0 241 #define ILS_ALL_INT1 0xFFFFFFFF 242 243 /* Interrupt Line Enable (ILE) */ 244 #define ILE_EINT1 BIT(1) 245 #define ILE_EINT0 BIT(0) 246 247 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ 248 #define RXFC_FWM_SHIFT 24 249 #define RXFC_FWM_MASK (0x7f < RXFC_FWM_SHIFT) 250 #define RXFC_FS_SHIFT 16 251 #define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT) 252 253 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ 254 #define RXFS_RFL BIT(25) 255 #define RXFS_FF BIT(24) 256 #define RXFS_FPI_SHIFT 16 257 #define RXFS_FPI_MASK 0x3f0000 258 #define RXFS_FGI_SHIFT 8 259 #define RXFS_FGI_MASK 0x3f00 260 #define RXFS_FFL_MASK 0x7f 261 262 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ 263 #define M_CAN_RXESC_8BYTES 0x0 264 #define M_CAN_RXESC_64BYTES 0x777 265 266 /* Tx Buffer Configuration(TXBC) */ 267 #define TXBC_NDTB_SHIFT 16 268 #define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT) 269 #define TXBC_TFQS_SHIFT 24 270 #define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT) 271 272 /* Tx FIFO/Queue Status (TXFQS) */ 273 #define TXFQS_TFQF BIT(21) 274 #define TXFQS_TFQPI_SHIFT 16 275 #define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT) 276 #define TXFQS_TFGI_SHIFT 8 277 #define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT) 278 #define TXFQS_TFFL_SHIFT 0 279 #define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT) 280 281 /* Tx Buffer Element Size Configuration(TXESC) */ 282 #define TXESC_TBDS_8BYTES 0x0 283 #define TXESC_TBDS_64BYTES 0x7 284 285 /* Tx Event FIFO Configuration (TXEFC) */ 286 #define TXEFC_EFS_SHIFT 16 287 #define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT) 288 289 /* Tx Event FIFO Status (TXEFS) */ 290 #define TXEFS_TEFL BIT(25) 291 #define TXEFS_EFF BIT(24) 292 #define TXEFS_EFGI_SHIFT 8 293 #define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT) 294 #define TXEFS_EFFL_SHIFT 0 295 #define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT) 296 297 /* Tx Event FIFO Acknowledge (TXEFA) */ 298 #define TXEFA_EFAI_SHIFT 0 299 #define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT) 300 301 /* Message RAM Configuration (in bytes) */ 302 #define SIDF_ELEMENT_SIZE 4 303 #define XIDF_ELEMENT_SIZE 8 304 #define RXF0_ELEMENT_SIZE 72 305 #define RXF1_ELEMENT_SIZE 72 306 #define RXB_ELEMENT_SIZE 72 307 #define TXE_ELEMENT_SIZE 8 308 #define TXB_ELEMENT_SIZE 72 309 310 /* Message RAM Elements */ 311 #define M_CAN_FIFO_ID 0x0 312 #define M_CAN_FIFO_DLC 0x4 313 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2)) 314 315 /* Rx Buffer Element */ 316 /* R0 */ 317 #define RX_BUF_ESI BIT(31) 318 #define RX_BUF_XTD BIT(30) 319 #define RX_BUF_RTR BIT(29) 320 /* R1 */ 321 #define RX_BUF_ANMF BIT(31) 322 #define RX_BUF_FDF BIT(21) 323 #define RX_BUF_BRS BIT(20) 324 325 /* Tx Buffer Element */ 326 /* T0 */ 327 #define TX_BUF_ESI BIT(31) 328 #define TX_BUF_XTD BIT(30) 329 #define TX_BUF_RTR BIT(29) 330 /* T1 */ 331 #define TX_BUF_EFC BIT(23) 332 #define TX_BUF_FDF BIT(21) 333 #define TX_BUF_BRS BIT(20) 334 #define TX_BUF_MM_SHIFT 24 335 #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT) 336 337 /* Tx event FIFO Element */ 338 /* E1 */ 339 #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT 340 #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT) 341 342 /* address offset and element number for each FIFO/Buffer in the Message RAM */ 343 struct mram_cfg { 344 u16 off; 345 u8 num; 346 }; 347 348 /* m_can private data structure */ 349 struct m_can_priv { 350 struct can_priv can; /* must be the first member */ 351 struct napi_struct napi; 352 struct net_device *dev; 353 struct device *device; 354 struct clk *hclk; 355 struct clk *cclk; 356 void __iomem *base; 357 u32 irqstatus; 358 int version; 359 360 /* message ram configuration */ 361 void __iomem *mram_base; 362 struct mram_cfg mcfg[MRAM_CFG_NUM]; 363 }; 364 365 static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg) 366 { 367 return readl(priv->base + reg); 368 } 369 370 static inline void m_can_write(const struct m_can_priv *priv, 371 enum m_can_reg reg, u32 val) 372 { 373 writel(val, priv->base + reg); 374 } 375 376 static inline u32 m_can_fifo_read(const struct m_can_priv *priv, 377 u32 fgi, unsigned int offset) 378 { 379 return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off + 380 fgi * RXF0_ELEMENT_SIZE + offset); 381 } 382 383 static inline void m_can_fifo_write(const struct m_can_priv *priv, 384 u32 fpi, unsigned int offset, u32 val) 385 { 386 writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off + 387 fpi * TXB_ELEMENT_SIZE + offset); 388 } 389 390 static inline u32 m_can_txe_fifo_read(const struct m_can_priv *priv, 391 u32 fgi, 392 u32 offset) { 393 return readl(priv->mram_base + priv->mcfg[MRAM_TXE].off + 394 fgi * TXE_ELEMENT_SIZE + offset); 395 } 396 397 static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv) 398 { 399 return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF); 400 } 401 402 static inline void m_can_config_endisable(const struct m_can_priv *priv, 403 bool enable) 404 { 405 u32 cccr = m_can_read(priv, M_CAN_CCCR); 406 u32 timeout = 10; 407 u32 val = 0; 408 409 if (enable) { 410 /* enable m_can configuration */ 411 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT); 412 udelay(5); 413 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ 414 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); 415 } else { 416 m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); 417 } 418 419 /* there's a delay for module initialization */ 420 if (enable) 421 val = CCCR_INIT | CCCR_CCE; 422 423 while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { 424 if (timeout == 0) { 425 netdev_warn(priv->dev, "Failed to init module\n"); 426 return; 427 } 428 timeout--; 429 udelay(1); 430 } 431 } 432 433 static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv) 434 { 435 /* Only interrupt line 0 is used in this driver */ 436 m_can_write(priv, M_CAN_ILE, ILE_EINT0); 437 } 438 439 static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv) 440 { 441 m_can_write(priv, M_CAN_ILE, 0x0); 442 } 443 444 static void m_can_read_fifo(struct net_device *dev, u32 rxfs) 445 { 446 struct net_device_stats *stats = &dev->stats; 447 struct m_can_priv *priv = netdev_priv(dev); 448 struct canfd_frame *cf; 449 struct sk_buff *skb; 450 u32 id, fgi, dlc; 451 int i; 452 453 /* calculate the fifo get index for where to read data */ 454 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT; 455 dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC); 456 if (dlc & RX_BUF_FDF) 457 skb = alloc_canfd_skb(dev, &cf); 458 else 459 skb = alloc_can_skb(dev, (struct can_frame **)&cf); 460 if (!skb) { 461 stats->rx_dropped++; 462 return; 463 } 464 465 if (dlc & RX_BUF_FDF) 466 cf->len = can_dlc2len((dlc >> 16) & 0x0F); 467 else 468 cf->len = get_can_dlc((dlc >> 16) & 0x0F); 469 470 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID); 471 if (id & RX_BUF_XTD) 472 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 473 else 474 cf->can_id = (id >> 18) & CAN_SFF_MASK; 475 476 if (id & RX_BUF_ESI) { 477 cf->flags |= CANFD_ESI; 478 netdev_dbg(dev, "ESI Error\n"); 479 } 480 481 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) { 482 cf->can_id |= CAN_RTR_FLAG; 483 } else { 484 if (dlc & RX_BUF_BRS) 485 cf->flags |= CANFD_BRS; 486 487 for (i = 0; i < cf->len; i += 4) 488 *(u32 *)(cf->data + i) = 489 m_can_fifo_read(priv, fgi, 490 M_CAN_FIFO_DATA(i / 4)); 491 } 492 493 /* acknowledge rx fifo 0 */ 494 m_can_write(priv, M_CAN_RXF0A, fgi); 495 496 stats->rx_packets++; 497 stats->rx_bytes += cf->len; 498 499 netif_receive_skb(skb); 500 } 501 502 static int m_can_do_rx_poll(struct net_device *dev, int quota) 503 { 504 struct m_can_priv *priv = netdev_priv(dev); 505 u32 pkts = 0; 506 u32 rxfs; 507 508 rxfs = m_can_read(priv, M_CAN_RXF0S); 509 if (!(rxfs & RXFS_FFL_MASK)) { 510 netdev_dbg(dev, "no messages in fifo0\n"); 511 return 0; 512 } 513 514 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) { 515 if (rxfs & RXFS_RFL) 516 netdev_warn(dev, "Rx FIFO 0 Message Lost\n"); 517 518 m_can_read_fifo(dev, rxfs); 519 520 quota--; 521 pkts++; 522 rxfs = m_can_read(priv, M_CAN_RXF0S); 523 } 524 525 if (pkts) 526 can_led_event(dev, CAN_LED_EVENT_RX); 527 528 return pkts; 529 } 530 531 static int m_can_handle_lost_msg(struct net_device *dev) 532 { 533 struct net_device_stats *stats = &dev->stats; 534 struct sk_buff *skb; 535 struct can_frame *frame; 536 537 netdev_err(dev, "msg lost in rxf0\n"); 538 539 stats->rx_errors++; 540 stats->rx_over_errors++; 541 542 skb = alloc_can_err_skb(dev, &frame); 543 if (unlikely(!skb)) 544 return 0; 545 546 frame->can_id |= CAN_ERR_CRTL; 547 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 548 549 netif_receive_skb(skb); 550 551 return 1; 552 } 553 554 static int m_can_handle_lec_err(struct net_device *dev, 555 enum m_can_lec_type lec_type) 556 { 557 struct m_can_priv *priv = netdev_priv(dev); 558 struct net_device_stats *stats = &dev->stats; 559 struct can_frame *cf; 560 struct sk_buff *skb; 561 562 priv->can.can_stats.bus_error++; 563 stats->rx_errors++; 564 565 /* propagate the error condition to the CAN stack */ 566 skb = alloc_can_err_skb(dev, &cf); 567 if (unlikely(!skb)) 568 return 0; 569 570 /* check for 'last error code' which tells us the 571 * type of the last error to occur on the CAN bus 572 */ 573 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 574 575 switch (lec_type) { 576 case LEC_STUFF_ERROR: 577 netdev_dbg(dev, "stuff error\n"); 578 cf->data[2] |= CAN_ERR_PROT_STUFF; 579 break; 580 case LEC_FORM_ERROR: 581 netdev_dbg(dev, "form error\n"); 582 cf->data[2] |= CAN_ERR_PROT_FORM; 583 break; 584 case LEC_ACK_ERROR: 585 netdev_dbg(dev, "ack error\n"); 586 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 587 break; 588 case LEC_BIT1_ERROR: 589 netdev_dbg(dev, "bit1 error\n"); 590 cf->data[2] |= CAN_ERR_PROT_BIT1; 591 break; 592 case LEC_BIT0_ERROR: 593 netdev_dbg(dev, "bit0 error\n"); 594 cf->data[2] |= CAN_ERR_PROT_BIT0; 595 break; 596 case LEC_CRC_ERROR: 597 netdev_dbg(dev, "CRC error\n"); 598 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 599 break; 600 default: 601 break; 602 } 603 604 stats->rx_packets++; 605 stats->rx_bytes += cf->can_dlc; 606 netif_receive_skb(skb); 607 608 return 1; 609 } 610 611 static int __m_can_get_berr_counter(const struct net_device *dev, 612 struct can_berr_counter *bec) 613 { 614 struct m_can_priv *priv = netdev_priv(dev); 615 unsigned int ecr; 616 617 ecr = m_can_read(priv, M_CAN_ECR); 618 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT; 619 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT; 620 621 return 0; 622 } 623 624 static int m_can_clk_start(struct m_can_priv *priv) 625 { 626 int err; 627 628 err = clk_prepare_enable(priv->hclk); 629 if (err) 630 return err; 631 632 err = clk_prepare_enable(priv->cclk); 633 if (err) 634 clk_disable_unprepare(priv->hclk); 635 636 return err; 637 } 638 639 static void m_can_clk_stop(struct m_can_priv *priv) 640 { 641 clk_disable_unprepare(priv->cclk); 642 clk_disable_unprepare(priv->hclk); 643 } 644 645 static int m_can_get_berr_counter(const struct net_device *dev, 646 struct can_berr_counter *bec) 647 { 648 struct m_can_priv *priv = netdev_priv(dev); 649 int err; 650 651 err = m_can_clk_start(priv); 652 if (err) 653 return err; 654 655 __m_can_get_berr_counter(dev, bec); 656 657 m_can_clk_stop(priv); 658 659 return 0; 660 } 661 662 static int m_can_handle_state_change(struct net_device *dev, 663 enum can_state new_state) 664 { 665 struct m_can_priv *priv = netdev_priv(dev); 666 struct net_device_stats *stats = &dev->stats; 667 struct can_frame *cf; 668 struct sk_buff *skb; 669 struct can_berr_counter bec; 670 unsigned int ecr; 671 672 switch (new_state) { 673 case CAN_STATE_ERROR_ACTIVE: 674 /* error warning state */ 675 priv->can.can_stats.error_warning++; 676 priv->can.state = CAN_STATE_ERROR_WARNING; 677 break; 678 case CAN_STATE_ERROR_PASSIVE: 679 /* error passive state */ 680 priv->can.can_stats.error_passive++; 681 priv->can.state = CAN_STATE_ERROR_PASSIVE; 682 break; 683 case CAN_STATE_BUS_OFF: 684 /* bus-off state */ 685 priv->can.state = CAN_STATE_BUS_OFF; 686 m_can_disable_all_interrupts(priv); 687 priv->can.can_stats.bus_off++; 688 can_bus_off(dev); 689 break; 690 default: 691 break; 692 } 693 694 /* propagate the error condition to the CAN stack */ 695 skb = alloc_can_err_skb(dev, &cf); 696 if (unlikely(!skb)) 697 return 0; 698 699 __m_can_get_berr_counter(dev, &bec); 700 701 switch (new_state) { 702 case CAN_STATE_ERROR_ACTIVE: 703 /* error warning state */ 704 cf->can_id |= CAN_ERR_CRTL; 705 cf->data[1] = (bec.txerr > bec.rxerr) ? 706 CAN_ERR_CRTL_TX_WARNING : 707 CAN_ERR_CRTL_RX_WARNING; 708 cf->data[6] = bec.txerr; 709 cf->data[7] = bec.rxerr; 710 break; 711 case CAN_STATE_ERROR_PASSIVE: 712 /* error passive state */ 713 cf->can_id |= CAN_ERR_CRTL; 714 ecr = m_can_read(priv, M_CAN_ECR); 715 if (ecr & ECR_RP) 716 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 717 if (bec.txerr > 127) 718 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 719 cf->data[6] = bec.txerr; 720 cf->data[7] = bec.rxerr; 721 break; 722 case CAN_STATE_BUS_OFF: 723 /* bus-off state */ 724 cf->can_id |= CAN_ERR_BUSOFF; 725 break; 726 default: 727 break; 728 } 729 730 stats->rx_packets++; 731 stats->rx_bytes += cf->can_dlc; 732 netif_receive_skb(skb); 733 734 return 1; 735 } 736 737 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) 738 { 739 struct m_can_priv *priv = netdev_priv(dev); 740 int work_done = 0; 741 742 if ((psr & PSR_EW) && 743 (priv->can.state != CAN_STATE_ERROR_WARNING)) { 744 netdev_dbg(dev, "entered error warning state\n"); 745 work_done += m_can_handle_state_change(dev, 746 CAN_STATE_ERROR_WARNING); 747 } 748 749 if ((psr & PSR_EP) && 750 (priv->can.state != CAN_STATE_ERROR_PASSIVE)) { 751 netdev_dbg(dev, "entered error passive state\n"); 752 work_done += m_can_handle_state_change(dev, 753 CAN_STATE_ERROR_PASSIVE); 754 } 755 756 if ((psr & PSR_BO) && 757 (priv->can.state != CAN_STATE_BUS_OFF)) { 758 netdev_dbg(dev, "entered error bus off state\n"); 759 work_done += m_can_handle_state_change(dev, 760 CAN_STATE_BUS_OFF); 761 } 762 763 return work_done; 764 } 765 766 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) 767 { 768 if (irqstatus & IR_WDI) 769 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); 770 if (irqstatus & IR_ELO) 771 netdev_err(dev, "Error Logging Overflow\n"); 772 if (irqstatus & IR_BEU) 773 netdev_err(dev, "Bit Error Uncorrected\n"); 774 if (irqstatus & IR_BEC) 775 netdev_err(dev, "Bit Error Corrected\n"); 776 if (irqstatus & IR_TOO) 777 netdev_err(dev, "Timeout reached\n"); 778 if (irqstatus & IR_MRAF) 779 netdev_err(dev, "Message RAM access failure occurred\n"); 780 } 781 782 static inline bool is_lec_err(u32 psr) 783 { 784 psr &= LEC_UNUSED; 785 786 return psr && (psr != LEC_UNUSED); 787 } 788 789 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, 790 u32 psr) 791 { 792 struct m_can_priv *priv = netdev_priv(dev); 793 int work_done = 0; 794 795 if (irqstatus & IR_RF0L) 796 work_done += m_can_handle_lost_msg(dev); 797 798 /* handle lec errors on the bus */ 799 if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 800 is_lec_err(psr)) 801 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED); 802 803 /* other unproccessed error interrupts */ 804 m_can_handle_other_err(dev, irqstatus); 805 806 return work_done; 807 } 808 809 static int m_can_poll(struct napi_struct *napi, int quota) 810 { 811 struct net_device *dev = napi->dev; 812 struct m_can_priv *priv = netdev_priv(dev); 813 int work_done = 0; 814 u32 irqstatus, psr; 815 816 irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR); 817 if (!irqstatus) 818 goto end; 819 820 psr = m_can_read(priv, M_CAN_PSR); 821 if (irqstatus & IR_ERR_STATE) 822 work_done += m_can_handle_state_errors(dev, psr); 823 824 if (irqstatus & IR_ERR_BUS_30X) 825 work_done += m_can_handle_bus_errors(dev, irqstatus, psr); 826 827 if (irqstatus & IR_RF0N) 828 work_done += m_can_do_rx_poll(dev, (quota - work_done)); 829 830 if (work_done < quota) { 831 napi_complete_done(napi, work_done); 832 m_can_enable_all_interrupts(priv); 833 } 834 835 end: 836 return work_done; 837 } 838 839 static void m_can_echo_tx_event(struct net_device *dev) 840 { 841 u32 txe_count = 0; 842 u32 m_can_txefs; 843 u32 fgi = 0; 844 int i = 0; 845 unsigned int msg_mark; 846 847 struct m_can_priv *priv = netdev_priv(dev); 848 struct net_device_stats *stats = &dev->stats; 849 850 /* read tx event fifo status */ 851 m_can_txefs = m_can_read(priv, M_CAN_TXEFS); 852 853 /* Get Tx Event fifo element count */ 854 txe_count = (m_can_txefs & TXEFS_EFFL_MASK) 855 >> TXEFS_EFFL_SHIFT; 856 857 /* Get and process all sent elements */ 858 for (i = 0; i < txe_count; i++) { 859 /* retrieve get index */ 860 fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK) 861 >> TXEFS_EFGI_SHIFT; 862 863 /* get message marker */ 864 msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) & 865 TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT; 866 867 /* ack txe element */ 868 m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK & 869 (fgi << TXEFA_EFAI_SHIFT))); 870 871 /* update stats */ 872 stats->tx_bytes += can_get_echo_skb(dev, msg_mark); 873 stats->tx_packets++; 874 } 875 } 876 877 static irqreturn_t m_can_isr(int irq, void *dev_id) 878 { 879 struct net_device *dev = (struct net_device *)dev_id; 880 struct m_can_priv *priv = netdev_priv(dev); 881 struct net_device_stats *stats = &dev->stats; 882 u32 ir; 883 884 ir = m_can_read(priv, M_CAN_IR); 885 if (!ir) 886 return IRQ_NONE; 887 888 /* ACK all irqs */ 889 if (ir & IR_ALL_INT) 890 m_can_write(priv, M_CAN_IR, ir); 891 892 /* schedule NAPI in case of 893 * - rx IRQ 894 * - state change IRQ 895 * - bus error IRQ and bus error reporting 896 */ 897 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) { 898 priv->irqstatus = ir; 899 m_can_disable_all_interrupts(priv); 900 napi_schedule(&priv->napi); 901 } 902 903 if (priv->version == 30) { 904 if (ir & IR_TC) { 905 /* Transmission Complete Interrupt*/ 906 stats->tx_bytes += can_get_echo_skb(dev, 0); 907 stats->tx_packets++; 908 can_led_event(dev, CAN_LED_EVENT_TX); 909 netif_wake_queue(dev); 910 } 911 } else { 912 if (ir & IR_TEFN) { 913 /* New TX FIFO Element arrived */ 914 m_can_echo_tx_event(dev); 915 can_led_event(dev, CAN_LED_EVENT_TX); 916 if (netif_queue_stopped(dev) && 917 !m_can_tx_fifo_full(priv)) 918 netif_wake_queue(dev); 919 } 920 } 921 922 return IRQ_HANDLED; 923 } 924 925 static const struct can_bittiming_const m_can_bittiming_const_30X = { 926 .name = KBUILD_MODNAME, 927 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 928 .tseg1_max = 64, 929 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 930 .tseg2_max = 16, 931 .sjw_max = 16, 932 .brp_min = 1, 933 .brp_max = 1024, 934 .brp_inc = 1, 935 }; 936 937 static const struct can_bittiming_const m_can_data_bittiming_const_30X = { 938 .name = KBUILD_MODNAME, 939 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 940 .tseg1_max = 16, 941 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 942 .tseg2_max = 8, 943 .sjw_max = 4, 944 .brp_min = 1, 945 .brp_max = 32, 946 .brp_inc = 1, 947 }; 948 949 static const struct can_bittiming_const m_can_bittiming_const_31X = { 950 .name = KBUILD_MODNAME, 951 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 952 .tseg1_max = 256, 953 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 954 .tseg2_max = 128, 955 .sjw_max = 128, 956 .brp_min = 1, 957 .brp_max = 512, 958 .brp_inc = 1, 959 }; 960 961 static const struct can_bittiming_const m_can_data_bittiming_const_31X = { 962 .name = KBUILD_MODNAME, 963 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */ 964 .tseg1_max = 32, 965 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 966 .tseg2_max = 16, 967 .sjw_max = 16, 968 .brp_min = 1, 969 .brp_max = 32, 970 .brp_inc = 1, 971 }; 972 973 static int m_can_set_bittiming(struct net_device *dev) 974 { 975 struct m_can_priv *priv = netdev_priv(dev); 976 const struct can_bittiming *bt = &priv->can.bittiming; 977 const struct can_bittiming *dbt = &priv->can.data_bittiming; 978 u16 brp, sjw, tseg1, tseg2; 979 u32 reg_btp; 980 981 brp = bt->brp - 1; 982 sjw = bt->sjw - 1; 983 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 984 tseg2 = bt->phase_seg2 - 1; 985 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) | 986 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT); 987 m_can_write(priv, M_CAN_NBTP, reg_btp); 988 989 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 990 brp = dbt->brp - 1; 991 sjw = dbt->sjw - 1; 992 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; 993 tseg2 = dbt->phase_seg2 - 1; 994 reg_btp = (brp << DBTP_DBRP_SHIFT) | (sjw << DBTP_DSJW_SHIFT) | 995 (tseg1 << DBTP_DTSEG1_SHIFT) | 996 (tseg2 << DBTP_DTSEG2_SHIFT); 997 m_can_write(priv, M_CAN_DBTP, reg_btp); 998 } 999 1000 return 0; 1001 } 1002 1003 /* Configure M_CAN chip: 1004 * - set rx buffer/fifo element size 1005 * - configure rx fifo 1006 * - accept non-matching frame into fifo 0 1007 * - configure tx buffer 1008 * - >= v3.1.x: TX FIFO is used 1009 * - configure mode 1010 * - setup bittiming 1011 */ 1012 static void m_can_chip_config(struct net_device *dev) 1013 { 1014 struct m_can_priv *priv = netdev_priv(dev); 1015 u32 cccr, test; 1016 1017 m_can_config_endisable(priv, true); 1018 1019 /* RX Buffer/FIFO Element Size 64 bytes data field */ 1020 m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_64BYTES); 1021 1022 /* Accept Non-matching Frames Into FIFO 0 */ 1023 m_can_write(priv, M_CAN_GFC, 0x0); 1024 1025 if (priv->version == 30) { 1026 /* only support one Tx Buffer currently */ 1027 m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) | 1028 priv->mcfg[MRAM_TXB].off); 1029 } else { 1030 /* TX FIFO is used for newer IP Core versions */ 1031 m_can_write(priv, M_CAN_TXBC, 1032 (priv->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) | 1033 (priv->mcfg[MRAM_TXB].off)); 1034 } 1035 1036 /* support 64 bytes payload */ 1037 m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES); 1038 1039 /* TX Event FIFO */ 1040 if (priv->version == 30) { 1041 m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) | 1042 priv->mcfg[MRAM_TXE].off); 1043 } else { 1044 /* Full TX Event FIFO is used */ 1045 m_can_write(priv, M_CAN_TXEFC, 1046 ((priv->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT) 1047 & TXEFC_EFS_MASK) | 1048 priv->mcfg[MRAM_TXE].off); 1049 } 1050 1051 /* rx fifo configuration, blocking mode, fifo size 1 */ 1052 m_can_write(priv, M_CAN_RXF0C, 1053 (priv->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) | 1054 priv->mcfg[MRAM_RXF0].off); 1055 1056 m_can_write(priv, M_CAN_RXF1C, 1057 (priv->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) | 1058 priv->mcfg[MRAM_RXF1].off); 1059 1060 cccr = m_can_read(priv, M_CAN_CCCR); 1061 test = m_can_read(priv, M_CAN_TEST); 1062 test &= ~TEST_LBCK; 1063 if (priv->version == 30) { 1064 /* Version 3.0.x */ 1065 1066 cccr &= ~(CCCR_TEST | CCCR_MON | 1067 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | 1068 (CCCR_CME_MASK << CCCR_CME_SHIFT)); 1069 1070 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1071 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT; 1072 1073 } else { 1074 /* Version 3.1.x or 3.2.x */ 1075 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE); 1076 1077 /* Only 3.2.x has NISO Bit implemented */ 1078 if (priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 1079 cccr |= CCCR_NISO; 1080 1081 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1082 cccr |= (CCCR_BRSE | CCCR_FDOE); 1083 } 1084 1085 /* Loopback Mode */ 1086 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1087 cccr |= CCCR_TEST | CCCR_MON; 1088 test |= TEST_LBCK; 1089 } 1090 1091 /* Enable Monitoring (all versions) */ 1092 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1093 cccr |= CCCR_MON; 1094 1095 /* Write config */ 1096 m_can_write(priv, M_CAN_CCCR, cccr); 1097 m_can_write(priv, M_CAN_TEST, test); 1098 1099 /* Enable interrupts */ 1100 m_can_write(priv, M_CAN_IR, IR_ALL_INT); 1101 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1102 if (priv->version == 30) 1103 m_can_write(priv, M_CAN_IE, IR_ALL_INT & 1104 ~(IR_ERR_LEC_30X)); 1105 else 1106 m_can_write(priv, M_CAN_IE, IR_ALL_INT & 1107 ~(IR_ERR_LEC_31X)); 1108 else 1109 m_can_write(priv, M_CAN_IE, IR_ALL_INT); 1110 1111 /* route all interrupts to INT0 */ 1112 m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0); 1113 1114 /* set bittiming params */ 1115 m_can_set_bittiming(dev); 1116 1117 m_can_config_endisable(priv, false); 1118 } 1119 1120 static void m_can_start(struct net_device *dev) 1121 { 1122 struct m_can_priv *priv = netdev_priv(dev); 1123 1124 /* basic m_can configuration */ 1125 m_can_chip_config(dev); 1126 1127 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1128 1129 m_can_enable_all_interrupts(priv); 1130 } 1131 1132 static int m_can_set_mode(struct net_device *dev, enum can_mode mode) 1133 { 1134 switch (mode) { 1135 case CAN_MODE_START: 1136 m_can_start(dev); 1137 netif_wake_queue(dev); 1138 break; 1139 default: 1140 return -EOPNOTSUPP; 1141 } 1142 1143 return 0; 1144 } 1145 1146 static void free_m_can_dev(struct net_device *dev) 1147 { 1148 free_candev(dev); 1149 } 1150 1151 /* Checks core release number of M_CAN 1152 * returns 0 if an unsupported device is detected 1153 * else it returns the release and step coded as: 1154 * return value = 10 * <release> + 1 * <step> 1155 */ 1156 static int m_can_check_core_release(void __iomem *m_can_base) 1157 { 1158 u32 crel_reg; 1159 u8 rel; 1160 u8 step; 1161 int res; 1162 struct m_can_priv temp_priv = { 1163 .base = m_can_base 1164 }; 1165 1166 /* Read Core Release Version and split into version number 1167 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; 1168 */ 1169 crel_reg = m_can_read(&temp_priv, M_CAN_CREL); 1170 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT); 1171 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT); 1172 1173 if (rel == 3) { 1174 /* M_CAN v3.x.y: create return value */ 1175 res = 30 + step; 1176 } else { 1177 /* Unsupported M_CAN version */ 1178 res = 0; 1179 } 1180 1181 return res; 1182 } 1183 1184 /* Selectable Non ISO support only in version 3.2.x 1185 * This function checks if the bit is writable. 1186 */ 1187 static bool m_can_niso_supported(const struct m_can_priv *priv) 1188 { 1189 u32 cccr_reg, cccr_poll; 1190 int niso_timeout; 1191 1192 m_can_config_endisable(priv, true); 1193 cccr_reg = m_can_read(priv, M_CAN_CCCR); 1194 cccr_reg |= CCCR_NISO; 1195 m_can_write(priv, M_CAN_CCCR, cccr_reg); 1196 1197 niso_timeout = readl_poll_timeout((priv->base + M_CAN_CCCR), cccr_poll, 1198 (cccr_poll == cccr_reg), 0, 10); 1199 1200 /* Clear NISO */ 1201 cccr_reg &= ~(CCCR_NISO); 1202 m_can_write(priv, M_CAN_CCCR, cccr_reg); 1203 1204 m_can_config_endisable(priv, false); 1205 1206 /* return false if time out (-ETIMEDOUT), else return true */ 1207 return !niso_timeout; 1208 } 1209 1210 static struct net_device *alloc_m_can_dev(struct platform_device *pdev, 1211 void __iomem *addr, u32 tx_fifo_size) 1212 { 1213 struct net_device *dev; 1214 struct m_can_priv *priv; 1215 int m_can_version; 1216 unsigned int echo_buffer_count; 1217 1218 m_can_version = m_can_check_core_release(addr); 1219 /* return if unsupported version */ 1220 if (!m_can_version) { 1221 dev = NULL; 1222 goto return_dev; 1223 } 1224 1225 /* If version < 3.1.x, then only one echo buffer is used */ 1226 echo_buffer_count = ((m_can_version == 30) 1227 ? 1U 1228 : (unsigned int)tx_fifo_size); 1229 1230 dev = alloc_candev(sizeof(*priv), echo_buffer_count); 1231 if (!dev) { 1232 dev = NULL; 1233 goto return_dev; 1234 } 1235 priv = netdev_priv(dev); 1236 netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT); 1237 1238 /* Shared properties of all M_CAN versions */ 1239 priv->version = m_can_version; 1240 priv->dev = dev; 1241 priv->base = addr; 1242 priv->can.do_set_mode = m_can_set_mode; 1243 priv->can.do_get_berr_counter = m_can_get_berr_counter; 1244 1245 /* Set M_CAN supported operations */ 1246 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1247 CAN_CTRLMODE_LISTENONLY | 1248 CAN_CTRLMODE_BERR_REPORTING | 1249 CAN_CTRLMODE_FD; 1250 1251 /* Set properties depending on M_CAN version */ 1252 switch (priv->version) { 1253 case 30: 1254 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ 1255 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1256 priv->can.bittiming_const = &m_can_bittiming_const_30X; 1257 priv->can.data_bittiming_const = 1258 &m_can_data_bittiming_const_30X; 1259 break; 1260 case 31: 1261 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ 1262 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1263 priv->can.bittiming_const = &m_can_bittiming_const_31X; 1264 priv->can.data_bittiming_const = 1265 &m_can_data_bittiming_const_31X; 1266 break; 1267 case 32: 1268 priv->can.bittiming_const = &m_can_bittiming_const_31X; 1269 priv->can.data_bittiming_const = 1270 &m_can_data_bittiming_const_31X; 1271 priv->can.ctrlmode_supported |= (m_can_niso_supported(priv) 1272 ? CAN_CTRLMODE_FD_NON_ISO 1273 : 0); 1274 break; 1275 default: 1276 /* Unsupported device: free candev */ 1277 free_m_can_dev(dev); 1278 dev_err(&pdev->dev, "Unsupported version number: %2d", 1279 priv->version); 1280 dev = NULL; 1281 break; 1282 } 1283 1284 return_dev: 1285 return dev; 1286 } 1287 1288 static int m_can_open(struct net_device *dev) 1289 { 1290 struct m_can_priv *priv = netdev_priv(dev); 1291 int err; 1292 1293 err = m_can_clk_start(priv); 1294 if (err) 1295 return err; 1296 1297 /* open the can device */ 1298 err = open_candev(dev); 1299 if (err) { 1300 netdev_err(dev, "failed to open can device\n"); 1301 goto exit_disable_clks; 1302 } 1303 1304 /* register interrupt handler */ 1305 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, 1306 dev); 1307 if (err < 0) { 1308 netdev_err(dev, "failed to request interrupt\n"); 1309 goto exit_irq_fail; 1310 } 1311 1312 /* start the m_can controller */ 1313 m_can_start(dev); 1314 1315 can_led_event(dev, CAN_LED_EVENT_OPEN); 1316 napi_enable(&priv->napi); 1317 netif_start_queue(dev); 1318 1319 return 0; 1320 1321 exit_irq_fail: 1322 close_candev(dev); 1323 exit_disable_clks: 1324 m_can_clk_stop(priv); 1325 return err; 1326 } 1327 1328 static void m_can_stop(struct net_device *dev) 1329 { 1330 struct m_can_priv *priv = netdev_priv(dev); 1331 1332 /* disable all interrupts */ 1333 m_can_disable_all_interrupts(priv); 1334 1335 /* set the state as STOPPED */ 1336 priv->can.state = CAN_STATE_STOPPED; 1337 } 1338 1339 static int m_can_close(struct net_device *dev) 1340 { 1341 struct m_can_priv *priv = netdev_priv(dev); 1342 1343 netif_stop_queue(dev); 1344 napi_disable(&priv->napi); 1345 m_can_stop(dev); 1346 m_can_clk_stop(priv); 1347 free_irq(dev->irq, dev); 1348 close_candev(dev); 1349 can_led_event(dev, CAN_LED_EVENT_STOP); 1350 1351 return 0; 1352 } 1353 1354 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx) 1355 { 1356 struct m_can_priv *priv = netdev_priv(dev); 1357 /*get wrap around for loopback skb index */ 1358 unsigned int wrap = priv->can.echo_skb_max; 1359 int next_idx; 1360 1361 /* calculate next index */ 1362 next_idx = (++putidx >= wrap ? 0 : putidx); 1363 1364 /* check if occupied */ 1365 return !!priv->can.echo_skb[next_idx]; 1366 } 1367 1368 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, 1369 struct net_device *dev) 1370 { 1371 struct m_can_priv *priv = netdev_priv(dev); 1372 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 1373 u32 id, cccr, fdflags; 1374 int i; 1375 int putidx; 1376 1377 if (can_dropped_invalid_skb(dev, skb)) 1378 return NETDEV_TX_OK; 1379 1380 /* Generate ID field for TX buffer Element */ 1381 /* Common to all supported M_CAN versions */ 1382 if (cf->can_id & CAN_EFF_FLAG) { 1383 id = cf->can_id & CAN_EFF_MASK; 1384 id |= TX_BUF_XTD; 1385 } else { 1386 id = ((cf->can_id & CAN_SFF_MASK) << 18); 1387 } 1388 1389 if (cf->can_id & CAN_RTR_FLAG) 1390 id |= TX_BUF_RTR; 1391 1392 if (priv->version == 30) { 1393 netif_stop_queue(dev); 1394 1395 /* message ram configuration */ 1396 m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id); 1397 m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, 1398 can_len2dlc(cf->len) << 16); 1399 1400 for (i = 0; i < cf->len; i += 4) 1401 m_can_fifo_write(priv, 0, 1402 M_CAN_FIFO_DATA(i / 4), 1403 *(u32 *)(cf->data + i)); 1404 1405 can_put_echo_skb(skb, dev, 0); 1406 1407 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1408 cccr = m_can_read(priv, M_CAN_CCCR); 1409 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT); 1410 if (can_is_canfd_skb(skb)) { 1411 if (cf->flags & CANFD_BRS) 1412 cccr |= CCCR_CMR_CANFD_BRS << 1413 CCCR_CMR_SHIFT; 1414 else 1415 cccr |= CCCR_CMR_CANFD << 1416 CCCR_CMR_SHIFT; 1417 } else { 1418 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT; 1419 } 1420 m_can_write(priv, M_CAN_CCCR, cccr); 1421 } 1422 m_can_write(priv, M_CAN_TXBTIE, 0x1); 1423 m_can_write(priv, M_CAN_TXBAR, 0x1); 1424 /* End of xmit function for version 3.0.x */ 1425 } else { 1426 /* Transmit routine for version >= v3.1.x */ 1427 1428 /* Check if FIFO full */ 1429 if (m_can_tx_fifo_full(priv)) { 1430 /* This shouldn't happen */ 1431 netif_stop_queue(dev); 1432 netdev_warn(dev, 1433 "TX queue active although FIFO is full."); 1434 return NETDEV_TX_BUSY; 1435 } 1436 1437 /* get put index for frame */ 1438 putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK) 1439 >> TXFQS_TFQPI_SHIFT); 1440 /* Write ID Field to FIFO Element */ 1441 m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id); 1442 1443 /* get CAN FD configuration of frame */ 1444 fdflags = 0; 1445 if (can_is_canfd_skb(skb)) { 1446 fdflags |= TX_BUF_FDF; 1447 if (cf->flags & CANFD_BRS) 1448 fdflags |= TX_BUF_BRS; 1449 } 1450 1451 /* Construct DLC Field. Also contains CAN-FD configuration 1452 * use put index of fifo as message marker 1453 * it is used in TX interrupt for 1454 * sending the correct echo frame 1455 */ 1456 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC, 1457 ((putidx << TX_BUF_MM_SHIFT) & 1458 TX_BUF_MM_MASK) | 1459 (can_len2dlc(cf->len) << 16) | 1460 fdflags | TX_BUF_EFC); 1461 1462 for (i = 0; i < cf->len; i += 4) 1463 m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4), 1464 *(u32 *)(cf->data + i)); 1465 1466 /* Push loopback echo. 1467 * Will be looped back on TX interrupt based on message marker 1468 */ 1469 can_put_echo_skb(skb, dev, putidx); 1470 1471 /* Enable TX FIFO element to start transfer */ 1472 m_can_write(priv, M_CAN_TXBAR, (1 << putidx)); 1473 1474 /* stop network queue if fifo full */ 1475 if (m_can_tx_fifo_full(priv) || 1476 m_can_next_echo_skb_occupied(dev, putidx)) 1477 netif_stop_queue(dev); 1478 } 1479 1480 return NETDEV_TX_OK; 1481 } 1482 1483 static const struct net_device_ops m_can_netdev_ops = { 1484 .ndo_open = m_can_open, 1485 .ndo_stop = m_can_close, 1486 .ndo_start_xmit = m_can_start_xmit, 1487 .ndo_change_mtu = can_change_mtu, 1488 }; 1489 1490 static int register_m_can_dev(struct net_device *dev) 1491 { 1492 dev->flags |= IFF_ECHO; /* we support local echo */ 1493 dev->netdev_ops = &m_can_netdev_ops; 1494 1495 return register_candev(dev); 1496 } 1497 1498 static void m_can_init_ram(struct m_can_priv *priv) 1499 { 1500 int end, i, start; 1501 1502 /* initialize the entire Message RAM in use to avoid possible 1503 * ECC/parity checksum errors when reading an uninitialized buffer 1504 */ 1505 start = priv->mcfg[MRAM_SIDF].off; 1506 end = priv->mcfg[MRAM_TXB].off + 1507 priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 1508 for (i = start; i < end; i += 4) 1509 writel(0x0, priv->mram_base + i); 1510 } 1511 1512 static void m_can_of_parse_mram(struct m_can_priv *priv, 1513 const u32 *mram_config_vals) 1514 { 1515 priv->mcfg[MRAM_SIDF].off = mram_config_vals[0]; 1516 priv->mcfg[MRAM_SIDF].num = mram_config_vals[1]; 1517 priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off + 1518 priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; 1519 priv->mcfg[MRAM_XIDF].num = mram_config_vals[2]; 1520 priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off + 1521 priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; 1522 priv->mcfg[MRAM_RXF0].num = mram_config_vals[3] & 1523 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1524 priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off + 1525 priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; 1526 priv->mcfg[MRAM_RXF1].num = mram_config_vals[4] & 1527 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1528 priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off + 1529 priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; 1530 priv->mcfg[MRAM_RXB].num = mram_config_vals[5]; 1531 priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off + 1532 priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; 1533 priv->mcfg[MRAM_TXE].num = mram_config_vals[6]; 1534 priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off + 1535 priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; 1536 priv->mcfg[MRAM_TXB].num = mram_config_vals[7] & 1537 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT); 1538 1539 dev_dbg(priv->device, 1540 "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", 1541 priv->mram_base, 1542 priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num, 1543 priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num, 1544 priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num, 1545 priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num, 1546 priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num, 1547 priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num, 1548 priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num); 1549 1550 m_can_init_ram(priv); 1551 } 1552 1553 static int m_can_plat_probe(struct platform_device *pdev) 1554 { 1555 struct net_device *dev; 1556 struct m_can_priv *priv; 1557 struct resource *res; 1558 void __iomem *addr; 1559 void __iomem *mram_addr; 1560 struct clk *hclk, *cclk; 1561 int irq, ret; 1562 struct device_node *np; 1563 u32 mram_config_vals[MRAM_CFG_LEN]; 1564 u32 tx_fifo_size; 1565 1566 np = pdev->dev.of_node; 1567 1568 hclk = devm_clk_get(&pdev->dev, "hclk"); 1569 cclk = devm_clk_get(&pdev->dev, "cclk"); 1570 1571 if (IS_ERR(hclk) || IS_ERR(cclk)) { 1572 dev_err(&pdev->dev, "no clock found\n"); 1573 ret = -ENODEV; 1574 goto failed_ret; 1575 } 1576 1577 /* Enable clocks. Necessary to read Core Release in order to determine 1578 * M_CAN version 1579 */ 1580 ret = clk_prepare_enable(hclk); 1581 if (ret) 1582 goto disable_hclk_ret; 1583 1584 ret = clk_prepare_enable(cclk); 1585 if (ret) 1586 goto disable_cclk_ret; 1587 1588 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can"); 1589 addr = devm_ioremap_resource(&pdev->dev, res); 1590 irq = platform_get_irq_byname(pdev, "int0"); 1591 1592 if (IS_ERR(addr) || irq < 0) { 1593 ret = -EINVAL; 1594 goto disable_cclk_ret; 1595 } 1596 1597 /* message ram could be shared */ 1598 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram"); 1599 if (!res) { 1600 ret = -ENODEV; 1601 goto disable_cclk_ret; 1602 } 1603 1604 mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1605 if (!mram_addr) { 1606 ret = -ENOMEM; 1607 goto disable_cclk_ret; 1608 } 1609 1610 /* get message ram configuration */ 1611 ret = of_property_read_u32_array(np, "bosch,mram-cfg", 1612 mram_config_vals, 1613 sizeof(mram_config_vals) / 4); 1614 if (ret) { 1615 dev_err(&pdev->dev, "Could not get Message RAM configuration."); 1616 goto disable_cclk_ret; 1617 } 1618 1619 /* Get TX FIFO size 1620 * Defines the total amount of echo buffers for loopback 1621 */ 1622 tx_fifo_size = mram_config_vals[7]; 1623 1624 /* allocate the m_can device */ 1625 dev = alloc_m_can_dev(pdev, addr, tx_fifo_size); 1626 if (!dev) { 1627 ret = -ENOMEM; 1628 goto disable_cclk_ret; 1629 } 1630 priv = netdev_priv(dev); 1631 dev->irq = irq; 1632 priv->device = &pdev->dev; 1633 priv->hclk = hclk; 1634 priv->cclk = cclk; 1635 priv->can.clock.freq = clk_get_rate(cclk); 1636 priv->mram_base = mram_addr; 1637 1638 m_can_of_parse_mram(priv, mram_config_vals); 1639 1640 platform_set_drvdata(pdev, dev); 1641 SET_NETDEV_DEV(dev, &pdev->dev); 1642 1643 ret = register_m_can_dev(dev); 1644 if (ret) { 1645 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 1646 KBUILD_MODNAME, ret); 1647 goto failed_free_dev; 1648 } 1649 1650 devm_can_led_init(dev); 1651 1652 dev_info(&pdev->dev, "%s device registered (irq=%d, version=%d)\n", 1653 KBUILD_MODNAME, dev->irq, priv->version); 1654 1655 /* Probe finished 1656 * Stop clocks. They will be reactivated once the M_CAN device is opened 1657 */ 1658 1659 goto disable_cclk_ret; 1660 1661 failed_free_dev: 1662 free_m_can_dev(dev); 1663 disable_cclk_ret: 1664 clk_disable_unprepare(cclk); 1665 disable_hclk_ret: 1666 clk_disable_unprepare(hclk); 1667 failed_ret: 1668 return ret; 1669 } 1670 1671 /* TODO: runtime PM with power down or sleep mode */ 1672 1673 static __maybe_unused int m_can_suspend(struct device *dev) 1674 { 1675 struct net_device *ndev = dev_get_drvdata(dev); 1676 struct m_can_priv *priv = netdev_priv(ndev); 1677 1678 if (netif_running(ndev)) { 1679 netif_stop_queue(ndev); 1680 netif_device_detach(ndev); 1681 m_can_stop(ndev); 1682 m_can_clk_stop(priv); 1683 } 1684 1685 priv->can.state = CAN_STATE_SLEEPING; 1686 1687 return 0; 1688 } 1689 1690 static __maybe_unused int m_can_resume(struct device *dev) 1691 { 1692 struct net_device *ndev = dev_get_drvdata(dev); 1693 struct m_can_priv *priv = netdev_priv(ndev); 1694 1695 m_can_init_ram(priv); 1696 1697 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1698 1699 if (netif_running(ndev)) { 1700 int ret; 1701 1702 ret = m_can_clk_start(priv); 1703 if (ret) 1704 return ret; 1705 1706 m_can_start(ndev); 1707 netif_device_attach(ndev); 1708 netif_start_queue(ndev); 1709 } 1710 1711 return 0; 1712 } 1713 1714 static void unregister_m_can_dev(struct net_device *dev) 1715 { 1716 unregister_candev(dev); 1717 } 1718 1719 static int m_can_plat_remove(struct platform_device *pdev) 1720 { 1721 struct net_device *dev = platform_get_drvdata(pdev); 1722 1723 unregister_m_can_dev(dev); 1724 platform_set_drvdata(pdev, NULL); 1725 1726 free_m_can_dev(dev); 1727 1728 return 0; 1729 } 1730 1731 static const struct dev_pm_ops m_can_pmops = { 1732 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume) 1733 }; 1734 1735 static const struct of_device_id m_can_of_table[] = { 1736 { .compatible = "bosch,m_can", .data = NULL }, 1737 { /* sentinel */ }, 1738 }; 1739 MODULE_DEVICE_TABLE(of, m_can_of_table); 1740 1741 static struct platform_driver m_can_plat_driver = { 1742 .driver = { 1743 .name = KBUILD_MODNAME, 1744 .of_match_table = m_can_of_table, 1745 .pm = &m_can_pmops, 1746 }, 1747 .probe = m_can_plat_probe, 1748 .remove = m_can_plat_remove, 1749 }; 1750 1751 module_platform_driver(m_can_plat_driver); 1752 1753 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); 1754 MODULE_LICENSE("GPL v2"); 1755 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); 1756