1 // SPDX-License-Identifier: GPL-2.0 2 // CAN bus driver for Bosch M_CAN controller 3 // Copyright (C) 2014 Freescale Semiconductor, Inc. 4 // Dong Aisheng <b29396@freescale.com> 5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/ 6 7 /* Bosch M_CAN user manual can be obtained from: 8 * https://github.com/linux-can/can-doc/tree/master/m_can 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/iopoll.h> 21 #include <linux/can/dev.h> 22 #include <linux/pinctrl/consumer.h> 23 24 #include "m_can.h" 25 26 /* registers definition */ 27 enum m_can_reg { 28 M_CAN_CREL = 0x0, 29 M_CAN_ENDN = 0x4, 30 M_CAN_CUST = 0x8, 31 M_CAN_DBTP = 0xc, 32 M_CAN_TEST = 0x10, 33 M_CAN_RWD = 0x14, 34 M_CAN_CCCR = 0x18, 35 M_CAN_NBTP = 0x1c, 36 M_CAN_TSCC = 0x20, 37 M_CAN_TSCV = 0x24, 38 M_CAN_TOCC = 0x28, 39 M_CAN_TOCV = 0x2c, 40 M_CAN_ECR = 0x40, 41 M_CAN_PSR = 0x44, 42 /* TDCR Register only available for version >=3.1.x */ 43 M_CAN_TDCR = 0x48, 44 M_CAN_IR = 0x50, 45 M_CAN_IE = 0x54, 46 M_CAN_ILS = 0x58, 47 M_CAN_ILE = 0x5c, 48 M_CAN_GFC = 0x80, 49 M_CAN_SIDFC = 0x84, 50 M_CAN_XIDFC = 0x88, 51 M_CAN_XIDAM = 0x90, 52 M_CAN_HPMS = 0x94, 53 M_CAN_NDAT1 = 0x98, 54 M_CAN_NDAT2 = 0x9c, 55 M_CAN_RXF0C = 0xa0, 56 M_CAN_RXF0S = 0xa4, 57 M_CAN_RXF0A = 0xa8, 58 M_CAN_RXBC = 0xac, 59 M_CAN_RXF1C = 0xb0, 60 M_CAN_RXF1S = 0xb4, 61 M_CAN_RXF1A = 0xb8, 62 M_CAN_RXESC = 0xbc, 63 M_CAN_TXBC = 0xc0, 64 M_CAN_TXFQS = 0xc4, 65 M_CAN_TXESC = 0xc8, 66 M_CAN_TXBRP = 0xcc, 67 M_CAN_TXBAR = 0xd0, 68 M_CAN_TXBCR = 0xd4, 69 M_CAN_TXBTO = 0xd8, 70 M_CAN_TXBCF = 0xdc, 71 M_CAN_TXBTIE = 0xe0, 72 M_CAN_TXBCIE = 0xe4, 73 M_CAN_TXEFC = 0xf0, 74 M_CAN_TXEFS = 0xf4, 75 M_CAN_TXEFA = 0xf8, 76 }; 77 78 /* napi related */ 79 #define M_CAN_NAPI_WEIGHT 64 80 81 /* message ram configuration data length */ 82 #define MRAM_CFG_LEN 8 83 84 /* Core Release Register (CREL) */ 85 #define CREL_REL_SHIFT 28 86 #define CREL_REL_MASK (0xF << CREL_REL_SHIFT) 87 #define CREL_STEP_SHIFT 24 88 #define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT) 89 #define CREL_SUBSTEP_SHIFT 20 90 #define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT) 91 92 /* Data Bit Timing & Prescaler Register (DBTP) */ 93 #define DBTP_TDC BIT(23) 94 #define DBTP_DBRP_SHIFT 16 95 #define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT) 96 #define DBTP_DTSEG1_SHIFT 8 97 #define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT) 98 #define DBTP_DTSEG2_SHIFT 4 99 #define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT) 100 #define DBTP_DSJW_SHIFT 0 101 #define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT) 102 103 /* Transmitter Delay Compensation Register (TDCR) */ 104 #define TDCR_TDCO_SHIFT 8 105 #define TDCR_TDCO_MASK (0x7F << TDCR_TDCO_SHIFT) 106 #define TDCR_TDCF_SHIFT 0 107 #define TDCR_TDCF_MASK (0x7F << TDCR_TDCF_SHIFT) 108 109 /* Test Register (TEST) */ 110 #define TEST_LBCK BIT(4) 111 112 /* CC Control Register(CCCR) */ 113 #define CCCR_CMR_MASK 0x3 114 #define CCCR_CMR_SHIFT 10 115 #define CCCR_CMR_CANFD 0x1 116 #define CCCR_CMR_CANFD_BRS 0x2 117 #define CCCR_CMR_CAN 0x3 118 #define CCCR_CME_MASK 0x3 119 #define CCCR_CME_SHIFT 8 120 #define CCCR_CME_CAN 0 121 #define CCCR_CME_CANFD 0x1 122 #define CCCR_CME_CANFD_BRS 0x2 123 #define CCCR_TXP BIT(14) 124 #define CCCR_TEST BIT(7) 125 #define CCCR_DAR BIT(6) 126 #define CCCR_MON BIT(5) 127 #define CCCR_CSR BIT(4) 128 #define CCCR_CSA BIT(3) 129 #define CCCR_ASM BIT(2) 130 #define CCCR_CCE BIT(1) 131 #define CCCR_INIT BIT(0) 132 #define CCCR_CANFD 0x10 133 /* for version >=3.1.x */ 134 #define CCCR_EFBI BIT(13) 135 #define CCCR_PXHD BIT(12) 136 #define CCCR_BRSE BIT(9) 137 #define CCCR_FDOE BIT(8) 138 /* only for version >=3.2.x */ 139 #define CCCR_NISO BIT(15) 140 141 /* Nominal Bit Timing & Prescaler Register (NBTP) */ 142 #define NBTP_NSJW_SHIFT 25 143 #define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT) 144 #define NBTP_NBRP_SHIFT 16 145 #define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT) 146 #define NBTP_NTSEG1_SHIFT 8 147 #define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT) 148 #define NBTP_NTSEG2_SHIFT 0 149 #define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT) 150 151 /* Error Counter Register(ECR) */ 152 #define ECR_RP BIT(15) 153 #define ECR_REC_SHIFT 8 154 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT) 155 #define ECR_TEC_SHIFT 0 156 #define ECR_TEC_MASK 0xff 157 158 /* Protocol Status Register(PSR) */ 159 #define PSR_BO BIT(7) 160 #define PSR_EW BIT(6) 161 #define PSR_EP BIT(5) 162 #define PSR_LEC_MASK 0x7 163 164 /* Interrupt Register(IR) */ 165 #define IR_ALL_INT 0xffffffff 166 167 /* Renamed bits for versions > 3.1.x */ 168 #define IR_ARA BIT(29) 169 #define IR_PED BIT(28) 170 #define IR_PEA BIT(27) 171 172 /* Bits for version 3.0.x */ 173 #define IR_STE BIT(31) 174 #define IR_FOE BIT(30) 175 #define IR_ACKE BIT(29) 176 #define IR_BE BIT(28) 177 #define IR_CRCE BIT(27) 178 #define IR_WDI BIT(26) 179 #define IR_BO BIT(25) 180 #define IR_EW BIT(24) 181 #define IR_EP BIT(23) 182 #define IR_ELO BIT(22) 183 #define IR_BEU BIT(21) 184 #define IR_BEC BIT(20) 185 #define IR_DRX BIT(19) 186 #define IR_TOO BIT(18) 187 #define IR_MRAF BIT(17) 188 #define IR_TSW BIT(16) 189 #define IR_TEFL BIT(15) 190 #define IR_TEFF BIT(14) 191 #define IR_TEFW BIT(13) 192 #define IR_TEFN BIT(12) 193 #define IR_TFE BIT(11) 194 #define IR_TCF BIT(10) 195 #define IR_TC BIT(9) 196 #define IR_HPM BIT(8) 197 #define IR_RF1L BIT(7) 198 #define IR_RF1F BIT(6) 199 #define IR_RF1W BIT(5) 200 #define IR_RF1N BIT(4) 201 #define IR_RF0L BIT(3) 202 #define IR_RF0F BIT(2) 203 #define IR_RF0W BIT(1) 204 #define IR_RF0N BIT(0) 205 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) 206 207 /* Interrupts for version 3.0.x */ 208 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) 209 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \ 210 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 211 IR_RF1L | IR_RF0L) 212 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X) 213 /* Interrupts for version >= 3.1.x */ 214 #define IR_ERR_LEC_31X (IR_PED | IR_PEA) 215 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \ 216 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ 217 IR_RF1L | IR_RF0L) 218 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X) 219 220 /* Interrupt Line Select (ILS) */ 221 #define ILS_ALL_INT0 0x0 222 #define ILS_ALL_INT1 0xFFFFFFFF 223 224 /* Interrupt Line Enable (ILE) */ 225 #define ILE_EINT1 BIT(1) 226 #define ILE_EINT0 BIT(0) 227 228 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ 229 #define RXFC_FWM_SHIFT 24 230 #define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT) 231 #define RXFC_FS_SHIFT 16 232 #define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT) 233 234 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ 235 #define RXFS_RFL BIT(25) 236 #define RXFS_FF BIT(24) 237 #define RXFS_FPI_SHIFT 16 238 #define RXFS_FPI_MASK 0x3f0000 239 #define RXFS_FGI_SHIFT 8 240 #define RXFS_FGI_MASK 0x3f00 241 #define RXFS_FFL_MASK 0x7f 242 243 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ 244 #define M_CAN_RXESC_8BYTES 0x0 245 #define M_CAN_RXESC_64BYTES 0x777 246 247 /* Tx Buffer Configuration(TXBC) */ 248 #define TXBC_NDTB_SHIFT 16 249 #define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT) 250 #define TXBC_TFQS_SHIFT 24 251 #define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT) 252 253 /* Tx FIFO/Queue Status (TXFQS) */ 254 #define TXFQS_TFQF BIT(21) 255 #define TXFQS_TFQPI_SHIFT 16 256 #define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT) 257 #define TXFQS_TFGI_SHIFT 8 258 #define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT) 259 #define TXFQS_TFFL_SHIFT 0 260 #define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT) 261 262 /* Tx Buffer Element Size Configuration(TXESC) */ 263 #define TXESC_TBDS_8BYTES 0x0 264 #define TXESC_TBDS_64BYTES 0x7 265 266 /* Tx Event FIFO Configuration (TXEFC) */ 267 #define TXEFC_EFS_SHIFT 16 268 #define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT) 269 270 /* Tx Event FIFO Status (TXEFS) */ 271 #define TXEFS_TEFL BIT(25) 272 #define TXEFS_EFF BIT(24) 273 #define TXEFS_EFGI_SHIFT 8 274 #define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT) 275 #define TXEFS_EFFL_SHIFT 0 276 #define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT) 277 278 /* Tx Event FIFO Acknowledge (TXEFA) */ 279 #define TXEFA_EFAI_SHIFT 0 280 #define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT) 281 282 /* Message RAM Configuration (in bytes) */ 283 #define SIDF_ELEMENT_SIZE 4 284 #define XIDF_ELEMENT_SIZE 8 285 #define RXF0_ELEMENT_SIZE 72 286 #define RXF1_ELEMENT_SIZE 72 287 #define RXB_ELEMENT_SIZE 72 288 #define TXE_ELEMENT_SIZE 8 289 #define TXB_ELEMENT_SIZE 72 290 291 /* Message RAM Elements */ 292 #define M_CAN_FIFO_ID 0x0 293 #define M_CAN_FIFO_DLC 0x4 294 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2)) 295 296 /* Rx Buffer Element */ 297 /* R0 */ 298 #define RX_BUF_ESI BIT(31) 299 #define RX_BUF_XTD BIT(30) 300 #define RX_BUF_RTR BIT(29) 301 /* R1 */ 302 #define RX_BUF_ANMF BIT(31) 303 #define RX_BUF_FDF BIT(21) 304 #define RX_BUF_BRS BIT(20) 305 306 /* Tx Buffer Element */ 307 /* T0 */ 308 #define TX_BUF_ESI BIT(31) 309 #define TX_BUF_XTD BIT(30) 310 #define TX_BUF_RTR BIT(29) 311 /* T1 */ 312 #define TX_BUF_EFC BIT(23) 313 #define TX_BUF_FDF BIT(21) 314 #define TX_BUF_BRS BIT(20) 315 #define TX_BUF_MM_SHIFT 24 316 #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT) 317 318 /* Tx event FIFO Element */ 319 /* E1 */ 320 #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT 321 #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT) 322 323 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) 324 { 325 return cdev->ops->read_reg(cdev, reg); 326 } 327 328 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, 329 u32 val) 330 { 331 cdev->ops->write_reg(cdev, reg, val); 332 } 333 334 static u32 m_can_fifo_read(struct m_can_classdev *cdev, 335 u32 fgi, unsigned int offset) 336 { 337 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + 338 offset; 339 340 return cdev->ops->read_fifo(cdev, addr_offset); 341 } 342 343 static void m_can_fifo_write(struct m_can_classdev *cdev, 344 u32 fpi, unsigned int offset, u32 val) 345 { 346 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + 347 offset; 348 349 cdev->ops->write_fifo(cdev, addr_offset, val); 350 } 351 352 static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev, 353 u32 fpi, u32 val) 354 { 355 cdev->ops->write_fifo(cdev, fpi, val); 356 } 357 358 static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset) 359 { 360 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + 361 offset; 362 363 return cdev->ops->read_fifo(cdev, addr_offset); 364 } 365 366 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev) 367 { 368 return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF); 369 } 370 371 static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable) 372 { 373 u32 cccr = m_can_read(cdev, M_CAN_CCCR); 374 u32 timeout = 10; 375 u32 val = 0; 376 377 /* Clear the Clock stop request if it was set */ 378 if (cccr & CCCR_CSR) 379 cccr &= ~CCCR_CSR; 380 381 if (enable) { 382 /* enable m_can configuration */ 383 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT); 384 udelay(5); 385 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ 386 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); 387 } else { 388 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); 389 } 390 391 /* there's a delay for module initialization */ 392 if (enable) 393 val = CCCR_INIT | CCCR_CCE; 394 395 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { 396 if (timeout == 0) { 397 netdev_warn(cdev->net, "Failed to init module\n"); 398 return; 399 } 400 timeout--; 401 udelay(1); 402 } 403 } 404 405 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev) 406 { 407 /* Only interrupt line 0 is used in this driver */ 408 m_can_write(cdev, M_CAN_ILE, ILE_EINT0); 409 } 410 411 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev) 412 { 413 m_can_write(cdev, M_CAN_ILE, 0x0); 414 } 415 416 static void m_can_clean(struct net_device *net) 417 { 418 struct m_can_classdev *cdev = netdev_priv(net); 419 420 if (cdev->tx_skb) { 421 int putidx = 0; 422 423 net->stats.tx_errors++; 424 if (cdev->version > 30) 425 putidx = ((m_can_read(cdev, M_CAN_TXFQS) & 426 TXFQS_TFQPI_MASK) >> TXFQS_TFQPI_SHIFT); 427 428 can_free_echo_skb(cdev->net, putidx); 429 cdev->tx_skb = NULL; 430 } 431 } 432 433 static void m_can_read_fifo(struct net_device *dev, u32 rxfs) 434 { 435 struct net_device_stats *stats = &dev->stats; 436 struct m_can_classdev *cdev = netdev_priv(dev); 437 struct canfd_frame *cf; 438 struct sk_buff *skb; 439 u32 id, fgi, dlc; 440 int i; 441 442 /* calculate the fifo get index for where to read data */ 443 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT; 444 dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC); 445 if (dlc & RX_BUF_FDF) 446 skb = alloc_canfd_skb(dev, &cf); 447 else 448 skb = alloc_can_skb(dev, (struct can_frame **)&cf); 449 if (!skb) { 450 stats->rx_dropped++; 451 return; 452 } 453 454 if (dlc & RX_BUF_FDF) 455 cf->len = can_fd_dlc2len((dlc >> 16) & 0x0F); 456 else 457 cf->len = can_cc_dlc2len((dlc >> 16) & 0x0F); 458 459 id = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID); 460 if (id & RX_BUF_XTD) 461 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; 462 else 463 cf->can_id = (id >> 18) & CAN_SFF_MASK; 464 465 if (id & RX_BUF_ESI) { 466 cf->flags |= CANFD_ESI; 467 netdev_dbg(dev, "ESI Error\n"); 468 } 469 470 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) { 471 cf->can_id |= CAN_RTR_FLAG; 472 } else { 473 if (dlc & RX_BUF_BRS) 474 cf->flags |= CANFD_BRS; 475 476 for (i = 0; i < cf->len; i += 4) 477 *(u32 *)(cf->data + i) = 478 m_can_fifo_read(cdev, fgi, 479 M_CAN_FIFO_DATA(i / 4)); 480 } 481 482 /* acknowledge rx fifo 0 */ 483 m_can_write(cdev, M_CAN_RXF0A, fgi); 484 485 stats->rx_packets++; 486 stats->rx_bytes += cf->len; 487 488 netif_receive_skb(skb); 489 } 490 491 static int m_can_do_rx_poll(struct net_device *dev, int quota) 492 { 493 struct m_can_classdev *cdev = netdev_priv(dev); 494 u32 pkts = 0; 495 u32 rxfs; 496 497 rxfs = m_can_read(cdev, M_CAN_RXF0S); 498 if (!(rxfs & RXFS_FFL_MASK)) { 499 netdev_dbg(dev, "no messages in fifo0\n"); 500 return 0; 501 } 502 503 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) { 504 if (rxfs & RXFS_RFL) 505 netdev_warn(dev, "Rx FIFO 0 Message Lost\n"); 506 507 m_can_read_fifo(dev, rxfs); 508 509 quota--; 510 pkts++; 511 rxfs = m_can_read(cdev, M_CAN_RXF0S); 512 } 513 514 if (pkts) 515 can_led_event(dev, CAN_LED_EVENT_RX); 516 517 return pkts; 518 } 519 520 static int m_can_handle_lost_msg(struct net_device *dev) 521 { 522 struct net_device_stats *stats = &dev->stats; 523 struct sk_buff *skb; 524 struct can_frame *frame; 525 526 netdev_err(dev, "msg lost in rxf0\n"); 527 528 stats->rx_errors++; 529 stats->rx_over_errors++; 530 531 skb = alloc_can_err_skb(dev, &frame); 532 if (unlikely(!skb)) 533 return 0; 534 535 frame->can_id |= CAN_ERR_CRTL; 536 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 537 538 netif_receive_skb(skb); 539 540 return 1; 541 } 542 543 static int m_can_handle_lec_err(struct net_device *dev, 544 enum m_can_lec_type lec_type) 545 { 546 struct m_can_classdev *cdev = netdev_priv(dev); 547 struct net_device_stats *stats = &dev->stats; 548 struct can_frame *cf; 549 struct sk_buff *skb; 550 551 cdev->can.can_stats.bus_error++; 552 stats->rx_errors++; 553 554 /* propagate the error condition to the CAN stack */ 555 skb = alloc_can_err_skb(dev, &cf); 556 if (unlikely(!skb)) 557 return 0; 558 559 /* check for 'last error code' which tells us the 560 * type of the last error to occur on the CAN bus 561 */ 562 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 563 564 switch (lec_type) { 565 case LEC_STUFF_ERROR: 566 netdev_dbg(dev, "stuff error\n"); 567 cf->data[2] |= CAN_ERR_PROT_STUFF; 568 break; 569 case LEC_FORM_ERROR: 570 netdev_dbg(dev, "form error\n"); 571 cf->data[2] |= CAN_ERR_PROT_FORM; 572 break; 573 case LEC_ACK_ERROR: 574 netdev_dbg(dev, "ack error\n"); 575 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 576 break; 577 case LEC_BIT1_ERROR: 578 netdev_dbg(dev, "bit1 error\n"); 579 cf->data[2] |= CAN_ERR_PROT_BIT1; 580 break; 581 case LEC_BIT0_ERROR: 582 netdev_dbg(dev, "bit0 error\n"); 583 cf->data[2] |= CAN_ERR_PROT_BIT0; 584 break; 585 case LEC_CRC_ERROR: 586 netdev_dbg(dev, "CRC error\n"); 587 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 588 break; 589 default: 590 break; 591 } 592 593 stats->rx_packets++; 594 stats->rx_bytes += cf->len; 595 netif_receive_skb(skb); 596 597 return 1; 598 } 599 600 static int __m_can_get_berr_counter(const struct net_device *dev, 601 struct can_berr_counter *bec) 602 { 603 struct m_can_classdev *cdev = netdev_priv(dev); 604 unsigned int ecr; 605 606 ecr = m_can_read(cdev, M_CAN_ECR); 607 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT; 608 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT; 609 610 return 0; 611 } 612 613 static int m_can_clk_start(struct m_can_classdev *cdev) 614 { 615 if (cdev->pm_clock_support == 0) 616 return 0; 617 618 return pm_runtime_resume_and_get(cdev->dev); 619 } 620 621 static void m_can_clk_stop(struct m_can_classdev *cdev) 622 { 623 if (cdev->pm_clock_support) 624 pm_runtime_put_sync(cdev->dev); 625 } 626 627 static int m_can_get_berr_counter(const struct net_device *dev, 628 struct can_berr_counter *bec) 629 { 630 struct m_can_classdev *cdev = netdev_priv(dev); 631 int err; 632 633 err = m_can_clk_start(cdev); 634 if (err) 635 return err; 636 637 __m_can_get_berr_counter(dev, bec); 638 639 m_can_clk_stop(cdev); 640 641 return 0; 642 } 643 644 static int m_can_handle_state_change(struct net_device *dev, 645 enum can_state new_state) 646 { 647 struct m_can_classdev *cdev = netdev_priv(dev); 648 struct net_device_stats *stats = &dev->stats; 649 struct can_frame *cf; 650 struct sk_buff *skb; 651 struct can_berr_counter bec; 652 unsigned int ecr; 653 654 switch (new_state) { 655 case CAN_STATE_ERROR_WARNING: 656 /* error warning state */ 657 cdev->can.can_stats.error_warning++; 658 cdev->can.state = CAN_STATE_ERROR_WARNING; 659 break; 660 case CAN_STATE_ERROR_PASSIVE: 661 /* error passive state */ 662 cdev->can.can_stats.error_passive++; 663 cdev->can.state = CAN_STATE_ERROR_PASSIVE; 664 break; 665 case CAN_STATE_BUS_OFF: 666 /* bus-off state */ 667 cdev->can.state = CAN_STATE_BUS_OFF; 668 m_can_disable_all_interrupts(cdev); 669 cdev->can.can_stats.bus_off++; 670 can_bus_off(dev); 671 break; 672 default: 673 break; 674 } 675 676 /* propagate the error condition to the CAN stack */ 677 skb = alloc_can_err_skb(dev, &cf); 678 if (unlikely(!skb)) 679 return 0; 680 681 __m_can_get_berr_counter(dev, &bec); 682 683 switch (new_state) { 684 case CAN_STATE_ERROR_WARNING: 685 /* error warning state */ 686 cf->can_id |= CAN_ERR_CRTL; 687 cf->data[1] = (bec.txerr > bec.rxerr) ? 688 CAN_ERR_CRTL_TX_WARNING : 689 CAN_ERR_CRTL_RX_WARNING; 690 cf->data[6] = bec.txerr; 691 cf->data[7] = bec.rxerr; 692 break; 693 case CAN_STATE_ERROR_PASSIVE: 694 /* error passive state */ 695 cf->can_id |= CAN_ERR_CRTL; 696 ecr = m_can_read(cdev, M_CAN_ECR); 697 if (ecr & ECR_RP) 698 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 699 if (bec.txerr > 127) 700 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 701 cf->data[6] = bec.txerr; 702 cf->data[7] = bec.rxerr; 703 break; 704 case CAN_STATE_BUS_OFF: 705 /* bus-off state */ 706 cf->can_id |= CAN_ERR_BUSOFF; 707 break; 708 default: 709 break; 710 } 711 712 stats->rx_packets++; 713 stats->rx_bytes += cf->len; 714 netif_receive_skb(skb); 715 716 return 1; 717 } 718 719 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) 720 { 721 struct m_can_classdev *cdev = netdev_priv(dev); 722 int work_done = 0; 723 724 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { 725 netdev_dbg(dev, "entered error warning state\n"); 726 work_done += m_can_handle_state_change(dev, 727 CAN_STATE_ERROR_WARNING); 728 } 729 730 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { 731 netdev_dbg(dev, "entered error passive state\n"); 732 work_done += m_can_handle_state_change(dev, 733 CAN_STATE_ERROR_PASSIVE); 734 } 735 736 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { 737 netdev_dbg(dev, "entered error bus off state\n"); 738 work_done += m_can_handle_state_change(dev, 739 CAN_STATE_BUS_OFF); 740 } 741 742 return work_done; 743 } 744 745 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) 746 { 747 if (irqstatus & IR_WDI) 748 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); 749 if (irqstatus & IR_ELO) 750 netdev_err(dev, "Error Logging Overflow\n"); 751 if (irqstatus & IR_BEU) 752 netdev_err(dev, "Bit Error Uncorrected\n"); 753 if (irqstatus & IR_BEC) 754 netdev_err(dev, "Bit Error Corrected\n"); 755 if (irqstatus & IR_TOO) 756 netdev_err(dev, "Timeout reached\n"); 757 if (irqstatus & IR_MRAF) 758 netdev_err(dev, "Message RAM access failure occurred\n"); 759 } 760 761 static inline bool is_lec_err(u32 psr) 762 { 763 psr &= LEC_UNUSED; 764 765 return psr && (psr != LEC_UNUSED); 766 } 767 768 static inline bool m_can_is_protocol_err(u32 irqstatus) 769 { 770 return irqstatus & IR_ERR_LEC_31X; 771 } 772 773 static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus) 774 { 775 struct net_device_stats *stats = &dev->stats; 776 struct m_can_classdev *cdev = netdev_priv(dev); 777 struct can_frame *cf; 778 struct sk_buff *skb; 779 780 /* propagate the error condition to the CAN stack */ 781 skb = alloc_can_err_skb(dev, &cf); 782 783 /* update tx error stats since there is protocol error */ 784 stats->tx_errors++; 785 786 /* update arbitration lost status */ 787 if (cdev->version >= 31 && (irqstatus & IR_PEA)) { 788 netdev_dbg(dev, "Protocol error in Arbitration fail\n"); 789 cdev->can.can_stats.arbitration_lost++; 790 if (skb) { 791 cf->can_id |= CAN_ERR_LOSTARB; 792 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC; 793 } 794 } 795 796 if (unlikely(!skb)) { 797 netdev_dbg(dev, "allocation of skb failed\n"); 798 return 0; 799 } 800 netif_receive_skb(skb); 801 802 return 1; 803 } 804 805 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, 806 u32 psr) 807 { 808 struct m_can_classdev *cdev = netdev_priv(dev); 809 int work_done = 0; 810 811 if (irqstatus & IR_RF0L) 812 work_done += m_can_handle_lost_msg(dev); 813 814 /* handle lec errors on the bus */ 815 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 816 is_lec_err(psr)) 817 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED); 818 819 /* handle protocol errors in arbitration phase */ 820 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 821 m_can_is_protocol_err(irqstatus)) 822 work_done += m_can_handle_protocol_error(dev, irqstatus); 823 824 /* other unproccessed error interrupts */ 825 m_can_handle_other_err(dev, irqstatus); 826 827 return work_done; 828 } 829 830 static int m_can_rx_handler(struct net_device *dev, int quota) 831 { 832 struct m_can_classdev *cdev = netdev_priv(dev); 833 int work_done = 0; 834 u32 irqstatus, psr; 835 836 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR); 837 if (!irqstatus) 838 goto end; 839 840 /* Errata workaround for issue "Needless activation of MRAF irq" 841 * During frame reception while the MCAN is in Error Passive state 842 * and the Receive Error Counter has the value MCAN_ECR.REC = 127, 843 * it may happen that MCAN_IR.MRAF is set although there was no 844 * Message RAM access failure. 845 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated 846 * The Message RAM Access Failure interrupt routine needs to check 847 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127. 848 * In this case, reset MCAN_IR.MRAF. No further action is required. 849 */ 850 if (cdev->version <= 31 && irqstatus & IR_MRAF && 851 m_can_read(cdev, M_CAN_ECR) & ECR_RP) { 852 struct can_berr_counter bec; 853 854 __m_can_get_berr_counter(dev, &bec); 855 if (bec.rxerr == 127) { 856 m_can_write(cdev, M_CAN_IR, IR_MRAF); 857 irqstatus &= ~IR_MRAF; 858 } 859 } 860 861 psr = m_can_read(cdev, M_CAN_PSR); 862 863 if (irqstatus & IR_ERR_STATE) 864 work_done += m_can_handle_state_errors(dev, psr); 865 866 if (irqstatus & IR_ERR_BUS_30X) 867 work_done += m_can_handle_bus_errors(dev, irqstatus, psr); 868 869 if (irqstatus & IR_RF0N) 870 work_done += m_can_do_rx_poll(dev, (quota - work_done)); 871 end: 872 return work_done; 873 } 874 875 static int m_can_rx_peripheral(struct net_device *dev) 876 { 877 struct m_can_classdev *cdev = netdev_priv(dev); 878 879 m_can_rx_handler(dev, 1); 880 881 m_can_enable_all_interrupts(cdev); 882 883 return 0; 884 } 885 886 static int m_can_poll(struct napi_struct *napi, int quota) 887 { 888 struct net_device *dev = napi->dev; 889 struct m_can_classdev *cdev = netdev_priv(dev); 890 int work_done; 891 892 work_done = m_can_rx_handler(dev, quota); 893 if (work_done < quota) { 894 napi_complete_done(napi, work_done); 895 m_can_enable_all_interrupts(cdev); 896 } 897 898 return work_done; 899 } 900 901 static void m_can_echo_tx_event(struct net_device *dev) 902 { 903 u32 txe_count = 0; 904 u32 m_can_txefs; 905 u32 fgi = 0; 906 int i = 0; 907 unsigned int msg_mark; 908 909 struct m_can_classdev *cdev = netdev_priv(dev); 910 struct net_device_stats *stats = &dev->stats; 911 912 /* read tx event fifo status */ 913 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); 914 915 /* Get Tx Event fifo element count */ 916 txe_count = (m_can_txefs & TXEFS_EFFL_MASK) >> TXEFS_EFFL_SHIFT; 917 918 /* Get and process all sent elements */ 919 for (i = 0; i < txe_count; i++) { 920 /* retrieve get index */ 921 fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK) >> 922 TXEFS_EFGI_SHIFT; 923 924 /* get message marker */ 925 msg_mark = (m_can_txe_fifo_read(cdev, fgi, 4) & 926 TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT; 927 928 /* ack txe element */ 929 m_can_write(cdev, M_CAN_TXEFA, (TXEFA_EFAI_MASK & 930 (fgi << TXEFA_EFAI_SHIFT))); 931 932 /* update stats */ 933 stats->tx_bytes += can_get_echo_skb(dev, msg_mark); 934 stats->tx_packets++; 935 } 936 } 937 938 static irqreturn_t m_can_isr(int irq, void *dev_id) 939 { 940 struct net_device *dev = (struct net_device *)dev_id; 941 struct m_can_classdev *cdev = netdev_priv(dev); 942 struct net_device_stats *stats = &dev->stats; 943 u32 ir; 944 945 if (pm_runtime_suspended(cdev->dev)) 946 return IRQ_NONE; 947 ir = m_can_read(cdev, M_CAN_IR); 948 if (!ir) 949 return IRQ_NONE; 950 951 /* ACK all irqs */ 952 if (ir & IR_ALL_INT) 953 m_can_write(cdev, M_CAN_IR, ir); 954 955 if (cdev->ops->clear_interrupts) 956 cdev->ops->clear_interrupts(cdev); 957 958 /* schedule NAPI in case of 959 * - rx IRQ 960 * - state change IRQ 961 * - bus error IRQ and bus error reporting 962 */ 963 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) { 964 cdev->irqstatus = ir; 965 m_can_disable_all_interrupts(cdev); 966 if (!cdev->is_peripheral) 967 napi_schedule(&cdev->napi); 968 else 969 m_can_rx_peripheral(dev); 970 } 971 972 if (cdev->version == 30) { 973 if (ir & IR_TC) { 974 /* Transmission Complete Interrupt*/ 975 stats->tx_bytes += can_get_echo_skb(dev, 0); 976 stats->tx_packets++; 977 can_led_event(dev, CAN_LED_EVENT_TX); 978 netif_wake_queue(dev); 979 } 980 } else { 981 if (ir & IR_TEFN) { 982 /* New TX FIFO Element arrived */ 983 m_can_echo_tx_event(dev); 984 can_led_event(dev, CAN_LED_EVENT_TX); 985 if (netif_queue_stopped(dev) && 986 !m_can_tx_fifo_full(cdev)) 987 netif_wake_queue(dev); 988 } 989 } 990 991 return IRQ_HANDLED; 992 } 993 994 static const struct can_bittiming_const m_can_bittiming_const_30X = { 995 .name = KBUILD_MODNAME, 996 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 997 .tseg1_max = 64, 998 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 999 .tseg2_max = 16, 1000 .sjw_max = 16, 1001 .brp_min = 1, 1002 .brp_max = 1024, 1003 .brp_inc = 1, 1004 }; 1005 1006 static const struct can_bittiming_const m_can_data_bittiming_const_30X = { 1007 .name = KBUILD_MODNAME, 1008 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1009 .tseg1_max = 16, 1010 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1011 .tseg2_max = 8, 1012 .sjw_max = 4, 1013 .brp_min = 1, 1014 .brp_max = 32, 1015 .brp_inc = 1, 1016 }; 1017 1018 static const struct can_bittiming_const m_can_bittiming_const_31X = { 1019 .name = KBUILD_MODNAME, 1020 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1021 .tseg1_max = 256, 1022 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */ 1023 .tseg2_max = 128, 1024 .sjw_max = 128, 1025 .brp_min = 1, 1026 .brp_max = 512, 1027 .brp_inc = 1, 1028 }; 1029 1030 static const struct can_bittiming_const m_can_data_bittiming_const_31X = { 1031 .name = KBUILD_MODNAME, 1032 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */ 1033 .tseg1_max = 32, 1034 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1035 .tseg2_max = 16, 1036 .sjw_max = 16, 1037 .brp_min = 1, 1038 .brp_max = 32, 1039 .brp_inc = 1, 1040 }; 1041 1042 static int m_can_set_bittiming(struct net_device *dev) 1043 { 1044 struct m_can_classdev *cdev = netdev_priv(dev); 1045 const struct can_bittiming *bt = &cdev->can.bittiming; 1046 const struct can_bittiming *dbt = &cdev->can.data_bittiming; 1047 u16 brp, sjw, tseg1, tseg2; 1048 u32 reg_btp; 1049 1050 brp = bt->brp - 1; 1051 sjw = bt->sjw - 1; 1052 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 1053 tseg2 = bt->phase_seg2 - 1; 1054 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) | 1055 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT); 1056 m_can_write(cdev, M_CAN_NBTP, reg_btp); 1057 1058 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1059 reg_btp = 0; 1060 brp = dbt->brp - 1; 1061 sjw = dbt->sjw - 1; 1062 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; 1063 tseg2 = dbt->phase_seg2 - 1; 1064 1065 /* TDC is only needed for bitrates beyond 2.5 MBit/s. 1066 * This is mentioned in the "Bit Time Requirements for CAN FD" 1067 * paper presented at the International CAN Conference 2013 1068 */ 1069 if (dbt->bitrate > 2500000) { 1070 u32 tdco, ssp; 1071 1072 /* Use the same value of secondary sampling point 1073 * as the data sampling point 1074 */ 1075 ssp = dbt->sample_point; 1076 1077 /* Equation based on Bosch's M_CAN User Manual's 1078 * Transmitter Delay Compensation Section 1079 */ 1080 tdco = (cdev->can.clock.freq / 1000) * 1081 ssp / dbt->bitrate; 1082 1083 /* Max valid TDCO value is 127 */ 1084 if (tdco > 127) { 1085 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n", 1086 tdco); 1087 tdco = 127; 1088 } 1089 1090 reg_btp |= DBTP_TDC; 1091 m_can_write(cdev, M_CAN_TDCR, 1092 tdco << TDCR_TDCO_SHIFT); 1093 } 1094 1095 reg_btp |= (brp << DBTP_DBRP_SHIFT) | 1096 (sjw << DBTP_DSJW_SHIFT) | 1097 (tseg1 << DBTP_DTSEG1_SHIFT) | 1098 (tseg2 << DBTP_DTSEG2_SHIFT); 1099 1100 m_can_write(cdev, M_CAN_DBTP, reg_btp); 1101 } 1102 1103 return 0; 1104 } 1105 1106 /* Configure M_CAN chip: 1107 * - set rx buffer/fifo element size 1108 * - configure rx fifo 1109 * - accept non-matching frame into fifo 0 1110 * - configure tx buffer 1111 * - >= v3.1.x: TX FIFO is used 1112 * - configure mode 1113 * - setup bittiming 1114 */ 1115 static void m_can_chip_config(struct net_device *dev) 1116 { 1117 struct m_can_classdev *cdev = netdev_priv(dev); 1118 u32 cccr, test; 1119 1120 m_can_config_endisable(cdev, true); 1121 1122 /* RX Buffer/FIFO Element Size 64 bytes data field */ 1123 m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES); 1124 1125 /* Accept Non-matching Frames Into FIFO 0 */ 1126 m_can_write(cdev, M_CAN_GFC, 0x0); 1127 1128 if (cdev->version == 30) { 1129 /* only support one Tx Buffer currently */ 1130 m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) | 1131 cdev->mcfg[MRAM_TXB].off); 1132 } else { 1133 /* TX FIFO is used for newer IP Core versions */ 1134 m_can_write(cdev, M_CAN_TXBC, 1135 (cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) | 1136 (cdev->mcfg[MRAM_TXB].off)); 1137 } 1138 1139 /* support 64 bytes payload */ 1140 m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES); 1141 1142 /* TX Event FIFO */ 1143 if (cdev->version == 30) { 1144 m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) | 1145 cdev->mcfg[MRAM_TXE].off); 1146 } else { 1147 /* Full TX Event FIFO is used */ 1148 m_can_write(cdev, M_CAN_TXEFC, 1149 ((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT) 1150 & TXEFC_EFS_MASK) | 1151 cdev->mcfg[MRAM_TXE].off); 1152 } 1153 1154 /* rx fifo configuration, blocking mode, fifo size 1 */ 1155 m_can_write(cdev, M_CAN_RXF0C, 1156 (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) | 1157 cdev->mcfg[MRAM_RXF0].off); 1158 1159 m_can_write(cdev, M_CAN_RXF1C, 1160 (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) | 1161 cdev->mcfg[MRAM_RXF1].off); 1162 1163 cccr = m_can_read(cdev, M_CAN_CCCR); 1164 test = m_can_read(cdev, M_CAN_TEST); 1165 test &= ~TEST_LBCK; 1166 if (cdev->version == 30) { 1167 /* Version 3.0.x */ 1168 1169 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR | 1170 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | 1171 (CCCR_CME_MASK << CCCR_CME_SHIFT)); 1172 1173 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1174 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT; 1175 1176 } else { 1177 /* Version 3.1.x or 3.2.x */ 1178 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE | 1179 CCCR_NISO | CCCR_DAR); 1180 1181 /* Only 3.2.x has NISO Bit implemented */ 1182 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 1183 cccr |= CCCR_NISO; 1184 1185 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1186 cccr |= (CCCR_BRSE | CCCR_FDOE); 1187 } 1188 1189 /* Loopback Mode */ 1190 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1191 cccr |= CCCR_TEST | CCCR_MON; 1192 test |= TEST_LBCK; 1193 } 1194 1195 /* Enable Monitoring (all versions) */ 1196 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1197 cccr |= CCCR_MON; 1198 1199 /* Disable Auto Retransmission (all versions) */ 1200 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 1201 cccr |= CCCR_DAR; 1202 1203 /* Write config */ 1204 m_can_write(cdev, M_CAN_CCCR, cccr); 1205 m_can_write(cdev, M_CAN_TEST, test); 1206 1207 /* Enable interrupts */ 1208 m_can_write(cdev, M_CAN_IR, IR_ALL_INT); 1209 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1210 if (cdev->version == 30) 1211 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & 1212 ~(IR_ERR_LEC_30X)); 1213 else 1214 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & 1215 ~(IR_ERR_LEC_31X)); 1216 else 1217 m_can_write(cdev, M_CAN_IE, IR_ALL_INT); 1218 1219 /* route all interrupts to INT0 */ 1220 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); 1221 1222 /* set bittiming params */ 1223 m_can_set_bittiming(dev); 1224 1225 m_can_config_endisable(cdev, false); 1226 1227 if (cdev->ops->init) 1228 cdev->ops->init(cdev); 1229 } 1230 1231 static void m_can_start(struct net_device *dev) 1232 { 1233 struct m_can_classdev *cdev = netdev_priv(dev); 1234 1235 /* basic m_can configuration */ 1236 m_can_chip_config(dev); 1237 1238 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 1239 1240 m_can_enable_all_interrupts(cdev); 1241 } 1242 1243 static int m_can_set_mode(struct net_device *dev, enum can_mode mode) 1244 { 1245 switch (mode) { 1246 case CAN_MODE_START: 1247 m_can_clean(dev); 1248 m_can_start(dev); 1249 netif_wake_queue(dev); 1250 break; 1251 default: 1252 return -EOPNOTSUPP; 1253 } 1254 1255 return 0; 1256 } 1257 1258 /* Checks core release number of M_CAN 1259 * returns 0 if an unsupported device is detected 1260 * else it returns the release and step coded as: 1261 * return value = 10 * <release> + 1 * <step> 1262 */ 1263 static int m_can_check_core_release(struct m_can_classdev *cdev) 1264 { 1265 u32 crel_reg; 1266 u8 rel; 1267 u8 step; 1268 int res; 1269 1270 /* Read Core Release Version and split into version number 1271 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; 1272 */ 1273 crel_reg = m_can_read(cdev, M_CAN_CREL); 1274 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT); 1275 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT); 1276 1277 if (rel == 3) { 1278 /* M_CAN v3.x.y: create return value */ 1279 res = 30 + step; 1280 } else { 1281 /* Unsupported M_CAN version */ 1282 res = 0; 1283 } 1284 1285 return res; 1286 } 1287 1288 /* Selectable Non ISO support only in version 3.2.x 1289 * This function checks if the bit is writable. 1290 */ 1291 static bool m_can_niso_supported(struct m_can_classdev *cdev) 1292 { 1293 u32 cccr_reg, cccr_poll = 0; 1294 int niso_timeout = -ETIMEDOUT; 1295 int i; 1296 1297 m_can_config_endisable(cdev, true); 1298 cccr_reg = m_can_read(cdev, M_CAN_CCCR); 1299 cccr_reg |= CCCR_NISO; 1300 m_can_write(cdev, M_CAN_CCCR, cccr_reg); 1301 1302 for (i = 0; i <= 10; i++) { 1303 cccr_poll = m_can_read(cdev, M_CAN_CCCR); 1304 if (cccr_poll == cccr_reg) { 1305 niso_timeout = 0; 1306 break; 1307 } 1308 1309 usleep_range(1, 5); 1310 } 1311 1312 /* Clear NISO */ 1313 cccr_reg &= ~(CCCR_NISO); 1314 m_can_write(cdev, M_CAN_CCCR, cccr_reg); 1315 1316 m_can_config_endisable(cdev, false); 1317 1318 /* return false if time out (-ETIMEDOUT), else return true */ 1319 return !niso_timeout; 1320 } 1321 1322 static int m_can_dev_setup(struct m_can_classdev *cdev) 1323 { 1324 struct net_device *dev = cdev->net; 1325 int m_can_version; 1326 1327 m_can_version = m_can_check_core_release(cdev); 1328 /* return if unsupported version */ 1329 if (!m_can_version) { 1330 dev_err(cdev->dev, "Unsupported version number: %2d", 1331 m_can_version); 1332 return -EINVAL; 1333 } 1334 1335 if (!cdev->is_peripheral) 1336 netif_napi_add(dev, &cdev->napi, 1337 m_can_poll, M_CAN_NAPI_WEIGHT); 1338 1339 /* Shared properties of all M_CAN versions */ 1340 cdev->version = m_can_version; 1341 cdev->can.do_set_mode = m_can_set_mode; 1342 cdev->can.do_get_berr_counter = m_can_get_berr_counter; 1343 1344 /* Set M_CAN supported operations */ 1345 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1346 CAN_CTRLMODE_LISTENONLY | 1347 CAN_CTRLMODE_BERR_REPORTING | 1348 CAN_CTRLMODE_FD | 1349 CAN_CTRLMODE_ONE_SHOT; 1350 1351 /* Set properties depending on M_CAN version */ 1352 switch (cdev->version) { 1353 case 30: 1354 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ 1355 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1356 cdev->can.bittiming_const = cdev->bit_timing ? 1357 cdev->bit_timing : &m_can_bittiming_const_30X; 1358 1359 cdev->can.data_bittiming_const = cdev->data_timing ? 1360 cdev->data_timing : 1361 &m_can_data_bittiming_const_30X; 1362 break; 1363 case 31: 1364 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ 1365 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1366 cdev->can.bittiming_const = cdev->bit_timing ? 1367 cdev->bit_timing : &m_can_bittiming_const_31X; 1368 1369 cdev->can.data_bittiming_const = cdev->data_timing ? 1370 cdev->data_timing : 1371 &m_can_data_bittiming_const_31X; 1372 break; 1373 case 32: 1374 case 33: 1375 /* Support both MCAN version v3.2.x and v3.3.0 */ 1376 cdev->can.bittiming_const = cdev->bit_timing ? 1377 cdev->bit_timing : &m_can_bittiming_const_31X; 1378 1379 cdev->can.data_bittiming_const = cdev->data_timing ? 1380 cdev->data_timing : 1381 &m_can_data_bittiming_const_31X; 1382 1383 cdev->can.ctrlmode_supported |= 1384 (m_can_niso_supported(cdev) ? 1385 CAN_CTRLMODE_FD_NON_ISO : 0); 1386 break; 1387 default: 1388 dev_err(cdev->dev, "Unsupported version number: %2d", 1389 cdev->version); 1390 return -EINVAL; 1391 } 1392 1393 if (cdev->ops->init) 1394 cdev->ops->init(cdev); 1395 1396 return 0; 1397 } 1398 1399 static void m_can_stop(struct net_device *dev) 1400 { 1401 struct m_can_classdev *cdev = netdev_priv(dev); 1402 1403 /* disable all interrupts */ 1404 m_can_disable_all_interrupts(cdev); 1405 1406 /* Set init mode to disengage from the network */ 1407 m_can_config_endisable(cdev, true); 1408 1409 /* set the state as STOPPED */ 1410 cdev->can.state = CAN_STATE_STOPPED; 1411 } 1412 1413 static int m_can_close(struct net_device *dev) 1414 { 1415 struct m_can_classdev *cdev = netdev_priv(dev); 1416 1417 netif_stop_queue(dev); 1418 1419 if (!cdev->is_peripheral) 1420 napi_disable(&cdev->napi); 1421 1422 m_can_stop(dev); 1423 m_can_clk_stop(cdev); 1424 free_irq(dev->irq, dev); 1425 1426 if (cdev->is_peripheral) { 1427 cdev->tx_skb = NULL; 1428 destroy_workqueue(cdev->tx_wq); 1429 cdev->tx_wq = NULL; 1430 } 1431 1432 close_candev(dev); 1433 can_led_event(dev, CAN_LED_EVENT_STOP); 1434 1435 return 0; 1436 } 1437 1438 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx) 1439 { 1440 struct m_can_classdev *cdev = netdev_priv(dev); 1441 /*get wrap around for loopback skb index */ 1442 unsigned int wrap = cdev->can.echo_skb_max; 1443 int next_idx; 1444 1445 /* calculate next index */ 1446 next_idx = (++putidx >= wrap ? 0 : putidx); 1447 1448 /* check if occupied */ 1449 return !!cdev->can.echo_skb[next_idx]; 1450 } 1451 1452 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) 1453 { 1454 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data; 1455 struct net_device *dev = cdev->net; 1456 struct sk_buff *skb = cdev->tx_skb; 1457 u32 id, cccr, fdflags; 1458 int i; 1459 int putidx; 1460 1461 /* Generate ID field for TX buffer Element */ 1462 /* Common to all supported M_CAN versions */ 1463 if (cf->can_id & CAN_EFF_FLAG) { 1464 id = cf->can_id & CAN_EFF_MASK; 1465 id |= TX_BUF_XTD; 1466 } else { 1467 id = ((cf->can_id & CAN_SFF_MASK) << 18); 1468 } 1469 1470 if (cf->can_id & CAN_RTR_FLAG) 1471 id |= TX_BUF_RTR; 1472 1473 if (cdev->version == 30) { 1474 netif_stop_queue(dev); 1475 1476 /* message ram configuration */ 1477 m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, id); 1478 m_can_fifo_write(cdev, 0, M_CAN_FIFO_DLC, 1479 can_fd_len2dlc(cf->len) << 16); 1480 1481 for (i = 0; i < cf->len; i += 4) 1482 m_can_fifo_write(cdev, 0, 1483 M_CAN_FIFO_DATA(i / 4), 1484 *(u32 *)(cf->data + i)); 1485 1486 can_put_echo_skb(skb, dev, 0); 1487 1488 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1489 cccr = m_can_read(cdev, M_CAN_CCCR); 1490 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT); 1491 if (can_is_canfd_skb(skb)) { 1492 if (cf->flags & CANFD_BRS) 1493 cccr |= CCCR_CMR_CANFD_BRS << 1494 CCCR_CMR_SHIFT; 1495 else 1496 cccr |= CCCR_CMR_CANFD << 1497 CCCR_CMR_SHIFT; 1498 } else { 1499 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT; 1500 } 1501 m_can_write(cdev, M_CAN_CCCR, cccr); 1502 } 1503 m_can_write(cdev, M_CAN_TXBTIE, 0x1); 1504 m_can_write(cdev, M_CAN_TXBAR, 0x1); 1505 /* End of xmit function for version 3.0.x */ 1506 } else { 1507 /* Transmit routine for version >= v3.1.x */ 1508 1509 /* Check if FIFO full */ 1510 if (m_can_tx_fifo_full(cdev)) { 1511 /* This shouldn't happen */ 1512 netif_stop_queue(dev); 1513 netdev_warn(dev, 1514 "TX queue active although FIFO is full."); 1515 1516 if (cdev->is_peripheral) { 1517 kfree_skb(skb); 1518 dev->stats.tx_dropped++; 1519 return NETDEV_TX_OK; 1520 } else { 1521 return NETDEV_TX_BUSY; 1522 } 1523 } 1524 1525 /* get put index for frame */ 1526 putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK) 1527 >> TXFQS_TFQPI_SHIFT); 1528 /* Write ID Field to FIFO Element */ 1529 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id); 1530 1531 /* get CAN FD configuration of frame */ 1532 fdflags = 0; 1533 if (can_is_canfd_skb(skb)) { 1534 fdflags |= TX_BUF_FDF; 1535 if (cf->flags & CANFD_BRS) 1536 fdflags |= TX_BUF_BRS; 1537 } 1538 1539 /* Construct DLC Field. Also contains CAN-FD configuration 1540 * use put index of fifo as message marker 1541 * it is used in TX interrupt for 1542 * sending the correct echo frame 1543 */ 1544 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC, 1545 ((putidx << TX_BUF_MM_SHIFT) & 1546 TX_BUF_MM_MASK) | 1547 (can_fd_len2dlc(cf->len) << 16) | 1548 fdflags | TX_BUF_EFC); 1549 1550 for (i = 0; i < cf->len; i += 4) 1551 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA(i / 4), 1552 *(u32 *)(cf->data + i)); 1553 1554 /* Push loopback echo. 1555 * Will be looped back on TX interrupt based on message marker 1556 */ 1557 can_put_echo_skb(skb, dev, putidx); 1558 1559 /* Enable TX FIFO element to start transfer */ 1560 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx)); 1561 1562 /* stop network queue if fifo full */ 1563 if (m_can_tx_fifo_full(cdev) || 1564 m_can_next_echo_skb_occupied(dev, putidx)) 1565 netif_stop_queue(dev); 1566 } 1567 1568 return NETDEV_TX_OK; 1569 } 1570 1571 static void m_can_tx_work_queue(struct work_struct *ws) 1572 { 1573 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev, 1574 tx_work); 1575 1576 m_can_tx_handler(cdev); 1577 cdev->tx_skb = NULL; 1578 } 1579 1580 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, 1581 struct net_device *dev) 1582 { 1583 struct m_can_classdev *cdev = netdev_priv(dev); 1584 1585 if (can_dropped_invalid_skb(dev, skb)) 1586 return NETDEV_TX_OK; 1587 1588 if (cdev->is_peripheral) { 1589 if (cdev->tx_skb) { 1590 netdev_err(dev, "hard_xmit called while tx busy\n"); 1591 return NETDEV_TX_BUSY; 1592 } 1593 1594 if (cdev->can.state == CAN_STATE_BUS_OFF) { 1595 m_can_clean(dev); 1596 } else { 1597 /* Need to stop the queue to avoid numerous requests 1598 * from being sent. Suggested improvement is to create 1599 * a queueing mechanism that will queue the skbs and 1600 * process them in order. 1601 */ 1602 cdev->tx_skb = skb; 1603 netif_stop_queue(cdev->net); 1604 queue_work(cdev->tx_wq, &cdev->tx_work); 1605 } 1606 } else { 1607 cdev->tx_skb = skb; 1608 return m_can_tx_handler(cdev); 1609 } 1610 1611 return NETDEV_TX_OK; 1612 } 1613 1614 static int m_can_open(struct net_device *dev) 1615 { 1616 struct m_can_classdev *cdev = netdev_priv(dev); 1617 int err; 1618 1619 err = m_can_clk_start(cdev); 1620 if (err) 1621 return err; 1622 1623 /* open the can device */ 1624 err = open_candev(dev); 1625 if (err) { 1626 netdev_err(dev, "failed to open can device\n"); 1627 goto exit_disable_clks; 1628 } 1629 1630 /* register interrupt handler */ 1631 if (cdev->is_peripheral) { 1632 cdev->tx_skb = NULL; 1633 cdev->tx_wq = alloc_workqueue("mcan_wq", 1634 WQ_FREEZABLE | WQ_MEM_RECLAIM, 0); 1635 if (!cdev->tx_wq) { 1636 err = -ENOMEM; 1637 goto out_wq_fail; 1638 } 1639 1640 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue); 1641 1642 err = request_threaded_irq(dev->irq, NULL, m_can_isr, 1643 IRQF_ONESHOT, 1644 dev->name, dev); 1645 } else { 1646 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, 1647 dev); 1648 } 1649 1650 if (err < 0) { 1651 netdev_err(dev, "failed to request interrupt\n"); 1652 goto exit_irq_fail; 1653 } 1654 1655 /* start the m_can controller */ 1656 m_can_start(dev); 1657 1658 can_led_event(dev, CAN_LED_EVENT_OPEN); 1659 1660 if (!cdev->is_peripheral) 1661 napi_enable(&cdev->napi); 1662 1663 netif_start_queue(dev); 1664 1665 return 0; 1666 1667 exit_irq_fail: 1668 if (cdev->is_peripheral) 1669 destroy_workqueue(cdev->tx_wq); 1670 out_wq_fail: 1671 close_candev(dev); 1672 exit_disable_clks: 1673 m_can_clk_stop(cdev); 1674 return err; 1675 } 1676 1677 static const struct net_device_ops m_can_netdev_ops = { 1678 .ndo_open = m_can_open, 1679 .ndo_stop = m_can_close, 1680 .ndo_start_xmit = m_can_start_xmit, 1681 .ndo_change_mtu = can_change_mtu, 1682 }; 1683 1684 static int register_m_can_dev(struct net_device *dev) 1685 { 1686 dev->flags |= IFF_ECHO; /* we support local echo */ 1687 dev->netdev_ops = &m_can_netdev_ops; 1688 1689 return register_candev(dev); 1690 } 1691 1692 static void m_can_of_parse_mram(struct m_can_classdev *cdev, 1693 const u32 *mram_config_vals) 1694 { 1695 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; 1696 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; 1697 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + 1698 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; 1699 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; 1700 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + 1701 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; 1702 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & 1703 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1704 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + 1705 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; 1706 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & 1707 (RXFC_FS_MASK >> RXFC_FS_SHIFT); 1708 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + 1709 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; 1710 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; 1711 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + 1712 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; 1713 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; 1714 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + 1715 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; 1716 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & 1717 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT); 1718 1719 dev_dbg(cdev->dev, 1720 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", 1721 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num, 1722 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num, 1723 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num, 1724 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num, 1725 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num, 1726 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num, 1727 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num); 1728 } 1729 1730 void m_can_init_ram(struct m_can_classdev *cdev) 1731 { 1732 int end, i, start; 1733 1734 /* initialize the entire Message RAM in use to avoid possible 1735 * ECC/parity checksum errors when reading an uninitialized buffer 1736 */ 1737 start = cdev->mcfg[MRAM_SIDF].off; 1738 end = cdev->mcfg[MRAM_TXB].off + 1739 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 1740 1741 for (i = start; i < end; i += 4) 1742 m_can_fifo_write_no_off(cdev, i, 0x0); 1743 } 1744 EXPORT_SYMBOL_GPL(m_can_init_ram); 1745 1746 int m_can_class_get_clocks(struct m_can_classdev *cdev) 1747 { 1748 int ret = 0; 1749 1750 cdev->hclk = devm_clk_get(cdev->dev, "hclk"); 1751 cdev->cclk = devm_clk_get(cdev->dev, "cclk"); 1752 1753 if (IS_ERR(cdev->cclk)) { 1754 dev_err(cdev->dev, "no clock found\n"); 1755 ret = -ENODEV; 1756 } 1757 1758 return ret; 1759 } 1760 EXPORT_SYMBOL_GPL(m_can_class_get_clocks); 1761 1762 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, 1763 int sizeof_priv) 1764 { 1765 struct m_can_classdev *class_dev = NULL; 1766 u32 mram_config_vals[MRAM_CFG_LEN]; 1767 struct net_device *net_dev; 1768 u32 tx_fifo_size; 1769 int ret; 1770 1771 ret = fwnode_property_read_u32_array(dev_fwnode(dev), 1772 "bosch,mram-cfg", 1773 mram_config_vals, 1774 sizeof(mram_config_vals) / 4); 1775 if (ret) { 1776 dev_err(dev, "Could not get Message RAM configuration."); 1777 goto out; 1778 } 1779 1780 /* Get TX FIFO size 1781 * Defines the total amount of echo buffers for loopback 1782 */ 1783 tx_fifo_size = mram_config_vals[7]; 1784 1785 /* allocate the m_can device */ 1786 net_dev = alloc_candev(sizeof_priv, tx_fifo_size); 1787 if (!net_dev) { 1788 dev_err(dev, "Failed to allocate CAN device"); 1789 goto out; 1790 } 1791 1792 class_dev = netdev_priv(net_dev); 1793 if (!class_dev) { 1794 dev_err(dev, "Failed to init netdev cdevate"); 1795 goto out; 1796 } 1797 1798 class_dev->net = net_dev; 1799 class_dev->dev = dev; 1800 SET_NETDEV_DEV(net_dev, dev); 1801 1802 m_can_of_parse_mram(class_dev, mram_config_vals); 1803 out: 1804 return class_dev; 1805 } 1806 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev); 1807 1808 void m_can_class_free_dev(struct net_device *net) 1809 { 1810 free_candev(net); 1811 } 1812 EXPORT_SYMBOL_GPL(m_can_class_free_dev); 1813 1814 int m_can_class_register(struct m_can_classdev *cdev) 1815 { 1816 int ret; 1817 1818 if (cdev->pm_clock_support) { 1819 ret = m_can_clk_start(cdev); 1820 if (ret) 1821 return ret; 1822 } 1823 1824 ret = m_can_dev_setup(cdev); 1825 if (ret) 1826 goto clk_disable; 1827 1828 ret = register_m_can_dev(cdev->net); 1829 if (ret) { 1830 dev_err(cdev->dev, "registering %s failed (err=%d)\n", 1831 cdev->net->name, ret); 1832 goto clk_disable; 1833 } 1834 1835 devm_can_led_init(cdev->net); 1836 1837 of_can_transceiver(cdev->net); 1838 1839 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n", 1840 KBUILD_MODNAME, cdev->net->irq, cdev->version); 1841 1842 /* Probe finished 1843 * Stop clocks. They will be reactivated once the M_CAN device is opened 1844 */ 1845 clk_disable: 1846 m_can_clk_stop(cdev); 1847 1848 return ret; 1849 } 1850 EXPORT_SYMBOL_GPL(m_can_class_register); 1851 1852 void m_can_class_unregister(struct m_can_classdev *cdev) 1853 { 1854 unregister_candev(cdev->net); 1855 } 1856 EXPORT_SYMBOL_GPL(m_can_class_unregister); 1857 1858 int m_can_class_suspend(struct device *dev) 1859 { 1860 struct m_can_classdev *cdev = dev_get_drvdata(dev); 1861 struct net_device *ndev = cdev->net; 1862 1863 if (netif_running(ndev)) { 1864 netif_stop_queue(ndev); 1865 netif_device_detach(ndev); 1866 m_can_stop(ndev); 1867 m_can_clk_stop(cdev); 1868 } 1869 1870 pinctrl_pm_select_sleep_state(dev); 1871 1872 cdev->can.state = CAN_STATE_SLEEPING; 1873 1874 return 0; 1875 } 1876 EXPORT_SYMBOL_GPL(m_can_class_suspend); 1877 1878 int m_can_class_resume(struct device *dev) 1879 { 1880 struct m_can_classdev *cdev = dev_get_drvdata(dev); 1881 struct net_device *ndev = cdev->net; 1882 1883 pinctrl_pm_select_default_state(dev); 1884 1885 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 1886 1887 if (netif_running(ndev)) { 1888 int ret; 1889 1890 ret = m_can_clk_start(cdev); 1891 if (ret) 1892 return ret; 1893 1894 m_can_init_ram(cdev); 1895 m_can_start(ndev); 1896 netif_device_attach(ndev); 1897 netif_start_queue(ndev); 1898 } 1899 1900 return 0; 1901 } 1902 EXPORT_SYMBOL_GPL(m_can_class_resume); 1903 1904 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); 1905 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 1906 MODULE_LICENSE("GPL v2"); 1907 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); 1908