1 // SPDX-License-Identifier: GPL-2.0 2 // CAN bus driver for Bosch M_CAN controller 3 // Copyright (C) 2014 Freescale Semiconductor, Inc. 4 // Dong Aisheng <b29396@freescale.com> 5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/ 6 7 /* Bosch M_CAN user manual can be obtained from: 8 * https://github.com/linux-can/can-doc/tree/master/m_can 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/can/dev.h> 13 #include <linux/ethtool.h> 14 #include <linux/hrtimer.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/netdevice.h> 21 #include <linux/of.h> 22 #include <linux/phy/phy.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 27 #include "m_can.h" 28 29 /* registers definition */ 30 enum m_can_reg { 31 M_CAN_CREL = 0x0, 32 M_CAN_ENDN = 0x4, 33 M_CAN_CUST = 0x8, 34 M_CAN_DBTP = 0xc, 35 M_CAN_TEST = 0x10, 36 M_CAN_RWD = 0x14, 37 M_CAN_CCCR = 0x18, 38 M_CAN_NBTP = 0x1c, 39 M_CAN_TSCC = 0x20, 40 M_CAN_TSCV = 0x24, 41 M_CAN_TOCC = 0x28, 42 M_CAN_TOCV = 0x2c, 43 M_CAN_ECR = 0x40, 44 M_CAN_PSR = 0x44, 45 /* TDCR Register only available for version >=3.1.x */ 46 M_CAN_TDCR = 0x48, 47 M_CAN_IR = 0x50, 48 M_CAN_IE = 0x54, 49 M_CAN_ILS = 0x58, 50 M_CAN_ILE = 0x5c, 51 M_CAN_GFC = 0x80, 52 M_CAN_SIDFC = 0x84, 53 M_CAN_XIDFC = 0x88, 54 M_CAN_XIDAM = 0x90, 55 M_CAN_HPMS = 0x94, 56 M_CAN_NDAT1 = 0x98, 57 M_CAN_NDAT2 = 0x9c, 58 M_CAN_RXF0C = 0xa0, 59 M_CAN_RXF0S = 0xa4, 60 M_CAN_RXF0A = 0xa8, 61 M_CAN_RXBC = 0xac, 62 M_CAN_RXF1C = 0xb0, 63 M_CAN_RXF1S = 0xb4, 64 M_CAN_RXF1A = 0xb8, 65 M_CAN_RXESC = 0xbc, 66 M_CAN_TXBC = 0xc0, 67 M_CAN_TXFQS = 0xc4, 68 M_CAN_TXESC = 0xc8, 69 M_CAN_TXBRP = 0xcc, 70 M_CAN_TXBAR = 0xd0, 71 M_CAN_TXBCR = 0xd4, 72 M_CAN_TXBTO = 0xd8, 73 M_CAN_TXBCF = 0xdc, 74 M_CAN_TXBTIE = 0xe0, 75 M_CAN_TXBCIE = 0xe4, 76 M_CAN_TXEFC = 0xf0, 77 M_CAN_TXEFS = 0xf4, 78 M_CAN_TXEFA = 0xf8, 79 }; 80 81 /* message ram configuration data length */ 82 #define MRAM_CFG_LEN 8 83 84 /* Core Release Register (CREL) */ 85 #define CREL_REL_MASK GENMASK(31, 28) 86 #define CREL_STEP_MASK GENMASK(27, 24) 87 #define CREL_SUBSTEP_MASK GENMASK(23, 20) 88 89 /* Data Bit Timing & Prescaler Register (DBTP) */ 90 #define DBTP_TDC BIT(23) 91 #define DBTP_DBRP_MASK GENMASK(20, 16) 92 #define DBTP_DTSEG1_MASK GENMASK(12, 8) 93 #define DBTP_DTSEG2_MASK GENMASK(7, 4) 94 #define DBTP_DSJW_MASK GENMASK(3, 0) 95 96 /* Transmitter Delay Compensation Register (TDCR) */ 97 #define TDCR_TDCO_MASK GENMASK(14, 8) 98 #define TDCR_TDCF_MASK GENMASK(6, 0) 99 100 /* Test Register (TEST) */ 101 #define TEST_LBCK BIT(4) 102 103 /* CC Control Register (CCCR) */ 104 #define CCCR_TXP BIT(14) 105 #define CCCR_TEST BIT(7) 106 #define CCCR_DAR BIT(6) 107 #define CCCR_MON BIT(5) 108 #define CCCR_CSR BIT(4) 109 #define CCCR_CSA BIT(3) 110 #define CCCR_ASM BIT(2) 111 #define CCCR_CCE BIT(1) 112 #define CCCR_INIT BIT(0) 113 /* for version 3.0.x */ 114 #define CCCR_CMR_MASK GENMASK(11, 10) 115 #define CCCR_CMR_CANFD 0x1 116 #define CCCR_CMR_CANFD_BRS 0x2 117 #define CCCR_CMR_CAN 0x3 118 #define CCCR_CME_MASK GENMASK(9, 8) 119 #define CCCR_CME_CAN 0 120 #define CCCR_CME_CANFD 0x1 121 #define CCCR_CME_CANFD_BRS 0x2 122 /* for version >=3.1.x */ 123 #define CCCR_EFBI BIT(13) 124 #define CCCR_PXHD BIT(12) 125 #define CCCR_BRSE BIT(9) 126 #define CCCR_FDOE BIT(8) 127 /* for version >=3.2.x */ 128 #define CCCR_NISO BIT(15) 129 /* for version >=3.3.x */ 130 #define CCCR_WMM BIT(11) 131 #define CCCR_UTSU BIT(10) 132 133 /* Nominal Bit Timing & Prescaler Register (NBTP) */ 134 #define NBTP_NSJW_MASK GENMASK(31, 25) 135 #define NBTP_NBRP_MASK GENMASK(24, 16) 136 #define NBTP_NTSEG1_MASK GENMASK(15, 8) 137 #define NBTP_NTSEG2_MASK GENMASK(6, 0) 138 139 /* Timestamp Counter Configuration Register (TSCC) */ 140 #define TSCC_TCP_MASK GENMASK(19, 16) 141 #define TSCC_TSS_MASK GENMASK(1, 0) 142 #define TSCC_TSS_DISABLE 0x0 143 #define TSCC_TSS_INTERNAL 0x1 144 #define TSCC_TSS_EXTERNAL 0x2 145 146 /* Timestamp Counter Value Register (TSCV) */ 147 #define TSCV_TSC_MASK GENMASK(15, 0) 148 149 /* Error Counter Register (ECR) */ 150 #define ECR_RP BIT(15) 151 #define ECR_REC_MASK GENMASK(14, 8) 152 #define ECR_TEC_MASK GENMASK(7, 0) 153 154 /* Protocol Status Register (PSR) */ 155 #define PSR_BO BIT(7) 156 #define PSR_EW BIT(6) 157 #define PSR_EP BIT(5) 158 #define PSR_LEC_MASK GENMASK(2, 0) 159 #define PSR_DLEC_MASK GENMASK(10, 8) 160 161 /* Interrupt Register (IR) */ 162 #define IR_ALL_INT 0xffffffff 163 164 /* Renamed bits for versions > 3.1.x */ 165 #define IR_ARA BIT(29) 166 #define IR_PED BIT(28) 167 #define IR_PEA BIT(27) 168 169 /* Bits for version 3.0.x */ 170 #define IR_STE BIT(31) 171 #define IR_FOE BIT(30) 172 #define IR_ACKE BIT(29) 173 #define IR_BE BIT(28) 174 #define IR_CRCE BIT(27) 175 #define IR_WDI BIT(26) 176 #define IR_BO BIT(25) 177 #define IR_EW BIT(24) 178 #define IR_EP BIT(23) 179 #define IR_ELO BIT(22) 180 #define IR_BEU BIT(21) 181 #define IR_BEC BIT(20) 182 #define IR_DRX BIT(19) 183 #define IR_TOO BIT(18) 184 #define IR_MRAF BIT(17) 185 #define IR_TSW BIT(16) 186 #define IR_TEFL BIT(15) 187 #define IR_TEFF BIT(14) 188 #define IR_TEFW BIT(13) 189 #define IR_TEFN BIT(12) 190 #define IR_TFE BIT(11) 191 #define IR_TCF BIT(10) 192 #define IR_TC BIT(9) 193 #define IR_HPM BIT(8) 194 #define IR_RF1L BIT(7) 195 #define IR_RF1F BIT(6) 196 #define IR_RF1W BIT(5) 197 #define IR_RF1N BIT(4) 198 #define IR_RF0L BIT(3) 199 #define IR_RF0F BIT(2) 200 #define IR_RF0W BIT(1) 201 #define IR_RF0N BIT(0) 202 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) 203 204 /* Interrupts for version 3.0.x */ 205 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) 206 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_BEU | IR_BEC | \ 207 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \ 208 IR_RF0L) 209 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X) 210 211 /* Interrupts for version >= 3.1.x */ 212 #define IR_ERR_LEC_31X (IR_PED | IR_PEA) 213 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_BEU | IR_BEC | \ 214 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \ 215 IR_RF0L) 216 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X) 217 218 /* Interrupt Line Select (ILS) */ 219 #define ILS_ALL_INT0 0x0 220 #define ILS_ALL_INT1 0xFFFFFFFF 221 222 /* Interrupt Line Enable (ILE) */ 223 #define ILE_EINT1 BIT(1) 224 #define ILE_EINT0 BIT(0) 225 226 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ 227 #define RXFC_FWM_MASK GENMASK(30, 24) 228 #define RXFC_FS_MASK GENMASK(22, 16) 229 230 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ 231 #define RXFS_RFL BIT(25) 232 #define RXFS_FF BIT(24) 233 #define RXFS_FPI_MASK GENMASK(21, 16) 234 #define RXFS_FGI_MASK GENMASK(13, 8) 235 #define RXFS_FFL_MASK GENMASK(6, 0) 236 237 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ 238 #define RXESC_RBDS_MASK GENMASK(10, 8) 239 #define RXESC_F1DS_MASK GENMASK(6, 4) 240 #define RXESC_F0DS_MASK GENMASK(2, 0) 241 #define RXESC_64B 0x7 242 243 /* Tx Buffer Configuration (TXBC) */ 244 #define TXBC_TFQS_MASK GENMASK(29, 24) 245 #define TXBC_NDTB_MASK GENMASK(21, 16) 246 247 /* Tx FIFO/Queue Status (TXFQS) */ 248 #define TXFQS_TFQF BIT(21) 249 #define TXFQS_TFQPI_MASK GENMASK(20, 16) 250 #define TXFQS_TFGI_MASK GENMASK(12, 8) 251 #define TXFQS_TFFL_MASK GENMASK(5, 0) 252 253 /* Tx Buffer Element Size Configuration (TXESC) */ 254 #define TXESC_TBDS_MASK GENMASK(2, 0) 255 #define TXESC_TBDS_64B 0x7 256 257 /* Tx Event FIFO Configuration (TXEFC) */ 258 #define TXEFC_EFS_MASK GENMASK(21, 16) 259 260 /* Tx Event FIFO Status (TXEFS) */ 261 #define TXEFS_TEFL BIT(25) 262 #define TXEFS_EFF BIT(24) 263 #define TXEFS_EFGI_MASK GENMASK(12, 8) 264 #define TXEFS_EFFL_MASK GENMASK(5, 0) 265 266 /* Tx Event FIFO Acknowledge (TXEFA) */ 267 #define TXEFA_EFAI_MASK GENMASK(4, 0) 268 269 /* Message RAM Configuration (in bytes) */ 270 #define SIDF_ELEMENT_SIZE 4 271 #define XIDF_ELEMENT_SIZE 8 272 #define RXF0_ELEMENT_SIZE 72 273 #define RXF1_ELEMENT_SIZE 72 274 #define RXB_ELEMENT_SIZE 72 275 #define TXE_ELEMENT_SIZE 8 276 #define TXB_ELEMENT_SIZE 72 277 278 /* Message RAM Elements */ 279 #define M_CAN_FIFO_ID 0x0 280 #define M_CAN_FIFO_DLC 0x4 281 #define M_CAN_FIFO_DATA 0x8 282 283 /* Rx Buffer Element */ 284 /* R0 */ 285 #define RX_BUF_ESI BIT(31) 286 #define RX_BUF_XTD BIT(30) 287 #define RX_BUF_RTR BIT(29) 288 /* R1 */ 289 #define RX_BUF_ANMF BIT(31) 290 #define RX_BUF_FDF BIT(21) 291 #define RX_BUF_BRS BIT(20) 292 #define RX_BUF_RXTS_MASK GENMASK(15, 0) 293 294 /* Tx Buffer Element */ 295 /* T0 */ 296 #define TX_BUF_ESI BIT(31) 297 #define TX_BUF_XTD BIT(30) 298 #define TX_BUF_RTR BIT(29) 299 /* T1 */ 300 #define TX_BUF_EFC BIT(23) 301 #define TX_BUF_FDF BIT(21) 302 #define TX_BUF_BRS BIT(20) 303 #define TX_BUF_MM_MASK GENMASK(31, 24) 304 #define TX_BUF_DLC_MASK GENMASK(19, 16) 305 306 /* Tx event FIFO Element */ 307 /* E1 */ 308 #define TX_EVENT_MM_MASK GENMASK(31, 24) 309 #define TX_EVENT_TXTS_MASK GENMASK(15, 0) 310 311 /* Hrtimer polling interval */ 312 #define HRTIMER_POLL_INTERVAL_MS 1 313 314 /* The ID and DLC registers are adjacent in M_CAN FIFO memory, 315 * and we can save a (potentially slow) bus round trip by combining 316 * reads and writes to them. 317 */ 318 struct id_and_dlc { 319 u32 id; 320 u32 dlc; 321 }; 322 323 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) 324 { 325 return cdev->ops->read_reg(cdev, reg); 326 } 327 328 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, 329 u32 val) 330 { 331 cdev->ops->write_reg(cdev, reg, val); 332 } 333 334 static int 335 m_can_fifo_read(struct m_can_classdev *cdev, 336 u32 fgi, unsigned int offset, void *val, size_t val_count) 337 { 338 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + 339 offset; 340 341 if (val_count == 0) 342 return 0; 343 344 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count); 345 } 346 347 static int 348 m_can_fifo_write(struct m_can_classdev *cdev, 349 u32 fpi, unsigned int offset, const void *val, size_t val_count) 350 { 351 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + 352 offset; 353 354 if (val_count == 0) 355 return 0; 356 357 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count); 358 } 359 360 static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev, 361 u32 fpi, u32 val) 362 { 363 return cdev->ops->write_fifo(cdev, fpi, &val, 1); 364 } 365 366 static int 367 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val) 368 { 369 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + 370 offset; 371 372 return cdev->ops->read_fifo(cdev, addr_offset, val, 1); 373 } 374 375 static inline bool _m_can_tx_fifo_full(u32 txfqs) 376 { 377 return !!(txfqs & TXFQS_TFQF); 378 } 379 380 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev) 381 { 382 return _m_can_tx_fifo_full(m_can_read(cdev, M_CAN_TXFQS)); 383 } 384 385 static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable) 386 { 387 u32 cccr = m_can_read(cdev, M_CAN_CCCR); 388 u32 timeout = 10; 389 u32 val = 0; 390 391 /* Clear the Clock stop request if it was set */ 392 if (cccr & CCCR_CSR) 393 cccr &= ~CCCR_CSR; 394 395 if (enable) { 396 /* enable m_can configuration */ 397 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT); 398 udelay(5); 399 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ 400 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); 401 } else { 402 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); 403 } 404 405 /* there's a delay for module initialization */ 406 if (enable) 407 val = CCCR_INIT | CCCR_CCE; 408 409 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { 410 if (timeout == 0) { 411 netdev_warn(cdev->net, "Failed to init module\n"); 412 return; 413 } 414 timeout--; 415 udelay(1); 416 } 417 } 418 419 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev) 420 { 421 if (!cdev->net->irq) { 422 dev_dbg(cdev->dev, "Start hrtimer\n"); 423 hrtimer_start(&cdev->hrtimer, 424 ms_to_ktime(HRTIMER_POLL_INTERVAL_MS), 425 HRTIMER_MODE_REL_PINNED); 426 } 427 428 /* Only interrupt line 0 is used in this driver */ 429 m_can_write(cdev, M_CAN_ILE, ILE_EINT0); 430 } 431 432 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev) 433 { 434 m_can_write(cdev, M_CAN_ILE, 0x0); 435 436 if (!cdev->net->irq) { 437 dev_dbg(cdev->dev, "Stop hrtimer\n"); 438 hrtimer_cancel(&cdev->hrtimer); 439 } 440 } 441 442 /* Retrieve internal timestamp counter from TSCV.TSC, and shift it to 32-bit 443 * width. 444 */ 445 static u32 m_can_get_timestamp(struct m_can_classdev *cdev) 446 { 447 u32 tscv; 448 u32 tsc; 449 450 tscv = m_can_read(cdev, M_CAN_TSCV); 451 tsc = FIELD_GET(TSCV_TSC_MASK, tscv); 452 453 return (tsc << 16); 454 } 455 456 static void m_can_clean(struct net_device *net) 457 { 458 struct m_can_classdev *cdev = netdev_priv(net); 459 460 if (cdev->tx_skb) { 461 int putidx = 0; 462 463 net->stats.tx_errors++; 464 if (cdev->version > 30) 465 putidx = FIELD_GET(TXFQS_TFQPI_MASK, 466 m_can_read(cdev, M_CAN_TXFQS)); 467 468 can_free_echo_skb(cdev->net, putidx, NULL); 469 cdev->tx_skb = NULL; 470 } 471 } 472 473 /* For peripherals, pass skb to rx-offload, which will push skb from 474 * napi. For non-peripherals, RX is done in napi already, so push 475 * directly. timestamp is used to ensure good skb ordering in 476 * rx-offload and is ignored for non-peripherals. 477 */ 478 static void m_can_receive_skb(struct m_can_classdev *cdev, 479 struct sk_buff *skb, 480 u32 timestamp) 481 { 482 if (cdev->is_peripheral) { 483 struct net_device_stats *stats = &cdev->net->stats; 484 int err; 485 486 err = can_rx_offload_queue_timestamp(&cdev->offload, skb, 487 timestamp); 488 if (err) 489 stats->rx_fifo_errors++; 490 } else { 491 netif_receive_skb(skb); 492 } 493 } 494 495 static int m_can_read_fifo(struct net_device *dev, u32 fgi) 496 { 497 struct net_device_stats *stats = &dev->stats; 498 struct m_can_classdev *cdev = netdev_priv(dev); 499 struct canfd_frame *cf; 500 struct sk_buff *skb; 501 struct id_and_dlc fifo_header; 502 u32 timestamp = 0; 503 int err; 504 505 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &fifo_header, 2); 506 if (err) 507 goto out_fail; 508 509 if (fifo_header.dlc & RX_BUF_FDF) 510 skb = alloc_canfd_skb(dev, &cf); 511 else 512 skb = alloc_can_skb(dev, (struct can_frame **)&cf); 513 if (!skb) { 514 stats->rx_dropped++; 515 return 0; 516 } 517 518 if (fifo_header.dlc & RX_BUF_FDF) 519 cf->len = can_fd_dlc2len((fifo_header.dlc >> 16) & 0x0F); 520 else 521 cf->len = can_cc_dlc2len((fifo_header.dlc >> 16) & 0x0F); 522 523 if (fifo_header.id & RX_BUF_XTD) 524 cf->can_id = (fifo_header.id & CAN_EFF_MASK) | CAN_EFF_FLAG; 525 else 526 cf->can_id = (fifo_header.id >> 18) & CAN_SFF_MASK; 527 528 if (fifo_header.id & RX_BUF_ESI) { 529 cf->flags |= CANFD_ESI; 530 netdev_dbg(dev, "ESI Error\n"); 531 } 532 533 if (!(fifo_header.dlc & RX_BUF_FDF) && (fifo_header.id & RX_BUF_RTR)) { 534 cf->can_id |= CAN_RTR_FLAG; 535 } else { 536 if (fifo_header.dlc & RX_BUF_BRS) 537 cf->flags |= CANFD_BRS; 538 539 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA, 540 cf->data, DIV_ROUND_UP(cf->len, 4)); 541 if (err) 542 goto out_free_skb; 543 544 stats->rx_bytes += cf->len; 545 } 546 stats->rx_packets++; 547 548 timestamp = FIELD_GET(RX_BUF_RXTS_MASK, fifo_header.dlc) << 16; 549 550 m_can_receive_skb(cdev, skb, timestamp); 551 552 return 0; 553 554 out_free_skb: 555 kfree_skb(skb); 556 out_fail: 557 netdev_err(dev, "FIFO read returned %d\n", err); 558 return err; 559 } 560 561 static int m_can_do_rx_poll(struct net_device *dev, int quota) 562 { 563 struct m_can_classdev *cdev = netdev_priv(dev); 564 u32 pkts = 0; 565 u32 rxfs; 566 u32 rx_count; 567 u32 fgi; 568 int ack_fgi = -1; 569 int i; 570 int err = 0; 571 572 rxfs = m_can_read(cdev, M_CAN_RXF0S); 573 if (!(rxfs & RXFS_FFL_MASK)) { 574 netdev_dbg(dev, "no messages in fifo0\n"); 575 return 0; 576 } 577 578 rx_count = FIELD_GET(RXFS_FFL_MASK, rxfs); 579 fgi = FIELD_GET(RXFS_FGI_MASK, rxfs); 580 581 for (i = 0; i < rx_count && quota > 0; ++i) { 582 err = m_can_read_fifo(dev, fgi); 583 if (err) 584 break; 585 586 quota--; 587 pkts++; 588 ack_fgi = fgi; 589 fgi = (++fgi >= cdev->mcfg[MRAM_RXF0].num ? 0 : fgi); 590 } 591 592 if (ack_fgi != -1) 593 m_can_write(cdev, M_CAN_RXF0A, ack_fgi); 594 595 if (err) 596 return err; 597 598 return pkts; 599 } 600 601 static int m_can_handle_lost_msg(struct net_device *dev) 602 { 603 struct m_can_classdev *cdev = netdev_priv(dev); 604 struct net_device_stats *stats = &dev->stats; 605 struct sk_buff *skb; 606 struct can_frame *frame; 607 u32 timestamp = 0; 608 609 netdev_err(dev, "msg lost in rxf0\n"); 610 611 stats->rx_errors++; 612 stats->rx_over_errors++; 613 614 skb = alloc_can_err_skb(dev, &frame); 615 if (unlikely(!skb)) 616 return 0; 617 618 frame->can_id |= CAN_ERR_CRTL; 619 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 620 621 if (cdev->is_peripheral) 622 timestamp = m_can_get_timestamp(cdev); 623 624 m_can_receive_skb(cdev, skb, timestamp); 625 626 return 1; 627 } 628 629 static int m_can_handle_lec_err(struct net_device *dev, 630 enum m_can_lec_type lec_type) 631 { 632 struct m_can_classdev *cdev = netdev_priv(dev); 633 struct net_device_stats *stats = &dev->stats; 634 struct can_frame *cf; 635 struct sk_buff *skb; 636 u32 timestamp = 0; 637 638 cdev->can.can_stats.bus_error++; 639 stats->rx_errors++; 640 641 /* propagate the error condition to the CAN stack */ 642 skb = alloc_can_err_skb(dev, &cf); 643 if (unlikely(!skb)) 644 return 0; 645 646 /* check for 'last error code' which tells us the 647 * type of the last error to occur on the CAN bus 648 */ 649 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 650 651 switch (lec_type) { 652 case LEC_STUFF_ERROR: 653 netdev_dbg(dev, "stuff error\n"); 654 cf->data[2] |= CAN_ERR_PROT_STUFF; 655 break; 656 case LEC_FORM_ERROR: 657 netdev_dbg(dev, "form error\n"); 658 cf->data[2] |= CAN_ERR_PROT_FORM; 659 break; 660 case LEC_ACK_ERROR: 661 netdev_dbg(dev, "ack error\n"); 662 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 663 break; 664 case LEC_BIT1_ERROR: 665 netdev_dbg(dev, "bit1 error\n"); 666 cf->data[2] |= CAN_ERR_PROT_BIT1; 667 break; 668 case LEC_BIT0_ERROR: 669 netdev_dbg(dev, "bit0 error\n"); 670 cf->data[2] |= CAN_ERR_PROT_BIT0; 671 break; 672 case LEC_CRC_ERROR: 673 netdev_dbg(dev, "CRC error\n"); 674 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 675 break; 676 default: 677 break; 678 } 679 680 if (cdev->is_peripheral) 681 timestamp = m_can_get_timestamp(cdev); 682 683 m_can_receive_skb(cdev, skb, timestamp); 684 685 return 1; 686 } 687 688 static int __m_can_get_berr_counter(const struct net_device *dev, 689 struct can_berr_counter *bec) 690 { 691 struct m_can_classdev *cdev = netdev_priv(dev); 692 unsigned int ecr; 693 694 ecr = m_can_read(cdev, M_CAN_ECR); 695 bec->rxerr = FIELD_GET(ECR_REC_MASK, ecr); 696 bec->txerr = FIELD_GET(ECR_TEC_MASK, ecr); 697 698 return 0; 699 } 700 701 static int m_can_clk_start(struct m_can_classdev *cdev) 702 { 703 if (cdev->pm_clock_support == 0) 704 return 0; 705 706 return pm_runtime_resume_and_get(cdev->dev); 707 } 708 709 static void m_can_clk_stop(struct m_can_classdev *cdev) 710 { 711 if (cdev->pm_clock_support) 712 pm_runtime_put_sync(cdev->dev); 713 } 714 715 static int m_can_get_berr_counter(const struct net_device *dev, 716 struct can_berr_counter *bec) 717 { 718 struct m_can_classdev *cdev = netdev_priv(dev); 719 int err; 720 721 err = m_can_clk_start(cdev); 722 if (err) 723 return err; 724 725 __m_can_get_berr_counter(dev, bec); 726 727 m_can_clk_stop(cdev); 728 729 return 0; 730 } 731 732 static int m_can_handle_state_change(struct net_device *dev, 733 enum can_state new_state) 734 { 735 struct m_can_classdev *cdev = netdev_priv(dev); 736 struct can_frame *cf; 737 struct sk_buff *skb; 738 struct can_berr_counter bec; 739 unsigned int ecr; 740 u32 timestamp = 0; 741 742 switch (new_state) { 743 case CAN_STATE_ERROR_WARNING: 744 /* error warning state */ 745 cdev->can.can_stats.error_warning++; 746 cdev->can.state = CAN_STATE_ERROR_WARNING; 747 break; 748 case CAN_STATE_ERROR_PASSIVE: 749 /* error passive state */ 750 cdev->can.can_stats.error_passive++; 751 cdev->can.state = CAN_STATE_ERROR_PASSIVE; 752 break; 753 case CAN_STATE_BUS_OFF: 754 /* bus-off state */ 755 cdev->can.state = CAN_STATE_BUS_OFF; 756 m_can_disable_all_interrupts(cdev); 757 cdev->can.can_stats.bus_off++; 758 can_bus_off(dev); 759 break; 760 default: 761 break; 762 } 763 764 /* propagate the error condition to the CAN stack */ 765 skb = alloc_can_err_skb(dev, &cf); 766 if (unlikely(!skb)) 767 return 0; 768 769 __m_can_get_berr_counter(dev, &bec); 770 771 switch (new_state) { 772 case CAN_STATE_ERROR_WARNING: 773 /* error warning state */ 774 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 775 cf->data[1] = (bec.txerr > bec.rxerr) ? 776 CAN_ERR_CRTL_TX_WARNING : 777 CAN_ERR_CRTL_RX_WARNING; 778 cf->data[6] = bec.txerr; 779 cf->data[7] = bec.rxerr; 780 break; 781 case CAN_STATE_ERROR_PASSIVE: 782 /* error passive state */ 783 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 784 ecr = m_can_read(cdev, M_CAN_ECR); 785 if (ecr & ECR_RP) 786 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 787 if (bec.txerr > 127) 788 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 789 cf->data[6] = bec.txerr; 790 cf->data[7] = bec.rxerr; 791 break; 792 case CAN_STATE_BUS_OFF: 793 /* bus-off state */ 794 cf->can_id |= CAN_ERR_BUSOFF; 795 break; 796 default: 797 break; 798 } 799 800 if (cdev->is_peripheral) 801 timestamp = m_can_get_timestamp(cdev); 802 803 m_can_receive_skb(cdev, skb, timestamp); 804 805 return 1; 806 } 807 808 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) 809 { 810 struct m_can_classdev *cdev = netdev_priv(dev); 811 int work_done = 0; 812 813 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { 814 netdev_dbg(dev, "entered error warning state\n"); 815 work_done += m_can_handle_state_change(dev, 816 CAN_STATE_ERROR_WARNING); 817 } 818 819 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { 820 netdev_dbg(dev, "entered error passive state\n"); 821 work_done += m_can_handle_state_change(dev, 822 CAN_STATE_ERROR_PASSIVE); 823 } 824 825 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { 826 netdev_dbg(dev, "entered error bus off state\n"); 827 work_done += m_can_handle_state_change(dev, 828 CAN_STATE_BUS_OFF); 829 } 830 831 return work_done; 832 } 833 834 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) 835 { 836 if (irqstatus & IR_WDI) 837 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); 838 if (irqstatus & IR_BEU) 839 netdev_err(dev, "Bit Error Uncorrected\n"); 840 if (irqstatus & IR_BEC) 841 netdev_err(dev, "Bit Error Corrected\n"); 842 if (irqstatus & IR_TOO) 843 netdev_err(dev, "Timeout reached\n"); 844 if (irqstatus & IR_MRAF) 845 netdev_err(dev, "Message RAM access failure occurred\n"); 846 } 847 848 static inline bool is_lec_err(u8 lec) 849 { 850 return lec != LEC_NO_ERROR && lec != LEC_NO_CHANGE; 851 } 852 853 static inline bool m_can_is_protocol_err(u32 irqstatus) 854 { 855 return irqstatus & IR_ERR_LEC_31X; 856 } 857 858 static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus) 859 { 860 struct net_device_stats *stats = &dev->stats; 861 struct m_can_classdev *cdev = netdev_priv(dev); 862 struct can_frame *cf; 863 struct sk_buff *skb; 864 u32 timestamp = 0; 865 866 /* propagate the error condition to the CAN stack */ 867 skb = alloc_can_err_skb(dev, &cf); 868 869 /* update tx error stats since there is protocol error */ 870 stats->tx_errors++; 871 872 /* update arbitration lost status */ 873 if (cdev->version >= 31 && (irqstatus & IR_PEA)) { 874 netdev_dbg(dev, "Protocol error in Arbitration fail\n"); 875 cdev->can.can_stats.arbitration_lost++; 876 if (skb) { 877 cf->can_id |= CAN_ERR_LOSTARB; 878 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC; 879 } 880 } 881 882 if (unlikely(!skb)) { 883 netdev_dbg(dev, "allocation of skb failed\n"); 884 return 0; 885 } 886 887 if (cdev->is_peripheral) 888 timestamp = m_can_get_timestamp(cdev); 889 890 m_can_receive_skb(cdev, skb, timestamp); 891 892 return 1; 893 } 894 895 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, 896 u32 psr) 897 { 898 struct m_can_classdev *cdev = netdev_priv(dev); 899 int work_done = 0; 900 901 if (irqstatus & IR_RF0L) 902 work_done += m_can_handle_lost_msg(dev); 903 904 /* handle lec errors on the bus */ 905 if (cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { 906 u8 lec = FIELD_GET(PSR_LEC_MASK, psr); 907 u8 dlec = FIELD_GET(PSR_DLEC_MASK, psr); 908 909 if (is_lec_err(lec)) { 910 netdev_dbg(dev, "Arbitration phase error detected\n"); 911 work_done += m_can_handle_lec_err(dev, lec); 912 } 913 914 if (is_lec_err(dlec)) { 915 netdev_dbg(dev, "Data phase error detected\n"); 916 work_done += m_can_handle_lec_err(dev, dlec); 917 } 918 } 919 920 /* handle protocol errors in arbitration phase */ 921 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 922 m_can_is_protocol_err(irqstatus)) 923 work_done += m_can_handle_protocol_error(dev, irqstatus); 924 925 /* other unproccessed error interrupts */ 926 m_can_handle_other_err(dev, irqstatus); 927 928 return work_done; 929 } 930 931 static int m_can_rx_handler(struct net_device *dev, int quota, u32 irqstatus) 932 { 933 struct m_can_classdev *cdev = netdev_priv(dev); 934 int rx_work_or_err; 935 int work_done = 0; 936 937 if (!irqstatus) 938 goto end; 939 940 /* Errata workaround for issue "Needless activation of MRAF irq" 941 * During frame reception while the MCAN is in Error Passive state 942 * and the Receive Error Counter has the value MCAN_ECR.REC = 127, 943 * it may happen that MCAN_IR.MRAF is set although there was no 944 * Message RAM access failure. 945 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated 946 * The Message RAM Access Failure interrupt routine needs to check 947 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127. 948 * In this case, reset MCAN_IR.MRAF. No further action is required. 949 */ 950 if (cdev->version <= 31 && irqstatus & IR_MRAF && 951 m_can_read(cdev, M_CAN_ECR) & ECR_RP) { 952 struct can_berr_counter bec; 953 954 __m_can_get_berr_counter(dev, &bec); 955 if (bec.rxerr == 127) { 956 m_can_write(cdev, M_CAN_IR, IR_MRAF); 957 irqstatus &= ~IR_MRAF; 958 } 959 } 960 961 if (irqstatus & IR_ERR_STATE) 962 work_done += m_can_handle_state_errors(dev, 963 m_can_read(cdev, M_CAN_PSR)); 964 965 if (irqstatus & IR_ERR_BUS_30X) 966 work_done += m_can_handle_bus_errors(dev, irqstatus, 967 m_can_read(cdev, M_CAN_PSR)); 968 969 if (irqstatus & IR_RF0N) { 970 rx_work_or_err = m_can_do_rx_poll(dev, (quota - work_done)); 971 if (rx_work_or_err < 0) 972 return rx_work_or_err; 973 974 work_done += rx_work_or_err; 975 } 976 end: 977 return work_done; 978 } 979 980 static int m_can_rx_peripheral(struct net_device *dev, u32 irqstatus) 981 { 982 struct m_can_classdev *cdev = netdev_priv(dev); 983 int work_done; 984 985 work_done = m_can_rx_handler(dev, NAPI_POLL_WEIGHT, irqstatus); 986 987 /* Don't re-enable interrupts if the driver had a fatal error 988 * (e.g., FIFO read failure). 989 */ 990 if (work_done < 0) 991 m_can_disable_all_interrupts(cdev); 992 993 return work_done; 994 } 995 996 static int m_can_poll(struct napi_struct *napi, int quota) 997 { 998 struct net_device *dev = napi->dev; 999 struct m_can_classdev *cdev = netdev_priv(dev); 1000 int work_done; 1001 u32 irqstatus; 1002 1003 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR); 1004 1005 work_done = m_can_rx_handler(dev, quota, irqstatus); 1006 1007 /* Don't re-enable interrupts if the driver had a fatal error 1008 * (e.g., FIFO read failure). 1009 */ 1010 if (work_done >= 0 && work_done < quota) { 1011 napi_complete_done(napi, work_done); 1012 m_can_enable_all_interrupts(cdev); 1013 } 1014 1015 return work_done; 1016 } 1017 1018 /* Echo tx skb and update net stats. Peripherals use rx-offload for 1019 * echo. timestamp is used for peripherals to ensure correct ordering 1020 * by rx-offload, and is ignored for non-peripherals. 1021 */ 1022 static void m_can_tx_update_stats(struct m_can_classdev *cdev, 1023 unsigned int msg_mark, 1024 u32 timestamp) 1025 { 1026 struct net_device *dev = cdev->net; 1027 struct net_device_stats *stats = &dev->stats; 1028 1029 if (cdev->is_peripheral) 1030 stats->tx_bytes += 1031 can_rx_offload_get_echo_skb_queue_timestamp(&cdev->offload, 1032 msg_mark, 1033 timestamp, 1034 NULL); 1035 else 1036 stats->tx_bytes += can_get_echo_skb(dev, msg_mark, NULL); 1037 1038 stats->tx_packets++; 1039 } 1040 1041 static int m_can_echo_tx_event(struct net_device *dev) 1042 { 1043 u32 txe_count = 0; 1044 u32 m_can_txefs; 1045 u32 fgi = 0; 1046 int ack_fgi = -1; 1047 int i = 0; 1048 int err = 0; 1049 unsigned int msg_mark; 1050 1051 struct m_can_classdev *cdev = netdev_priv(dev); 1052 1053 /* read tx event fifo status */ 1054 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); 1055 1056 /* Get Tx Event fifo element count */ 1057 txe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs); 1058 fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_txefs); 1059 1060 /* Get and process all sent elements */ 1061 for (i = 0; i < txe_count; i++) { 1062 u32 txe, timestamp = 0; 1063 1064 /* get message marker, timestamp */ 1065 err = m_can_txe_fifo_read(cdev, fgi, 4, &txe); 1066 if (err) { 1067 netdev_err(dev, "TXE FIFO read returned %d\n", err); 1068 break; 1069 } 1070 1071 msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe); 1072 timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe) << 16; 1073 1074 ack_fgi = fgi; 1075 fgi = (++fgi >= cdev->mcfg[MRAM_TXE].num ? 0 : fgi); 1076 1077 /* update stats */ 1078 m_can_tx_update_stats(cdev, msg_mark, timestamp); 1079 } 1080 1081 if (ack_fgi != -1) 1082 m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK, 1083 ack_fgi)); 1084 1085 return err; 1086 } 1087 1088 static irqreturn_t m_can_isr(int irq, void *dev_id) 1089 { 1090 struct net_device *dev = (struct net_device *)dev_id; 1091 struct m_can_classdev *cdev = netdev_priv(dev); 1092 u32 ir; 1093 1094 if (pm_runtime_suspended(cdev->dev)) 1095 return IRQ_NONE; 1096 ir = m_can_read(cdev, M_CAN_IR); 1097 if (!ir) 1098 return IRQ_NONE; 1099 1100 /* ACK all irqs */ 1101 m_can_write(cdev, M_CAN_IR, ir); 1102 1103 if (cdev->ops->clear_interrupts) 1104 cdev->ops->clear_interrupts(cdev); 1105 1106 /* schedule NAPI in case of 1107 * - rx IRQ 1108 * - state change IRQ 1109 * - bus error IRQ and bus error reporting 1110 */ 1111 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) { 1112 cdev->irqstatus = ir; 1113 if (!cdev->is_peripheral) { 1114 m_can_disable_all_interrupts(cdev); 1115 napi_schedule(&cdev->napi); 1116 } else if (m_can_rx_peripheral(dev, ir) < 0) { 1117 goto out_fail; 1118 } 1119 } 1120 1121 if (cdev->version == 30) { 1122 if (ir & IR_TC) { 1123 /* Transmission Complete Interrupt*/ 1124 u32 timestamp = 0; 1125 1126 if (cdev->is_peripheral) 1127 timestamp = m_can_get_timestamp(cdev); 1128 m_can_tx_update_stats(cdev, 0, timestamp); 1129 netif_wake_queue(dev); 1130 } 1131 } else { 1132 if (ir & IR_TEFN) { 1133 /* New TX FIFO Element arrived */ 1134 if (m_can_echo_tx_event(dev) != 0) 1135 goto out_fail; 1136 1137 if (netif_queue_stopped(dev) && 1138 !m_can_tx_fifo_full(cdev)) 1139 netif_wake_queue(dev); 1140 } 1141 } 1142 1143 if (cdev->is_peripheral) 1144 can_rx_offload_threaded_irq_finish(&cdev->offload); 1145 1146 return IRQ_HANDLED; 1147 1148 out_fail: 1149 m_can_disable_all_interrupts(cdev); 1150 return IRQ_HANDLED; 1151 } 1152 1153 static const struct can_bittiming_const m_can_bittiming_const_30X = { 1154 .name = KBUILD_MODNAME, 1155 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1156 .tseg1_max = 64, 1157 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1158 .tseg2_max = 16, 1159 .sjw_max = 16, 1160 .brp_min = 1, 1161 .brp_max = 1024, 1162 .brp_inc = 1, 1163 }; 1164 1165 static const struct can_bittiming_const m_can_data_bittiming_const_30X = { 1166 .name = KBUILD_MODNAME, 1167 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1168 .tseg1_max = 16, 1169 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1170 .tseg2_max = 8, 1171 .sjw_max = 4, 1172 .brp_min = 1, 1173 .brp_max = 32, 1174 .brp_inc = 1, 1175 }; 1176 1177 static const struct can_bittiming_const m_can_bittiming_const_31X = { 1178 .name = KBUILD_MODNAME, 1179 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1180 .tseg1_max = 256, 1181 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */ 1182 .tseg2_max = 128, 1183 .sjw_max = 128, 1184 .brp_min = 1, 1185 .brp_max = 512, 1186 .brp_inc = 1, 1187 }; 1188 1189 static const struct can_bittiming_const m_can_data_bittiming_const_31X = { 1190 .name = KBUILD_MODNAME, 1191 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */ 1192 .tseg1_max = 32, 1193 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1194 .tseg2_max = 16, 1195 .sjw_max = 16, 1196 .brp_min = 1, 1197 .brp_max = 32, 1198 .brp_inc = 1, 1199 }; 1200 1201 static int m_can_set_bittiming(struct net_device *dev) 1202 { 1203 struct m_can_classdev *cdev = netdev_priv(dev); 1204 const struct can_bittiming *bt = &cdev->can.bittiming; 1205 const struct can_bittiming *dbt = &cdev->can.data_bittiming; 1206 u16 brp, sjw, tseg1, tseg2; 1207 u32 reg_btp; 1208 1209 brp = bt->brp - 1; 1210 sjw = bt->sjw - 1; 1211 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 1212 tseg2 = bt->phase_seg2 - 1; 1213 reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) | 1214 FIELD_PREP(NBTP_NSJW_MASK, sjw) | 1215 FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) | 1216 FIELD_PREP(NBTP_NTSEG2_MASK, tseg2); 1217 m_can_write(cdev, M_CAN_NBTP, reg_btp); 1218 1219 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1220 reg_btp = 0; 1221 brp = dbt->brp - 1; 1222 sjw = dbt->sjw - 1; 1223 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; 1224 tseg2 = dbt->phase_seg2 - 1; 1225 1226 /* TDC is only needed for bitrates beyond 2.5 MBit/s. 1227 * This is mentioned in the "Bit Time Requirements for CAN FD" 1228 * paper presented at the International CAN Conference 2013 1229 */ 1230 if (dbt->bitrate > 2500000) { 1231 u32 tdco, ssp; 1232 1233 /* Use the same value of secondary sampling point 1234 * as the data sampling point 1235 */ 1236 ssp = dbt->sample_point; 1237 1238 /* Equation based on Bosch's M_CAN User Manual's 1239 * Transmitter Delay Compensation Section 1240 */ 1241 tdco = (cdev->can.clock.freq / 1000) * 1242 ssp / dbt->bitrate; 1243 1244 /* Max valid TDCO value is 127 */ 1245 if (tdco > 127) { 1246 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n", 1247 tdco); 1248 tdco = 127; 1249 } 1250 1251 reg_btp |= DBTP_TDC; 1252 m_can_write(cdev, M_CAN_TDCR, 1253 FIELD_PREP(TDCR_TDCO_MASK, tdco)); 1254 } 1255 1256 reg_btp |= FIELD_PREP(DBTP_DBRP_MASK, brp) | 1257 FIELD_PREP(DBTP_DSJW_MASK, sjw) | 1258 FIELD_PREP(DBTP_DTSEG1_MASK, tseg1) | 1259 FIELD_PREP(DBTP_DTSEG2_MASK, tseg2); 1260 1261 m_can_write(cdev, M_CAN_DBTP, reg_btp); 1262 } 1263 1264 return 0; 1265 } 1266 1267 /* Configure M_CAN chip: 1268 * - set rx buffer/fifo element size 1269 * - configure rx fifo 1270 * - accept non-matching frame into fifo 0 1271 * - configure tx buffer 1272 * - >= v3.1.x: TX FIFO is used 1273 * - configure mode 1274 * - setup bittiming 1275 * - configure timestamp generation 1276 */ 1277 static int m_can_chip_config(struct net_device *dev) 1278 { 1279 struct m_can_classdev *cdev = netdev_priv(dev); 1280 u32 interrupts = IR_ALL_INT; 1281 u32 cccr, test; 1282 int err; 1283 1284 err = m_can_init_ram(cdev); 1285 if (err) { 1286 dev_err(cdev->dev, "Message RAM configuration failed\n"); 1287 return err; 1288 } 1289 1290 /* Disable unused interrupts */ 1291 interrupts &= ~(IR_ARA | IR_ELO | IR_DRX | IR_TEFF | IR_TEFW | IR_TFE | 1292 IR_TCF | IR_HPM | IR_RF1F | IR_RF1W | IR_RF1N | 1293 IR_RF0F | IR_RF0W); 1294 1295 m_can_config_endisable(cdev, true); 1296 1297 /* RX Buffer/FIFO Element Size 64 bytes data field */ 1298 m_can_write(cdev, M_CAN_RXESC, 1299 FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) | 1300 FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) | 1301 FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B)); 1302 1303 /* Accept Non-matching Frames Into FIFO 0 */ 1304 m_can_write(cdev, M_CAN_GFC, 0x0); 1305 1306 if (cdev->version == 30) { 1307 /* only support one Tx Buffer currently */ 1308 m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) | 1309 cdev->mcfg[MRAM_TXB].off); 1310 } else { 1311 /* TX FIFO is used for newer IP Core versions */ 1312 m_can_write(cdev, M_CAN_TXBC, 1313 FIELD_PREP(TXBC_TFQS_MASK, 1314 cdev->mcfg[MRAM_TXB].num) | 1315 cdev->mcfg[MRAM_TXB].off); 1316 } 1317 1318 /* support 64 bytes payload */ 1319 m_can_write(cdev, M_CAN_TXESC, 1320 FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B)); 1321 1322 /* TX Event FIFO */ 1323 if (cdev->version == 30) { 1324 m_can_write(cdev, M_CAN_TXEFC, 1325 FIELD_PREP(TXEFC_EFS_MASK, 1) | 1326 cdev->mcfg[MRAM_TXE].off); 1327 } else { 1328 /* Full TX Event FIFO is used */ 1329 m_can_write(cdev, M_CAN_TXEFC, 1330 FIELD_PREP(TXEFC_EFS_MASK, 1331 cdev->mcfg[MRAM_TXE].num) | 1332 cdev->mcfg[MRAM_TXE].off); 1333 } 1334 1335 /* rx fifo configuration, blocking mode, fifo size 1 */ 1336 m_can_write(cdev, M_CAN_RXF0C, 1337 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) | 1338 cdev->mcfg[MRAM_RXF0].off); 1339 1340 m_can_write(cdev, M_CAN_RXF1C, 1341 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) | 1342 cdev->mcfg[MRAM_RXF1].off); 1343 1344 cccr = m_can_read(cdev, M_CAN_CCCR); 1345 test = m_can_read(cdev, M_CAN_TEST); 1346 test &= ~TEST_LBCK; 1347 if (cdev->version == 30) { 1348 /* Version 3.0.x */ 1349 1350 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR | 1351 FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) | 1352 FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK))); 1353 1354 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1355 cccr |= FIELD_PREP(CCCR_CME_MASK, CCCR_CME_CANFD_BRS); 1356 1357 } else { 1358 /* Version 3.1.x or 3.2.x */ 1359 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE | 1360 CCCR_NISO | CCCR_DAR); 1361 1362 /* Only 3.2.x has NISO Bit implemented */ 1363 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 1364 cccr |= CCCR_NISO; 1365 1366 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1367 cccr |= (CCCR_BRSE | CCCR_FDOE); 1368 } 1369 1370 /* Loopback Mode */ 1371 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1372 cccr |= CCCR_TEST | CCCR_MON; 1373 test |= TEST_LBCK; 1374 } 1375 1376 /* Enable Monitoring (all versions) */ 1377 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1378 cccr |= CCCR_MON; 1379 1380 /* Disable Auto Retransmission (all versions) */ 1381 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 1382 cccr |= CCCR_DAR; 1383 1384 /* Write config */ 1385 m_can_write(cdev, M_CAN_CCCR, cccr); 1386 m_can_write(cdev, M_CAN_TEST, test); 1387 1388 /* Enable interrupts */ 1389 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 1390 if (cdev->version == 30) 1391 interrupts &= ~(IR_ERR_LEC_30X); 1392 else 1393 interrupts &= ~(IR_ERR_LEC_31X); 1394 } 1395 m_can_write(cdev, M_CAN_IE, interrupts); 1396 1397 /* route all interrupts to INT0 */ 1398 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); 1399 1400 /* set bittiming params */ 1401 m_can_set_bittiming(dev); 1402 1403 /* enable internal timestamp generation, with a prescaler of 16. The 1404 * prescaler is applied to the nominal bit timing 1405 */ 1406 m_can_write(cdev, M_CAN_TSCC, 1407 FIELD_PREP(TSCC_TCP_MASK, 0xf) | 1408 FIELD_PREP(TSCC_TSS_MASK, TSCC_TSS_INTERNAL)); 1409 1410 m_can_config_endisable(cdev, false); 1411 1412 if (cdev->ops->init) 1413 cdev->ops->init(cdev); 1414 1415 return 0; 1416 } 1417 1418 static int m_can_start(struct net_device *dev) 1419 { 1420 struct m_can_classdev *cdev = netdev_priv(dev); 1421 int ret; 1422 1423 /* basic m_can configuration */ 1424 ret = m_can_chip_config(dev); 1425 if (ret) 1426 return ret; 1427 1428 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 1429 1430 m_can_enable_all_interrupts(cdev); 1431 1432 return 0; 1433 } 1434 1435 static int m_can_set_mode(struct net_device *dev, enum can_mode mode) 1436 { 1437 switch (mode) { 1438 case CAN_MODE_START: 1439 m_can_clean(dev); 1440 m_can_start(dev); 1441 netif_wake_queue(dev); 1442 break; 1443 default: 1444 return -EOPNOTSUPP; 1445 } 1446 1447 return 0; 1448 } 1449 1450 /* Checks core release number of M_CAN 1451 * returns 0 if an unsupported device is detected 1452 * else it returns the release and step coded as: 1453 * return value = 10 * <release> + 1 * <step> 1454 */ 1455 static int m_can_check_core_release(struct m_can_classdev *cdev) 1456 { 1457 u32 crel_reg; 1458 u8 rel; 1459 u8 step; 1460 int res; 1461 1462 /* Read Core Release Version and split into version number 1463 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; 1464 */ 1465 crel_reg = m_can_read(cdev, M_CAN_CREL); 1466 rel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg); 1467 step = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg); 1468 1469 if (rel == 3) { 1470 /* M_CAN v3.x.y: create return value */ 1471 res = 30 + step; 1472 } else { 1473 /* Unsupported M_CAN version */ 1474 res = 0; 1475 } 1476 1477 return res; 1478 } 1479 1480 /* Selectable Non ISO support only in version 3.2.x 1481 * This function checks if the bit is writable. 1482 */ 1483 static bool m_can_niso_supported(struct m_can_classdev *cdev) 1484 { 1485 u32 cccr_reg, cccr_poll = 0; 1486 int niso_timeout = -ETIMEDOUT; 1487 int i; 1488 1489 m_can_config_endisable(cdev, true); 1490 cccr_reg = m_can_read(cdev, M_CAN_CCCR); 1491 cccr_reg |= CCCR_NISO; 1492 m_can_write(cdev, M_CAN_CCCR, cccr_reg); 1493 1494 for (i = 0; i <= 10; i++) { 1495 cccr_poll = m_can_read(cdev, M_CAN_CCCR); 1496 if (cccr_poll == cccr_reg) { 1497 niso_timeout = 0; 1498 break; 1499 } 1500 1501 usleep_range(1, 5); 1502 } 1503 1504 /* Clear NISO */ 1505 cccr_reg &= ~(CCCR_NISO); 1506 m_can_write(cdev, M_CAN_CCCR, cccr_reg); 1507 1508 m_can_config_endisable(cdev, false); 1509 1510 /* return false if time out (-ETIMEDOUT), else return true */ 1511 return !niso_timeout; 1512 } 1513 1514 static int m_can_dev_setup(struct m_can_classdev *cdev) 1515 { 1516 struct net_device *dev = cdev->net; 1517 int m_can_version, err; 1518 1519 m_can_version = m_can_check_core_release(cdev); 1520 /* return if unsupported version */ 1521 if (!m_can_version) { 1522 dev_err(cdev->dev, "Unsupported version number: %2d", 1523 m_can_version); 1524 return -EINVAL; 1525 } 1526 1527 if (!cdev->is_peripheral) 1528 netif_napi_add(dev, &cdev->napi, m_can_poll); 1529 1530 /* Shared properties of all M_CAN versions */ 1531 cdev->version = m_can_version; 1532 cdev->can.do_set_mode = m_can_set_mode; 1533 cdev->can.do_get_berr_counter = m_can_get_berr_counter; 1534 1535 /* Set M_CAN supported operations */ 1536 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1537 CAN_CTRLMODE_LISTENONLY | 1538 CAN_CTRLMODE_BERR_REPORTING | 1539 CAN_CTRLMODE_FD | 1540 CAN_CTRLMODE_ONE_SHOT; 1541 1542 /* Set properties depending on M_CAN version */ 1543 switch (cdev->version) { 1544 case 30: 1545 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ 1546 err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1547 if (err) 1548 return err; 1549 cdev->can.bittiming_const = &m_can_bittiming_const_30X; 1550 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X; 1551 break; 1552 case 31: 1553 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ 1554 err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1555 if (err) 1556 return err; 1557 cdev->can.bittiming_const = &m_can_bittiming_const_31X; 1558 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; 1559 break; 1560 case 32: 1561 case 33: 1562 /* Support both MCAN version v3.2.x and v3.3.0 */ 1563 cdev->can.bittiming_const = &m_can_bittiming_const_31X; 1564 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; 1565 1566 cdev->can.ctrlmode_supported |= 1567 (m_can_niso_supported(cdev) ? 1568 CAN_CTRLMODE_FD_NON_ISO : 0); 1569 break; 1570 default: 1571 dev_err(cdev->dev, "Unsupported version number: %2d", 1572 cdev->version); 1573 return -EINVAL; 1574 } 1575 1576 if (cdev->ops->init) 1577 cdev->ops->init(cdev); 1578 1579 return 0; 1580 } 1581 1582 static void m_can_stop(struct net_device *dev) 1583 { 1584 struct m_can_classdev *cdev = netdev_priv(dev); 1585 1586 /* disable all interrupts */ 1587 m_can_disable_all_interrupts(cdev); 1588 1589 /* Set init mode to disengage from the network */ 1590 m_can_config_endisable(cdev, true); 1591 1592 /* set the state as STOPPED */ 1593 cdev->can.state = CAN_STATE_STOPPED; 1594 } 1595 1596 static int m_can_close(struct net_device *dev) 1597 { 1598 struct m_can_classdev *cdev = netdev_priv(dev); 1599 1600 netif_stop_queue(dev); 1601 1602 m_can_stop(dev); 1603 free_irq(dev->irq, dev); 1604 1605 if (cdev->is_peripheral) { 1606 cdev->tx_skb = NULL; 1607 destroy_workqueue(cdev->tx_wq); 1608 cdev->tx_wq = NULL; 1609 can_rx_offload_disable(&cdev->offload); 1610 } else { 1611 napi_disable(&cdev->napi); 1612 } 1613 1614 close_candev(dev); 1615 1616 m_can_clk_stop(cdev); 1617 phy_power_off(cdev->transceiver); 1618 1619 return 0; 1620 } 1621 1622 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx) 1623 { 1624 struct m_can_classdev *cdev = netdev_priv(dev); 1625 /*get wrap around for loopback skb index */ 1626 unsigned int wrap = cdev->can.echo_skb_max; 1627 int next_idx; 1628 1629 /* calculate next index */ 1630 next_idx = (++putidx >= wrap ? 0 : putidx); 1631 1632 /* check if occupied */ 1633 return !!cdev->can.echo_skb[next_idx]; 1634 } 1635 1636 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) 1637 { 1638 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data; 1639 struct net_device *dev = cdev->net; 1640 struct sk_buff *skb = cdev->tx_skb; 1641 struct id_and_dlc fifo_header; 1642 u32 cccr, fdflags; 1643 u32 txfqs; 1644 int err; 1645 int putidx; 1646 1647 cdev->tx_skb = NULL; 1648 1649 /* Generate ID field for TX buffer Element */ 1650 /* Common to all supported M_CAN versions */ 1651 if (cf->can_id & CAN_EFF_FLAG) { 1652 fifo_header.id = cf->can_id & CAN_EFF_MASK; 1653 fifo_header.id |= TX_BUF_XTD; 1654 } else { 1655 fifo_header.id = ((cf->can_id & CAN_SFF_MASK) << 18); 1656 } 1657 1658 if (cf->can_id & CAN_RTR_FLAG) 1659 fifo_header.id |= TX_BUF_RTR; 1660 1661 if (cdev->version == 30) { 1662 netif_stop_queue(dev); 1663 1664 fifo_header.dlc = can_fd_len2dlc(cf->len) << 16; 1665 1666 /* Write the frame ID, DLC, and payload to the FIFO element. */ 1667 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &fifo_header, 2); 1668 if (err) 1669 goto out_fail; 1670 1671 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA, 1672 cf->data, DIV_ROUND_UP(cf->len, 4)); 1673 if (err) 1674 goto out_fail; 1675 1676 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1677 cccr = m_can_read(cdev, M_CAN_CCCR); 1678 cccr &= ~CCCR_CMR_MASK; 1679 if (can_is_canfd_skb(skb)) { 1680 if (cf->flags & CANFD_BRS) 1681 cccr |= FIELD_PREP(CCCR_CMR_MASK, 1682 CCCR_CMR_CANFD_BRS); 1683 else 1684 cccr |= FIELD_PREP(CCCR_CMR_MASK, 1685 CCCR_CMR_CANFD); 1686 } else { 1687 cccr |= FIELD_PREP(CCCR_CMR_MASK, CCCR_CMR_CAN); 1688 } 1689 m_can_write(cdev, M_CAN_CCCR, cccr); 1690 } 1691 m_can_write(cdev, M_CAN_TXBTIE, 0x1); 1692 1693 can_put_echo_skb(skb, dev, 0, 0); 1694 1695 m_can_write(cdev, M_CAN_TXBAR, 0x1); 1696 /* End of xmit function for version 3.0.x */ 1697 } else { 1698 /* Transmit routine for version >= v3.1.x */ 1699 1700 txfqs = m_can_read(cdev, M_CAN_TXFQS); 1701 1702 /* Check if FIFO full */ 1703 if (_m_can_tx_fifo_full(txfqs)) { 1704 /* This shouldn't happen */ 1705 netif_stop_queue(dev); 1706 netdev_warn(dev, 1707 "TX queue active although FIFO is full."); 1708 1709 if (cdev->is_peripheral) { 1710 kfree_skb(skb); 1711 dev->stats.tx_dropped++; 1712 return NETDEV_TX_OK; 1713 } else { 1714 return NETDEV_TX_BUSY; 1715 } 1716 } 1717 1718 /* get put index for frame */ 1719 putidx = FIELD_GET(TXFQS_TFQPI_MASK, txfqs); 1720 1721 /* Construct DLC Field, with CAN-FD configuration. 1722 * Use the put index of the fifo as the message marker, 1723 * used in the TX interrupt for sending the correct echo frame. 1724 */ 1725 1726 /* get CAN FD configuration of frame */ 1727 fdflags = 0; 1728 if (can_is_canfd_skb(skb)) { 1729 fdflags |= TX_BUF_FDF; 1730 if (cf->flags & CANFD_BRS) 1731 fdflags |= TX_BUF_BRS; 1732 } 1733 1734 fifo_header.dlc = FIELD_PREP(TX_BUF_MM_MASK, putidx) | 1735 FIELD_PREP(TX_BUF_DLC_MASK, can_fd_len2dlc(cf->len)) | 1736 fdflags | TX_BUF_EFC; 1737 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, &fifo_header, 2); 1738 if (err) 1739 goto out_fail; 1740 1741 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA, 1742 cf->data, DIV_ROUND_UP(cf->len, 4)); 1743 if (err) 1744 goto out_fail; 1745 1746 /* Push loopback echo. 1747 * Will be looped back on TX interrupt based on message marker 1748 */ 1749 can_put_echo_skb(skb, dev, putidx, 0); 1750 1751 /* Enable TX FIFO element to start transfer */ 1752 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx)); 1753 1754 /* stop network queue if fifo full */ 1755 if (m_can_tx_fifo_full(cdev) || 1756 m_can_next_echo_skb_occupied(dev, putidx)) 1757 netif_stop_queue(dev); 1758 } 1759 1760 return NETDEV_TX_OK; 1761 1762 out_fail: 1763 netdev_err(dev, "FIFO write returned %d\n", err); 1764 m_can_disable_all_interrupts(cdev); 1765 return NETDEV_TX_BUSY; 1766 } 1767 1768 static void m_can_tx_work_queue(struct work_struct *ws) 1769 { 1770 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev, 1771 tx_work); 1772 1773 m_can_tx_handler(cdev); 1774 } 1775 1776 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, 1777 struct net_device *dev) 1778 { 1779 struct m_can_classdev *cdev = netdev_priv(dev); 1780 1781 if (can_dev_dropped_skb(dev, skb)) 1782 return NETDEV_TX_OK; 1783 1784 if (cdev->is_peripheral) { 1785 if (cdev->tx_skb) { 1786 netdev_err(dev, "hard_xmit called while tx busy\n"); 1787 return NETDEV_TX_BUSY; 1788 } 1789 1790 if (cdev->can.state == CAN_STATE_BUS_OFF) { 1791 m_can_clean(dev); 1792 } else { 1793 /* Need to stop the queue to avoid numerous requests 1794 * from being sent. Suggested improvement is to create 1795 * a queueing mechanism that will queue the skbs and 1796 * process them in order. 1797 */ 1798 cdev->tx_skb = skb; 1799 netif_stop_queue(cdev->net); 1800 queue_work(cdev->tx_wq, &cdev->tx_work); 1801 } 1802 } else { 1803 cdev->tx_skb = skb; 1804 return m_can_tx_handler(cdev); 1805 } 1806 1807 return NETDEV_TX_OK; 1808 } 1809 1810 static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) 1811 { 1812 struct m_can_classdev *cdev = container_of(timer, struct 1813 m_can_classdev, hrtimer); 1814 1815 m_can_isr(0, cdev->net); 1816 1817 hrtimer_forward_now(timer, ms_to_ktime(HRTIMER_POLL_INTERVAL_MS)); 1818 1819 return HRTIMER_RESTART; 1820 } 1821 1822 static int m_can_open(struct net_device *dev) 1823 { 1824 struct m_can_classdev *cdev = netdev_priv(dev); 1825 int err; 1826 1827 err = phy_power_on(cdev->transceiver); 1828 if (err) 1829 return err; 1830 1831 err = m_can_clk_start(cdev); 1832 if (err) 1833 goto out_phy_power_off; 1834 1835 /* open the can device */ 1836 err = open_candev(dev); 1837 if (err) { 1838 netdev_err(dev, "failed to open can device\n"); 1839 goto exit_disable_clks; 1840 } 1841 1842 if (cdev->is_peripheral) 1843 can_rx_offload_enable(&cdev->offload); 1844 else 1845 napi_enable(&cdev->napi); 1846 1847 /* register interrupt handler */ 1848 if (cdev->is_peripheral) { 1849 cdev->tx_skb = NULL; 1850 cdev->tx_wq = alloc_workqueue("mcan_wq", 1851 WQ_FREEZABLE | WQ_MEM_RECLAIM, 0); 1852 if (!cdev->tx_wq) { 1853 err = -ENOMEM; 1854 goto out_wq_fail; 1855 } 1856 1857 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue); 1858 1859 err = request_threaded_irq(dev->irq, NULL, m_can_isr, 1860 IRQF_ONESHOT, 1861 dev->name, dev); 1862 } else if (dev->irq) { 1863 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, 1864 dev); 1865 } 1866 1867 if (err < 0) { 1868 netdev_err(dev, "failed to request interrupt\n"); 1869 goto exit_irq_fail; 1870 } 1871 1872 /* start the m_can controller */ 1873 err = m_can_start(dev); 1874 if (err) 1875 goto exit_start_fail; 1876 1877 netif_start_queue(dev); 1878 1879 return 0; 1880 1881 exit_start_fail: 1882 if (cdev->is_peripheral || dev->irq) 1883 free_irq(dev->irq, dev); 1884 exit_irq_fail: 1885 if (cdev->is_peripheral) 1886 destroy_workqueue(cdev->tx_wq); 1887 out_wq_fail: 1888 if (cdev->is_peripheral) 1889 can_rx_offload_disable(&cdev->offload); 1890 else 1891 napi_disable(&cdev->napi); 1892 close_candev(dev); 1893 exit_disable_clks: 1894 m_can_clk_stop(cdev); 1895 out_phy_power_off: 1896 phy_power_off(cdev->transceiver); 1897 return err; 1898 } 1899 1900 static const struct net_device_ops m_can_netdev_ops = { 1901 .ndo_open = m_can_open, 1902 .ndo_stop = m_can_close, 1903 .ndo_start_xmit = m_can_start_xmit, 1904 .ndo_change_mtu = can_change_mtu, 1905 }; 1906 1907 static const struct ethtool_ops m_can_ethtool_ops = { 1908 .get_ts_info = ethtool_op_get_ts_info, 1909 }; 1910 1911 static int register_m_can_dev(struct net_device *dev) 1912 { 1913 dev->flags |= IFF_ECHO; /* we support local echo */ 1914 dev->netdev_ops = &m_can_netdev_ops; 1915 dev->ethtool_ops = &m_can_ethtool_ops; 1916 1917 return register_candev(dev); 1918 } 1919 1920 int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size) 1921 { 1922 u32 total_size; 1923 1924 total_size = cdev->mcfg[MRAM_TXB].off - cdev->mcfg[MRAM_SIDF].off + 1925 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 1926 if (total_size > mram_max_size) { 1927 dev_err(cdev->dev, "Total size of mram config(%u) exceeds mram(%u)\n", 1928 total_size, mram_max_size); 1929 return -EINVAL; 1930 } 1931 1932 return 0; 1933 } 1934 EXPORT_SYMBOL_GPL(m_can_check_mram_cfg); 1935 1936 static void m_can_of_parse_mram(struct m_can_classdev *cdev, 1937 const u32 *mram_config_vals) 1938 { 1939 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; 1940 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; 1941 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + 1942 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; 1943 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; 1944 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + 1945 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; 1946 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & 1947 FIELD_MAX(RXFC_FS_MASK); 1948 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + 1949 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; 1950 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & 1951 FIELD_MAX(RXFC_FS_MASK); 1952 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + 1953 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; 1954 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; 1955 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + 1956 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; 1957 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; 1958 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + 1959 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; 1960 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & 1961 FIELD_MAX(TXBC_NDTB_MASK); 1962 1963 dev_dbg(cdev->dev, 1964 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", 1965 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num, 1966 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num, 1967 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num, 1968 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num, 1969 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num, 1970 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num, 1971 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num); 1972 } 1973 1974 int m_can_init_ram(struct m_can_classdev *cdev) 1975 { 1976 int end, i, start; 1977 int err = 0; 1978 1979 /* initialize the entire Message RAM in use to avoid possible 1980 * ECC/parity checksum errors when reading an uninitialized buffer 1981 */ 1982 start = cdev->mcfg[MRAM_SIDF].off; 1983 end = cdev->mcfg[MRAM_TXB].off + 1984 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 1985 1986 for (i = start; i < end; i += 4) { 1987 err = m_can_fifo_write_no_off(cdev, i, 0x0); 1988 if (err) 1989 break; 1990 } 1991 1992 return err; 1993 } 1994 EXPORT_SYMBOL_GPL(m_can_init_ram); 1995 1996 int m_can_class_get_clocks(struct m_can_classdev *cdev) 1997 { 1998 int ret = 0; 1999 2000 cdev->hclk = devm_clk_get(cdev->dev, "hclk"); 2001 cdev->cclk = devm_clk_get(cdev->dev, "cclk"); 2002 2003 if (IS_ERR(cdev->hclk) || IS_ERR(cdev->cclk)) { 2004 dev_err(cdev->dev, "no clock found\n"); 2005 ret = -ENODEV; 2006 } 2007 2008 return ret; 2009 } 2010 EXPORT_SYMBOL_GPL(m_can_class_get_clocks); 2011 2012 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, 2013 int sizeof_priv) 2014 { 2015 struct m_can_classdev *class_dev = NULL; 2016 u32 mram_config_vals[MRAM_CFG_LEN]; 2017 struct net_device *net_dev; 2018 u32 tx_fifo_size; 2019 int ret; 2020 2021 ret = fwnode_property_read_u32_array(dev_fwnode(dev), 2022 "bosch,mram-cfg", 2023 mram_config_vals, 2024 sizeof(mram_config_vals) / 4); 2025 if (ret) { 2026 dev_err(dev, "Could not get Message RAM configuration."); 2027 goto out; 2028 } 2029 2030 /* Get TX FIFO size 2031 * Defines the total amount of echo buffers for loopback 2032 */ 2033 tx_fifo_size = mram_config_vals[7]; 2034 2035 /* allocate the m_can device */ 2036 net_dev = alloc_candev(sizeof_priv, tx_fifo_size); 2037 if (!net_dev) { 2038 dev_err(dev, "Failed to allocate CAN device"); 2039 goto out; 2040 } 2041 2042 class_dev = netdev_priv(net_dev); 2043 class_dev->net = net_dev; 2044 class_dev->dev = dev; 2045 SET_NETDEV_DEV(net_dev, dev); 2046 2047 m_can_of_parse_mram(class_dev, mram_config_vals); 2048 out: 2049 return class_dev; 2050 } 2051 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev); 2052 2053 void m_can_class_free_dev(struct net_device *net) 2054 { 2055 free_candev(net); 2056 } 2057 EXPORT_SYMBOL_GPL(m_can_class_free_dev); 2058 2059 int m_can_class_register(struct m_can_classdev *cdev) 2060 { 2061 int ret; 2062 2063 if (cdev->pm_clock_support) { 2064 ret = m_can_clk_start(cdev); 2065 if (ret) 2066 return ret; 2067 } 2068 2069 if (cdev->is_peripheral) { 2070 ret = can_rx_offload_add_manual(cdev->net, &cdev->offload, 2071 NAPI_POLL_WEIGHT); 2072 if (ret) 2073 goto clk_disable; 2074 } 2075 2076 if (!cdev->net->irq) 2077 cdev->hrtimer.function = &hrtimer_callback; 2078 2079 ret = m_can_dev_setup(cdev); 2080 if (ret) 2081 goto rx_offload_del; 2082 2083 ret = register_m_can_dev(cdev->net); 2084 if (ret) { 2085 dev_err(cdev->dev, "registering %s failed (err=%d)\n", 2086 cdev->net->name, ret); 2087 goto rx_offload_del; 2088 } 2089 2090 of_can_transceiver(cdev->net); 2091 2092 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n", 2093 KBUILD_MODNAME, cdev->net->irq, cdev->version); 2094 2095 /* Probe finished 2096 * Stop clocks. They will be reactivated once the M_CAN device is opened 2097 */ 2098 m_can_clk_stop(cdev); 2099 2100 return 0; 2101 2102 rx_offload_del: 2103 if (cdev->is_peripheral) 2104 can_rx_offload_del(&cdev->offload); 2105 clk_disable: 2106 m_can_clk_stop(cdev); 2107 2108 return ret; 2109 } 2110 EXPORT_SYMBOL_GPL(m_can_class_register); 2111 2112 void m_can_class_unregister(struct m_can_classdev *cdev) 2113 { 2114 if (cdev->is_peripheral) 2115 can_rx_offload_del(&cdev->offload); 2116 unregister_candev(cdev->net); 2117 } 2118 EXPORT_SYMBOL_GPL(m_can_class_unregister); 2119 2120 int m_can_class_suspend(struct device *dev) 2121 { 2122 struct m_can_classdev *cdev = dev_get_drvdata(dev); 2123 struct net_device *ndev = cdev->net; 2124 2125 if (netif_running(ndev)) { 2126 netif_stop_queue(ndev); 2127 netif_device_detach(ndev); 2128 m_can_stop(ndev); 2129 m_can_clk_stop(cdev); 2130 } 2131 2132 pinctrl_pm_select_sleep_state(dev); 2133 2134 cdev->can.state = CAN_STATE_SLEEPING; 2135 2136 return 0; 2137 } 2138 EXPORT_SYMBOL_GPL(m_can_class_suspend); 2139 2140 int m_can_class_resume(struct device *dev) 2141 { 2142 struct m_can_classdev *cdev = dev_get_drvdata(dev); 2143 struct net_device *ndev = cdev->net; 2144 2145 pinctrl_pm_select_default_state(dev); 2146 2147 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 2148 2149 if (netif_running(ndev)) { 2150 int ret; 2151 2152 ret = m_can_clk_start(cdev); 2153 if (ret) 2154 return ret; 2155 ret = m_can_start(ndev); 2156 if (ret) { 2157 m_can_clk_stop(cdev); 2158 2159 return ret; 2160 } 2161 2162 netif_device_attach(ndev); 2163 netif_start_queue(ndev); 2164 } 2165 2166 return 0; 2167 } 2168 EXPORT_SYMBOL_GPL(m_can_class_resume); 2169 2170 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); 2171 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 2172 MODULE_LICENSE("GPL v2"); 2173 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); 2174