1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 /* Copyright (C) 2018 KVASER AB, Sweden. All rights reserved. 3 * Parts of this driver are based on the following: 4 * - Kvaser linux pciefd driver (version 5.25) 5 * - PEAK linux canfd driver 6 * - Altera Avalon EPCS flash controller driver 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/device.h> 12 #include <linux/ethtool.h> 13 #include <linux/pci.h> 14 #include <linux/can/dev.h> 15 #include <linux/timer.h> 16 #include <linux/netdevice.h> 17 #include <linux/crc32.h> 18 #include <linux/iopoll.h> 19 20 MODULE_LICENSE("Dual BSD/GPL"); 21 MODULE_AUTHOR("Kvaser AB <support@kvaser.com>"); 22 MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices"); 23 24 #define KVASER_PCIEFD_DRV_NAME "kvaser_pciefd" 25 26 #define KVASER_PCIEFD_WAIT_TIMEOUT msecs_to_jiffies(1000) 27 #define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200)) 28 #define KVASER_PCIEFD_MAX_ERR_REP 256 29 #define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17 30 #define KVASER_PCIEFD_MAX_CAN_CHANNELS 4 31 #define KVASER_PCIEFD_DMA_COUNT 2 32 33 #define KVASER_PCIEFD_DMA_SIZE (4 * 1024) 34 #define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0) 35 36 #define KVASER_PCIEFD_VENDOR 0x1a07 37 #define KVASER_PCIEFD_4HS_ID 0x0d 38 #define KVASER_PCIEFD_2HS_ID 0x0e 39 #define KVASER_PCIEFD_HS_ID 0x0f 40 #define KVASER_PCIEFD_MINIPCIE_HS_ID 0x10 41 #define KVASER_PCIEFD_MINIPCIE_2HS_ID 0x11 42 43 /* PCIe IRQ registers */ 44 #define KVASER_PCIEFD_IRQ_REG 0x40 45 #define KVASER_PCIEFD_IEN_REG 0x50 46 /* DMA map */ 47 #define KVASER_PCIEFD_DMA_MAP_BASE 0x1000 48 /* Kvaser KCAN CAN controller registers */ 49 #define KVASER_PCIEFD_KCAN0_BASE 0x10000 50 #define KVASER_PCIEFD_KCAN_BASE_OFFSET 0x1000 51 #define KVASER_PCIEFD_KCAN_FIFO_REG 0x100 52 #define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180 53 #define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0 54 #define KVASER_PCIEFD_KCAN_CMD_REG 0x400 55 #define KVASER_PCIEFD_KCAN_IEN_REG 0x408 56 #define KVASER_PCIEFD_KCAN_IRQ_REG 0x410 57 #define KVASER_PCIEFD_KCAN_TX_NPACKETS_REG 0x414 58 #define KVASER_PCIEFD_KCAN_STAT_REG 0x418 59 #define KVASER_PCIEFD_KCAN_MODE_REG 0x41c 60 #define KVASER_PCIEFD_KCAN_BTRN_REG 0x420 61 #define KVASER_PCIEFD_KCAN_BUS_LOAD_REG 0x424 62 #define KVASER_PCIEFD_KCAN_BTRD_REG 0x428 63 #define KVASER_PCIEFD_KCAN_PWM_REG 0x430 64 /* Loopback control register */ 65 #define KVASER_PCIEFD_LOOP_REG 0x1f000 66 /* System identification and information registers */ 67 #define KVASER_PCIEFD_SYSID_BASE 0x1f020 68 #define KVASER_PCIEFD_SYSID_VERSION_REG (KVASER_PCIEFD_SYSID_BASE + 0x8) 69 #define KVASER_PCIEFD_SYSID_CANFREQ_REG (KVASER_PCIEFD_SYSID_BASE + 0xc) 70 #define KVASER_PCIEFD_SYSID_BUSFREQ_REG (KVASER_PCIEFD_SYSID_BASE + 0x10) 71 #define KVASER_PCIEFD_SYSID_BUILD_REG (KVASER_PCIEFD_SYSID_BASE + 0x14) 72 /* Shared receive buffer registers */ 73 #define KVASER_PCIEFD_SRB_BASE 0x1f200 74 #define KVASER_PCIEFD_SRB_CMD_REG (KVASER_PCIEFD_SRB_BASE + 0x200) 75 #define KVASER_PCIEFD_SRB_IEN_REG (KVASER_PCIEFD_SRB_BASE + 0x204) 76 #define KVASER_PCIEFD_SRB_IRQ_REG (KVASER_PCIEFD_SRB_BASE + 0x20c) 77 #define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210) 78 #define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218) 79 /* EPCS flash controller registers */ 80 #define KVASER_PCIEFD_SPI_BASE 0x1fc00 81 #define KVASER_PCIEFD_SPI_RX_REG KVASER_PCIEFD_SPI_BASE 82 #define KVASER_PCIEFD_SPI_TX_REG (KVASER_PCIEFD_SPI_BASE + 0x4) 83 #define KVASER_PCIEFD_SPI_STATUS_REG (KVASER_PCIEFD_SPI_BASE + 0x8) 84 #define KVASER_PCIEFD_SPI_CTRL_REG (KVASER_PCIEFD_SPI_BASE + 0xc) 85 #define KVASER_PCIEFD_SPI_SSEL_REG (KVASER_PCIEFD_SPI_BASE + 0x14) 86 87 #define KVASER_PCIEFD_IRQ_ALL_MSK 0x1f 88 #define KVASER_PCIEFD_IRQ_SRB BIT(4) 89 90 #define KVASER_PCIEFD_SYSID_NRCHAN_SHIFT 24 91 #define KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT 16 92 #define KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT 1 93 94 /* Reset DMA buffer 0, 1 and FIFO offset */ 95 #define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4) 96 #define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5) 97 #define KVASER_PCIEFD_SRB_CMD_FOR BIT(0) 98 99 /* DMA packet done, buffer 0 and 1 */ 100 #define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8) 101 #define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9) 102 /* DMA overflow, buffer 0 and 1 */ 103 #define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10) 104 #define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11) 105 /* DMA underflow, buffer 0 and 1 */ 106 #define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12) 107 #define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13) 108 109 /* DMA idle */ 110 #define KVASER_PCIEFD_SRB_STAT_DI BIT(15) 111 /* DMA support */ 112 #define KVASER_PCIEFD_SRB_STAT_DMA BIT(24) 113 114 /* DMA Enable */ 115 #define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0) 116 117 /* EPCS flash controller definitions */ 118 #define KVASER_PCIEFD_CFG_IMG_SZ (64 * 1024) 119 #define KVASER_PCIEFD_CFG_IMG_OFFSET (31 * 65536L) 120 #define KVASER_PCIEFD_CFG_MAX_PARAMS 256 121 #define KVASER_PCIEFD_CFG_MAGIC 0xcafef00d 122 #define KVASER_PCIEFD_CFG_PARAM_MAX_SZ 24 123 #define KVASER_PCIEFD_CFG_SYS_VER 1 124 #define KVASER_PCIEFD_CFG_PARAM_NR_CHAN 130 125 #define KVASER_PCIEFD_SPI_TMT BIT(5) 126 #define KVASER_PCIEFD_SPI_TRDY BIT(6) 127 #define KVASER_PCIEFD_SPI_RRDY BIT(7) 128 #define KVASER_PCIEFD_FLASH_ID_EPCS16 0x14 129 /* Commands for controlling the onboard flash */ 130 #define KVASER_PCIEFD_FLASH_RES_CMD 0xab 131 #define KVASER_PCIEFD_FLASH_READ_CMD 0x3 132 #define KVASER_PCIEFD_FLASH_STATUS_CMD 0x5 133 134 /* Kvaser KCAN definitions */ 135 #define KVASER_PCIEFD_KCAN_CTRL_EFLUSH (4 << 29) 136 #define KVASER_PCIEFD_KCAN_CTRL_EFRAME (5 << 29) 137 138 #define KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT 16 139 /* Request status packet */ 140 #define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0) 141 /* Abort, flush and reset */ 142 #define KVASER_PCIEFD_KCAN_CMD_AT BIT(1) 143 144 /* Tx FIFO unaligned read */ 145 #define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0) 146 /* Tx FIFO unaligned end */ 147 #define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1) 148 /* Bus parameter protection error */ 149 #define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2) 150 /* FDF bit when controller is in classic mode */ 151 #define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3) 152 /* Rx FIFO overflow */ 153 #define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5) 154 /* Abort done */ 155 #define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13) 156 /* Tx buffer flush done */ 157 #define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14) 158 /* Tx FIFO overflow */ 159 #define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15) 160 /* Tx FIFO empty */ 161 #define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16) 162 /* Transmitter unaligned */ 163 #define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17) 164 165 #define KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT 16 166 167 #define KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT 24 168 /* Abort request */ 169 #define KVASER_PCIEFD_KCAN_STAT_AR BIT(7) 170 /* Idle state. Controller in reset mode and no abort or flush pending */ 171 #define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10) 172 /* Bus off */ 173 #define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11) 174 /* Reset mode request */ 175 #define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14) 176 /* Controller in reset mode */ 177 #define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15) 178 /* Controller got one-shot capability */ 179 #define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16) 180 /* Controller got CAN FD capability */ 181 #define KVASER_PCIEFD_KCAN_STAT_FD BIT(19) 182 #define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK (KVASER_PCIEFD_KCAN_STAT_AR | \ 183 KVASER_PCIEFD_KCAN_STAT_BOFF | KVASER_PCIEFD_KCAN_STAT_RMR | \ 184 KVASER_PCIEFD_KCAN_STAT_IRM) 185 186 /* Reset mode */ 187 #define KVASER_PCIEFD_KCAN_MODE_RM BIT(8) 188 /* Listen only mode */ 189 #define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9) 190 /* Error packet enable */ 191 #define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12) 192 /* CAN FD non-ISO */ 193 #define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15) 194 /* Acknowledgment packet type */ 195 #define KVASER_PCIEFD_KCAN_MODE_APT BIT(20) 196 /* Active error flag enable. Clear to force error passive */ 197 #define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23) 198 /* Classic CAN mode */ 199 #define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31) 200 201 #define KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT 13 202 #define KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT 17 203 #define KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT 26 204 205 #define KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT 16 206 207 /* Kvaser KCAN packet types */ 208 #define KVASER_PCIEFD_PACK_TYPE_DATA 0 209 #define KVASER_PCIEFD_PACK_TYPE_ACK 1 210 #define KVASER_PCIEFD_PACK_TYPE_TXRQ 2 211 #define KVASER_PCIEFD_PACK_TYPE_ERROR 3 212 #define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 4 213 #define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 5 214 #define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 6 215 #define KVASER_PCIEFD_PACK_TYPE_STATUS 8 216 #define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 9 217 218 /* Kvaser KCAN packet common definitions */ 219 #define KVASER_PCIEFD_PACKET_SEQ_MSK 0xff 220 #define KVASER_PCIEFD_PACKET_CHID_SHIFT 25 221 #define KVASER_PCIEFD_PACKET_TYPE_SHIFT 28 222 223 /* Kvaser KCAN TDATA and RDATA first word */ 224 #define KVASER_PCIEFD_RPACKET_IDE BIT(30) 225 #define KVASER_PCIEFD_RPACKET_RTR BIT(29) 226 /* Kvaser KCAN TDATA and RDATA second word */ 227 #define KVASER_PCIEFD_RPACKET_ESI BIT(13) 228 #define KVASER_PCIEFD_RPACKET_BRS BIT(14) 229 #define KVASER_PCIEFD_RPACKET_FDF BIT(15) 230 #define KVASER_PCIEFD_RPACKET_DLC_SHIFT 8 231 /* Kvaser KCAN TDATA second word */ 232 #define KVASER_PCIEFD_TPACKET_SMS BIT(16) 233 #define KVASER_PCIEFD_TPACKET_AREQ BIT(31) 234 235 /* Kvaser KCAN APACKET */ 236 #define KVASER_PCIEFD_APACKET_FLU BIT(8) 237 #define KVASER_PCIEFD_APACKET_CT BIT(9) 238 #define KVASER_PCIEFD_APACKET_ABL BIT(10) 239 #define KVASER_PCIEFD_APACKET_NACK BIT(11) 240 241 /* Kvaser KCAN SPACK first word */ 242 #define KVASER_PCIEFD_SPACK_RXERR_SHIFT 8 243 #define KVASER_PCIEFD_SPACK_BOFF BIT(16) 244 #define KVASER_PCIEFD_SPACK_IDET BIT(20) 245 #define KVASER_PCIEFD_SPACK_IRM BIT(21) 246 #define KVASER_PCIEFD_SPACK_RMCD BIT(22) 247 /* Kvaser KCAN SPACK second word */ 248 #define KVASER_PCIEFD_SPACK_AUTO BIT(21) 249 #define KVASER_PCIEFD_SPACK_EWLR BIT(23) 250 #define KVASER_PCIEFD_SPACK_EPLR BIT(24) 251 252 /* Kvaser KCAN_EPACK second word */ 253 #define KVASER_PCIEFD_EPACK_DIR_TX BIT(0) 254 255 struct kvaser_pciefd; 256 257 struct kvaser_pciefd_can { 258 struct can_priv can; 259 struct kvaser_pciefd *kv_pcie; 260 void __iomem *reg_base; 261 struct can_berr_counter bec; 262 u8 cmd_seq; 263 int err_rep_cnt; 264 int echo_idx; 265 spinlock_t lock; /* Locks sensitive registers (e.g. MODE) */ 266 spinlock_t echo_lock; /* Locks the message echo buffer */ 267 struct timer_list bec_poll_timer; 268 struct completion start_comp, flush_comp; 269 }; 270 271 struct kvaser_pciefd { 272 struct pci_dev *pci; 273 void __iomem *reg_base; 274 struct kvaser_pciefd_can *can[KVASER_PCIEFD_MAX_CAN_CHANNELS]; 275 void *dma_data[KVASER_PCIEFD_DMA_COUNT]; 276 u8 nr_channels; 277 u32 bus_freq; 278 u32 freq; 279 u32 freq_to_ticks_div; 280 }; 281 282 struct kvaser_pciefd_rx_packet { 283 u32 header[2]; 284 u64 timestamp; 285 }; 286 287 struct kvaser_pciefd_tx_packet { 288 u32 header[2]; 289 u8 data[64]; 290 }; 291 292 static const struct can_bittiming_const kvaser_pciefd_bittiming_const = { 293 .name = KVASER_PCIEFD_DRV_NAME, 294 .tseg1_min = 1, 295 .tseg1_max = 512, 296 .tseg2_min = 1, 297 .tseg2_max = 32, 298 .sjw_max = 16, 299 .brp_min = 1, 300 .brp_max = 8192, 301 .brp_inc = 1, 302 }; 303 304 struct kvaser_pciefd_cfg_param { 305 __le32 magic; 306 __le32 nr; 307 __le32 len; 308 u8 data[KVASER_PCIEFD_CFG_PARAM_MAX_SZ]; 309 }; 310 311 struct kvaser_pciefd_cfg_img { 312 __le32 version; 313 __le32 magic; 314 __le32 crc; 315 struct kvaser_pciefd_cfg_param params[KVASER_PCIEFD_CFG_MAX_PARAMS]; 316 }; 317 318 static struct pci_device_id kvaser_pciefd_id_table[] = { 319 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_ID), }, 320 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_ID), }, 321 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_ID), }, 322 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_ID), }, 323 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_ID), }, 324 { 0,}, 325 }; 326 MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table); 327 328 /* Onboard flash memory functions */ 329 static int kvaser_pciefd_spi_wait_loop(struct kvaser_pciefd *pcie, int msk) 330 { 331 u32 res; 332 333 return readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG, 334 res, res & msk, 0, 10); 335 } 336 337 static int kvaser_pciefd_spi_cmd(struct kvaser_pciefd *pcie, const u8 *tx, 338 u32 tx_len, u8 *rx, u32 rx_len) 339 { 340 int c; 341 342 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG); 343 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG); 344 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); 345 346 c = tx_len; 347 while (c--) { 348 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY)) 349 return -EIO; 350 351 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); 352 353 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY)) 354 return -EIO; 355 356 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); 357 } 358 359 c = rx_len; 360 while (c-- > 0) { 361 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY)) 362 return -EIO; 363 364 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); 365 366 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY)) 367 return -EIO; 368 369 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); 370 } 371 372 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TMT)) 373 return -EIO; 374 375 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG); 376 377 if (c != -1) { 378 dev_err(&pcie->pci->dev, "Flash SPI transfer failed\n"); 379 return -EIO; 380 } 381 382 return 0; 383 } 384 385 static int kvaser_pciefd_cfg_read_and_verify(struct kvaser_pciefd *pcie, 386 struct kvaser_pciefd_cfg_img *img) 387 { 388 int offset = KVASER_PCIEFD_CFG_IMG_OFFSET; 389 int res, crc; 390 u8 *crc_buff; 391 392 u8 cmd[] = { 393 KVASER_PCIEFD_FLASH_READ_CMD, 394 (u8)((offset >> 16) & 0xff), 395 (u8)((offset >> 8) & 0xff), 396 (u8)(offset & 0xff) 397 }; 398 399 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), (u8 *)img, 400 KVASER_PCIEFD_CFG_IMG_SZ); 401 if (res) 402 return res; 403 404 crc_buff = (u8 *)img->params; 405 406 if (le32_to_cpu(img->version) != KVASER_PCIEFD_CFG_SYS_VER) { 407 dev_err(&pcie->pci->dev, 408 "Config flash corrupted, version number is wrong\n"); 409 return -ENODEV; 410 } 411 412 if (le32_to_cpu(img->magic) != KVASER_PCIEFD_CFG_MAGIC) { 413 dev_err(&pcie->pci->dev, 414 "Config flash corrupted, magic number is wrong\n"); 415 return -ENODEV; 416 } 417 418 crc = ~crc32_be(0xffffffff, crc_buff, sizeof(img->params)); 419 if (le32_to_cpu(img->crc) != crc) { 420 dev_err(&pcie->pci->dev, 421 "Stored CRC does not match flash image contents\n"); 422 return -EIO; 423 } 424 425 return 0; 426 } 427 428 static void kvaser_pciefd_cfg_read_params(struct kvaser_pciefd *pcie, 429 struct kvaser_pciefd_cfg_img *img) 430 { 431 struct kvaser_pciefd_cfg_param *param; 432 433 param = &img->params[KVASER_PCIEFD_CFG_PARAM_NR_CHAN]; 434 memcpy(&pcie->nr_channels, param->data, le32_to_cpu(param->len)); 435 } 436 437 static int kvaser_pciefd_read_cfg(struct kvaser_pciefd *pcie) 438 { 439 int res; 440 struct kvaser_pciefd_cfg_img *img; 441 442 /* Read electronic signature */ 443 u8 cmd[] = {KVASER_PCIEFD_FLASH_RES_CMD, 0, 0, 0}; 444 445 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), cmd, 1); 446 if (res) 447 return -EIO; 448 449 img = kmalloc(KVASER_PCIEFD_CFG_IMG_SZ, GFP_KERNEL); 450 if (!img) 451 return -ENOMEM; 452 453 if (cmd[0] != KVASER_PCIEFD_FLASH_ID_EPCS16) { 454 dev_err(&pcie->pci->dev, 455 "Flash id is 0x%x instead of expected EPCS16 (0x%x)\n", 456 cmd[0], KVASER_PCIEFD_FLASH_ID_EPCS16); 457 458 res = -ENODEV; 459 goto image_free; 460 } 461 462 cmd[0] = KVASER_PCIEFD_FLASH_STATUS_CMD; 463 res = kvaser_pciefd_spi_cmd(pcie, cmd, 1, cmd, 1); 464 if (res) { 465 goto image_free; 466 } else if (cmd[0] & 1) { 467 res = -EIO; 468 /* No write is ever done, the WIP should never be set */ 469 dev_err(&pcie->pci->dev, "Unexpected WIP bit set in flash\n"); 470 goto image_free; 471 } 472 473 res = kvaser_pciefd_cfg_read_and_verify(pcie, img); 474 if (res) { 475 res = -EIO; 476 goto image_free; 477 } 478 479 kvaser_pciefd_cfg_read_params(pcie, img); 480 481 image_free: 482 kfree(img); 483 return res; 484 } 485 486 static void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can) 487 { 488 u32 cmd; 489 490 cmd = KVASER_PCIEFD_KCAN_CMD_SRQ; 491 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT; 492 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); 493 } 494 495 static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can) 496 { 497 u32 mode; 498 unsigned long irq; 499 500 spin_lock_irqsave(&can->lock, irq); 501 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 502 if (!(mode & KVASER_PCIEFD_KCAN_MODE_EPEN)) { 503 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN; 504 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 505 } 506 spin_unlock_irqrestore(&can->lock, irq); 507 } 508 509 static void kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can *can) 510 { 511 u32 mode; 512 unsigned long irq; 513 514 spin_lock_irqsave(&can->lock, irq); 515 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 516 mode &= ~KVASER_PCIEFD_KCAN_MODE_EPEN; 517 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 518 spin_unlock_irqrestore(&can->lock, irq); 519 } 520 521 static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can) 522 { 523 u32 msk; 524 525 msk = KVASER_PCIEFD_KCAN_IRQ_TE | KVASER_PCIEFD_KCAN_IRQ_ROF | 526 KVASER_PCIEFD_KCAN_IRQ_TOF | KVASER_PCIEFD_KCAN_IRQ_ABD | 527 KVASER_PCIEFD_KCAN_IRQ_TAE | KVASER_PCIEFD_KCAN_IRQ_TAL | 528 KVASER_PCIEFD_KCAN_IRQ_FDIC | KVASER_PCIEFD_KCAN_IRQ_BPP | 529 KVASER_PCIEFD_KCAN_IRQ_TAR | KVASER_PCIEFD_KCAN_IRQ_TFD; 530 531 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 532 533 return 0; 534 } 535 536 static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can) 537 { 538 u32 mode; 539 unsigned long irq; 540 541 spin_lock_irqsave(&can->lock, irq); 542 543 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 544 if (can->can.ctrlmode & CAN_CTRLMODE_FD) { 545 mode &= ~KVASER_PCIEFD_KCAN_MODE_CCM; 546 if (can->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 547 mode |= KVASER_PCIEFD_KCAN_MODE_NIFDEN; 548 else 549 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN; 550 } else { 551 mode |= KVASER_PCIEFD_KCAN_MODE_CCM; 552 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN; 553 } 554 555 if (can->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 556 mode |= KVASER_PCIEFD_KCAN_MODE_LOM; 557 558 mode |= KVASER_PCIEFD_KCAN_MODE_EEN; 559 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN; 560 /* Use ACK packet type */ 561 mode &= ~KVASER_PCIEFD_KCAN_MODE_APT; 562 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM; 563 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 564 565 spin_unlock_irqrestore(&can->lock, irq); 566 } 567 568 static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can) 569 { 570 u32 status; 571 unsigned long irq; 572 573 spin_lock_irqsave(&can->lock, irq); 574 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 575 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD, 576 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 577 578 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG); 579 if (status & KVASER_PCIEFD_KCAN_STAT_IDLE) { 580 u32 cmd; 581 582 /* If controller is already idle, run abort, flush and reset */ 583 cmd = KVASER_PCIEFD_KCAN_CMD_AT; 584 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT; 585 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); 586 } else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) { 587 u32 mode; 588 589 /* Put controller in reset mode */ 590 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 591 mode |= KVASER_PCIEFD_KCAN_MODE_RM; 592 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 593 } 594 595 spin_unlock_irqrestore(&can->lock, irq); 596 } 597 598 static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) 599 { 600 u32 mode; 601 unsigned long irq; 602 603 del_timer(&can->bec_poll_timer); 604 605 if (!completion_done(&can->flush_comp)) 606 kvaser_pciefd_start_controller_flush(can); 607 608 if (!wait_for_completion_timeout(&can->flush_comp, 609 KVASER_PCIEFD_WAIT_TIMEOUT)) { 610 netdev_err(can->can.dev, "Timeout during bus on flush\n"); 611 return -ETIMEDOUT; 612 } 613 614 spin_lock_irqsave(&can->lock, irq); 615 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 616 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 617 618 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD, 619 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 620 621 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 622 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM; 623 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 624 spin_unlock_irqrestore(&can->lock, irq); 625 626 if (!wait_for_completion_timeout(&can->start_comp, 627 KVASER_PCIEFD_WAIT_TIMEOUT)) { 628 netdev_err(can->can.dev, "Timeout during bus on reset\n"); 629 return -ETIMEDOUT; 630 } 631 /* Reset interrupt handling */ 632 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 633 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 634 635 kvaser_pciefd_set_tx_irq(can); 636 kvaser_pciefd_setup_controller(can); 637 638 can->can.state = CAN_STATE_ERROR_ACTIVE; 639 netif_wake_queue(can->can.dev); 640 can->bec.txerr = 0; 641 can->bec.rxerr = 0; 642 can->err_rep_cnt = 0; 643 644 return 0; 645 } 646 647 static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can) 648 { 649 u8 top; 650 u32 pwm_ctrl; 651 unsigned long irq; 652 653 spin_lock_irqsave(&can->lock, irq); 654 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); 655 top = (pwm_ctrl >> KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT) & 0xff; 656 657 /* Set duty cycle to zero */ 658 pwm_ctrl |= top; 659 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); 660 spin_unlock_irqrestore(&can->lock, irq); 661 } 662 663 static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can) 664 { 665 int top, trigger; 666 u32 pwm_ctrl; 667 unsigned long irq; 668 669 kvaser_pciefd_pwm_stop(can); 670 spin_lock_irqsave(&can->lock, irq); 671 672 /* Set frequency to 500 KHz*/ 673 top = can->kv_pcie->bus_freq / (2 * 500000) - 1; 674 675 pwm_ctrl = top & 0xff; 676 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT; 677 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); 678 679 /* Set duty cycle to 95 */ 680 trigger = (100 * top - 95 * (top + 1) + 50) / 100; 681 pwm_ctrl = trigger & 0xff; 682 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT; 683 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); 684 spin_unlock_irqrestore(&can->lock, irq); 685 } 686 687 static int kvaser_pciefd_open(struct net_device *netdev) 688 { 689 int err; 690 struct kvaser_pciefd_can *can = netdev_priv(netdev); 691 692 err = open_candev(netdev); 693 if (err) 694 return err; 695 696 err = kvaser_pciefd_bus_on(can); 697 if (err) { 698 close_candev(netdev); 699 return err; 700 } 701 702 return 0; 703 } 704 705 static int kvaser_pciefd_stop(struct net_device *netdev) 706 { 707 struct kvaser_pciefd_can *can = netdev_priv(netdev); 708 int ret = 0; 709 710 /* Don't interrupt ongoing flush */ 711 if (!completion_done(&can->flush_comp)) 712 kvaser_pciefd_start_controller_flush(can); 713 714 if (!wait_for_completion_timeout(&can->flush_comp, 715 KVASER_PCIEFD_WAIT_TIMEOUT)) { 716 netdev_err(can->can.dev, "Timeout during stop\n"); 717 ret = -ETIMEDOUT; 718 } else { 719 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 720 del_timer(&can->bec_poll_timer); 721 } 722 close_candev(netdev); 723 724 return ret; 725 } 726 727 static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p, 728 struct kvaser_pciefd_can *can, 729 struct sk_buff *skb) 730 { 731 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 732 int packet_size; 733 int seq = can->echo_idx; 734 735 memset(p, 0, sizeof(*p)); 736 737 if (can->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 738 p->header[1] |= KVASER_PCIEFD_TPACKET_SMS; 739 740 if (cf->can_id & CAN_RTR_FLAG) 741 p->header[0] |= KVASER_PCIEFD_RPACKET_RTR; 742 743 if (cf->can_id & CAN_EFF_FLAG) 744 p->header[0] |= KVASER_PCIEFD_RPACKET_IDE; 745 746 p->header[0] |= cf->can_id & CAN_EFF_MASK; 747 p->header[1] |= can_fd_len2dlc(cf->len) << KVASER_PCIEFD_RPACKET_DLC_SHIFT; 748 p->header[1] |= KVASER_PCIEFD_TPACKET_AREQ; 749 750 if (can_is_canfd_skb(skb)) { 751 p->header[1] |= KVASER_PCIEFD_RPACKET_FDF; 752 if (cf->flags & CANFD_BRS) 753 p->header[1] |= KVASER_PCIEFD_RPACKET_BRS; 754 if (cf->flags & CANFD_ESI) 755 p->header[1] |= KVASER_PCIEFD_RPACKET_ESI; 756 } 757 758 p->header[1] |= seq & KVASER_PCIEFD_PACKET_SEQ_MSK; 759 760 packet_size = cf->len; 761 memcpy(p->data, cf->data, packet_size); 762 763 return DIV_ROUND_UP(packet_size, 4); 764 } 765 766 static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, 767 struct net_device *netdev) 768 { 769 struct kvaser_pciefd_can *can = netdev_priv(netdev); 770 unsigned long irq_flags; 771 struct kvaser_pciefd_tx_packet packet; 772 int nwords; 773 u8 count; 774 775 if (can_dropped_invalid_skb(netdev, skb)) 776 return NETDEV_TX_OK; 777 778 nwords = kvaser_pciefd_prepare_tx_packet(&packet, can, skb); 779 780 spin_lock_irqsave(&can->echo_lock, irq_flags); 781 782 /* Prepare and save echo skb in internal slot */ 783 can_put_echo_skb(skb, netdev, can->echo_idx, 0); 784 785 /* Move echo index to the next slot */ 786 can->echo_idx = (can->echo_idx + 1) % can->can.echo_skb_max; 787 788 /* Write header to fifo */ 789 iowrite32(packet.header[0], 790 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG); 791 iowrite32(packet.header[1], 792 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG); 793 794 if (nwords) { 795 u32 data_last = ((u32 *)packet.data)[nwords - 1]; 796 797 /* Write data to fifo, except last word */ 798 iowrite32_rep(can->reg_base + 799 KVASER_PCIEFD_KCAN_FIFO_REG, packet.data, 800 nwords - 1); 801 /* Write last word to end of fifo */ 802 __raw_writel(data_last, can->reg_base + 803 KVASER_PCIEFD_KCAN_FIFO_LAST_REG); 804 } else { 805 /* Complete write to fifo */ 806 __raw_writel(0, can->reg_base + 807 KVASER_PCIEFD_KCAN_FIFO_LAST_REG); 808 } 809 810 count = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG); 811 /* No room for a new message, stop the queue until at least one 812 * successful transmit 813 */ 814 if (count >= KVASER_PCIEFD_CAN_TX_MAX_COUNT || 815 can->can.echo_skb[can->echo_idx]) 816 netif_stop_queue(netdev); 817 818 spin_unlock_irqrestore(&can->echo_lock, irq_flags); 819 820 return NETDEV_TX_OK; 821 } 822 823 static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data) 824 { 825 u32 mode, test, btrn; 826 unsigned long irq_flags; 827 int ret; 828 struct can_bittiming *bt; 829 830 if (data) 831 bt = &can->can.data_bittiming; 832 else 833 bt = &can->can.bittiming; 834 835 btrn = ((bt->phase_seg2 - 1) & 0x1f) << 836 KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT | 837 (((bt->prop_seg + bt->phase_seg1) - 1) & 0x1ff) << 838 KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT | 839 ((bt->sjw - 1) & 0xf) << KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT | 840 ((bt->brp - 1) & 0x1fff); 841 842 spin_lock_irqsave(&can->lock, irq_flags); 843 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 844 845 /* Put the circuit in reset mode */ 846 iowrite32(mode | KVASER_PCIEFD_KCAN_MODE_RM, 847 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 848 849 /* Can only set bittiming if in reset mode */ 850 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG, 851 test, test & KVASER_PCIEFD_KCAN_MODE_RM, 852 0, 10); 853 854 if (ret) { 855 spin_unlock_irqrestore(&can->lock, irq_flags); 856 return -EBUSY; 857 } 858 859 if (data) 860 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG); 861 else 862 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG); 863 864 /* Restore previous reset mode status */ 865 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 866 867 spin_unlock_irqrestore(&can->lock, irq_flags); 868 return 0; 869 } 870 871 static int kvaser_pciefd_set_nominal_bittiming(struct net_device *ndev) 872 { 873 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), false); 874 } 875 876 static int kvaser_pciefd_set_data_bittiming(struct net_device *ndev) 877 { 878 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), true); 879 } 880 881 static int kvaser_pciefd_set_mode(struct net_device *ndev, enum can_mode mode) 882 { 883 struct kvaser_pciefd_can *can = netdev_priv(ndev); 884 int ret = 0; 885 886 switch (mode) { 887 case CAN_MODE_START: 888 if (!can->can.restart_ms) 889 ret = kvaser_pciefd_bus_on(can); 890 break; 891 default: 892 return -EOPNOTSUPP; 893 } 894 895 return ret; 896 } 897 898 static int kvaser_pciefd_get_berr_counter(const struct net_device *ndev, 899 struct can_berr_counter *bec) 900 { 901 struct kvaser_pciefd_can *can = netdev_priv(ndev); 902 903 bec->rxerr = can->bec.rxerr; 904 bec->txerr = can->bec.txerr; 905 return 0; 906 } 907 908 static void kvaser_pciefd_bec_poll_timer(struct timer_list *data) 909 { 910 struct kvaser_pciefd_can *can = from_timer(can, data, bec_poll_timer); 911 912 kvaser_pciefd_enable_err_gen(can); 913 kvaser_pciefd_request_status(can); 914 can->err_rep_cnt = 0; 915 } 916 917 static const struct net_device_ops kvaser_pciefd_netdev_ops = { 918 .ndo_open = kvaser_pciefd_open, 919 .ndo_stop = kvaser_pciefd_stop, 920 .ndo_eth_ioctl = can_eth_ioctl_hwts, 921 .ndo_start_xmit = kvaser_pciefd_start_xmit, 922 .ndo_change_mtu = can_change_mtu, 923 }; 924 925 static const struct ethtool_ops kvaser_pciefd_ethtool_ops = { 926 .get_ts_info = can_ethtool_op_get_ts_info_hwts, 927 }; 928 929 static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) 930 { 931 int i; 932 933 for (i = 0; i < pcie->nr_channels; i++) { 934 struct net_device *netdev; 935 struct kvaser_pciefd_can *can; 936 u32 status, tx_npackets; 937 938 netdev = alloc_candev(sizeof(struct kvaser_pciefd_can), 939 KVASER_PCIEFD_CAN_TX_MAX_COUNT); 940 if (!netdev) 941 return -ENOMEM; 942 943 can = netdev_priv(netdev); 944 netdev->netdev_ops = &kvaser_pciefd_netdev_ops; 945 netdev->ethtool_ops = &kvaser_pciefd_ethtool_ops; 946 can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE + 947 i * KVASER_PCIEFD_KCAN_BASE_OFFSET; 948 949 can->kv_pcie = pcie; 950 can->cmd_seq = 0; 951 can->err_rep_cnt = 0; 952 can->bec.txerr = 0; 953 can->bec.rxerr = 0; 954 955 init_completion(&can->start_comp); 956 init_completion(&can->flush_comp); 957 timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer, 958 0); 959 960 /* Disable Bus load reporting */ 961 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG); 962 963 tx_npackets = ioread32(can->reg_base + 964 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG); 965 if (((tx_npackets >> KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT) & 966 0xff) < KVASER_PCIEFD_CAN_TX_MAX_COUNT) { 967 dev_err(&pcie->pci->dev, 968 "Max Tx count is smaller than expected\n"); 969 970 free_candev(netdev); 971 return -ENODEV; 972 } 973 974 can->can.clock.freq = pcie->freq; 975 can->can.echo_skb_max = KVASER_PCIEFD_CAN_TX_MAX_COUNT; 976 can->echo_idx = 0; 977 spin_lock_init(&can->echo_lock); 978 spin_lock_init(&can->lock); 979 can->can.bittiming_const = &kvaser_pciefd_bittiming_const; 980 can->can.data_bittiming_const = &kvaser_pciefd_bittiming_const; 981 982 can->can.do_set_bittiming = kvaser_pciefd_set_nominal_bittiming; 983 can->can.do_set_data_bittiming = 984 kvaser_pciefd_set_data_bittiming; 985 986 can->can.do_set_mode = kvaser_pciefd_set_mode; 987 can->can.do_get_berr_counter = kvaser_pciefd_get_berr_counter; 988 989 can->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | 990 CAN_CTRLMODE_FD | 991 CAN_CTRLMODE_FD_NON_ISO; 992 993 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG); 994 if (!(status & KVASER_PCIEFD_KCAN_STAT_FD)) { 995 dev_err(&pcie->pci->dev, 996 "CAN FD not supported as expected %d\n", i); 997 998 free_candev(netdev); 999 return -ENODEV; 1000 } 1001 1002 if (status & KVASER_PCIEFD_KCAN_STAT_CAP) 1003 can->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT; 1004 1005 netdev->flags |= IFF_ECHO; 1006 1007 SET_NETDEV_DEV(netdev, &pcie->pci->dev); 1008 1009 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 1010 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | 1011 KVASER_PCIEFD_KCAN_IRQ_TFD, 1012 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 1013 1014 pcie->can[i] = can; 1015 kvaser_pciefd_pwm_start(can); 1016 } 1017 1018 return 0; 1019 } 1020 1021 static int kvaser_pciefd_reg_candev(struct kvaser_pciefd *pcie) 1022 { 1023 int i; 1024 1025 for (i = 0; i < pcie->nr_channels; i++) { 1026 int err = register_candev(pcie->can[i]->can.dev); 1027 1028 if (err) { 1029 int j; 1030 1031 /* Unregister all successfully registered devices. */ 1032 for (j = 0; j < i; j++) 1033 unregister_candev(pcie->can[j]->can.dev); 1034 return err; 1035 } 1036 } 1037 1038 return 0; 1039 } 1040 1041 static void kvaser_pciefd_write_dma_map(struct kvaser_pciefd *pcie, 1042 dma_addr_t addr, int offset) 1043 { 1044 u32 word1, word2; 1045 1046 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1047 word1 = addr | KVASER_PCIEFD_64BIT_DMA_BIT; 1048 word2 = addr >> 32; 1049 #else 1050 word1 = addr; 1051 word2 = 0; 1052 #endif 1053 iowrite32(word1, pcie->reg_base + offset); 1054 iowrite32(word2, pcie->reg_base + offset + 4); 1055 } 1056 1057 static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) 1058 { 1059 int i; 1060 u32 srb_status; 1061 dma_addr_t dma_addr[KVASER_PCIEFD_DMA_COUNT]; 1062 1063 /* Disable the DMA */ 1064 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); 1065 for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) { 1066 unsigned int offset = KVASER_PCIEFD_DMA_MAP_BASE + 8 * i; 1067 1068 pcie->dma_data[i] = 1069 dmam_alloc_coherent(&pcie->pci->dev, 1070 KVASER_PCIEFD_DMA_SIZE, 1071 &dma_addr[i], 1072 GFP_KERNEL); 1073 1074 if (!pcie->dma_data[i] || !dma_addr[i]) { 1075 dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n", 1076 KVASER_PCIEFD_DMA_SIZE); 1077 return -ENOMEM; 1078 } 1079 1080 kvaser_pciefd_write_dma_map(pcie, dma_addr[i], offset); 1081 } 1082 1083 /* Reset Rx FIFO, and both DMA buffers */ 1084 iowrite32(KVASER_PCIEFD_SRB_CMD_FOR | KVASER_PCIEFD_SRB_CMD_RDB0 | 1085 KVASER_PCIEFD_SRB_CMD_RDB1, 1086 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1087 1088 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG); 1089 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI)) { 1090 dev_err(&pcie->pci->dev, "DMA not idle before enabling\n"); 1091 return -EIO; 1092 } 1093 1094 /* Enable the DMA */ 1095 iowrite32(KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE, 1096 pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); 1097 1098 return 0; 1099 } 1100 1101 static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie) 1102 { 1103 u32 sysid, srb_status, build; 1104 u8 sysid_nr_chan; 1105 int ret; 1106 1107 ret = kvaser_pciefd_read_cfg(pcie); 1108 if (ret) 1109 return ret; 1110 1111 sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG); 1112 sysid_nr_chan = (sysid >> KVASER_PCIEFD_SYSID_NRCHAN_SHIFT) & 0xff; 1113 if (pcie->nr_channels != sysid_nr_chan) { 1114 dev_err(&pcie->pci->dev, 1115 "Number of channels does not match: %u vs %u\n", 1116 pcie->nr_channels, 1117 sysid_nr_chan); 1118 return -ENODEV; 1119 } 1120 1121 if (pcie->nr_channels > KVASER_PCIEFD_MAX_CAN_CHANNELS) 1122 pcie->nr_channels = KVASER_PCIEFD_MAX_CAN_CHANNELS; 1123 1124 build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG); 1125 dev_dbg(&pcie->pci->dev, "Version %u.%u.%u\n", 1126 (sysid >> KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT) & 0xff, 1127 sysid & 0xff, 1128 (build >> KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT) & 0x7fff); 1129 1130 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG); 1131 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) { 1132 dev_err(&pcie->pci->dev, 1133 "Hardware without DMA is not supported\n"); 1134 return -ENODEV; 1135 } 1136 1137 pcie->bus_freq = ioread32(pcie->reg_base + 1138 KVASER_PCIEFD_SYSID_BUSFREQ_REG); 1139 pcie->freq = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_CANFREQ_REG); 1140 pcie->freq_to_ticks_div = pcie->freq / 1000000; 1141 if (pcie->freq_to_ticks_div == 0) 1142 pcie->freq_to_ticks_div = 1; 1143 1144 /* Turn off all loopback functionality */ 1145 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG); 1146 return ret; 1147 } 1148 1149 static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie, 1150 struct kvaser_pciefd_rx_packet *p, 1151 __le32 *data) 1152 { 1153 struct sk_buff *skb; 1154 struct canfd_frame *cf; 1155 struct can_priv *priv; 1156 struct net_device_stats *stats; 1157 struct skb_shared_hwtstamps *shhwtstamps; 1158 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1159 1160 if (ch_id >= pcie->nr_channels) 1161 return -EIO; 1162 1163 priv = &pcie->can[ch_id]->can; 1164 stats = &priv->dev->stats; 1165 1166 if (p->header[1] & KVASER_PCIEFD_RPACKET_FDF) { 1167 skb = alloc_canfd_skb(priv->dev, &cf); 1168 if (!skb) { 1169 stats->rx_dropped++; 1170 return -ENOMEM; 1171 } 1172 1173 if (p->header[1] & KVASER_PCIEFD_RPACKET_BRS) 1174 cf->flags |= CANFD_BRS; 1175 1176 if (p->header[1] & KVASER_PCIEFD_RPACKET_ESI) 1177 cf->flags |= CANFD_ESI; 1178 } else { 1179 skb = alloc_can_skb(priv->dev, (struct can_frame **)&cf); 1180 if (!skb) { 1181 stats->rx_dropped++; 1182 return -ENOMEM; 1183 } 1184 } 1185 1186 cf->can_id = p->header[0] & CAN_EFF_MASK; 1187 if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE) 1188 cf->can_id |= CAN_EFF_FLAG; 1189 1190 cf->len = can_fd_dlc2len(p->header[1] >> KVASER_PCIEFD_RPACKET_DLC_SHIFT); 1191 1192 if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR) { 1193 cf->can_id |= CAN_RTR_FLAG; 1194 } else { 1195 memcpy(cf->data, data, cf->len); 1196 1197 stats->rx_bytes += cf->len; 1198 } 1199 stats->rx_packets++; 1200 1201 shhwtstamps = skb_hwtstamps(skb); 1202 1203 shhwtstamps->hwtstamp = 1204 ns_to_ktime(div_u64(p->timestamp * 1000, 1205 pcie->freq_to_ticks_div)); 1206 1207 return netif_rx(skb); 1208 } 1209 1210 static void kvaser_pciefd_change_state(struct kvaser_pciefd_can *can, 1211 struct can_frame *cf, 1212 enum can_state new_state, 1213 enum can_state tx_state, 1214 enum can_state rx_state) 1215 { 1216 can_change_state(can->can.dev, cf, tx_state, rx_state); 1217 1218 if (new_state == CAN_STATE_BUS_OFF) { 1219 struct net_device *ndev = can->can.dev; 1220 unsigned long irq_flags; 1221 1222 spin_lock_irqsave(&can->lock, irq_flags); 1223 netif_stop_queue(can->can.dev); 1224 spin_unlock_irqrestore(&can->lock, irq_flags); 1225 1226 /* Prevent CAN controller from auto recover from bus off */ 1227 if (!can->can.restart_ms) { 1228 kvaser_pciefd_start_controller_flush(can); 1229 can_bus_off(ndev); 1230 } 1231 } 1232 } 1233 1234 static void kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet *p, 1235 struct can_berr_counter *bec, 1236 enum can_state *new_state, 1237 enum can_state *tx_state, 1238 enum can_state *rx_state) 1239 { 1240 if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF || 1241 p->header[0] & KVASER_PCIEFD_SPACK_IRM) 1242 *new_state = CAN_STATE_BUS_OFF; 1243 else if (bec->txerr >= 255 || bec->rxerr >= 255) 1244 *new_state = CAN_STATE_BUS_OFF; 1245 else if (p->header[1] & KVASER_PCIEFD_SPACK_EPLR) 1246 *new_state = CAN_STATE_ERROR_PASSIVE; 1247 else if (bec->txerr >= 128 || bec->rxerr >= 128) 1248 *new_state = CAN_STATE_ERROR_PASSIVE; 1249 else if (p->header[1] & KVASER_PCIEFD_SPACK_EWLR) 1250 *new_state = CAN_STATE_ERROR_WARNING; 1251 else if (bec->txerr >= 96 || bec->rxerr >= 96) 1252 *new_state = CAN_STATE_ERROR_WARNING; 1253 else 1254 *new_state = CAN_STATE_ERROR_ACTIVE; 1255 1256 *tx_state = bec->txerr >= bec->rxerr ? *new_state : 0; 1257 *rx_state = bec->txerr <= bec->rxerr ? *new_state : 0; 1258 } 1259 1260 static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can, 1261 struct kvaser_pciefd_rx_packet *p) 1262 { 1263 struct can_berr_counter bec; 1264 enum can_state old_state, new_state, tx_state, rx_state; 1265 struct net_device *ndev = can->can.dev; 1266 struct sk_buff *skb; 1267 struct can_frame *cf = NULL; 1268 struct skb_shared_hwtstamps *shhwtstamps; 1269 struct net_device_stats *stats = &ndev->stats; 1270 1271 old_state = can->can.state; 1272 1273 bec.txerr = p->header[0] & 0xff; 1274 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff; 1275 1276 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, 1277 &rx_state); 1278 1279 skb = alloc_can_err_skb(ndev, &cf); 1280 1281 if (new_state != old_state) { 1282 kvaser_pciefd_change_state(can, cf, new_state, tx_state, 1283 rx_state); 1284 1285 if (old_state == CAN_STATE_BUS_OFF && 1286 new_state == CAN_STATE_ERROR_ACTIVE && 1287 can->can.restart_ms) { 1288 can->can.can_stats.restarts++; 1289 if (skb) 1290 cf->can_id |= CAN_ERR_RESTARTED; 1291 } 1292 } 1293 1294 can->err_rep_cnt++; 1295 can->can.can_stats.bus_error++; 1296 if (p->header[1] & KVASER_PCIEFD_EPACK_DIR_TX) 1297 stats->tx_errors++; 1298 else 1299 stats->rx_errors++; 1300 1301 can->bec.txerr = bec.txerr; 1302 can->bec.rxerr = bec.rxerr; 1303 1304 if (!skb) { 1305 stats->rx_dropped++; 1306 return -ENOMEM; 1307 } 1308 1309 shhwtstamps = skb_hwtstamps(skb); 1310 shhwtstamps->hwtstamp = 1311 ns_to_ktime(div_u64(p->timestamp * 1000, 1312 can->kv_pcie->freq_to_ticks_div)); 1313 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_CNT; 1314 1315 cf->data[6] = bec.txerr; 1316 cf->data[7] = bec.rxerr; 1317 1318 netif_rx(skb); 1319 return 0; 1320 } 1321 1322 static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie, 1323 struct kvaser_pciefd_rx_packet *p) 1324 { 1325 struct kvaser_pciefd_can *can; 1326 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1327 1328 if (ch_id >= pcie->nr_channels) 1329 return -EIO; 1330 1331 can = pcie->can[ch_id]; 1332 1333 kvaser_pciefd_rx_error_frame(can, p); 1334 if (can->err_rep_cnt >= KVASER_PCIEFD_MAX_ERR_REP) 1335 /* Do not report more errors, until bec_poll_timer expires */ 1336 kvaser_pciefd_disable_err_gen(can); 1337 /* Start polling the error counters */ 1338 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ); 1339 return 0; 1340 } 1341 1342 static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can, 1343 struct kvaser_pciefd_rx_packet *p) 1344 { 1345 struct can_berr_counter bec; 1346 enum can_state old_state, new_state, tx_state, rx_state; 1347 1348 old_state = can->can.state; 1349 1350 bec.txerr = p->header[0] & 0xff; 1351 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff; 1352 1353 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, 1354 &rx_state); 1355 1356 if (new_state != old_state) { 1357 struct net_device *ndev = can->can.dev; 1358 struct sk_buff *skb; 1359 struct can_frame *cf; 1360 struct skb_shared_hwtstamps *shhwtstamps; 1361 1362 skb = alloc_can_err_skb(ndev, &cf); 1363 if (!skb) { 1364 struct net_device_stats *stats = &ndev->stats; 1365 1366 stats->rx_dropped++; 1367 return -ENOMEM; 1368 } 1369 1370 kvaser_pciefd_change_state(can, cf, new_state, tx_state, 1371 rx_state); 1372 1373 if (old_state == CAN_STATE_BUS_OFF && 1374 new_state == CAN_STATE_ERROR_ACTIVE && 1375 can->can.restart_ms) { 1376 can->can.can_stats.restarts++; 1377 cf->can_id |= CAN_ERR_RESTARTED; 1378 } 1379 1380 shhwtstamps = skb_hwtstamps(skb); 1381 shhwtstamps->hwtstamp = 1382 ns_to_ktime(div_u64(p->timestamp * 1000, 1383 can->kv_pcie->freq_to_ticks_div)); 1384 1385 cf->data[6] = bec.txerr; 1386 cf->data[7] = bec.rxerr; 1387 1388 netif_rx(skb); 1389 } 1390 can->bec.txerr = bec.txerr; 1391 can->bec.rxerr = bec.rxerr; 1392 /* Check if we need to poll the error counters */ 1393 if (bec.txerr || bec.rxerr) 1394 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ); 1395 1396 return 0; 1397 } 1398 1399 static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie, 1400 struct kvaser_pciefd_rx_packet *p) 1401 { 1402 struct kvaser_pciefd_can *can; 1403 u8 cmdseq; 1404 u32 status; 1405 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1406 1407 if (ch_id >= pcie->nr_channels) 1408 return -EIO; 1409 1410 can = pcie->can[ch_id]; 1411 1412 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG); 1413 cmdseq = (status >> KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT) & 0xff; 1414 1415 /* Reset done, start abort and flush */ 1416 if (p->header[0] & KVASER_PCIEFD_SPACK_IRM && 1417 p->header[0] & KVASER_PCIEFD_SPACK_RMCD && 1418 p->header[1] & KVASER_PCIEFD_SPACK_AUTO && 1419 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) && 1420 status & KVASER_PCIEFD_KCAN_STAT_IDLE) { 1421 u32 cmd; 1422 1423 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD, 1424 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 1425 cmd = KVASER_PCIEFD_KCAN_CMD_AT; 1426 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT; 1427 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); 1428 1429 iowrite32(KVASER_PCIEFD_KCAN_IRQ_TFD, 1430 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 1431 } else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET && 1432 p->header[0] & KVASER_PCIEFD_SPACK_IRM && 1433 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) && 1434 status & KVASER_PCIEFD_KCAN_STAT_IDLE) { 1435 /* Reset detected, send end of flush if no packet are in FIFO */ 1436 u8 count = ioread32(can->reg_base + 1437 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff; 1438 1439 if (!count) 1440 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH, 1441 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG); 1442 } else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) && 1443 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK)) { 1444 /* Response to status request received */ 1445 kvaser_pciefd_handle_status_resp(can, p); 1446 if (can->can.state != CAN_STATE_BUS_OFF && 1447 can->can.state != CAN_STATE_ERROR_ACTIVE) { 1448 mod_timer(&can->bec_poll_timer, 1449 KVASER_PCIEFD_BEC_POLL_FREQ); 1450 } 1451 } else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD && 1452 !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK)) { 1453 /* Reset to bus on detected */ 1454 if (!completion_done(&can->start_comp)) 1455 complete(&can->start_comp); 1456 } 1457 1458 return 0; 1459 } 1460 1461 static int kvaser_pciefd_handle_eack_packet(struct kvaser_pciefd *pcie, 1462 struct kvaser_pciefd_rx_packet *p) 1463 { 1464 struct kvaser_pciefd_can *can; 1465 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1466 1467 if (ch_id >= pcie->nr_channels) 1468 return -EIO; 1469 1470 can = pcie->can[ch_id]; 1471 1472 /* If this is the last flushed packet, send end of flush */ 1473 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) { 1474 u8 count = ioread32(can->reg_base + 1475 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff; 1476 1477 if (count == 0) 1478 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH, 1479 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG); 1480 } else { 1481 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK; 1482 int dlc = can_get_echo_skb(can->can.dev, echo_idx, NULL); 1483 struct net_device_stats *stats = &can->can.dev->stats; 1484 1485 stats->tx_bytes += dlc; 1486 stats->tx_packets++; 1487 1488 if (netif_queue_stopped(can->can.dev)) 1489 netif_wake_queue(can->can.dev); 1490 } 1491 1492 return 0; 1493 } 1494 1495 static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can, 1496 struct kvaser_pciefd_rx_packet *p) 1497 { 1498 struct sk_buff *skb; 1499 struct net_device_stats *stats = &can->can.dev->stats; 1500 struct can_frame *cf; 1501 1502 skb = alloc_can_err_skb(can->can.dev, &cf); 1503 1504 stats->tx_errors++; 1505 if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) { 1506 if (skb) 1507 cf->can_id |= CAN_ERR_LOSTARB; 1508 can->can.can_stats.arbitration_lost++; 1509 } else if (skb) { 1510 cf->can_id |= CAN_ERR_ACK; 1511 } 1512 1513 if (skb) { 1514 cf->can_id |= CAN_ERR_BUSERROR; 1515 netif_rx(skb); 1516 } else { 1517 stats->rx_dropped++; 1518 netdev_warn(can->can.dev, "No memory left for err_skb\n"); 1519 } 1520 } 1521 1522 static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie, 1523 struct kvaser_pciefd_rx_packet *p) 1524 { 1525 struct kvaser_pciefd_can *can; 1526 bool one_shot_fail = false; 1527 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1528 1529 if (ch_id >= pcie->nr_channels) 1530 return -EIO; 1531 1532 can = pcie->can[ch_id]; 1533 /* Ignore control packet ACK */ 1534 if (p->header[0] & KVASER_PCIEFD_APACKET_CT) 1535 return 0; 1536 1537 if (p->header[0] & KVASER_PCIEFD_APACKET_NACK) { 1538 kvaser_pciefd_handle_nack_packet(can, p); 1539 one_shot_fail = true; 1540 } 1541 1542 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) { 1543 netdev_dbg(can->can.dev, "Packet was flushed\n"); 1544 } else { 1545 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK; 1546 int dlc = can_get_echo_skb(can->can.dev, echo_idx, NULL); 1547 u8 count = ioread32(can->reg_base + 1548 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff; 1549 1550 if (count < KVASER_PCIEFD_CAN_TX_MAX_COUNT && 1551 netif_queue_stopped(can->can.dev)) 1552 netif_wake_queue(can->can.dev); 1553 1554 if (!one_shot_fail) { 1555 struct net_device_stats *stats = &can->can.dev->stats; 1556 1557 stats->tx_bytes += dlc; 1558 stats->tx_packets++; 1559 } 1560 } 1561 1562 return 0; 1563 } 1564 1565 static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie, 1566 struct kvaser_pciefd_rx_packet *p) 1567 { 1568 struct kvaser_pciefd_can *can; 1569 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1570 1571 if (ch_id >= pcie->nr_channels) 1572 return -EIO; 1573 1574 can = pcie->can[ch_id]; 1575 1576 if (!completion_done(&can->flush_comp)) 1577 complete(&can->flush_comp); 1578 1579 return 0; 1580 } 1581 1582 static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos, 1583 int dma_buf) 1584 { 1585 __le32 *buffer = pcie->dma_data[dma_buf]; 1586 __le64 timestamp; 1587 struct kvaser_pciefd_rx_packet packet; 1588 struct kvaser_pciefd_rx_packet *p = &packet; 1589 u8 type; 1590 int pos = *start_pos; 1591 int size; 1592 int ret = 0; 1593 1594 size = le32_to_cpu(buffer[pos++]); 1595 if (!size) { 1596 *start_pos = 0; 1597 return 0; 1598 } 1599 1600 p->header[0] = le32_to_cpu(buffer[pos++]); 1601 p->header[1] = le32_to_cpu(buffer[pos++]); 1602 1603 /* Read 64-bit timestamp */ 1604 memcpy(×tamp, &buffer[pos], sizeof(__le64)); 1605 pos += 2; 1606 p->timestamp = le64_to_cpu(timestamp); 1607 1608 type = (p->header[1] >> KVASER_PCIEFD_PACKET_TYPE_SHIFT) & 0xf; 1609 switch (type) { 1610 case KVASER_PCIEFD_PACK_TYPE_DATA: 1611 ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]); 1612 if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) { 1613 u8 data_len; 1614 1615 data_len = can_fd_dlc2len(p->header[1] >> 1616 KVASER_PCIEFD_RPACKET_DLC_SHIFT); 1617 pos += DIV_ROUND_UP(data_len, 4); 1618 } 1619 break; 1620 1621 case KVASER_PCIEFD_PACK_TYPE_ACK: 1622 ret = kvaser_pciefd_handle_ack_packet(pcie, p); 1623 break; 1624 1625 case KVASER_PCIEFD_PACK_TYPE_STATUS: 1626 ret = kvaser_pciefd_handle_status_packet(pcie, p); 1627 break; 1628 1629 case KVASER_PCIEFD_PACK_TYPE_ERROR: 1630 ret = kvaser_pciefd_handle_error_packet(pcie, p); 1631 break; 1632 1633 case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK: 1634 ret = kvaser_pciefd_handle_eack_packet(pcie, p); 1635 break; 1636 1637 case KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK: 1638 ret = kvaser_pciefd_handle_eflush_packet(pcie, p); 1639 break; 1640 1641 case KVASER_PCIEFD_PACK_TYPE_ACK_DATA: 1642 case KVASER_PCIEFD_PACK_TYPE_BUS_LOAD: 1643 case KVASER_PCIEFD_PACK_TYPE_TXRQ: 1644 dev_info(&pcie->pci->dev, 1645 "Received unexpected packet type 0x%08X\n", type); 1646 break; 1647 1648 default: 1649 dev_err(&pcie->pci->dev, "Unknown packet type 0x%08X\n", type); 1650 ret = -EIO; 1651 break; 1652 } 1653 1654 if (ret) 1655 return ret; 1656 1657 /* Position does not point to the end of the package, 1658 * corrupted packet size? 1659 */ 1660 if ((*start_pos + size) != pos) 1661 return -EIO; 1662 1663 /* Point to the next packet header, if any */ 1664 *start_pos = pos; 1665 1666 return ret; 1667 } 1668 1669 static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf) 1670 { 1671 int pos = 0; 1672 int res = 0; 1673 1674 do { 1675 res = kvaser_pciefd_read_packet(pcie, &pos, dma_buf); 1676 } while (!res && pos > 0 && pos < KVASER_PCIEFD_DMA_SIZE); 1677 1678 return res; 1679 } 1680 1681 static int kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie) 1682 { 1683 u32 irq; 1684 1685 irq = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG); 1686 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD0) { 1687 kvaser_pciefd_read_buffer(pcie, 0); 1688 /* Reset DMA buffer 0 */ 1689 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0, 1690 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1691 } 1692 1693 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD1) { 1694 kvaser_pciefd_read_buffer(pcie, 1); 1695 /* Reset DMA buffer 1 */ 1696 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1, 1697 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1698 } 1699 1700 if (irq & KVASER_PCIEFD_SRB_IRQ_DOF0 || 1701 irq & KVASER_PCIEFD_SRB_IRQ_DOF1 || 1702 irq & KVASER_PCIEFD_SRB_IRQ_DUF0 || 1703 irq & KVASER_PCIEFD_SRB_IRQ_DUF1) 1704 dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq); 1705 1706 iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG); 1707 return 0; 1708 } 1709 1710 static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can) 1711 { 1712 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 1713 1714 if (irq & KVASER_PCIEFD_KCAN_IRQ_TOF) 1715 netdev_err(can->can.dev, "Tx FIFO overflow\n"); 1716 1717 if (irq & KVASER_PCIEFD_KCAN_IRQ_TFD) { 1718 u8 count = ioread32(can->reg_base + 1719 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff; 1720 1721 if (count == 0) 1722 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH, 1723 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG); 1724 } 1725 1726 if (irq & KVASER_PCIEFD_KCAN_IRQ_BPP) 1727 netdev_err(can->can.dev, 1728 "Fail to change bittiming, when not in reset mode\n"); 1729 1730 if (irq & KVASER_PCIEFD_KCAN_IRQ_FDIC) 1731 netdev_err(can->can.dev, "CAN FD frame in CAN mode\n"); 1732 1733 if (irq & KVASER_PCIEFD_KCAN_IRQ_ROF) 1734 netdev_err(can->can.dev, "Rx FIFO overflow\n"); 1735 1736 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 1737 return 0; 1738 } 1739 1740 static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev) 1741 { 1742 struct kvaser_pciefd *pcie = (struct kvaser_pciefd *)dev; 1743 u32 board_irq; 1744 int i; 1745 1746 board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG); 1747 1748 if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MSK)) 1749 return IRQ_NONE; 1750 1751 if (board_irq & KVASER_PCIEFD_IRQ_SRB) 1752 kvaser_pciefd_receive_irq(pcie); 1753 1754 for (i = 0; i < pcie->nr_channels; i++) { 1755 if (!pcie->can[i]) { 1756 dev_err(&pcie->pci->dev, 1757 "IRQ mask points to unallocated controller\n"); 1758 break; 1759 } 1760 1761 /* Check that mask matches channel (i) IRQ mask */ 1762 if (board_irq & (1 << i)) 1763 kvaser_pciefd_transmit_irq(pcie->can[i]); 1764 } 1765 1766 iowrite32(board_irq, pcie->reg_base + KVASER_PCIEFD_IRQ_REG); 1767 return IRQ_HANDLED; 1768 } 1769 1770 static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie) 1771 { 1772 int i; 1773 struct kvaser_pciefd_can *can; 1774 1775 for (i = 0; i < pcie->nr_channels; i++) { 1776 can = pcie->can[i]; 1777 if (can) { 1778 iowrite32(0, 1779 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 1780 kvaser_pciefd_pwm_stop(can); 1781 free_candev(can->can.dev); 1782 } 1783 } 1784 } 1785 1786 static int kvaser_pciefd_probe(struct pci_dev *pdev, 1787 const struct pci_device_id *id) 1788 { 1789 int err; 1790 struct kvaser_pciefd *pcie; 1791 1792 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); 1793 if (!pcie) 1794 return -ENOMEM; 1795 1796 pci_set_drvdata(pdev, pcie); 1797 pcie->pci = pdev; 1798 1799 err = pci_enable_device(pdev); 1800 if (err) 1801 return err; 1802 1803 err = pci_request_regions(pdev, KVASER_PCIEFD_DRV_NAME); 1804 if (err) 1805 goto err_disable_pci; 1806 1807 pcie->reg_base = pci_iomap(pdev, 0, 0); 1808 if (!pcie->reg_base) { 1809 err = -ENOMEM; 1810 goto err_release_regions; 1811 } 1812 1813 err = kvaser_pciefd_setup_board(pcie); 1814 if (err) 1815 goto err_pci_iounmap; 1816 1817 err = kvaser_pciefd_setup_dma(pcie); 1818 if (err) 1819 goto err_pci_iounmap; 1820 1821 pci_set_master(pdev); 1822 1823 err = kvaser_pciefd_setup_can_ctrls(pcie); 1824 if (err) 1825 goto err_teardown_can_ctrls; 1826 1827 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1, 1828 pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG); 1829 1830 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1 | 1831 KVASER_PCIEFD_SRB_IRQ_DOF0 | KVASER_PCIEFD_SRB_IRQ_DOF1 | 1832 KVASER_PCIEFD_SRB_IRQ_DUF0 | KVASER_PCIEFD_SRB_IRQ_DUF1, 1833 pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG); 1834 1835 /* Reset IRQ handling, expected to be off before */ 1836 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK, 1837 pcie->reg_base + KVASER_PCIEFD_IRQ_REG); 1838 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK, 1839 pcie->reg_base + KVASER_PCIEFD_IEN_REG); 1840 1841 /* Ready the DMA buffers */ 1842 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0, 1843 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1844 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1, 1845 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1846 1847 err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler, 1848 IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie); 1849 if (err) 1850 goto err_teardown_can_ctrls; 1851 1852 err = kvaser_pciefd_reg_candev(pcie); 1853 if (err) 1854 goto err_free_irq; 1855 1856 return 0; 1857 1858 err_free_irq: 1859 free_irq(pcie->pci->irq, pcie); 1860 1861 err_teardown_can_ctrls: 1862 kvaser_pciefd_teardown_can_ctrls(pcie); 1863 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); 1864 pci_clear_master(pdev); 1865 1866 err_pci_iounmap: 1867 pci_iounmap(pdev, pcie->reg_base); 1868 1869 err_release_regions: 1870 pci_release_regions(pdev); 1871 1872 err_disable_pci: 1873 pci_disable_device(pdev); 1874 1875 return err; 1876 } 1877 1878 static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie) 1879 { 1880 struct kvaser_pciefd_can *can; 1881 int i; 1882 1883 for (i = 0; i < pcie->nr_channels; i++) { 1884 can = pcie->can[i]; 1885 if (can) { 1886 iowrite32(0, 1887 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 1888 unregister_candev(can->can.dev); 1889 del_timer(&can->bec_poll_timer); 1890 kvaser_pciefd_pwm_stop(can); 1891 free_candev(can->can.dev); 1892 } 1893 } 1894 } 1895 1896 static void kvaser_pciefd_remove(struct pci_dev *pdev) 1897 { 1898 struct kvaser_pciefd *pcie = pci_get_drvdata(pdev); 1899 1900 kvaser_pciefd_remove_all_ctrls(pcie); 1901 1902 /* Turn off IRQ generation */ 1903 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); 1904 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK, 1905 pcie->reg_base + KVASER_PCIEFD_IRQ_REG); 1906 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG); 1907 1908 free_irq(pcie->pci->irq, pcie); 1909 1910 pci_clear_master(pdev); 1911 pci_iounmap(pdev, pcie->reg_base); 1912 pci_release_regions(pdev); 1913 pci_disable_device(pdev); 1914 } 1915 1916 static struct pci_driver kvaser_pciefd = { 1917 .name = KVASER_PCIEFD_DRV_NAME, 1918 .id_table = kvaser_pciefd_id_table, 1919 .probe = kvaser_pciefd_probe, 1920 .remove = kvaser_pciefd_remove, 1921 }; 1922 1923 module_pci_driver(kvaser_pciefd) 1924