1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 /* Copyright (C) 2018 KVASER AB, Sweden. All rights reserved. 3 * Parts of this driver are based on the following: 4 * - Kvaser linux pciefd driver (version 5.25) 5 * - PEAK linux canfd driver 6 * - Altera Avalon EPCS flash controller driver 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/device.h> 12 #include <linux/pci.h> 13 #include <linux/can/dev.h> 14 #include <linux/timer.h> 15 #include <linux/netdevice.h> 16 #include <linux/crc32.h> 17 #include <linux/iopoll.h> 18 19 MODULE_LICENSE("Dual BSD/GPL"); 20 MODULE_AUTHOR("Kvaser AB <support@kvaser.com>"); 21 MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices"); 22 23 #define KVASER_PCIEFD_DRV_NAME "kvaser_pciefd" 24 25 #define KVASER_PCIEFD_WAIT_TIMEOUT msecs_to_jiffies(1000) 26 #define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200)) 27 #define KVASER_PCIEFD_MAX_ERR_REP 256 28 #define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17 29 #define KVASER_PCIEFD_MAX_CAN_CHANNELS 4 30 #define KVASER_PCIEFD_DMA_COUNT 2 31 32 #define KVASER_PCIEFD_DMA_SIZE (4 * 1024) 33 #define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0) 34 35 #define KVASER_PCIEFD_VENDOR 0x1a07 36 #define KVASER_PCIEFD_4HS_ID 0x0d 37 #define KVASER_PCIEFD_2HS_ID 0x0e 38 #define KVASER_PCIEFD_HS_ID 0x0f 39 #define KVASER_PCIEFD_MINIPCIE_HS_ID 0x10 40 #define KVASER_PCIEFD_MINIPCIE_2HS_ID 0x11 41 42 /* PCIe IRQ registers */ 43 #define KVASER_PCIEFD_IRQ_REG 0x40 44 #define KVASER_PCIEFD_IEN_REG 0x50 45 /* DMA map */ 46 #define KVASER_PCIEFD_DMA_MAP_BASE 0x1000 47 /* Kvaser KCAN CAN controller registers */ 48 #define KVASER_PCIEFD_KCAN0_BASE 0x10000 49 #define KVASER_PCIEFD_KCAN_BASE_OFFSET 0x1000 50 #define KVASER_PCIEFD_KCAN_FIFO_REG 0x100 51 #define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180 52 #define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0 53 #define KVASER_PCIEFD_KCAN_CMD_REG 0x400 54 #define KVASER_PCIEFD_KCAN_IEN_REG 0x408 55 #define KVASER_PCIEFD_KCAN_IRQ_REG 0x410 56 #define KVASER_PCIEFD_KCAN_TX_NPACKETS_REG 0x414 57 #define KVASER_PCIEFD_KCAN_STAT_REG 0x418 58 #define KVASER_PCIEFD_KCAN_MODE_REG 0x41c 59 #define KVASER_PCIEFD_KCAN_BTRN_REG 0x420 60 #define KVASER_PCIEFD_KCAN_BTRD_REG 0x428 61 #define KVASER_PCIEFD_KCAN_PWM_REG 0x430 62 /* Loopback control register */ 63 #define KVASER_PCIEFD_LOOP_REG 0x1f000 64 /* System identification and information registers */ 65 #define KVASER_PCIEFD_SYSID_BASE 0x1f020 66 #define KVASER_PCIEFD_SYSID_VERSION_REG (KVASER_PCIEFD_SYSID_BASE + 0x8) 67 #define KVASER_PCIEFD_SYSID_CANFREQ_REG (KVASER_PCIEFD_SYSID_BASE + 0xc) 68 #define KVASER_PCIEFD_SYSID_BUILD_REG (KVASER_PCIEFD_SYSID_BASE + 0x14) 69 /* Shared receive buffer registers */ 70 #define KVASER_PCIEFD_SRB_BASE 0x1f200 71 #define KVASER_PCIEFD_SRB_CMD_REG (KVASER_PCIEFD_SRB_BASE + 0x200) 72 #define KVASER_PCIEFD_SRB_IEN_REG (KVASER_PCIEFD_SRB_BASE + 0x204) 73 #define KVASER_PCIEFD_SRB_IRQ_REG (KVASER_PCIEFD_SRB_BASE + 0x20c) 74 #define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210) 75 #define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218) 76 /* EPCS flash controller registers */ 77 #define KVASER_PCIEFD_SPI_BASE 0x1fc00 78 #define KVASER_PCIEFD_SPI_RX_REG KVASER_PCIEFD_SPI_BASE 79 #define KVASER_PCIEFD_SPI_TX_REG (KVASER_PCIEFD_SPI_BASE + 0x4) 80 #define KVASER_PCIEFD_SPI_STATUS_REG (KVASER_PCIEFD_SPI_BASE + 0x8) 81 #define KVASER_PCIEFD_SPI_CTRL_REG (KVASER_PCIEFD_SPI_BASE + 0xc) 82 #define KVASER_PCIEFD_SPI_SSEL_REG (KVASER_PCIEFD_SPI_BASE + 0x14) 83 84 #define KVASER_PCIEFD_IRQ_ALL_MSK 0x1f 85 #define KVASER_PCIEFD_IRQ_SRB BIT(4) 86 87 #define KVASER_PCIEFD_SYSID_NRCHAN_SHIFT 24 88 #define KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT 16 89 #define KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT 1 90 91 /* Reset DMA buffer 0, 1 and FIFO offset */ 92 #define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4) 93 #define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5) 94 #define KVASER_PCIEFD_SRB_CMD_FOR BIT(0) 95 96 /* DMA packet done, buffer 0 and 1 */ 97 #define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8) 98 #define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9) 99 /* DMA overflow, buffer 0 and 1 */ 100 #define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10) 101 #define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11) 102 /* DMA underflow, buffer 0 and 1 */ 103 #define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12) 104 #define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13) 105 106 /* DMA idle */ 107 #define KVASER_PCIEFD_SRB_STAT_DI BIT(15) 108 /* DMA support */ 109 #define KVASER_PCIEFD_SRB_STAT_DMA BIT(24) 110 111 /* DMA Enable */ 112 #define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0) 113 114 /* EPCS flash controller definitions */ 115 #define KVASER_PCIEFD_CFG_IMG_SZ (64 * 1024) 116 #define KVASER_PCIEFD_CFG_IMG_OFFSET (31 * 65536L) 117 #define KVASER_PCIEFD_CFG_MAX_PARAMS 256 118 #define KVASER_PCIEFD_CFG_MAGIC 0xcafef00d 119 #define KVASER_PCIEFD_CFG_PARAM_MAX_SZ 24 120 #define KVASER_PCIEFD_CFG_SYS_VER 1 121 #define KVASER_PCIEFD_CFG_PARAM_NR_CHAN 130 122 #define KVASER_PCIEFD_SPI_TMT BIT(5) 123 #define KVASER_PCIEFD_SPI_TRDY BIT(6) 124 #define KVASER_PCIEFD_SPI_RRDY BIT(7) 125 #define KVASER_PCIEFD_FLASH_ID_EPCS16 0x14 126 /* Commands for controlling the onboard flash */ 127 #define KVASER_PCIEFD_FLASH_RES_CMD 0xab 128 #define KVASER_PCIEFD_FLASH_READ_CMD 0x3 129 #define KVASER_PCIEFD_FLASH_STATUS_CMD 0x5 130 131 /* Kvaser KCAN definitions */ 132 #define KVASER_PCIEFD_KCAN_CTRL_EFLUSH (4 << 29) 133 #define KVASER_PCIEFD_KCAN_CTRL_EFRAME (5 << 29) 134 135 #define KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT 16 136 /* Request status packet */ 137 #define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0) 138 /* Abort, flush and reset */ 139 #define KVASER_PCIEFD_KCAN_CMD_AT BIT(1) 140 141 /* Tx FIFO unaligned read */ 142 #define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0) 143 /* Tx FIFO unaligned end */ 144 #define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1) 145 /* Bus parameter protection error */ 146 #define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2) 147 /* FDF bit when controller is in classic mode */ 148 #define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3) 149 /* Rx FIFO overflow */ 150 #define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5) 151 /* Abort done */ 152 #define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13) 153 /* Tx buffer flush done */ 154 #define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14) 155 /* Tx FIFO overflow */ 156 #define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15) 157 /* Tx FIFO empty */ 158 #define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16) 159 /* Transmitter unaligned */ 160 #define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17) 161 162 #define KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT 16 163 164 #define KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT 24 165 /* Abort request */ 166 #define KVASER_PCIEFD_KCAN_STAT_AR BIT(7) 167 /* Idle state. Controller in reset mode and no abort or flush pending */ 168 #define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10) 169 /* Bus off */ 170 #define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11) 171 /* Reset mode request */ 172 #define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14) 173 /* Controller in reset mode */ 174 #define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15) 175 /* Controller got one-shot capability */ 176 #define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16) 177 /* Controller got CAN FD capability */ 178 #define KVASER_PCIEFD_KCAN_STAT_FD BIT(19) 179 #define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK (KVASER_PCIEFD_KCAN_STAT_AR | \ 180 KVASER_PCIEFD_KCAN_STAT_BOFF | KVASER_PCIEFD_KCAN_STAT_RMR | \ 181 KVASER_PCIEFD_KCAN_STAT_IRM) 182 183 /* Reset mode */ 184 #define KVASER_PCIEFD_KCAN_MODE_RM BIT(8) 185 /* Listen only mode */ 186 #define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9) 187 /* Error packet enable */ 188 #define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12) 189 /* CAN FD non-ISO */ 190 #define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15) 191 /* Acknowledgment packet type */ 192 #define KVASER_PCIEFD_KCAN_MODE_APT BIT(20) 193 /* Active error flag enable. Clear to force error passive */ 194 #define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23) 195 /* Classic CAN mode */ 196 #define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31) 197 198 #define KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT 13 199 #define KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT 17 200 #define KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT 26 201 202 #define KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT 16 203 204 /* Kvaser KCAN packet types */ 205 #define KVASER_PCIEFD_PACK_TYPE_DATA 0 206 #define KVASER_PCIEFD_PACK_TYPE_ACK 1 207 #define KVASER_PCIEFD_PACK_TYPE_TXRQ 2 208 #define KVASER_PCIEFD_PACK_TYPE_ERROR 3 209 #define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 4 210 #define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 5 211 #define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 6 212 #define KVASER_PCIEFD_PACK_TYPE_STATUS 8 213 #define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 9 214 215 /* Kvaser KCAN packet common definitions */ 216 #define KVASER_PCIEFD_PACKET_SEQ_MSK 0xff 217 #define KVASER_PCIEFD_PACKET_CHID_SHIFT 25 218 #define KVASER_PCIEFD_PACKET_TYPE_SHIFT 28 219 220 /* Kvaser KCAN TDATA and RDATA first word */ 221 #define KVASER_PCIEFD_RPACKET_IDE BIT(30) 222 #define KVASER_PCIEFD_RPACKET_RTR BIT(29) 223 /* Kvaser KCAN TDATA and RDATA second word */ 224 #define KVASER_PCIEFD_RPACKET_ESI BIT(13) 225 #define KVASER_PCIEFD_RPACKET_BRS BIT(14) 226 #define KVASER_PCIEFD_RPACKET_FDF BIT(15) 227 #define KVASER_PCIEFD_RPACKET_DLC_SHIFT 8 228 /* Kvaser KCAN TDATA second word */ 229 #define KVASER_PCIEFD_TPACKET_SMS BIT(16) 230 #define KVASER_PCIEFD_TPACKET_AREQ BIT(31) 231 232 /* Kvaser KCAN APACKET */ 233 #define KVASER_PCIEFD_APACKET_FLU BIT(8) 234 #define KVASER_PCIEFD_APACKET_CT BIT(9) 235 #define KVASER_PCIEFD_APACKET_ABL BIT(10) 236 #define KVASER_PCIEFD_APACKET_NACK BIT(11) 237 238 /* Kvaser KCAN SPACK first word */ 239 #define KVASER_PCIEFD_SPACK_RXERR_SHIFT 8 240 #define KVASER_PCIEFD_SPACK_BOFF BIT(16) 241 #define KVASER_PCIEFD_SPACK_IDET BIT(20) 242 #define KVASER_PCIEFD_SPACK_IRM BIT(21) 243 #define KVASER_PCIEFD_SPACK_RMCD BIT(22) 244 /* Kvaser KCAN SPACK second word */ 245 #define KVASER_PCIEFD_SPACK_AUTO BIT(21) 246 #define KVASER_PCIEFD_SPACK_EWLR BIT(23) 247 #define KVASER_PCIEFD_SPACK_EPLR BIT(24) 248 249 struct kvaser_pciefd; 250 251 struct kvaser_pciefd_can { 252 struct can_priv can; 253 struct kvaser_pciefd *kv_pcie; 254 void __iomem *reg_base; 255 struct can_berr_counter bec; 256 u8 cmd_seq; 257 int err_rep_cnt; 258 int echo_idx; 259 spinlock_t lock; /* Locks sensitive registers (e.g. MODE) */ 260 spinlock_t echo_lock; /* Locks the message echo buffer */ 261 struct timer_list bec_poll_timer; 262 struct completion start_comp, flush_comp; 263 }; 264 265 struct kvaser_pciefd { 266 struct pci_dev *pci; 267 void __iomem *reg_base; 268 struct kvaser_pciefd_can *can[KVASER_PCIEFD_MAX_CAN_CHANNELS]; 269 void *dma_data[KVASER_PCIEFD_DMA_COUNT]; 270 u8 nr_channels; 271 u32 freq; 272 u32 freq_to_ticks_div; 273 }; 274 275 struct kvaser_pciefd_rx_packet { 276 u32 header[2]; 277 u64 timestamp; 278 }; 279 280 struct kvaser_pciefd_tx_packet { 281 u32 header[2]; 282 u8 data[64]; 283 }; 284 285 static const struct can_bittiming_const kvaser_pciefd_bittiming_const = { 286 .name = KVASER_PCIEFD_DRV_NAME, 287 .tseg1_min = 1, 288 .tseg1_max = 255, 289 .tseg2_min = 1, 290 .tseg2_max = 32, 291 .sjw_max = 16, 292 .brp_min = 1, 293 .brp_max = 4096, 294 .brp_inc = 1, 295 }; 296 297 struct kvaser_pciefd_cfg_param { 298 __le32 magic; 299 __le32 nr; 300 __le32 len; 301 u8 data[KVASER_PCIEFD_CFG_PARAM_MAX_SZ]; 302 }; 303 304 struct kvaser_pciefd_cfg_img { 305 __le32 version; 306 __le32 magic; 307 __le32 crc; 308 struct kvaser_pciefd_cfg_param params[KVASER_PCIEFD_CFG_MAX_PARAMS]; 309 }; 310 311 static struct pci_device_id kvaser_pciefd_id_table[] = { 312 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_ID), }, 313 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_ID), }, 314 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_ID), }, 315 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_ID), }, 316 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_ID), }, 317 { 0,}, 318 }; 319 MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table); 320 321 /* Onboard flash memory functions */ 322 static int kvaser_pciefd_spi_wait_loop(struct kvaser_pciefd *pcie, int msk) 323 { 324 u32 res; 325 int ret; 326 327 ret = readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG, 328 res, res & msk, 0, 10); 329 330 return ret; 331 } 332 333 static int kvaser_pciefd_spi_cmd(struct kvaser_pciefd *pcie, const u8 *tx, 334 u32 tx_len, u8 *rx, u32 rx_len) 335 { 336 int c; 337 338 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG); 339 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG); 340 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); 341 342 c = tx_len; 343 while (c--) { 344 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY)) 345 return -EIO; 346 347 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); 348 349 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY)) 350 return -EIO; 351 352 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); 353 } 354 355 c = rx_len; 356 while (c-- > 0) { 357 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY)) 358 return -EIO; 359 360 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); 361 362 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY)) 363 return -EIO; 364 365 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); 366 } 367 368 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TMT)) 369 return -EIO; 370 371 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG); 372 373 if (c != -1) { 374 dev_err(&pcie->pci->dev, "Flash SPI transfer failed\n"); 375 return -EIO; 376 } 377 378 return 0; 379 } 380 381 static int kvaser_pciefd_cfg_read_and_verify(struct kvaser_pciefd *pcie, 382 struct kvaser_pciefd_cfg_img *img) 383 { 384 int offset = KVASER_PCIEFD_CFG_IMG_OFFSET; 385 int res, crc; 386 u8 *crc_buff; 387 388 u8 cmd[] = { 389 KVASER_PCIEFD_FLASH_READ_CMD, 390 (u8)((offset >> 16) & 0xff), 391 (u8)((offset >> 8) & 0xff), 392 (u8)(offset & 0xff) 393 }; 394 395 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), (u8 *)img, 396 KVASER_PCIEFD_CFG_IMG_SZ); 397 if (res) 398 return res; 399 400 crc_buff = (u8 *)img->params; 401 402 if (le32_to_cpu(img->version) != KVASER_PCIEFD_CFG_SYS_VER) { 403 dev_err(&pcie->pci->dev, 404 "Config flash corrupted, version number is wrong\n"); 405 return -ENODEV; 406 } 407 408 if (le32_to_cpu(img->magic) != KVASER_PCIEFD_CFG_MAGIC) { 409 dev_err(&pcie->pci->dev, 410 "Config flash corrupted, magic number is wrong\n"); 411 return -ENODEV; 412 } 413 414 crc = ~crc32_be(0xffffffff, crc_buff, sizeof(img->params)); 415 if (le32_to_cpu(img->crc) != crc) { 416 dev_err(&pcie->pci->dev, 417 "Stored CRC does not match flash image contents\n"); 418 return -EIO; 419 } 420 421 return 0; 422 } 423 424 static void kvaser_pciefd_cfg_read_params(struct kvaser_pciefd *pcie, 425 struct kvaser_pciefd_cfg_img *img) 426 { 427 struct kvaser_pciefd_cfg_param *param; 428 429 param = &img->params[KVASER_PCIEFD_CFG_PARAM_NR_CHAN]; 430 memcpy(&pcie->nr_channels, param->data, le32_to_cpu(param->len)); 431 } 432 433 static int kvaser_pciefd_read_cfg(struct kvaser_pciefd *pcie) 434 { 435 int res; 436 struct kvaser_pciefd_cfg_img *img; 437 438 /* Read electronic signature */ 439 u8 cmd[] = {KVASER_PCIEFD_FLASH_RES_CMD, 0, 0, 0}; 440 441 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), cmd, 1); 442 if (res) 443 return -EIO; 444 445 img = kmalloc(KVASER_PCIEFD_CFG_IMG_SZ, GFP_KERNEL); 446 if (!img) 447 return -ENOMEM; 448 449 if (cmd[0] != KVASER_PCIEFD_FLASH_ID_EPCS16) { 450 dev_err(&pcie->pci->dev, 451 "Flash id is 0x%x instead of expected EPCS16 (0x%x)\n", 452 cmd[0], KVASER_PCIEFD_FLASH_ID_EPCS16); 453 454 res = -ENODEV; 455 goto image_free; 456 } 457 458 cmd[0] = KVASER_PCIEFD_FLASH_STATUS_CMD; 459 res = kvaser_pciefd_spi_cmd(pcie, cmd, 1, cmd, 1); 460 if (res) { 461 goto image_free; 462 } else if (cmd[0] & 1) { 463 res = -EIO; 464 /* No write is ever done, the WIP should never be set */ 465 dev_err(&pcie->pci->dev, "Unexpected WIP bit set in flash\n"); 466 goto image_free; 467 } 468 469 res = kvaser_pciefd_cfg_read_and_verify(pcie, img); 470 if (res) { 471 res = -EIO; 472 goto image_free; 473 } 474 475 kvaser_pciefd_cfg_read_params(pcie, img); 476 477 image_free: 478 kfree(img); 479 return res; 480 } 481 482 static void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can) 483 { 484 u32 cmd; 485 486 cmd = KVASER_PCIEFD_KCAN_CMD_SRQ; 487 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT; 488 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); 489 } 490 491 static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can) 492 { 493 u32 mode; 494 unsigned long irq; 495 496 spin_lock_irqsave(&can->lock, irq); 497 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 498 if (!(mode & KVASER_PCIEFD_KCAN_MODE_EPEN)) { 499 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN; 500 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 501 } 502 spin_unlock_irqrestore(&can->lock, irq); 503 } 504 505 static void kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can *can) 506 { 507 u32 mode; 508 unsigned long irq; 509 510 spin_lock_irqsave(&can->lock, irq); 511 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 512 mode &= ~KVASER_PCIEFD_KCAN_MODE_EPEN; 513 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 514 spin_unlock_irqrestore(&can->lock, irq); 515 } 516 517 static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can) 518 { 519 u32 msk; 520 521 msk = KVASER_PCIEFD_KCAN_IRQ_TE | KVASER_PCIEFD_KCAN_IRQ_ROF | 522 KVASER_PCIEFD_KCAN_IRQ_TOF | KVASER_PCIEFD_KCAN_IRQ_ABD | 523 KVASER_PCIEFD_KCAN_IRQ_TAE | KVASER_PCIEFD_KCAN_IRQ_TAL | 524 KVASER_PCIEFD_KCAN_IRQ_FDIC | KVASER_PCIEFD_KCAN_IRQ_BPP | 525 KVASER_PCIEFD_KCAN_IRQ_TAR | KVASER_PCIEFD_KCAN_IRQ_TFD; 526 527 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 528 529 return 0; 530 } 531 532 static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can) 533 { 534 u32 mode; 535 unsigned long irq; 536 537 spin_lock_irqsave(&can->lock, irq); 538 539 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 540 if (can->can.ctrlmode & CAN_CTRLMODE_FD) { 541 mode &= ~KVASER_PCIEFD_KCAN_MODE_CCM; 542 if (can->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 543 mode |= KVASER_PCIEFD_KCAN_MODE_NIFDEN; 544 else 545 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN; 546 } else { 547 mode |= KVASER_PCIEFD_KCAN_MODE_CCM; 548 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN; 549 } 550 551 if (can->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 552 mode |= KVASER_PCIEFD_KCAN_MODE_LOM; 553 554 mode |= KVASER_PCIEFD_KCAN_MODE_EEN; 555 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN; 556 /* Use ACK packet type */ 557 mode &= ~KVASER_PCIEFD_KCAN_MODE_APT; 558 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM; 559 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 560 561 spin_unlock_irqrestore(&can->lock, irq); 562 } 563 564 static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can) 565 { 566 u32 status; 567 unsigned long irq; 568 569 spin_lock_irqsave(&can->lock, irq); 570 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 571 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD, 572 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 573 574 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG); 575 if (status & KVASER_PCIEFD_KCAN_STAT_IDLE) { 576 u32 cmd; 577 578 /* If controller is already idle, run abort, flush and reset */ 579 cmd = KVASER_PCIEFD_KCAN_CMD_AT; 580 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT; 581 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); 582 } else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) { 583 u32 mode; 584 585 /* Put controller in reset mode */ 586 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 587 mode |= KVASER_PCIEFD_KCAN_MODE_RM; 588 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 589 } 590 591 spin_unlock_irqrestore(&can->lock, irq); 592 } 593 594 static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) 595 { 596 u32 mode; 597 unsigned long irq; 598 599 del_timer(&can->bec_poll_timer); 600 601 if (!completion_done(&can->flush_comp)) 602 kvaser_pciefd_start_controller_flush(can); 603 604 if (!wait_for_completion_timeout(&can->flush_comp, 605 KVASER_PCIEFD_WAIT_TIMEOUT)) { 606 netdev_err(can->can.dev, "Timeout during bus on flush\n"); 607 return -ETIMEDOUT; 608 } 609 610 spin_lock_irqsave(&can->lock, irq); 611 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 612 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 613 614 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD, 615 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 616 617 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 618 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM; 619 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 620 spin_unlock_irqrestore(&can->lock, irq); 621 622 if (!wait_for_completion_timeout(&can->start_comp, 623 KVASER_PCIEFD_WAIT_TIMEOUT)) { 624 netdev_err(can->can.dev, "Timeout during bus on reset\n"); 625 return -ETIMEDOUT; 626 } 627 /* Reset interrupt handling */ 628 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 629 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 630 631 kvaser_pciefd_set_tx_irq(can); 632 kvaser_pciefd_setup_controller(can); 633 634 can->can.state = CAN_STATE_ERROR_ACTIVE; 635 netif_wake_queue(can->can.dev); 636 can->bec.txerr = 0; 637 can->bec.rxerr = 0; 638 can->err_rep_cnt = 0; 639 640 return 0; 641 } 642 643 static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can) 644 { 645 u8 top; 646 u32 pwm_ctrl; 647 unsigned long irq; 648 649 spin_lock_irqsave(&can->lock, irq); 650 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); 651 top = (pwm_ctrl >> KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT) & 0xff; 652 653 /* Set duty cycle to zero */ 654 pwm_ctrl |= top; 655 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); 656 spin_unlock_irqrestore(&can->lock, irq); 657 } 658 659 static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can) 660 { 661 int top, trigger; 662 u32 pwm_ctrl; 663 unsigned long irq; 664 665 kvaser_pciefd_pwm_stop(can); 666 spin_lock_irqsave(&can->lock, irq); 667 668 /* Set frequency to 500 KHz*/ 669 top = can->can.clock.freq / (2 * 500000) - 1; 670 671 pwm_ctrl = top & 0xff; 672 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT; 673 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); 674 675 /* Set duty cycle to 95 */ 676 trigger = (100 * top - 95 * (top + 1) + 50) / 100; 677 pwm_ctrl = trigger & 0xff; 678 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT; 679 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG); 680 spin_unlock_irqrestore(&can->lock, irq); 681 } 682 683 static int kvaser_pciefd_open(struct net_device *netdev) 684 { 685 int err; 686 struct kvaser_pciefd_can *can = netdev_priv(netdev); 687 688 err = open_candev(netdev); 689 if (err) 690 return err; 691 692 err = kvaser_pciefd_bus_on(can); 693 if (err) 694 return err; 695 696 return 0; 697 } 698 699 static int kvaser_pciefd_stop(struct net_device *netdev) 700 { 701 struct kvaser_pciefd_can *can = netdev_priv(netdev); 702 int ret = 0; 703 704 /* Don't interrupt ongoing flush */ 705 if (!completion_done(&can->flush_comp)) 706 kvaser_pciefd_start_controller_flush(can); 707 708 if (!wait_for_completion_timeout(&can->flush_comp, 709 KVASER_PCIEFD_WAIT_TIMEOUT)) { 710 netdev_err(can->can.dev, "Timeout during stop\n"); 711 ret = -ETIMEDOUT; 712 } else { 713 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 714 del_timer(&can->bec_poll_timer); 715 } 716 close_candev(netdev); 717 718 return ret; 719 } 720 721 static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p, 722 struct kvaser_pciefd_can *can, 723 struct sk_buff *skb) 724 { 725 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 726 int packet_size; 727 int seq = can->echo_idx; 728 729 memset(p, 0, sizeof(*p)); 730 731 if (can->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 732 p->header[1] |= KVASER_PCIEFD_TPACKET_SMS; 733 734 if (cf->can_id & CAN_RTR_FLAG) 735 p->header[0] |= KVASER_PCIEFD_RPACKET_RTR; 736 737 if (cf->can_id & CAN_EFF_FLAG) 738 p->header[0] |= KVASER_PCIEFD_RPACKET_IDE; 739 740 p->header[0] |= cf->can_id & CAN_EFF_MASK; 741 p->header[1] |= can_len2dlc(cf->len) << KVASER_PCIEFD_RPACKET_DLC_SHIFT; 742 p->header[1] |= KVASER_PCIEFD_TPACKET_AREQ; 743 744 if (can_is_canfd_skb(skb)) { 745 p->header[1] |= KVASER_PCIEFD_RPACKET_FDF; 746 if (cf->flags & CANFD_BRS) 747 p->header[1] |= KVASER_PCIEFD_RPACKET_BRS; 748 if (cf->flags & CANFD_ESI) 749 p->header[1] |= KVASER_PCIEFD_RPACKET_ESI; 750 } 751 752 p->header[1] |= seq & KVASER_PCIEFD_PACKET_SEQ_MSK; 753 754 packet_size = cf->len; 755 memcpy(p->data, cf->data, packet_size); 756 757 return DIV_ROUND_UP(packet_size, 4); 758 } 759 760 static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, 761 struct net_device *netdev) 762 { 763 struct kvaser_pciefd_can *can = netdev_priv(netdev); 764 unsigned long irq_flags; 765 struct kvaser_pciefd_tx_packet packet; 766 int nwords; 767 u8 count; 768 769 if (can_dropped_invalid_skb(netdev, skb)) 770 return NETDEV_TX_OK; 771 772 nwords = kvaser_pciefd_prepare_tx_packet(&packet, can, skb); 773 774 spin_lock_irqsave(&can->echo_lock, irq_flags); 775 776 /* Prepare and save echo skb in internal slot */ 777 can_put_echo_skb(skb, netdev, can->echo_idx); 778 779 /* Move echo index to the next slot */ 780 can->echo_idx = (can->echo_idx + 1) % can->can.echo_skb_max; 781 782 /* Write header to fifo */ 783 iowrite32(packet.header[0], 784 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG); 785 iowrite32(packet.header[1], 786 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG); 787 788 if (nwords) { 789 u32 data_last = ((u32 *)packet.data)[nwords - 1]; 790 791 /* Write data to fifo, except last word */ 792 iowrite32_rep(can->reg_base + 793 KVASER_PCIEFD_KCAN_FIFO_REG, packet.data, 794 nwords - 1); 795 /* Write last word to end of fifo */ 796 __raw_writel(data_last, can->reg_base + 797 KVASER_PCIEFD_KCAN_FIFO_LAST_REG); 798 } else { 799 /* Complete write to fifo */ 800 __raw_writel(0, can->reg_base + 801 KVASER_PCIEFD_KCAN_FIFO_LAST_REG); 802 } 803 804 count = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG); 805 /* No room for a new message, stop the queue until at least one 806 * successful transmit 807 */ 808 if (count >= KVASER_PCIEFD_CAN_TX_MAX_COUNT || 809 can->can.echo_skb[can->echo_idx]) 810 netif_stop_queue(netdev); 811 812 spin_unlock_irqrestore(&can->echo_lock, irq_flags); 813 814 return NETDEV_TX_OK; 815 } 816 817 static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data) 818 { 819 u32 mode, test, btrn; 820 unsigned long irq_flags; 821 int ret; 822 struct can_bittiming *bt; 823 824 if (data) 825 bt = &can->can.data_bittiming; 826 else 827 bt = &can->can.bittiming; 828 829 btrn = ((bt->phase_seg2 - 1) & 0x1f) << 830 KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT | 831 (((bt->prop_seg + bt->phase_seg1) - 1) & 0x1ff) << 832 KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT | 833 ((bt->sjw - 1) & 0xf) << KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT | 834 ((bt->brp - 1) & 0x1fff); 835 836 spin_lock_irqsave(&can->lock, irq_flags); 837 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 838 839 /* Put the circuit in reset mode */ 840 iowrite32(mode | KVASER_PCIEFD_KCAN_MODE_RM, 841 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 842 843 /* Can only set bittiming if in reset mode */ 844 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG, 845 test, test & KVASER_PCIEFD_KCAN_MODE_RM, 846 0, 10); 847 848 if (ret) { 849 spin_unlock_irqrestore(&can->lock, irq_flags); 850 return -EBUSY; 851 } 852 853 if (data) 854 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG); 855 else 856 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG); 857 858 /* Restore previous reset mode status */ 859 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG); 860 861 spin_unlock_irqrestore(&can->lock, irq_flags); 862 return 0; 863 } 864 865 static int kvaser_pciefd_set_nominal_bittiming(struct net_device *ndev) 866 { 867 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), false); 868 } 869 870 static int kvaser_pciefd_set_data_bittiming(struct net_device *ndev) 871 { 872 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), true); 873 } 874 875 static int kvaser_pciefd_set_mode(struct net_device *ndev, enum can_mode mode) 876 { 877 struct kvaser_pciefd_can *can = netdev_priv(ndev); 878 int ret = 0; 879 880 switch (mode) { 881 case CAN_MODE_START: 882 if (!can->can.restart_ms) 883 ret = kvaser_pciefd_bus_on(can); 884 break; 885 default: 886 return -EOPNOTSUPP; 887 } 888 889 return ret; 890 } 891 892 static int kvaser_pciefd_get_berr_counter(const struct net_device *ndev, 893 struct can_berr_counter *bec) 894 { 895 struct kvaser_pciefd_can *can = netdev_priv(ndev); 896 897 bec->rxerr = can->bec.rxerr; 898 bec->txerr = can->bec.txerr; 899 return 0; 900 } 901 902 static void kvaser_pciefd_bec_poll_timer(struct timer_list *data) 903 { 904 struct kvaser_pciefd_can *can = from_timer(can, data, bec_poll_timer); 905 906 kvaser_pciefd_enable_err_gen(can); 907 kvaser_pciefd_request_status(can); 908 can->err_rep_cnt = 0; 909 } 910 911 static const struct net_device_ops kvaser_pciefd_netdev_ops = { 912 .ndo_open = kvaser_pciefd_open, 913 .ndo_stop = kvaser_pciefd_stop, 914 .ndo_start_xmit = kvaser_pciefd_start_xmit, 915 .ndo_change_mtu = can_change_mtu, 916 }; 917 918 static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) 919 { 920 int i; 921 922 for (i = 0; i < pcie->nr_channels; i++) { 923 struct net_device *netdev; 924 struct kvaser_pciefd_can *can; 925 u32 status, tx_npackets; 926 927 netdev = alloc_candev(sizeof(struct kvaser_pciefd_can), 928 KVASER_PCIEFD_CAN_TX_MAX_COUNT); 929 if (!netdev) 930 return -ENOMEM; 931 932 can = netdev_priv(netdev); 933 netdev->netdev_ops = &kvaser_pciefd_netdev_ops; 934 can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE + 935 i * KVASER_PCIEFD_KCAN_BASE_OFFSET; 936 937 can->kv_pcie = pcie; 938 can->cmd_seq = 0; 939 can->err_rep_cnt = 0; 940 can->bec.txerr = 0; 941 can->bec.rxerr = 0; 942 943 init_completion(&can->start_comp); 944 init_completion(&can->flush_comp); 945 timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer, 946 0); 947 948 tx_npackets = ioread32(can->reg_base + 949 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG); 950 if (((tx_npackets >> KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT) & 951 0xff) < KVASER_PCIEFD_CAN_TX_MAX_COUNT) { 952 dev_err(&pcie->pci->dev, 953 "Max Tx count is smaller than expected\n"); 954 955 free_candev(netdev); 956 return -ENODEV; 957 } 958 959 can->can.clock.freq = pcie->freq; 960 can->can.echo_skb_max = KVASER_PCIEFD_CAN_TX_MAX_COUNT; 961 can->echo_idx = 0; 962 spin_lock_init(&can->echo_lock); 963 spin_lock_init(&can->lock); 964 can->can.bittiming_const = &kvaser_pciefd_bittiming_const; 965 can->can.data_bittiming_const = &kvaser_pciefd_bittiming_const; 966 967 can->can.do_set_bittiming = kvaser_pciefd_set_nominal_bittiming; 968 can->can.do_set_data_bittiming = 969 kvaser_pciefd_set_data_bittiming; 970 971 can->can.do_set_mode = kvaser_pciefd_set_mode; 972 can->can.do_get_berr_counter = kvaser_pciefd_get_berr_counter; 973 974 can->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | 975 CAN_CTRLMODE_FD | 976 CAN_CTRLMODE_FD_NON_ISO; 977 978 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG); 979 if (!(status & KVASER_PCIEFD_KCAN_STAT_FD)) { 980 dev_err(&pcie->pci->dev, 981 "CAN FD not supported as expected %d\n", i); 982 983 free_candev(netdev); 984 return -ENODEV; 985 } 986 987 if (status & KVASER_PCIEFD_KCAN_STAT_CAP) 988 can->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT; 989 990 netdev->flags |= IFF_ECHO; 991 992 SET_NETDEV_DEV(netdev, &pcie->pci->dev); 993 994 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 995 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | 996 KVASER_PCIEFD_KCAN_IRQ_TFD, 997 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 998 999 pcie->can[i] = can; 1000 kvaser_pciefd_pwm_start(can); 1001 } 1002 1003 return 0; 1004 } 1005 1006 static int kvaser_pciefd_reg_candev(struct kvaser_pciefd *pcie) 1007 { 1008 int i; 1009 1010 for (i = 0; i < pcie->nr_channels; i++) { 1011 int err = register_candev(pcie->can[i]->can.dev); 1012 1013 if (err) { 1014 int j; 1015 1016 /* Unregister all successfully registered devices. */ 1017 for (j = 0; j < i; j++) 1018 unregister_candev(pcie->can[j]->can.dev); 1019 return err; 1020 } 1021 } 1022 1023 return 0; 1024 } 1025 1026 static void kvaser_pciefd_write_dma_map(struct kvaser_pciefd *pcie, 1027 dma_addr_t addr, int offset) 1028 { 1029 u32 word1, word2; 1030 1031 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1032 word1 = addr | KVASER_PCIEFD_64BIT_DMA_BIT; 1033 word2 = addr >> 32; 1034 #else 1035 word1 = addr; 1036 word2 = 0; 1037 #endif 1038 iowrite32(word1, pcie->reg_base + offset); 1039 iowrite32(word2, pcie->reg_base + offset + 4); 1040 } 1041 1042 static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) 1043 { 1044 int i; 1045 u32 srb_status; 1046 dma_addr_t dma_addr[KVASER_PCIEFD_DMA_COUNT]; 1047 1048 /* Disable the DMA */ 1049 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); 1050 for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) { 1051 unsigned int offset = KVASER_PCIEFD_DMA_MAP_BASE + 8 * i; 1052 1053 pcie->dma_data[i] = 1054 dmam_alloc_coherent(&pcie->pci->dev, 1055 KVASER_PCIEFD_DMA_SIZE, 1056 &dma_addr[i], 1057 GFP_KERNEL); 1058 1059 if (!pcie->dma_data[i] || !dma_addr[i]) { 1060 dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n", 1061 KVASER_PCIEFD_DMA_SIZE); 1062 return -ENOMEM; 1063 } 1064 1065 kvaser_pciefd_write_dma_map(pcie, dma_addr[i], offset); 1066 } 1067 1068 /* Reset Rx FIFO, and both DMA buffers */ 1069 iowrite32(KVASER_PCIEFD_SRB_CMD_FOR | KVASER_PCIEFD_SRB_CMD_RDB0 | 1070 KVASER_PCIEFD_SRB_CMD_RDB1, 1071 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1072 1073 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG); 1074 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI)) { 1075 dev_err(&pcie->pci->dev, "DMA not idle before enabling\n"); 1076 return -EIO; 1077 } 1078 1079 /* Enable the DMA */ 1080 iowrite32(KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE, 1081 pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); 1082 1083 return 0; 1084 } 1085 1086 static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie) 1087 { 1088 u32 sysid, srb_status, build; 1089 u8 sysid_nr_chan; 1090 int ret; 1091 1092 ret = kvaser_pciefd_read_cfg(pcie); 1093 if (ret) 1094 return ret; 1095 1096 sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG); 1097 sysid_nr_chan = (sysid >> KVASER_PCIEFD_SYSID_NRCHAN_SHIFT) & 0xff; 1098 if (pcie->nr_channels != sysid_nr_chan) { 1099 dev_err(&pcie->pci->dev, 1100 "Number of channels does not match: %u vs %u\n", 1101 pcie->nr_channels, 1102 sysid_nr_chan); 1103 return -ENODEV; 1104 } 1105 1106 if (pcie->nr_channels > KVASER_PCIEFD_MAX_CAN_CHANNELS) 1107 pcie->nr_channels = KVASER_PCIEFD_MAX_CAN_CHANNELS; 1108 1109 build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG); 1110 dev_dbg(&pcie->pci->dev, "Version %u.%u.%u\n", 1111 (sysid >> KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT) & 0xff, 1112 sysid & 0xff, 1113 (build >> KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT) & 0x7fff); 1114 1115 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG); 1116 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) { 1117 dev_err(&pcie->pci->dev, 1118 "Hardware without DMA is not supported\n"); 1119 return -ENODEV; 1120 } 1121 1122 pcie->freq = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_CANFREQ_REG); 1123 pcie->freq_to_ticks_div = pcie->freq / 1000000; 1124 if (pcie->freq_to_ticks_div == 0) 1125 pcie->freq_to_ticks_div = 1; 1126 1127 /* Turn off all loopback functionality */ 1128 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG); 1129 return ret; 1130 } 1131 1132 static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie, 1133 struct kvaser_pciefd_rx_packet *p, 1134 __le32 *data) 1135 { 1136 struct sk_buff *skb; 1137 struct canfd_frame *cf; 1138 struct can_priv *priv; 1139 struct net_device_stats *stats; 1140 struct skb_shared_hwtstamps *shhwtstamps; 1141 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1142 1143 if (ch_id >= pcie->nr_channels) 1144 return -EIO; 1145 1146 priv = &pcie->can[ch_id]->can; 1147 stats = &priv->dev->stats; 1148 1149 if (p->header[1] & KVASER_PCIEFD_RPACKET_FDF) { 1150 skb = alloc_canfd_skb(priv->dev, &cf); 1151 if (!skb) { 1152 stats->rx_dropped++; 1153 return -ENOMEM; 1154 } 1155 1156 if (p->header[1] & KVASER_PCIEFD_RPACKET_BRS) 1157 cf->flags |= CANFD_BRS; 1158 1159 if (p->header[1] & KVASER_PCIEFD_RPACKET_ESI) 1160 cf->flags |= CANFD_ESI; 1161 } else { 1162 skb = alloc_can_skb(priv->dev, (struct can_frame **)&cf); 1163 if (!skb) { 1164 stats->rx_dropped++; 1165 return -ENOMEM; 1166 } 1167 } 1168 1169 cf->can_id = p->header[0] & CAN_EFF_MASK; 1170 if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE) 1171 cf->can_id |= CAN_EFF_FLAG; 1172 1173 cf->len = can_dlc2len(p->header[1] >> KVASER_PCIEFD_RPACKET_DLC_SHIFT); 1174 1175 if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR) 1176 cf->can_id |= CAN_RTR_FLAG; 1177 else 1178 memcpy(cf->data, data, cf->len); 1179 1180 shhwtstamps = skb_hwtstamps(skb); 1181 1182 shhwtstamps->hwtstamp = 1183 ns_to_ktime(div_u64(p->timestamp * 1000, 1184 pcie->freq_to_ticks_div)); 1185 1186 stats->rx_bytes += cf->len; 1187 stats->rx_packets++; 1188 1189 return netif_rx(skb); 1190 } 1191 1192 static void kvaser_pciefd_change_state(struct kvaser_pciefd_can *can, 1193 struct can_frame *cf, 1194 enum can_state new_state, 1195 enum can_state tx_state, 1196 enum can_state rx_state) 1197 { 1198 can_change_state(can->can.dev, cf, tx_state, rx_state); 1199 1200 if (new_state == CAN_STATE_BUS_OFF) { 1201 struct net_device *ndev = can->can.dev; 1202 unsigned long irq_flags; 1203 1204 spin_lock_irqsave(&can->lock, irq_flags); 1205 netif_stop_queue(can->can.dev); 1206 spin_unlock_irqrestore(&can->lock, irq_flags); 1207 1208 /* Prevent CAN controller from auto recover from bus off */ 1209 if (!can->can.restart_ms) { 1210 kvaser_pciefd_start_controller_flush(can); 1211 can_bus_off(ndev); 1212 } 1213 } 1214 } 1215 1216 static void kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet *p, 1217 struct can_berr_counter *bec, 1218 enum can_state *new_state, 1219 enum can_state *tx_state, 1220 enum can_state *rx_state) 1221 { 1222 if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF || 1223 p->header[0] & KVASER_PCIEFD_SPACK_IRM) 1224 *new_state = CAN_STATE_BUS_OFF; 1225 else if (bec->txerr >= 255 || bec->rxerr >= 255) 1226 *new_state = CAN_STATE_BUS_OFF; 1227 else if (p->header[1] & KVASER_PCIEFD_SPACK_EPLR) 1228 *new_state = CAN_STATE_ERROR_PASSIVE; 1229 else if (bec->txerr >= 128 || bec->rxerr >= 128) 1230 *new_state = CAN_STATE_ERROR_PASSIVE; 1231 else if (p->header[1] & KVASER_PCIEFD_SPACK_EWLR) 1232 *new_state = CAN_STATE_ERROR_WARNING; 1233 else if (bec->txerr >= 96 || bec->rxerr >= 96) 1234 *new_state = CAN_STATE_ERROR_WARNING; 1235 else 1236 *new_state = CAN_STATE_ERROR_ACTIVE; 1237 1238 *tx_state = bec->txerr >= bec->rxerr ? *new_state : 0; 1239 *rx_state = bec->txerr <= bec->rxerr ? *new_state : 0; 1240 } 1241 1242 static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can, 1243 struct kvaser_pciefd_rx_packet *p) 1244 { 1245 struct can_berr_counter bec; 1246 enum can_state old_state, new_state, tx_state, rx_state; 1247 struct net_device *ndev = can->can.dev; 1248 struct sk_buff *skb; 1249 struct can_frame *cf = NULL; 1250 struct skb_shared_hwtstamps *shhwtstamps; 1251 struct net_device_stats *stats = &ndev->stats; 1252 1253 old_state = can->can.state; 1254 1255 bec.txerr = p->header[0] & 0xff; 1256 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff; 1257 1258 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, 1259 &rx_state); 1260 1261 skb = alloc_can_err_skb(ndev, &cf); 1262 1263 if (new_state != old_state) { 1264 kvaser_pciefd_change_state(can, cf, new_state, tx_state, 1265 rx_state); 1266 1267 if (old_state == CAN_STATE_BUS_OFF && 1268 new_state == CAN_STATE_ERROR_ACTIVE && 1269 can->can.restart_ms) { 1270 can->can.can_stats.restarts++; 1271 if (skb) 1272 cf->can_id |= CAN_ERR_RESTARTED; 1273 } 1274 } 1275 1276 can->err_rep_cnt++; 1277 can->can.can_stats.bus_error++; 1278 stats->rx_errors++; 1279 1280 can->bec.txerr = bec.txerr; 1281 can->bec.rxerr = bec.rxerr; 1282 1283 if (!skb) { 1284 stats->rx_dropped++; 1285 return -ENOMEM; 1286 } 1287 1288 shhwtstamps = skb_hwtstamps(skb); 1289 shhwtstamps->hwtstamp = 1290 ns_to_ktime(div_u64(p->timestamp * 1000, 1291 can->kv_pcie->freq_to_ticks_div)); 1292 cf->can_id |= CAN_ERR_BUSERROR; 1293 1294 cf->data[6] = bec.txerr; 1295 cf->data[7] = bec.rxerr; 1296 1297 stats->rx_packets++; 1298 stats->rx_bytes += cf->can_dlc; 1299 1300 netif_rx(skb); 1301 return 0; 1302 } 1303 1304 static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie, 1305 struct kvaser_pciefd_rx_packet *p) 1306 { 1307 struct kvaser_pciefd_can *can; 1308 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1309 1310 if (ch_id >= pcie->nr_channels) 1311 return -EIO; 1312 1313 can = pcie->can[ch_id]; 1314 1315 kvaser_pciefd_rx_error_frame(can, p); 1316 if (can->err_rep_cnt >= KVASER_PCIEFD_MAX_ERR_REP) 1317 /* Do not report more errors, until bec_poll_timer expires */ 1318 kvaser_pciefd_disable_err_gen(can); 1319 /* Start polling the error counters */ 1320 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ); 1321 return 0; 1322 } 1323 1324 static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can, 1325 struct kvaser_pciefd_rx_packet *p) 1326 { 1327 struct can_berr_counter bec; 1328 enum can_state old_state, new_state, tx_state, rx_state; 1329 1330 old_state = can->can.state; 1331 1332 bec.txerr = p->header[0] & 0xff; 1333 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff; 1334 1335 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, 1336 &rx_state); 1337 1338 if (new_state != old_state) { 1339 struct net_device *ndev = can->can.dev; 1340 struct sk_buff *skb; 1341 struct can_frame *cf; 1342 struct skb_shared_hwtstamps *shhwtstamps; 1343 1344 skb = alloc_can_err_skb(ndev, &cf); 1345 if (!skb) { 1346 struct net_device_stats *stats = &ndev->stats; 1347 1348 stats->rx_dropped++; 1349 return -ENOMEM; 1350 } 1351 1352 kvaser_pciefd_change_state(can, cf, new_state, tx_state, 1353 rx_state); 1354 1355 if (old_state == CAN_STATE_BUS_OFF && 1356 new_state == CAN_STATE_ERROR_ACTIVE && 1357 can->can.restart_ms) { 1358 can->can.can_stats.restarts++; 1359 cf->can_id |= CAN_ERR_RESTARTED; 1360 } 1361 1362 shhwtstamps = skb_hwtstamps(skb); 1363 shhwtstamps->hwtstamp = 1364 ns_to_ktime(div_u64(p->timestamp * 1000, 1365 can->kv_pcie->freq_to_ticks_div)); 1366 1367 cf->data[6] = bec.txerr; 1368 cf->data[7] = bec.rxerr; 1369 1370 netif_rx(skb); 1371 } 1372 can->bec.txerr = bec.txerr; 1373 can->bec.rxerr = bec.rxerr; 1374 /* Check if we need to poll the error counters */ 1375 if (bec.txerr || bec.rxerr) 1376 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ); 1377 1378 return 0; 1379 } 1380 1381 static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie, 1382 struct kvaser_pciefd_rx_packet *p) 1383 { 1384 struct kvaser_pciefd_can *can; 1385 u8 cmdseq; 1386 u32 status; 1387 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1388 1389 if (ch_id >= pcie->nr_channels) 1390 return -EIO; 1391 1392 can = pcie->can[ch_id]; 1393 1394 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG); 1395 cmdseq = (status >> KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT) & 0xff; 1396 1397 /* Reset done, start abort and flush */ 1398 if (p->header[0] & KVASER_PCIEFD_SPACK_IRM && 1399 p->header[0] & KVASER_PCIEFD_SPACK_RMCD && 1400 p->header[1] & KVASER_PCIEFD_SPACK_AUTO && 1401 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) && 1402 status & KVASER_PCIEFD_KCAN_STAT_IDLE) { 1403 u32 cmd; 1404 1405 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD, 1406 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 1407 cmd = KVASER_PCIEFD_KCAN_CMD_AT; 1408 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT; 1409 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG); 1410 1411 iowrite32(KVASER_PCIEFD_KCAN_IRQ_TFD, 1412 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 1413 } else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET && 1414 p->header[0] & KVASER_PCIEFD_SPACK_IRM && 1415 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) && 1416 status & KVASER_PCIEFD_KCAN_STAT_IDLE) { 1417 /* Reset detected, send end of flush if no packet are in FIFO */ 1418 u8 count = ioread32(can->reg_base + 1419 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff; 1420 1421 if (!count) 1422 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH, 1423 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG); 1424 } else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) && 1425 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK)) { 1426 /* Response to status request received */ 1427 kvaser_pciefd_handle_status_resp(can, p); 1428 if (can->can.state != CAN_STATE_BUS_OFF && 1429 can->can.state != CAN_STATE_ERROR_ACTIVE) { 1430 mod_timer(&can->bec_poll_timer, 1431 KVASER_PCIEFD_BEC_POLL_FREQ); 1432 } 1433 } else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD && 1434 !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK)) { 1435 /* Reset to bus on detected */ 1436 if (!completion_done(&can->start_comp)) 1437 complete(&can->start_comp); 1438 } 1439 1440 return 0; 1441 } 1442 1443 static int kvaser_pciefd_handle_eack_packet(struct kvaser_pciefd *pcie, 1444 struct kvaser_pciefd_rx_packet *p) 1445 { 1446 struct kvaser_pciefd_can *can; 1447 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1448 1449 if (ch_id >= pcie->nr_channels) 1450 return -EIO; 1451 1452 can = pcie->can[ch_id]; 1453 1454 /* If this is the last flushed packet, send end of flush */ 1455 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) { 1456 u8 count = ioread32(can->reg_base + 1457 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff; 1458 1459 if (count == 0) 1460 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH, 1461 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG); 1462 } else { 1463 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK; 1464 int dlc = can_get_echo_skb(can->can.dev, echo_idx); 1465 struct net_device_stats *stats = &can->can.dev->stats; 1466 1467 stats->tx_bytes += dlc; 1468 stats->tx_packets++; 1469 1470 if (netif_queue_stopped(can->can.dev)) 1471 netif_wake_queue(can->can.dev); 1472 } 1473 1474 return 0; 1475 } 1476 1477 static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can, 1478 struct kvaser_pciefd_rx_packet *p) 1479 { 1480 struct sk_buff *skb; 1481 struct net_device_stats *stats = &can->can.dev->stats; 1482 struct can_frame *cf; 1483 1484 skb = alloc_can_err_skb(can->can.dev, &cf); 1485 1486 stats->tx_errors++; 1487 if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) { 1488 if (skb) 1489 cf->can_id |= CAN_ERR_LOSTARB; 1490 can->can.can_stats.arbitration_lost++; 1491 } else if (skb) { 1492 cf->can_id |= CAN_ERR_ACK; 1493 } 1494 1495 if (skb) { 1496 cf->can_id |= CAN_ERR_BUSERROR; 1497 stats->rx_bytes += cf->can_dlc; 1498 stats->rx_packets++; 1499 netif_rx(skb); 1500 } else { 1501 stats->rx_dropped++; 1502 netdev_warn(can->can.dev, "No memory left for err_skb\n"); 1503 } 1504 } 1505 1506 static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie, 1507 struct kvaser_pciefd_rx_packet *p) 1508 { 1509 struct kvaser_pciefd_can *can; 1510 bool one_shot_fail = false; 1511 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1512 1513 if (ch_id >= pcie->nr_channels) 1514 return -EIO; 1515 1516 can = pcie->can[ch_id]; 1517 /* Ignore control packet ACK */ 1518 if (p->header[0] & KVASER_PCIEFD_APACKET_CT) 1519 return 0; 1520 1521 if (p->header[0] & KVASER_PCIEFD_APACKET_NACK) { 1522 kvaser_pciefd_handle_nack_packet(can, p); 1523 one_shot_fail = true; 1524 } 1525 1526 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) { 1527 netdev_dbg(can->can.dev, "Packet was flushed\n"); 1528 } else { 1529 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK; 1530 int dlc = can_get_echo_skb(can->can.dev, echo_idx); 1531 u8 count = ioread32(can->reg_base + 1532 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff; 1533 1534 if (count < KVASER_PCIEFD_CAN_TX_MAX_COUNT && 1535 netif_queue_stopped(can->can.dev)) 1536 netif_wake_queue(can->can.dev); 1537 1538 if (!one_shot_fail) { 1539 struct net_device_stats *stats = &can->can.dev->stats; 1540 1541 stats->tx_bytes += dlc; 1542 stats->tx_packets++; 1543 } 1544 } 1545 1546 return 0; 1547 } 1548 1549 static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie, 1550 struct kvaser_pciefd_rx_packet *p) 1551 { 1552 struct kvaser_pciefd_can *can; 1553 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7; 1554 1555 if (ch_id >= pcie->nr_channels) 1556 return -EIO; 1557 1558 can = pcie->can[ch_id]; 1559 1560 if (!completion_done(&can->flush_comp)) 1561 complete(&can->flush_comp); 1562 1563 return 0; 1564 } 1565 1566 static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos, 1567 int dma_buf) 1568 { 1569 __le32 *buffer = pcie->dma_data[dma_buf]; 1570 __le64 timestamp; 1571 struct kvaser_pciefd_rx_packet packet; 1572 struct kvaser_pciefd_rx_packet *p = &packet; 1573 u8 type; 1574 int pos = *start_pos; 1575 int size; 1576 int ret = 0; 1577 1578 size = le32_to_cpu(buffer[pos++]); 1579 if (!size) { 1580 *start_pos = 0; 1581 return 0; 1582 } 1583 1584 p->header[0] = le32_to_cpu(buffer[pos++]); 1585 p->header[1] = le32_to_cpu(buffer[pos++]); 1586 1587 /* Read 64-bit timestamp */ 1588 memcpy(×tamp, &buffer[pos], sizeof(__le64)); 1589 pos += 2; 1590 p->timestamp = le64_to_cpu(timestamp); 1591 1592 type = (p->header[1] >> KVASER_PCIEFD_PACKET_TYPE_SHIFT) & 0xf; 1593 switch (type) { 1594 case KVASER_PCIEFD_PACK_TYPE_DATA: 1595 ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]); 1596 if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) { 1597 u8 data_len; 1598 1599 data_len = can_dlc2len(p->header[1] >> 1600 KVASER_PCIEFD_RPACKET_DLC_SHIFT); 1601 pos += DIV_ROUND_UP(data_len, 4); 1602 } 1603 break; 1604 1605 case KVASER_PCIEFD_PACK_TYPE_ACK: 1606 ret = kvaser_pciefd_handle_ack_packet(pcie, p); 1607 break; 1608 1609 case KVASER_PCIEFD_PACK_TYPE_STATUS: 1610 ret = kvaser_pciefd_handle_status_packet(pcie, p); 1611 break; 1612 1613 case KVASER_PCIEFD_PACK_TYPE_ERROR: 1614 ret = kvaser_pciefd_handle_error_packet(pcie, p); 1615 break; 1616 1617 case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK: 1618 ret = kvaser_pciefd_handle_eack_packet(pcie, p); 1619 break; 1620 1621 case KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK: 1622 ret = kvaser_pciefd_handle_eflush_packet(pcie, p); 1623 break; 1624 1625 case KVASER_PCIEFD_PACK_TYPE_ACK_DATA: 1626 case KVASER_PCIEFD_PACK_TYPE_BUS_LOAD: 1627 case KVASER_PCIEFD_PACK_TYPE_TXRQ: 1628 dev_info(&pcie->pci->dev, 1629 "Received unexpected packet type 0x%08X\n", type); 1630 break; 1631 1632 default: 1633 dev_err(&pcie->pci->dev, "Unknown packet type 0x%08X\n", type); 1634 ret = -EIO; 1635 break; 1636 } 1637 1638 if (ret) 1639 return ret; 1640 1641 /* Position does not point to the end of the package, 1642 * corrupted packet size? 1643 */ 1644 if ((*start_pos + size) != pos) 1645 return -EIO; 1646 1647 /* Point to the next packet header, if any */ 1648 *start_pos = pos; 1649 1650 return ret; 1651 } 1652 1653 static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf) 1654 { 1655 int pos = 0; 1656 int res = 0; 1657 1658 do { 1659 res = kvaser_pciefd_read_packet(pcie, &pos, dma_buf); 1660 } while (!res && pos > 0 && pos < KVASER_PCIEFD_DMA_SIZE); 1661 1662 return res; 1663 } 1664 1665 static int kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie) 1666 { 1667 u32 irq; 1668 1669 irq = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG); 1670 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD0) { 1671 kvaser_pciefd_read_buffer(pcie, 0); 1672 /* Reset DMA buffer 0 */ 1673 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0, 1674 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1675 } 1676 1677 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD1) { 1678 kvaser_pciefd_read_buffer(pcie, 1); 1679 /* Reset DMA buffer 1 */ 1680 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1, 1681 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1682 } 1683 1684 if (irq & KVASER_PCIEFD_SRB_IRQ_DOF0 || 1685 irq & KVASER_PCIEFD_SRB_IRQ_DOF1 || 1686 irq & KVASER_PCIEFD_SRB_IRQ_DUF0 || 1687 irq & KVASER_PCIEFD_SRB_IRQ_DUF1) 1688 dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq); 1689 1690 iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG); 1691 return 0; 1692 } 1693 1694 static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can) 1695 { 1696 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 1697 1698 if (irq & KVASER_PCIEFD_KCAN_IRQ_TOF) 1699 netdev_err(can->can.dev, "Tx FIFO overflow\n"); 1700 1701 if (irq & KVASER_PCIEFD_KCAN_IRQ_TFD) { 1702 u8 count = ioread32(can->reg_base + 1703 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff; 1704 1705 if (count == 0) 1706 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH, 1707 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG); 1708 } 1709 1710 if (irq & KVASER_PCIEFD_KCAN_IRQ_BPP) 1711 netdev_err(can->can.dev, 1712 "Fail to change bittiming, when not in reset mode\n"); 1713 1714 if (irq & KVASER_PCIEFD_KCAN_IRQ_FDIC) 1715 netdev_err(can->can.dev, "CAN FD frame in CAN mode\n"); 1716 1717 if (irq & KVASER_PCIEFD_KCAN_IRQ_ROF) 1718 netdev_err(can->can.dev, "Rx FIFO overflow\n"); 1719 1720 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG); 1721 return 0; 1722 } 1723 1724 static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev) 1725 { 1726 struct kvaser_pciefd *pcie = (struct kvaser_pciefd *)dev; 1727 u32 board_irq; 1728 int i; 1729 1730 board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG); 1731 1732 if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MSK)) 1733 return IRQ_NONE; 1734 1735 if (board_irq & KVASER_PCIEFD_IRQ_SRB) 1736 kvaser_pciefd_receive_irq(pcie); 1737 1738 for (i = 0; i < pcie->nr_channels; i++) { 1739 if (!pcie->can[i]) { 1740 dev_err(&pcie->pci->dev, 1741 "IRQ mask points to unallocated controller\n"); 1742 break; 1743 } 1744 1745 /* Check that mask matches channel (i) IRQ mask */ 1746 if (board_irq & (1 << i)) 1747 kvaser_pciefd_transmit_irq(pcie->can[i]); 1748 } 1749 1750 iowrite32(board_irq, pcie->reg_base + KVASER_PCIEFD_IRQ_REG); 1751 return IRQ_HANDLED; 1752 } 1753 1754 static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie) 1755 { 1756 int i; 1757 struct kvaser_pciefd_can *can; 1758 1759 for (i = 0; i < pcie->nr_channels; i++) { 1760 can = pcie->can[i]; 1761 if (can) { 1762 iowrite32(0, 1763 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 1764 kvaser_pciefd_pwm_stop(can); 1765 free_candev(can->can.dev); 1766 } 1767 } 1768 } 1769 1770 static int kvaser_pciefd_probe(struct pci_dev *pdev, 1771 const struct pci_device_id *id) 1772 { 1773 int err; 1774 struct kvaser_pciefd *pcie; 1775 1776 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); 1777 if (!pcie) 1778 return -ENOMEM; 1779 1780 pci_set_drvdata(pdev, pcie); 1781 pcie->pci = pdev; 1782 1783 err = pci_enable_device(pdev); 1784 if (err) 1785 return err; 1786 1787 err = pci_request_regions(pdev, KVASER_PCIEFD_DRV_NAME); 1788 if (err) 1789 goto err_disable_pci; 1790 1791 pcie->reg_base = pci_iomap(pdev, 0, 0); 1792 if (!pcie->reg_base) { 1793 err = -ENOMEM; 1794 goto err_release_regions; 1795 } 1796 1797 err = kvaser_pciefd_setup_board(pcie); 1798 if (err) 1799 goto err_pci_iounmap; 1800 1801 err = kvaser_pciefd_setup_dma(pcie); 1802 if (err) 1803 goto err_pci_iounmap; 1804 1805 pci_set_master(pdev); 1806 1807 err = kvaser_pciefd_setup_can_ctrls(pcie); 1808 if (err) 1809 goto err_teardown_can_ctrls; 1810 1811 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1, 1812 pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG); 1813 1814 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1 | 1815 KVASER_PCIEFD_SRB_IRQ_DOF0 | KVASER_PCIEFD_SRB_IRQ_DOF1 | 1816 KVASER_PCIEFD_SRB_IRQ_DUF0 | KVASER_PCIEFD_SRB_IRQ_DUF1, 1817 pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG); 1818 1819 /* Reset IRQ handling, expected to be off before */ 1820 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK, 1821 pcie->reg_base + KVASER_PCIEFD_IRQ_REG); 1822 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK, 1823 pcie->reg_base + KVASER_PCIEFD_IEN_REG); 1824 1825 /* Ready the DMA buffers */ 1826 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0, 1827 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1828 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1, 1829 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG); 1830 1831 err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler, 1832 IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie); 1833 if (err) 1834 goto err_teardown_can_ctrls; 1835 1836 err = kvaser_pciefd_reg_candev(pcie); 1837 if (err) 1838 goto err_free_irq; 1839 1840 return 0; 1841 1842 err_free_irq: 1843 free_irq(pcie->pci->irq, pcie); 1844 1845 err_teardown_can_ctrls: 1846 kvaser_pciefd_teardown_can_ctrls(pcie); 1847 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); 1848 pci_clear_master(pdev); 1849 1850 err_pci_iounmap: 1851 pci_iounmap(pdev, pcie->reg_base); 1852 1853 err_release_regions: 1854 pci_release_regions(pdev); 1855 1856 err_disable_pci: 1857 pci_disable_device(pdev); 1858 1859 return err; 1860 } 1861 1862 static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie) 1863 { 1864 struct kvaser_pciefd_can *can; 1865 int i; 1866 1867 for (i = 0; i < pcie->nr_channels; i++) { 1868 can = pcie->can[i]; 1869 if (can) { 1870 iowrite32(0, 1871 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG); 1872 unregister_candev(can->can.dev); 1873 del_timer(&can->bec_poll_timer); 1874 kvaser_pciefd_pwm_stop(can); 1875 free_candev(can->can.dev); 1876 } 1877 } 1878 } 1879 1880 static void kvaser_pciefd_remove(struct pci_dev *pdev) 1881 { 1882 struct kvaser_pciefd *pcie = pci_get_drvdata(pdev); 1883 1884 kvaser_pciefd_remove_all_ctrls(pcie); 1885 1886 /* Turn off IRQ generation */ 1887 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG); 1888 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK, 1889 pcie->reg_base + KVASER_PCIEFD_IRQ_REG); 1890 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG); 1891 1892 free_irq(pcie->pci->irq, pcie); 1893 1894 pci_clear_master(pdev); 1895 pci_iounmap(pdev, pcie->reg_base); 1896 pci_release_regions(pdev); 1897 pci_disable_device(pdev); 1898 } 1899 1900 static struct pci_driver kvaser_pciefd = { 1901 .name = KVASER_PCIEFD_DRV_NAME, 1902 .id_table = kvaser_pciefd_id_table, 1903 .probe = kvaser_pciefd_probe, 1904 .remove = kvaser_pciefd_remove, 1905 }; 1906 1907 module_pci_driver(kvaser_pciefd) 1908