1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Socket CAN driver for Aeroflex Gaisler GRCAN and GRHCAN. 4 * 5 * 2012 (c) Aeroflex Gaisler AB 6 * 7 * This driver supports GRCAN and GRHCAN CAN controllers available in the GRLIB 8 * VHDL IP core library. 9 * 10 * Full documentation of the GRCAN core can be found here: 11 * http://www.gaisler.com/products/grlib/grip.pdf 12 * 13 * See "Documentation/devicetree/bindings/net/can/grcan.txt" for information on 14 * open firmware properties. 15 * 16 * See "Documentation/ABI/testing/sysfs-class-net-grcan" for information on the 17 * sysfs interface. 18 * 19 * See "Documentation/admin-guide/kernel-parameters.rst" for information on the module 20 * parameters. 21 * 22 * Contributors: Andreas Larsson <andreas@gaisler.com> 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/interrupt.h> 28 #include <linux/netdevice.h> 29 #include <linux/delay.h> 30 #include <linux/io.h> 31 #include <linux/can/dev.h> 32 #include <linux/spinlock.h> 33 #include <linux/of_platform.h> 34 #include <linux/of_irq.h> 35 36 #include <linux/dma-mapping.h> 37 38 #define DRV_NAME "grcan" 39 40 #define GRCAN_NAPI_WEIGHT 32 41 42 #define GRCAN_RESERVE_SIZE(slot1, slot2) (((slot2) - (slot1)) / 4 - 1) 43 44 struct grcan_registers { 45 u32 conf; /* 0x00 */ 46 u32 stat; /* 0x04 */ 47 u32 ctrl; /* 0x08 */ 48 u32 __reserved1[GRCAN_RESERVE_SIZE(0x08, 0x18)]; 49 u32 smask; /* 0x18 - CanMASK */ 50 u32 scode; /* 0x1c - CanCODE */ 51 u32 __reserved2[GRCAN_RESERVE_SIZE(0x1c, 0x100)]; 52 u32 pimsr; /* 0x100 */ 53 u32 pimr; /* 0x104 */ 54 u32 pisr; /* 0x108 */ 55 u32 pir; /* 0x10C */ 56 u32 imr; /* 0x110 */ 57 u32 picr; /* 0x114 */ 58 u32 __reserved3[GRCAN_RESERVE_SIZE(0x114, 0x200)]; 59 u32 txctrl; /* 0x200 */ 60 u32 txaddr; /* 0x204 */ 61 u32 txsize; /* 0x208 */ 62 u32 txwr; /* 0x20C */ 63 u32 txrd; /* 0x210 */ 64 u32 txirq; /* 0x214 */ 65 u32 __reserved4[GRCAN_RESERVE_SIZE(0x214, 0x300)]; 66 u32 rxctrl; /* 0x300 */ 67 u32 rxaddr; /* 0x304 */ 68 u32 rxsize; /* 0x308 */ 69 u32 rxwr; /* 0x30C */ 70 u32 rxrd; /* 0x310 */ 71 u32 rxirq; /* 0x314 */ 72 u32 rxmask; /* 0x318 */ 73 u32 rxcode; /* 0x31C */ 74 }; 75 76 #define GRCAN_CONF_ABORT 0x00000001 77 #define GRCAN_CONF_ENABLE0 0x00000002 78 #define GRCAN_CONF_ENABLE1 0x00000004 79 #define GRCAN_CONF_SELECT 0x00000008 80 #define GRCAN_CONF_SILENT 0x00000010 81 #define GRCAN_CONF_SAM 0x00000020 /* Available in some hardware */ 82 #define GRCAN_CONF_BPR 0x00000300 /* Note: not BRP */ 83 #define GRCAN_CONF_RSJ 0x00007000 84 #define GRCAN_CONF_PS1 0x00f00000 85 #define GRCAN_CONF_PS2 0x000f0000 86 #define GRCAN_CONF_SCALER 0xff000000 87 #define GRCAN_CONF_OPERATION \ 88 (GRCAN_CONF_ABORT | GRCAN_CONF_ENABLE0 | GRCAN_CONF_ENABLE1 \ 89 | GRCAN_CONF_SELECT | GRCAN_CONF_SILENT | GRCAN_CONF_SAM) 90 #define GRCAN_CONF_TIMING \ 91 (GRCAN_CONF_BPR | GRCAN_CONF_RSJ | GRCAN_CONF_PS1 \ 92 | GRCAN_CONF_PS2 | GRCAN_CONF_SCALER) 93 94 #define GRCAN_CONF_RSJ_MIN 1 95 #define GRCAN_CONF_RSJ_MAX 4 96 #define GRCAN_CONF_PS1_MIN 1 97 #define GRCAN_CONF_PS1_MAX 15 98 #define GRCAN_CONF_PS2_MIN 2 99 #define GRCAN_CONF_PS2_MAX 8 100 #define GRCAN_CONF_SCALER_MIN 0 101 #define GRCAN_CONF_SCALER_MAX 255 102 #define GRCAN_CONF_SCALER_INC 1 103 104 #define GRCAN_CONF_BPR_BIT 8 105 #define GRCAN_CONF_RSJ_BIT 12 106 #define GRCAN_CONF_PS1_BIT 20 107 #define GRCAN_CONF_PS2_BIT 16 108 #define GRCAN_CONF_SCALER_BIT 24 109 110 #define GRCAN_STAT_PASS 0x000001 111 #define GRCAN_STAT_OFF 0x000002 112 #define GRCAN_STAT_OR 0x000004 113 #define GRCAN_STAT_AHBERR 0x000008 114 #define GRCAN_STAT_ACTIVE 0x000010 115 #define GRCAN_STAT_RXERRCNT 0x00ff00 116 #define GRCAN_STAT_TXERRCNT 0xff0000 117 118 #define GRCAN_STAT_ERRCTR_RELATED (GRCAN_STAT_PASS | GRCAN_STAT_OFF) 119 120 #define GRCAN_STAT_RXERRCNT_BIT 8 121 #define GRCAN_STAT_TXERRCNT_BIT 16 122 123 #define GRCAN_STAT_ERRCNT_WARNING_LIMIT 96 124 #define GRCAN_STAT_ERRCNT_PASSIVE_LIMIT 127 125 126 #define GRCAN_CTRL_RESET 0x2 127 #define GRCAN_CTRL_ENABLE 0x1 128 129 #define GRCAN_TXCTRL_ENABLE 0x1 130 #define GRCAN_TXCTRL_ONGOING 0x2 131 #define GRCAN_TXCTRL_SINGLE 0x4 132 133 #define GRCAN_RXCTRL_ENABLE 0x1 134 #define GRCAN_RXCTRL_ONGOING 0x2 135 136 /* Relative offset of IRQ sources to AMBA Plug&Play */ 137 #define GRCAN_IRQIX_IRQ 0 138 #define GRCAN_IRQIX_TXSYNC 1 139 #define GRCAN_IRQIX_RXSYNC 2 140 141 #define GRCAN_IRQ_PASS 0x00001 142 #define GRCAN_IRQ_OFF 0x00002 143 #define GRCAN_IRQ_OR 0x00004 144 #define GRCAN_IRQ_RXAHBERR 0x00008 145 #define GRCAN_IRQ_TXAHBERR 0x00010 146 #define GRCAN_IRQ_RXIRQ 0x00020 147 #define GRCAN_IRQ_TXIRQ 0x00040 148 #define GRCAN_IRQ_RXFULL 0x00080 149 #define GRCAN_IRQ_TXEMPTY 0x00100 150 #define GRCAN_IRQ_RX 0x00200 151 #define GRCAN_IRQ_TX 0x00400 152 #define GRCAN_IRQ_RXSYNC 0x00800 153 #define GRCAN_IRQ_TXSYNC 0x01000 154 #define GRCAN_IRQ_RXERRCTR 0x02000 155 #define GRCAN_IRQ_TXERRCTR 0x04000 156 #define GRCAN_IRQ_RXMISS 0x08000 157 #define GRCAN_IRQ_TXLOSS 0x10000 158 159 #define GRCAN_IRQ_NONE 0 160 #define GRCAN_IRQ_ALL \ 161 (GRCAN_IRQ_PASS | GRCAN_IRQ_OFF | GRCAN_IRQ_OR \ 162 | GRCAN_IRQ_RXAHBERR | GRCAN_IRQ_TXAHBERR \ 163 | GRCAN_IRQ_RXIRQ | GRCAN_IRQ_TXIRQ \ 164 | GRCAN_IRQ_RXFULL | GRCAN_IRQ_TXEMPTY \ 165 | GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_RXSYNC \ 166 | GRCAN_IRQ_TXSYNC | GRCAN_IRQ_RXERRCTR \ 167 | GRCAN_IRQ_TXERRCTR | GRCAN_IRQ_RXMISS \ 168 | GRCAN_IRQ_TXLOSS) 169 170 #define GRCAN_IRQ_ERRCTR_RELATED (GRCAN_IRQ_RXERRCTR | GRCAN_IRQ_TXERRCTR \ 171 | GRCAN_IRQ_PASS | GRCAN_IRQ_OFF) 172 #define GRCAN_IRQ_ERRORS (GRCAN_IRQ_ERRCTR_RELATED | GRCAN_IRQ_OR \ 173 | GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR \ 174 | GRCAN_IRQ_TXLOSS) 175 #define GRCAN_IRQ_DEFAULT (GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_ERRORS) 176 177 #define GRCAN_MSG_SIZE 16 178 179 #define GRCAN_MSG_IDE 0x80000000 180 #define GRCAN_MSG_RTR 0x40000000 181 #define GRCAN_MSG_BID 0x1ffc0000 182 #define GRCAN_MSG_EID 0x1fffffff 183 #define GRCAN_MSG_IDE_BIT 31 184 #define GRCAN_MSG_RTR_BIT 30 185 #define GRCAN_MSG_BID_BIT 18 186 #define GRCAN_MSG_EID_BIT 0 187 188 #define GRCAN_MSG_DLC 0xf0000000 189 #define GRCAN_MSG_TXERRC 0x00ff0000 190 #define GRCAN_MSG_RXERRC 0x0000ff00 191 #define GRCAN_MSG_DLC_BIT 28 192 #define GRCAN_MSG_TXERRC_BIT 16 193 #define GRCAN_MSG_RXERRC_BIT 8 194 #define GRCAN_MSG_AHBERR 0x00000008 195 #define GRCAN_MSG_OR 0x00000004 196 #define GRCAN_MSG_OFF 0x00000002 197 #define GRCAN_MSG_PASS 0x00000001 198 199 #define GRCAN_MSG_DATA_SLOT_INDEX(i) (2 + (i) / 4) 200 #define GRCAN_MSG_DATA_SHIFT(i) ((3 - (i) % 4) * 8) 201 202 #define GRCAN_BUFFER_ALIGNMENT 1024 203 #define GRCAN_DEFAULT_BUFFER_SIZE 1024 204 #define GRCAN_VALID_TR_SIZE_MASK 0x001fffc0 205 206 #define GRCAN_INVALID_BUFFER_SIZE(s) \ 207 ((s) == 0 || ((s) & ~GRCAN_VALID_TR_SIZE_MASK)) 208 209 #if GRCAN_INVALID_BUFFER_SIZE(GRCAN_DEFAULT_BUFFER_SIZE) 210 #error "Invalid default buffer size" 211 #endif 212 213 struct grcan_dma_buffer { 214 size_t size; 215 void *buf; 216 dma_addr_t handle; 217 }; 218 219 struct grcan_dma { 220 size_t base_size; 221 void *base_buf; 222 dma_addr_t base_handle; 223 struct grcan_dma_buffer tx; 224 struct grcan_dma_buffer rx; 225 }; 226 227 /* GRCAN configuration parameters */ 228 struct grcan_device_config { 229 unsigned short enable0; 230 unsigned short enable1; 231 unsigned short select; 232 unsigned int txsize; 233 unsigned int rxsize; 234 }; 235 236 #define GRCAN_DEFAULT_DEVICE_CONFIG { \ 237 .enable0 = 0, \ 238 .enable1 = 0, \ 239 .select = 0, \ 240 .txsize = GRCAN_DEFAULT_BUFFER_SIZE, \ 241 .rxsize = GRCAN_DEFAULT_BUFFER_SIZE, \ 242 } 243 244 #define GRCAN_TXBUG_SAFE_GRLIB_VERSION 4100 245 #define GRLIB_VERSION_MASK 0xffff 246 247 /* GRCAN private data structure */ 248 struct grcan_priv { 249 struct can_priv can; /* must be the first member */ 250 struct net_device *dev; 251 struct device *ofdev_dev; 252 struct napi_struct napi; 253 254 struct grcan_registers __iomem *regs; /* ioremap'ed registers */ 255 struct grcan_device_config config; 256 struct grcan_dma dma; 257 258 struct sk_buff **echo_skb; /* We allocate this on our own */ 259 u8 *txdlc; /* Length of queued frames */ 260 261 /* The echo skb pointer, pointing into echo_skb and indicating which 262 * frames can be echoed back. See the "Notes on the tx cyclic buffer 263 * handling"-comment for grcan_start_xmit for more details. 264 */ 265 u32 eskbp; 266 267 /* Lock for controlling changes to the netif tx queue state, accesses to 268 * the echo_skb pointer eskbp and for making sure that a running reset 269 * and/or a close of the interface is done without interference from 270 * other parts of the code. 271 * 272 * The echo_skb pointer, eskbp, should only be accessed under this lock 273 * as it can be changed in several places and together with decisions on 274 * whether to wake up the tx queue. 275 * 276 * The tx queue must never be woken up if there is a running reset or 277 * close in progress. 278 * 279 * A running reset (see below on need_txbug_workaround) should never be 280 * done if the interface is closing down and several running resets 281 * should never be scheduled simultaneously. 282 */ 283 spinlock_t lock; 284 285 /* Whether a workaround is needed due to a bug in older hardware. In 286 * this case, the driver both tries to prevent the bug from being 287 * triggered and recovers, if the bug nevertheless happens, by doing a 288 * running reset. A running reset, resets the device and continues from 289 * where it were without being noticeable from outside the driver (apart 290 * from slight delays). 291 */ 292 bool need_txbug_workaround; 293 294 /* To trigger initization of running reset and to trigger running reset 295 * respectively in the case of a hanged device due to a txbug. 296 */ 297 struct timer_list hang_timer; 298 struct timer_list rr_timer; 299 300 /* To avoid waking up the netif queue and restarting timers 301 * when a reset is scheduled or when closing of the device is 302 * undergoing 303 */ 304 bool resetting; 305 bool closing; 306 }; 307 308 /* Wait time for a short wait for ongoing to clear */ 309 #define GRCAN_SHORTWAIT_USECS 10 310 311 /* Limit on the number of transmitted bits of an eff frame according to the CAN 312 * specification: 1 bit start of frame, 32 bits arbitration field, 6 bits 313 * control field, 8 bytes data field, 16 bits crc field, 2 bits ACK field and 7 314 * bits end of frame 315 */ 316 #define GRCAN_EFF_FRAME_MAX_BITS (1+32+6+8*8+16+2+7) 317 318 #if defined(__BIG_ENDIAN) 319 static inline u32 grcan_read_reg(u32 __iomem *reg) 320 { 321 return ioread32be(reg); 322 } 323 324 static inline void grcan_write_reg(u32 __iomem *reg, u32 val) 325 { 326 iowrite32be(val, reg); 327 } 328 #else 329 static inline u32 grcan_read_reg(u32 __iomem *reg) 330 { 331 return ioread32(reg); 332 } 333 334 static inline void grcan_write_reg(u32 __iomem *reg, u32 val) 335 { 336 iowrite32(val, reg); 337 } 338 #endif 339 340 static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask) 341 { 342 grcan_write_reg(reg, grcan_read_reg(reg) & ~mask); 343 } 344 345 static inline void grcan_set_bits(u32 __iomem *reg, u32 mask) 346 { 347 grcan_write_reg(reg, grcan_read_reg(reg) | mask); 348 } 349 350 static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask) 351 { 352 return grcan_read_reg(reg) & mask; 353 } 354 355 static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask) 356 { 357 u32 old = grcan_read_reg(reg); 358 359 grcan_write_reg(reg, (old & ~mask) | (value & mask)); 360 } 361 362 /* a and b should both be in [0,size] and a == b == size should not hold */ 363 static inline u32 grcan_ring_add(u32 a, u32 b, u32 size) 364 { 365 u32 sum = a + b; 366 367 if (sum < size) 368 return sum; 369 else 370 return sum - size; 371 } 372 373 /* a and b should both be in [0,size) */ 374 static inline u32 grcan_ring_sub(u32 a, u32 b, u32 size) 375 { 376 return grcan_ring_add(a, size - b, size); 377 } 378 379 /* Available slots for new transmissions */ 380 static inline u32 grcan_txspace(size_t txsize, u32 txwr, u32 eskbp) 381 { 382 u32 slots = txsize / GRCAN_MSG_SIZE - 1; 383 u32 used = grcan_ring_sub(txwr, eskbp, txsize) / GRCAN_MSG_SIZE; 384 385 return slots - used; 386 } 387 388 /* Configuration parameters that can be set via module parameters */ 389 static struct grcan_device_config grcan_module_config = 390 GRCAN_DEFAULT_DEVICE_CONFIG; 391 392 static const struct can_bittiming_const grcan_bittiming_const = { 393 .name = DRV_NAME, 394 .tseg1_min = GRCAN_CONF_PS1_MIN + 1, 395 .tseg1_max = GRCAN_CONF_PS1_MAX + 1, 396 .tseg2_min = GRCAN_CONF_PS2_MIN, 397 .tseg2_max = GRCAN_CONF_PS2_MAX, 398 .sjw_max = GRCAN_CONF_RSJ_MAX, 399 .brp_min = GRCAN_CONF_SCALER_MIN + 1, 400 .brp_max = GRCAN_CONF_SCALER_MAX + 1, 401 .brp_inc = GRCAN_CONF_SCALER_INC, 402 }; 403 404 static int grcan_set_bittiming(struct net_device *dev) 405 { 406 struct grcan_priv *priv = netdev_priv(dev); 407 struct grcan_registers __iomem *regs = priv->regs; 408 struct can_bittiming *bt = &priv->can.bittiming; 409 u32 timing = 0; 410 int bpr, rsj, ps1, ps2, scaler; 411 412 /* Should never happen - function will not be called when 413 * device is up 414 */ 415 if (grcan_read_bits(®s->ctrl, GRCAN_CTRL_ENABLE)) 416 return -EBUSY; 417 418 bpr = 0; /* Note bpr and brp are different concepts */ 419 rsj = bt->sjw; 420 ps1 = (bt->prop_seg + bt->phase_seg1) - 1; /* tseg1 - 1 */ 421 ps2 = bt->phase_seg2; 422 scaler = (bt->brp - 1); 423 netdev_dbg(dev, "Request for BPR=%d, RSJ=%d, PS1=%d, PS2=%d, SCALER=%d", 424 bpr, rsj, ps1, ps2, scaler); 425 if (!(ps1 > ps2)) { 426 netdev_err(dev, "PS1 > PS2 must hold: PS1=%d, PS2=%d\n", 427 ps1, ps2); 428 return -EINVAL; 429 } 430 if (!(ps2 >= rsj)) { 431 netdev_err(dev, "PS2 >= RSJ must hold: PS2=%d, RSJ=%d\n", 432 ps2, rsj); 433 return -EINVAL; 434 } 435 436 timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR; 437 timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ; 438 timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1; 439 timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2; 440 timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER; 441 netdev_info(dev, "setting timing=0x%x\n", timing); 442 grcan_write_bits(®s->conf, timing, GRCAN_CONF_TIMING); 443 444 return 0; 445 } 446 447 static int grcan_get_berr_counter(const struct net_device *dev, 448 struct can_berr_counter *bec) 449 { 450 struct grcan_priv *priv = netdev_priv(dev); 451 struct grcan_registers __iomem *regs = priv->regs; 452 u32 status = grcan_read_reg(®s->stat); 453 454 bec->txerr = (status & GRCAN_STAT_TXERRCNT) >> GRCAN_STAT_TXERRCNT_BIT; 455 bec->rxerr = (status & GRCAN_STAT_RXERRCNT) >> GRCAN_STAT_RXERRCNT_BIT; 456 return 0; 457 } 458 459 static int grcan_poll(struct napi_struct *napi, int budget); 460 461 /* Reset device, but keep configuration information */ 462 static void grcan_reset(struct net_device *dev) 463 { 464 struct grcan_priv *priv = netdev_priv(dev); 465 struct grcan_registers __iomem *regs = priv->regs; 466 u32 config = grcan_read_reg(®s->conf); 467 468 grcan_set_bits(®s->ctrl, GRCAN_CTRL_RESET); 469 grcan_write_reg(®s->conf, config); 470 471 priv->eskbp = grcan_read_reg(®s->txrd); 472 priv->can.state = CAN_STATE_STOPPED; 473 474 /* Turn off hardware filtering - regs->rxcode set to 0 by reset */ 475 grcan_write_reg(®s->rxmask, 0); 476 } 477 478 /* stop device without changing any configurations */ 479 static void grcan_stop_hardware(struct net_device *dev) 480 { 481 struct grcan_priv *priv = netdev_priv(dev); 482 struct grcan_registers __iomem *regs = priv->regs; 483 484 grcan_write_reg(®s->imr, GRCAN_IRQ_NONE); 485 grcan_clear_bits(®s->txctrl, GRCAN_TXCTRL_ENABLE); 486 grcan_clear_bits(®s->rxctrl, GRCAN_RXCTRL_ENABLE); 487 grcan_clear_bits(®s->ctrl, GRCAN_CTRL_ENABLE); 488 } 489 490 /* Let priv->eskbp catch up to regs->txrd and echo back the skbs if echo 491 * is true and free them otherwise. 492 * 493 * If budget is >= 0, stop after handling at most budget skbs. Otherwise, 494 * continue until priv->eskbp catches up to regs->txrd. 495 * 496 * priv->lock *must* be held when calling this function 497 */ 498 static int catch_up_echo_skb(struct net_device *dev, int budget, bool echo) 499 { 500 struct grcan_priv *priv = netdev_priv(dev); 501 struct grcan_registers __iomem *regs = priv->regs; 502 struct grcan_dma *dma = &priv->dma; 503 struct net_device_stats *stats = &dev->stats; 504 int i, work_done; 505 506 /* Updates to priv->eskbp and wake-ups of the queue needs to 507 * be atomic towards the reads of priv->eskbp and shut-downs 508 * of the queue in grcan_start_xmit. 509 */ 510 u32 txrd = grcan_read_reg(®s->txrd); 511 512 for (work_done = 0; work_done < budget || budget < 0; work_done++) { 513 if (priv->eskbp == txrd) 514 break; 515 i = priv->eskbp / GRCAN_MSG_SIZE; 516 if (echo) { 517 /* Normal echo of messages */ 518 stats->tx_packets++; 519 stats->tx_bytes += priv->txdlc[i]; 520 priv->txdlc[i] = 0; 521 can_get_echo_skb(dev, i, NULL); 522 } else { 523 /* For cleanup of untransmitted messages */ 524 can_free_echo_skb(dev, i, NULL); 525 } 526 527 priv->eskbp = grcan_ring_add(priv->eskbp, GRCAN_MSG_SIZE, 528 dma->tx.size); 529 txrd = grcan_read_reg(®s->txrd); 530 } 531 return work_done; 532 } 533 534 static void grcan_lost_one_shot_frame(struct net_device *dev) 535 { 536 struct grcan_priv *priv = netdev_priv(dev); 537 struct grcan_registers __iomem *regs = priv->regs; 538 struct grcan_dma *dma = &priv->dma; 539 u32 txrd; 540 unsigned long flags; 541 542 spin_lock_irqsave(&priv->lock, flags); 543 544 catch_up_echo_skb(dev, -1, true); 545 546 if (unlikely(grcan_read_bits(®s->txctrl, GRCAN_TXCTRL_ENABLE))) { 547 /* Should never happen */ 548 netdev_err(dev, "TXCTRL enabled at TXLOSS in one shot mode\n"); 549 } else { 550 /* By the time an GRCAN_IRQ_TXLOSS is generated in 551 * one-shot mode there is no problem in writing 552 * to TXRD even in versions of the hardware in 553 * which GRCAN_TXCTRL_ONGOING is not cleared properly 554 * in one-shot mode. 555 */ 556 557 /* Skip message and discard echo-skb */ 558 txrd = grcan_read_reg(®s->txrd); 559 txrd = grcan_ring_add(txrd, GRCAN_MSG_SIZE, dma->tx.size); 560 grcan_write_reg(®s->txrd, txrd); 561 catch_up_echo_skb(dev, -1, false); 562 563 if (!priv->resetting && !priv->closing && 564 !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) { 565 netif_wake_queue(dev); 566 grcan_set_bits(®s->txctrl, GRCAN_TXCTRL_ENABLE); 567 } 568 } 569 570 spin_unlock_irqrestore(&priv->lock, flags); 571 } 572 573 static void grcan_err(struct net_device *dev, u32 sources, u32 status) 574 { 575 struct grcan_priv *priv = netdev_priv(dev); 576 struct grcan_registers __iomem *regs = priv->regs; 577 struct grcan_dma *dma = &priv->dma; 578 struct net_device_stats *stats = &dev->stats; 579 struct can_frame cf; 580 581 /* Zero potential error_frame */ 582 memset(&cf, 0, sizeof(cf)); 583 584 /* Message lost interrupt. This might be due to arbitration error, but 585 * is also triggered when there is no one else on the can bus or when 586 * there is a problem with the hardware interface or the bus itself. As 587 * arbitration errors can not be singled out, no error frames are 588 * generated reporting this event as an arbitration error. 589 */ 590 if (sources & GRCAN_IRQ_TXLOSS) { 591 /* Take care of failed one-shot transmit */ 592 if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 593 grcan_lost_one_shot_frame(dev); 594 595 /* Stop printing as soon as error passive or bus off is in 596 * effect to limit the amount of txloss debug printouts. 597 */ 598 if (!(status & GRCAN_STAT_ERRCTR_RELATED)) { 599 netdev_dbg(dev, "tx message lost\n"); 600 stats->tx_errors++; 601 } 602 } 603 604 /* Conditions dealing with the error counters. There is no interrupt for 605 * error warning, but there are interrupts for increases of the error 606 * counters. 607 */ 608 if ((sources & GRCAN_IRQ_ERRCTR_RELATED) || 609 (status & GRCAN_STAT_ERRCTR_RELATED)) { 610 enum can_state state = priv->can.state; 611 enum can_state oldstate = state; 612 u32 txerr = (status & GRCAN_STAT_TXERRCNT) 613 >> GRCAN_STAT_TXERRCNT_BIT; 614 u32 rxerr = (status & GRCAN_STAT_RXERRCNT) 615 >> GRCAN_STAT_RXERRCNT_BIT; 616 617 /* Figure out current state */ 618 if (status & GRCAN_STAT_OFF) { 619 state = CAN_STATE_BUS_OFF; 620 } else if (status & GRCAN_STAT_PASS) { 621 state = CAN_STATE_ERROR_PASSIVE; 622 } else if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT || 623 rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) { 624 state = CAN_STATE_ERROR_WARNING; 625 } else { 626 state = CAN_STATE_ERROR_ACTIVE; 627 } 628 629 /* Handle and report state changes */ 630 if (state != oldstate) { 631 switch (state) { 632 case CAN_STATE_BUS_OFF: 633 netdev_dbg(dev, "bus-off\n"); 634 netif_carrier_off(dev); 635 priv->can.can_stats.bus_off++; 636 637 /* Prevent the hardware from recovering from bus 638 * off on its own if restart is disabled. 639 */ 640 if (!priv->can.restart_ms) 641 grcan_stop_hardware(dev); 642 643 cf.can_id |= CAN_ERR_BUSOFF; 644 break; 645 646 case CAN_STATE_ERROR_PASSIVE: 647 netdev_dbg(dev, "Error passive condition\n"); 648 priv->can.can_stats.error_passive++; 649 650 cf.can_id |= CAN_ERR_CRTL; 651 if (txerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT) 652 cf.data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 653 if (rxerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT) 654 cf.data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 655 break; 656 657 case CAN_STATE_ERROR_WARNING: 658 netdev_dbg(dev, "Error warning condition\n"); 659 priv->can.can_stats.error_warning++; 660 661 cf.can_id |= CAN_ERR_CRTL; 662 if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) 663 cf.data[1] |= CAN_ERR_CRTL_TX_WARNING; 664 if (rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) 665 cf.data[1] |= CAN_ERR_CRTL_RX_WARNING; 666 break; 667 668 case CAN_STATE_ERROR_ACTIVE: 669 netdev_dbg(dev, "Error active condition\n"); 670 cf.can_id |= CAN_ERR_CRTL; 671 break; 672 673 default: 674 /* There are no others at this point */ 675 break; 676 } 677 cf.data[6] = txerr; 678 cf.data[7] = rxerr; 679 priv->can.state = state; 680 } 681 682 /* Report automatic restarts */ 683 if (priv->can.restart_ms && oldstate == CAN_STATE_BUS_OFF) { 684 unsigned long flags; 685 686 cf.can_id |= CAN_ERR_RESTARTED; 687 netdev_dbg(dev, "restarted\n"); 688 priv->can.can_stats.restarts++; 689 netif_carrier_on(dev); 690 691 spin_lock_irqsave(&priv->lock, flags); 692 693 if (!priv->resetting && !priv->closing) { 694 u32 txwr = grcan_read_reg(®s->txwr); 695 696 if (grcan_txspace(dma->tx.size, txwr, 697 priv->eskbp)) 698 netif_wake_queue(dev); 699 } 700 701 spin_unlock_irqrestore(&priv->lock, flags); 702 } 703 } 704 705 /* Data overrun interrupt */ 706 if ((sources & GRCAN_IRQ_OR) || (status & GRCAN_STAT_OR)) { 707 netdev_dbg(dev, "got data overrun interrupt\n"); 708 stats->rx_over_errors++; 709 stats->rx_errors++; 710 711 cf.can_id |= CAN_ERR_CRTL; 712 cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 713 } 714 715 /* AHB bus error interrupts (not CAN bus errors) - shut down the 716 * device. 717 */ 718 if (sources & (GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR) || 719 (status & GRCAN_STAT_AHBERR)) { 720 char *txrx = ""; 721 unsigned long flags; 722 723 if (sources & GRCAN_IRQ_TXAHBERR) { 724 txrx = "on tx "; 725 stats->tx_errors++; 726 } else if (sources & GRCAN_IRQ_RXAHBERR) { 727 txrx = "on rx "; 728 stats->rx_errors++; 729 } 730 netdev_err(dev, "Fatal AHB bus error %s- halting device\n", 731 txrx); 732 733 spin_lock_irqsave(&priv->lock, flags); 734 735 /* Prevent anything to be enabled again and halt device */ 736 priv->closing = true; 737 netif_stop_queue(dev); 738 grcan_stop_hardware(dev); 739 priv->can.state = CAN_STATE_STOPPED; 740 741 spin_unlock_irqrestore(&priv->lock, flags); 742 } 743 744 /* Pass on error frame if something to report, 745 * i.e. id contains some information 746 */ 747 if (cf.can_id) { 748 struct can_frame *skb_cf; 749 struct sk_buff *skb = alloc_can_err_skb(dev, &skb_cf); 750 751 if (skb == NULL) { 752 netdev_dbg(dev, "could not allocate error frame\n"); 753 return; 754 } 755 skb_cf->can_id |= cf.can_id; 756 memcpy(skb_cf->data, cf.data, sizeof(cf.data)); 757 758 netif_rx(skb); 759 } 760 } 761 762 static irqreturn_t grcan_interrupt(int irq, void *dev_id) 763 { 764 struct net_device *dev = dev_id; 765 struct grcan_priv *priv = netdev_priv(dev); 766 struct grcan_registers __iomem *regs = priv->regs; 767 u32 sources, status; 768 769 /* Find out the source */ 770 sources = grcan_read_reg(®s->pimsr); 771 if (!sources) 772 return IRQ_NONE; 773 grcan_write_reg(®s->picr, sources); 774 status = grcan_read_reg(®s->stat); 775 776 /* If we got TX progress, the device has not hanged, 777 * so disable the hang timer 778 */ 779 if (priv->need_txbug_workaround && 780 (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_TXLOSS))) { 781 del_timer(&priv->hang_timer); 782 } 783 784 /* Frame(s) received or transmitted */ 785 if (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_RX)) { 786 /* Disable tx/rx interrupts and schedule poll(). No need for 787 * locking as interference from a running reset at worst leads 788 * to an extra interrupt. 789 */ 790 grcan_clear_bits(®s->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX); 791 napi_schedule(&priv->napi); 792 } 793 794 /* (Potential) error conditions to take care of */ 795 if (sources & GRCAN_IRQ_ERRORS) 796 grcan_err(dev, sources, status); 797 798 return IRQ_HANDLED; 799 } 800 801 /* Reset device and restart operations from where they were. 802 * 803 * This assumes that RXCTRL & RXCTRL is properly disabled and that RX 804 * is not ONGOING (TX might be stuck in ONGOING due to a harwrware bug 805 * for single shot) 806 */ 807 static void grcan_running_reset(struct timer_list *t) 808 { 809 struct grcan_priv *priv = from_timer(priv, t, rr_timer); 810 struct net_device *dev = priv->dev; 811 struct grcan_registers __iomem *regs = priv->regs; 812 unsigned long flags; 813 814 /* This temporarily messes with eskbp, so we need to lock 815 * priv->lock 816 */ 817 spin_lock_irqsave(&priv->lock, flags); 818 819 priv->resetting = false; 820 del_timer(&priv->hang_timer); 821 del_timer(&priv->rr_timer); 822 823 if (!priv->closing) { 824 /* Save and reset - config register preserved by grcan_reset */ 825 u32 imr = grcan_read_reg(®s->imr); 826 827 u32 txaddr = grcan_read_reg(®s->txaddr); 828 u32 txsize = grcan_read_reg(®s->txsize); 829 u32 txwr = grcan_read_reg(®s->txwr); 830 u32 txrd = grcan_read_reg(®s->txrd); 831 u32 eskbp = priv->eskbp; 832 833 u32 rxaddr = grcan_read_reg(®s->rxaddr); 834 u32 rxsize = grcan_read_reg(®s->rxsize); 835 u32 rxwr = grcan_read_reg(®s->rxwr); 836 u32 rxrd = grcan_read_reg(®s->rxrd); 837 838 grcan_reset(dev); 839 840 /* Restore */ 841 grcan_write_reg(®s->txaddr, txaddr); 842 grcan_write_reg(®s->txsize, txsize); 843 grcan_write_reg(®s->txwr, txwr); 844 grcan_write_reg(®s->txrd, txrd); 845 priv->eskbp = eskbp; 846 847 grcan_write_reg(®s->rxaddr, rxaddr); 848 grcan_write_reg(®s->rxsize, rxsize); 849 grcan_write_reg(®s->rxwr, rxwr); 850 grcan_write_reg(®s->rxrd, rxrd); 851 852 /* Turn on device again */ 853 grcan_write_reg(®s->imr, imr); 854 priv->can.state = CAN_STATE_ERROR_ACTIVE; 855 grcan_write_reg(®s->txctrl, GRCAN_TXCTRL_ENABLE 856 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT 857 ? GRCAN_TXCTRL_SINGLE : 0)); 858 grcan_write_reg(®s->rxctrl, GRCAN_RXCTRL_ENABLE); 859 grcan_write_reg(®s->ctrl, GRCAN_CTRL_ENABLE); 860 861 /* Start queue if there is size and listen-onle mode is not 862 * enabled 863 */ 864 if (grcan_txspace(priv->dma.tx.size, txwr, priv->eskbp) && 865 !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) 866 netif_wake_queue(dev); 867 } 868 869 spin_unlock_irqrestore(&priv->lock, flags); 870 871 netdev_err(dev, "Device reset and restored\n"); 872 } 873 874 /* Waiting time in usecs corresponding to the transmission of three maximum 875 * sized can frames in the given bitrate (in bits/sec). Waiting for this amount 876 * of time makes sure that the can controller have time to finish sending or 877 * receiving a frame with a good margin. 878 * 879 * usecs/sec * number of frames * bits/frame / bits/sec 880 */ 881 static inline u32 grcan_ongoing_wait_usecs(__u32 bitrate) 882 { 883 return 1000000 * 3 * GRCAN_EFF_FRAME_MAX_BITS / bitrate; 884 } 885 886 /* Set timer so that it will not fire until after a period in which the can 887 * controller have a good margin to finish transmitting a frame unless it has 888 * hanged 889 */ 890 static inline void grcan_reset_timer(struct timer_list *timer, __u32 bitrate) 891 { 892 u32 wait_jiffies = usecs_to_jiffies(grcan_ongoing_wait_usecs(bitrate)); 893 894 mod_timer(timer, jiffies + wait_jiffies); 895 } 896 897 /* Disable channels and schedule a running reset */ 898 static void grcan_initiate_running_reset(struct timer_list *t) 899 { 900 struct grcan_priv *priv = from_timer(priv, t, hang_timer); 901 struct net_device *dev = priv->dev; 902 struct grcan_registers __iomem *regs = priv->regs; 903 unsigned long flags; 904 905 netdev_err(dev, "Device seems hanged - reset scheduled\n"); 906 907 spin_lock_irqsave(&priv->lock, flags); 908 909 /* The main body of this function must never be executed again 910 * until after an execution of grcan_running_reset 911 */ 912 if (!priv->resetting && !priv->closing) { 913 priv->resetting = true; 914 netif_stop_queue(dev); 915 grcan_clear_bits(®s->txctrl, GRCAN_TXCTRL_ENABLE); 916 grcan_clear_bits(®s->rxctrl, GRCAN_RXCTRL_ENABLE); 917 grcan_reset_timer(&priv->rr_timer, priv->can.bittiming.bitrate); 918 } 919 920 spin_unlock_irqrestore(&priv->lock, flags); 921 } 922 923 static void grcan_free_dma_buffers(struct net_device *dev) 924 { 925 struct grcan_priv *priv = netdev_priv(dev); 926 struct grcan_dma *dma = &priv->dma; 927 928 dma_free_coherent(priv->ofdev_dev, dma->base_size, dma->base_buf, 929 dma->base_handle); 930 memset(dma, 0, sizeof(*dma)); 931 } 932 933 static int grcan_allocate_dma_buffers(struct net_device *dev, 934 size_t tsize, size_t rsize) 935 { 936 struct grcan_priv *priv = netdev_priv(dev); 937 struct grcan_dma *dma = &priv->dma; 938 struct grcan_dma_buffer *large = rsize > tsize ? &dma->rx : &dma->tx; 939 struct grcan_dma_buffer *small = rsize > tsize ? &dma->tx : &dma->rx; 940 size_t shift; 941 942 /* Need a whole number of GRCAN_BUFFER_ALIGNMENT for the large, 943 * i.e. first buffer 944 */ 945 size_t maxs = max(tsize, rsize); 946 size_t lsize = ALIGN(maxs, GRCAN_BUFFER_ALIGNMENT); 947 948 /* Put the small buffer after that */ 949 size_t ssize = min(tsize, rsize); 950 951 /* Extra GRCAN_BUFFER_ALIGNMENT to allow for alignment */ 952 dma->base_size = lsize + ssize + GRCAN_BUFFER_ALIGNMENT; 953 dma->base_buf = dma_alloc_coherent(priv->ofdev_dev, 954 dma->base_size, 955 &dma->base_handle, 956 GFP_KERNEL); 957 958 if (!dma->base_buf) 959 return -ENOMEM; 960 961 dma->tx.size = tsize; 962 dma->rx.size = rsize; 963 964 large->handle = ALIGN(dma->base_handle, GRCAN_BUFFER_ALIGNMENT); 965 small->handle = large->handle + lsize; 966 shift = large->handle - dma->base_handle; 967 968 large->buf = dma->base_buf + shift; 969 small->buf = large->buf + lsize; 970 971 return 0; 972 } 973 974 /* priv->lock *must* be held when calling this function */ 975 static int grcan_start(struct net_device *dev) 976 { 977 struct grcan_priv *priv = netdev_priv(dev); 978 struct grcan_registers __iomem *regs = priv->regs; 979 u32 confop, txctrl; 980 981 grcan_reset(dev); 982 983 grcan_write_reg(®s->txaddr, priv->dma.tx.handle); 984 grcan_write_reg(®s->txsize, priv->dma.tx.size); 985 /* regs->txwr, regs->txrd and priv->eskbp already set to 0 by reset */ 986 987 grcan_write_reg(®s->rxaddr, priv->dma.rx.handle); 988 grcan_write_reg(®s->rxsize, priv->dma.rx.size); 989 /* regs->rxwr and regs->rxrd already set to 0 by reset */ 990 991 /* Enable interrupts */ 992 grcan_read_reg(®s->pir); 993 grcan_write_reg(®s->imr, GRCAN_IRQ_DEFAULT); 994 995 /* Enable interfaces, channels and device */ 996 confop = GRCAN_CONF_ABORT 997 | (priv->config.enable0 ? GRCAN_CONF_ENABLE0 : 0) 998 | (priv->config.enable1 ? GRCAN_CONF_ENABLE1 : 0) 999 | (priv->config.select ? GRCAN_CONF_SELECT : 0) 1000 | (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY ? 1001 GRCAN_CONF_SILENT : 0) 1002 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ? 1003 GRCAN_CONF_SAM : 0); 1004 grcan_write_bits(®s->conf, confop, GRCAN_CONF_OPERATION); 1005 txctrl = GRCAN_TXCTRL_ENABLE 1006 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT 1007 ? GRCAN_TXCTRL_SINGLE : 0); 1008 grcan_write_reg(®s->txctrl, txctrl); 1009 grcan_write_reg(®s->rxctrl, GRCAN_RXCTRL_ENABLE); 1010 grcan_write_reg(®s->ctrl, GRCAN_CTRL_ENABLE); 1011 1012 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1013 1014 return 0; 1015 } 1016 1017 static int grcan_set_mode(struct net_device *dev, enum can_mode mode) 1018 { 1019 struct grcan_priv *priv = netdev_priv(dev); 1020 unsigned long flags; 1021 int err = 0; 1022 1023 if (mode == CAN_MODE_START) { 1024 /* This might be called to restart the device to recover from 1025 * bus off errors 1026 */ 1027 spin_lock_irqsave(&priv->lock, flags); 1028 if (priv->closing || priv->resetting) { 1029 err = -EBUSY; 1030 } else { 1031 netdev_info(dev, "Restarting device\n"); 1032 grcan_start(dev); 1033 if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) 1034 netif_wake_queue(dev); 1035 } 1036 spin_unlock_irqrestore(&priv->lock, flags); 1037 return err; 1038 } 1039 return -EOPNOTSUPP; 1040 } 1041 1042 static int grcan_open(struct net_device *dev) 1043 { 1044 struct grcan_priv *priv = netdev_priv(dev); 1045 struct grcan_dma *dma = &priv->dma; 1046 unsigned long flags; 1047 int err; 1048 1049 /* Allocate memory */ 1050 err = grcan_allocate_dma_buffers(dev, priv->config.txsize, 1051 priv->config.rxsize); 1052 if (err) { 1053 netdev_err(dev, "could not allocate DMA buffers\n"); 1054 return err; 1055 } 1056 1057 priv->echo_skb = kcalloc(dma->tx.size, sizeof(*priv->echo_skb), 1058 GFP_KERNEL); 1059 if (!priv->echo_skb) { 1060 err = -ENOMEM; 1061 goto exit_free_dma_buffers; 1062 } 1063 priv->can.echo_skb_max = dma->tx.size; 1064 priv->can.echo_skb = priv->echo_skb; 1065 1066 priv->txdlc = kcalloc(dma->tx.size, sizeof(*priv->txdlc), GFP_KERNEL); 1067 if (!priv->txdlc) { 1068 err = -ENOMEM; 1069 goto exit_free_echo_skb; 1070 } 1071 1072 /* Get can device up */ 1073 err = open_candev(dev); 1074 if (err) 1075 goto exit_free_txdlc; 1076 1077 err = request_irq(dev->irq, grcan_interrupt, IRQF_SHARED, 1078 dev->name, dev); 1079 if (err) 1080 goto exit_close_candev; 1081 1082 spin_lock_irqsave(&priv->lock, flags); 1083 1084 napi_enable(&priv->napi); 1085 grcan_start(dev); 1086 if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) 1087 netif_start_queue(dev); 1088 priv->resetting = false; 1089 priv->closing = false; 1090 1091 spin_unlock_irqrestore(&priv->lock, flags); 1092 1093 return 0; 1094 1095 exit_close_candev: 1096 close_candev(dev); 1097 exit_free_txdlc: 1098 kfree(priv->txdlc); 1099 exit_free_echo_skb: 1100 kfree(priv->echo_skb); 1101 exit_free_dma_buffers: 1102 grcan_free_dma_buffers(dev); 1103 return err; 1104 } 1105 1106 static int grcan_close(struct net_device *dev) 1107 { 1108 struct grcan_priv *priv = netdev_priv(dev); 1109 unsigned long flags; 1110 1111 napi_disable(&priv->napi); 1112 1113 spin_lock_irqsave(&priv->lock, flags); 1114 1115 priv->closing = true; 1116 if (priv->need_txbug_workaround) { 1117 spin_unlock_irqrestore(&priv->lock, flags); 1118 del_timer_sync(&priv->hang_timer); 1119 del_timer_sync(&priv->rr_timer); 1120 spin_lock_irqsave(&priv->lock, flags); 1121 } 1122 netif_stop_queue(dev); 1123 grcan_stop_hardware(dev); 1124 priv->can.state = CAN_STATE_STOPPED; 1125 1126 spin_unlock_irqrestore(&priv->lock, flags); 1127 1128 free_irq(dev->irq, dev); 1129 close_candev(dev); 1130 1131 grcan_free_dma_buffers(dev); 1132 priv->can.echo_skb_max = 0; 1133 priv->can.echo_skb = NULL; 1134 kfree(priv->echo_skb); 1135 kfree(priv->txdlc); 1136 1137 return 0; 1138 } 1139 1140 static void grcan_transmit_catch_up(struct net_device *dev) 1141 { 1142 struct grcan_priv *priv = netdev_priv(dev); 1143 unsigned long flags; 1144 int work_done; 1145 1146 spin_lock_irqsave(&priv->lock, flags); 1147 1148 work_done = catch_up_echo_skb(dev, -1, true); 1149 if (work_done) { 1150 if (!priv->resetting && !priv->closing && 1151 !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) 1152 netif_wake_queue(dev); 1153 1154 /* With napi we don't get TX interrupts for a while, 1155 * so prevent a running reset while catching up 1156 */ 1157 if (priv->need_txbug_workaround) 1158 del_timer(&priv->hang_timer); 1159 } 1160 1161 spin_unlock_irqrestore(&priv->lock, flags); 1162 } 1163 1164 static int grcan_receive(struct net_device *dev, int budget) 1165 { 1166 struct grcan_priv *priv = netdev_priv(dev); 1167 struct grcan_registers __iomem *regs = priv->regs; 1168 struct grcan_dma *dma = &priv->dma; 1169 struct net_device_stats *stats = &dev->stats; 1170 struct can_frame *cf; 1171 struct sk_buff *skb; 1172 u32 wr, rd, startrd; 1173 u32 *slot; 1174 u32 i, rtr, eff, j, shift; 1175 int work_done = 0; 1176 1177 rd = grcan_read_reg(®s->rxrd); 1178 startrd = rd; 1179 for (work_done = 0; work_done < budget; work_done++) { 1180 /* Check for packet to receive */ 1181 wr = grcan_read_reg(®s->rxwr); 1182 if (rd == wr) 1183 break; 1184 1185 /* Take care of packet */ 1186 skb = alloc_can_skb(dev, &cf); 1187 if (skb == NULL) { 1188 netdev_err(dev, 1189 "dropping frame: skb allocation failed\n"); 1190 stats->rx_dropped++; 1191 continue; 1192 } 1193 1194 slot = dma->rx.buf + rd; 1195 eff = slot[0] & GRCAN_MSG_IDE; 1196 rtr = slot[0] & GRCAN_MSG_RTR; 1197 if (eff) { 1198 cf->can_id = ((slot[0] & GRCAN_MSG_EID) 1199 >> GRCAN_MSG_EID_BIT); 1200 cf->can_id |= CAN_EFF_FLAG; 1201 } else { 1202 cf->can_id = ((slot[0] & GRCAN_MSG_BID) 1203 >> GRCAN_MSG_BID_BIT); 1204 } 1205 cf->len = can_cc_dlc2len((slot[1] & GRCAN_MSG_DLC) 1206 >> GRCAN_MSG_DLC_BIT); 1207 if (rtr) { 1208 cf->can_id |= CAN_RTR_FLAG; 1209 } else { 1210 for (i = 0; i < cf->len; i++) { 1211 j = GRCAN_MSG_DATA_SLOT_INDEX(i); 1212 shift = GRCAN_MSG_DATA_SHIFT(i); 1213 cf->data[i] = (u8)(slot[j] >> shift); 1214 } 1215 } 1216 1217 /* Update statistics and read pointer */ 1218 stats->rx_packets++; 1219 stats->rx_bytes += cf->len; 1220 netif_receive_skb(skb); 1221 1222 rd = grcan_ring_add(rd, GRCAN_MSG_SIZE, dma->rx.size); 1223 } 1224 1225 /* Make sure everything is read before allowing hardware to 1226 * use the memory 1227 */ 1228 mb(); 1229 1230 /* Update read pointer - no need to check for ongoing */ 1231 if (likely(rd != startrd)) 1232 grcan_write_reg(®s->rxrd, rd); 1233 1234 return work_done; 1235 } 1236 1237 static int grcan_poll(struct napi_struct *napi, int budget) 1238 { 1239 struct grcan_priv *priv = container_of(napi, struct grcan_priv, napi); 1240 struct net_device *dev = priv->dev; 1241 struct grcan_registers __iomem *regs = priv->regs; 1242 unsigned long flags; 1243 int work_done; 1244 1245 work_done = grcan_receive(dev, budget); 1246 1247 grcan_transmit_catch_up(dev); 1248 1249 if (work_done < budget) { 1250 napi_complete(napi); 1251 1252 /* Guarantee no interference with a running reset that otherwise 1253 * could turn off interrupts. 1254 */ 1255 spin_lock_irqsave(&priv->lock, flags); 1256 1257 /* Enable tx and rx interrupts again. No need to check 1258 * priv->closing as napi_disable in grcan_close is waiting for 1259 * scheduled napi calls to finish. 1260 */ 1261 grcan_set_bits(®s->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX); 1262 1263 spin_unlock_irqrestore(&priv->lock, flags); 1264 } 1265 1266 return work_done; 1267 } 1268 1269 /* Work tx bug by waiting while for the risky situation to clear. If that fails, 1270 * drop a frame in one-shot mode or indicate a busy device otherwise. 1271 * 1272 * Returns 0 on successful wait. Otherwise it sets *netdev_tx_status to the 1273 * value that should be returned by grcan_start_xmit when aborting the xmit. 1274 */ 1275 static int grcan_txbug_workaround(struct net_device *dev, struct sk_buff *skb, 1276 u32 txwr, u32 oneshotmode, 1277 netdev_tx_t *netdev_tx_status) 1278 { 1279 struct grcan_priv *priv = netdev_priv(dev); 1280 struct grcan_registers __iomem *regs = priv->regs; 1281 struct grcan_dma *dma = &priv->dma; 1282 int i; 1283 unsigned long flags; 1284 1285 /* Wait a while for ongoing to be cleared or read pointer to catch up to 1286 * write pointer. The latter is needed due to a bug in older versions of 1287 * GRCAN in which ONGOING is not cleared properly one-shot mode when a 1288 * transmission fails. 1289 */ 1290 for (i = 0; i < GRCAN_SHORTWAIT_USECS; i++) { 1291 udelay(1); 1292 if (!grcan_read_bits(®s->txctrl, GRCAN_TXCTRL_ONGOING) || 1293 grcan_read_reg(®s->txrd) == txwr) { 1294 return 0; 1295 } 1296 } 1297 1298 /* Clean up, in case the situation was not resolved */ 1299 spin_lock_irqsave(&priv->lock, flags); 1300 if (!priv->resetting && !priv->closing) { 1301 /* Queue might have been stopped earlier in grcan_start_xmit */ 1302 if (grcan_txspace(dma->tx.size, txwr, priv->eskbp)) 1303 netif_wake_queue(dev); 1304 /* Set a timer to resolve a hanged tx controller */ 1305 if (!timer_pending(&priv->hang_timer)) 1306 grcan_reset_timer(&priv->hang_timer, 1307 priv->can.bittiming.bitrate); 1308 } 1309 spin_unlock_irqrestore(&priv->lock, flags); 1310 1311 if (oneshotmode) { 1312 /* In one-shot mode we should never end up here because 1313 * then the interrupt handler increases txrd on TXLOSS, 1314 * but it is consistent with one-shot mode to drop the 1315 * frame in this case. 1316 */ 1317 kfree_skb(skb); 1318 *netdev_tx_status = NETDEV_TX_OK; 1319 } else { 1320 /* In normal mode the socket-can transmission queue get 1321 * to keep the frame so that it can be retransmitted 1322 * later 1323 */ 1324 *netdev_tx_status = NETDEV_TX_BUSY; 1325 } 1326 return -EBUSY; 1327 } 1328 1329 /* Notes on the tx cyclic buffer handling: 1330 * 1331 * regs->txwr - the next slot for the driver to put data to be sent 1332 * regs->txrd - the next slot for the device to read data 1333 * priv->eskbp - the next slot for the driver to call can_put_echo_skb for 1334 * 1335 * grcan_start_xmit can enter more messages as long as regs->txwr does 1336 * not reach priv->eskbp (within 1 message gap) 1337 * 1338 * The device sends messages until regs->txrd reaches regs->txwr 1339 * 1340 * The interrupt calls handler calls can_put_echo_skb until 1341 * priv->eskbp reaches regs->txrd 1342 */ 1343 static netdev_tx_t grcan_start_xmit(struct sk_buff *skb, 1344 struct net_device *dev) 1345 { 1346 struct grcan_priv *priv = netdev_priv(dev); 1347 struct grcan_registers __iomem *regs = priv->regs; 1348 struct grcan_dma *dma = &priv->dma; 1349 struct can_frame *cf = (struct can_frame *)skb->data; 1350 u32 id, txwr, txrd, space, txctrl; 1351 int slotindex; 1352 u32 *slot; 1353 u32 i, rtr, eff, dlc, tmp, err; 1354 int j, shift; 1355 unsigned long flags; 1356 u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT; 1357 1358 if (can_dropped_invalid_skb(dev, skb)) 1359 return NETDEV_TX_OK; 1360 1361 /* Trying to transmit in silent mode will generate error interrupts, but 1362 * this should never happen - the queue should not have been started. 1363 */ 1364 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1365 return NETDEV_TX_BUSY; 1366 1367 /* Reads of priv->eskbp and shut-downs of the queue needs to 1368 * be atomic towards the updates to priv->eskbp and wake-ups 1369 * of the queue in the interrupt handler. 1370 */ 1371 spin_lock_irqsave(&priv->lock, flags); 1372 1373 txwr = grcan_read_reg(®s->txwr); 1374 space = grcan_txspace(dma->tx.size, txwr, priv->eskbp); 1375 1376 slotindex = txwr / GRCAN_MSG_SIZE; 1377 slot = dma->tx.buf + txwr; 1378 1379 if (unlikely(space == 1)) 1380 netif_stop_queue(dev); 1381 1382 spin_unlock_irqrestore(&priv->lock, flags); 1383 /* End of critical section*/ 1384 1385 /* This should never happen. If circular buffer is full, the 1386 * netif_stop_queue should have been stopped already. 1387 */ 1388 if (unlikely(!space)) { 1389 netdev_err(dev, "No buffer space, but queue is non-stopped.\n"); 1390 return NETDEV_TX_BUSY; 1391 } 1392 1393 /* Convert and write CAN message to DMA buffer */ 1394 eff = cf->can_id & CAN_EFF_FLAG; 1395 rtr = cf->can_id & CAN_RTR_FLAG; 1396 id = cf->can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK); 1397 dlc = cf->len; 1398 if (eff) 1399 tmp = (id << GRCAN_MSG_EID_BIT) & GRCAN_MSG_EID; 1400 else 1401 tmp = (id << GRCAN_MSG_BID_BIT) & GRCAN_MSG_BID; 1402 slot[0] = (eff ? GRCAN_MSG_IDE : 0) | (rtr ? GRCAN_MSG_RTR : 0) | tmp; 1403 1404 slot[1] = ((dlc << GRCAN_MSG_DLC_BIT) & GRCAN_MSG_DLC); 1405 slot[2] = 0; 1406 slot[3] = 0; 1407 for (i = 0; i < dlc; i++) { 1408 j = GRCAN_MSG_DATA_SLOT_INDEX(i); 1409 shift = GRCAN_MSG_DATA_SHIFT(i); 1410 slot[j] |= cf->data[i] << shift; 1411 } 1412 1413 /* Checking that channel has not been disabled. These cases 1414 * should never happen 1415 */ 1416 txctrl = grcan_read_reg(®s->txctrl); 1417 if (!(txctrl & GRCAN_TXCTRL_ENABLE)) 1418 netdev_err(dev, "tx channel spuriously disabled\n"); 1419 1420 if (oneshotmode && !(txctrl & GRCAN_TXCTRL_SINGLE)) 1421 netdev_err(dev, "one-shot mode spuriously disabled\n"); 1422 1423 /* Bug workaround for old version of grcan where updating txwr 1424 * in the same clock cycle as the controller updates txrd to 1425 * the current txwr could hang the can controller 1426 */ 1427 if (priv->need_txbug_workaround) { 1428 txrd = grcan_read_reg(®s->txrd); 1429 if (unlikely(grcan_ring_sub(txwr, txrd, dma->tx.size) == 1)) { 1430 netdev_tx_t txstatus; 1431 1432 err = grcan_txbug_workaround(dev, skb, txwr, 1433 oneshotmode, &txstatus); 1434 if (err) 1435 return txstatus; 1436 } 1437 } 1438 1439 /* Prepare skb for echoing. This must be after the bug workaround above 1440 * as ownership of the skb is passed on by calling can_put_echo_skb. 1441 * Returning NETDEV_TX_BUSY or accessing skb or cf after a call to 1442 * can_put_echo_skb would be an error unless other measures are 1443 * taken. 1444 */ 1445 priv->txdlc[slotindex] = cf->len; /* Store dlc for statistics */ 1446 can_put_echo_skb(skb, dev, slotindex, 0); 1447 1448 /* Make sure everything is written before allowing hardware to 1449 * read from the memory 1450 */ 1451 wmb(); 1452 1453 /* Update write pointer to start transmission */ 1454 grcan_write_reg(®s->txwr, 1455 grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size)); 1456 1457 return NETDEV_TX_OK; 1458 } 1459 1460 /* ========== Setting up sysfs interface and module parameters ========== */ 1461 1462 #define GRCAN_NOT_BOOL(unsigned_val) ((unsigned_val) > 1) 1463 1464 #define GRCAN_MODULE_PARAM(name, mtype, valcheckf, desc) \ 1465 static void grcan_sanitize_##name(struct platform_device *pd) \ 1466 { \ 1467 struct grcan_device_config grcan_default_config \ 1468 = GRCAN_DEFAULT_DEVICE_CONFIG; \ 1469 if (valcheckf(grcan_module_config.name)) { \ 1470 dev_err(&pd->dev, \ 1471 "Invalid module parameter value for " \ 1472 #name " - setting default\n"); \ 1473 grcan_module_config.name = \ 1474 grcan_default_config.name; \ 1475 } \ 1476 } \ 1477 module_param_named(name, grcan_module_config.name, \ 1478 mtype, 0444); \ 1479 MODULE_PARM_DESC(name, desc) 1480 1481 #define GRCAN_CONFIG_ATTR(name, desc) \ 1482 static ssize_t grcan_store_##name(struct device *sdev, \ 1483 struct device_attribute *att, \ 1484 const char *buf, \ 1485 size_t count) \ 1486 { \ 1487 struct net_device *dev = to_net_dev(sdev); \ 1488 struct grcan_priv *priv = netdev_priv(dev); \ 1489 u8 val; \ 1490 int ret; \ 1491 if (dev->flags & IFF_UP) \ 1492 return -EBUSY; \ 1493 ret = kstrtou8(buf, 0, &val); \ 1494 if (ret < 0 || val > 1) \ 1495 return -EINVAL; \ 1496 priv->config.name = val; \ 1497 return count; \ 1498 } \ 1499 static ssize_t grcan_show_##name(struct device *sdev, \ 1500 struct device_attribute *att, \ 1501 char *buf) \ 1502 { \ 1503 struct net_device *dev = to_net_dev(sdev); \ 1504 struct grcan_priv *priv = netdev_priv(dev); \ 1505 return sprintf(buf, "%d\n", priv->config.name); \ 1506 } \ 1507 static DEVICE_ATTR(name, 0644, \ 1508 grcan_show_##name, \ 1509 grcan_store_##name); \ 1510 GRCAN_MODULE_PARAM(name, ushort, GRCAN_NOT_BOOL, desc) 1511 1512 /* The following configuration options are made available both via module 1513 * parameters and writable sysfs files. See the chapter about GRCAN in the 1514 * documentation for the GRLIB VHDL library for further details. 1515 */ 1516 GRCAN_CONFIG_ATTR(enable0, 1517 "Configuration of physical interface 0. Determines\n" \ 1518 "the \"Enable 0\" bit of the configuration register.\n" \ 1519 "Format: 0 | 1\nDefault: 0\n"); 1520 1521 GRCAN_CONFIG_ATTR(enable1, 1522 "Configuration of physical interface 1. Determines\n" \ 1523 "the \"Enable 1\" bit of the configuration register.\n" \ 1524 "Format: 0 | 1\nDefault: 0\n"); 1525 1526 GRCAN_CONFIG_ATTR(select, 1527 "Select which physical interface to use.\n" \ 1528 "Format: 0 | 1\nDefault: 0\n"); 1529 1530 /* The tx and rx buffer size configuration options are only available via module 1531 * parameters. 1532 */ 1533 GRCAN_MODULE_PARAM(txsize, uint, GRCAN_INVALID_BUFFER_SIZE, 1534 "Sets the size of the tx buffer.\n" \ 1535 "Format: <unsigned int> where (txsize & ~0x1fffc0) == 0\n" \ 1536 "Default: 1024\n"); 1537 GRCAN_MODULE_PARAM(rxsize, uint, GRCAN_INVALID_BUFFER_SIZE, 1538 "Sets the size of the rx buffer.\n" \ 1539 "Format: <unsigned int> where (size & ~0x1fffc0) == 0\n" \ 1540 "Default: 1024\n"); 1541 1542 /* Function that makes sure that configuration done using 1543 * module parameters are set to valid values 1544 */ 1545 static void grcan_sanitize_module_config(struct platform_device *ofdev) 1546 { 1547 grcan_sanitize_enable0(ofdev); 1548 grcan_sanitize_enable1(ofdev); 1549 grcan_sanitize_select(ofdev); 1550 grcan_sanitize_txsize(ofdev); 1551 grcan_sanitize_rxsize(ofdev); 1552 } 1553 1554 static const struct attribute *const sysfs_grcan_attrs[] = { 1555 /* Config attrs */ 1556 &dev_attr_enable0.attr, 1557 &dev_attr_enable1.attr, 1558 &dev_attr_select.attr, 1559 NULL, 1560 }; 1561 1562 static const struct attribute_group sysfs_grcan_group = { 1563 .name = "grcan", 1564 .attrs = (struct attribute **)sysfs_grcan_attrs, 1565 }; 1566 1567 /* ========== Setting up the driver ========== */ 1568 1569 static const struct net_device_ops grcan_netdev_ops = { 1570 .ndo_open = grcan_open, 1571 .ndo_stop = grcan_close, 1572 .ndo_start_xmit = grcan_start_xmit, 1573 .ndo_change_mtu = can_change_mtu, 1574 }; 1575 1576 static int grcan_setup_netdev(struct platform_device *ofdev, 1577 void __iomem *base, 1578 int irq, u32 ambafreq, bool txbug) 1579 { 1580 struct net_device *dev; 1581 struct grcan_priv *priv; 1582 struct grcan_registers __iomem *regs; 1583 int err; 1584 1585 dev = alloc_candev(sizeof(struct grcan_priv), 0); 1586 if (!dev) 1587 return -ENOMEM; 1588 1589 dev->irq = irq; 1590 dev->flags |= IFF_ECHO; 1591 dev->netdev_ops = &grcan_netdev_ops; 1592 dev->sysfs_groups[0] = &sysfs_grcan_group; 1593 1594 priv = netdev_priv(dev); 1595 memcpy(&priv->config, &grcan_module_config, 1596 sizeof(struct grcan_device_config)); 1597 priv->dev = dev; 1598 priv->ofdev_dev = &ofdev->dev; 1599 priv->regs = base; 1600 priv->can.bittiming_const = &grcan_bittiming_const; 1601 priv->can.do_set_bittiming = grcan_set_bittiming; 1602 priv->can.do_set_mode = grcan_set_mode; 1603 priv->can.do_get_berr_counter = grcan_get_berr_counter; 1604 priv->can.clock.freq = ambafreq; 1605 priv->can.ctrlmode_supported = 1606 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_ONE_SHOT; 1607 priv->need_txbug_workaround = txbug; 1608 1609 /* Discover if triple sampling is supported by hardware */ 1610 regs = priv->regs; 1611 grcan_set_bits(®s->ctrl, GRCAN_CTRL_RESET); 1612 grcan_set_bits(®s->conf, GRCAN_CONF_SAM); 1613 if (grcan_read_bits(®s->conf, GRCAN_CONF_SAM)) { 1614 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES; 1615 dev_dbg(&ofdev->dev, "Hardware supports triple-sampling\n"); 1616 } 1617 1618 spin_lock_init(&priv->lock); 1619 1620 if (priv->need_txbug_workaround) { 1621 timer_setup(&priv->rr_timer, grcan_running_reset, 0); 1622 timer_setup(&priv->hang_timer, grcan_initiate_running_reset, 0); 1623 } 1624 1625 netif_napi_add(dev, &priv->napi, grcan_poll, GRCAN_NAPI_WEIGHT); 1626 1627 SET_NETDEV_DEV(dev, &ofdev->dev); 1628 dev_info(&ofdev->dev, "regs=0x%p, irq=%d, clock=%d\n", 1629 priv->regs, dev->irq, priv->can.clock.freq); 1630 1631 err = register_candev(dev); 1632 if (err) 1633 goto exit_free_candev; 1634 1635 platform_set_drvdata(ofdev, dev); 1636 1637 /* Reset device to allow bit-timing to be set. No need to call 1638 * grcan_reset at this stage. That is done in grcan_open. 1639 */ 1640 grcan_write_reg(®s->ctrl, GRCAN_CTRL_RESET); 1641 1642 return 0; 1643 exit_free_candev: 1644 free_candev(dev); 1645 return err; 1646 } 1647 1648 static int grcan_probe(struct platform_device *ofdev) 1649 { 1650 struct device_node *np = ofdev->dev.of_node; 1651 struct device_node *sysid_parent; 1652 u32 sysid, ambafreq; 1653 int irq, err; 1654 void __iomem *base; 1655 bool txbug = true; 1656 1657 /* Compare GRLIB version number with the first that does not 1658 * have the tx bug (see start_xmit) 1659 */ 1660 sysid_parent = of_find_node_by_path("/ambapp0"); 1661 if (sysid_parent) { 1662 err = of_property_read_u32(sysid_parent, "systemid", &sysid); 1663 if (!err && ((sysid & GRLIB_VERSION_MASK) >= 1664 GRCAN_TXBUG_SAFE_GRLIB_VERSION)) 1665 txbug = false; 1666 of_node_put(sysid_parent); 1667 } 1668 1669 err = of_property_read_u32(np, "freq", &ambafreq); 1670 if (err) { 1671 dev_err(&ofdev->dev, "unable to fetch \"freq\" property\n"); 1672 goto exit_error; 1673 } 1674 1675 base = devm_platform_ioremap_resource(ofdev, 0); 1676 if (IS_ERR(base)) { 1677 err = PTR_ERR(base); 1678 goto exit_error; 1679 } 1680 1681 irq = irq_of_parse_and_map(np, GRCAN_IRQIX_IRQ); 1682 if (!irq) { 1683 dev_err(&ofdev->dev, "no irq found\n"); 1684 err = -ENODEV; 1685 goto exit_error; 1686 } 1687 1688 grcan_sanitize_module_config(ofdev); 1689 1690 err = grcan_setup_netdev(ofdev, base, irq, ambafreq, txbug); 1691 if (err) 1692 goto exit_dispose_irq; 1693 1694 return 0; 1695 1696 exit_dispose_irq: 1697 irq_dispose_mapping(irq); 1698 exit_error: 1699 dev_err(&ofdev->dev, 1700 "%s socket CAN driver initialization failed with error %d\n", 1701 DRV_NAME, err); 1702 return err; 1703 } 1704 1705 static int grcan_remove(struct platform_device *ofdev) 1706 { 1707 struct net_device *dev = platform_get_drvdata(ofdev); 1708 struct grcan_priv *priv = netdev_priv(dev); 1709 1710 unregister_candev(dev); /* Will in turn call grcan_close */ 1711 1712 irq_dispose_mapping(dev->irq); 1713 netif_napi_del(&priv->napi); 1714 free_candev(dev); 1715 1716 return 0; 1717 } 1718 1719 static const struct of_device_id grcan_match[] = { 1720 {.name = "GAISLER_GRCAN"}, 1721 {.name = "01_03d"}, 1722 {.name = "GAISLER_GRHCAN"}, 1723 {.name = "01_034"}, 1724 {}, 1725 }; 1726 1727 MODULE_DEVICE_TABLE(of, grcan_match); 1728 1729 static struct platform_driver grcan_driver = { 1730 .driver = { 1731 .name = DRV_NAME, 1732 .of_match_table = grcan_match, 1733 }, 1734 .probe = grcan_probe, 1735 .remove = grcan_remove, 1736 }; 1737 1738 module_platform_driver(grcan_driver); 1739 1740 MODULE_AUTHOR("Aeroflex Gaisler AB."); 1741 MODULE_DESCRIPTION("Socket CAN driver for Aeroflex Gaisler GRCAN"); 1742 MODULE_LICENSE("GPL"); 1743