1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // flexcan.c - FLEXCAN CAN controller driver
4 //
5 // Copyright (c) 2005-2006 Varma Electronics Oy
6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2014 David Jander, Protonic Holland
9 //
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 
12 #include <dt-bindings/firmware/imx/rsrc.h>
13 #include <linux/bitfield.h>
14 #include <linux/can.h>
15 #include <linux/can/dev.h>
16 #include <linux/can/error.h>
17 #include <linux/can/led.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/firmware/imx/sci.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/netdevice.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_device.h>
30 #include <linux/can/platform/flexcan.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regmap.h>
33 #include <linux/regulator/consumer.h>
34 
35 #include "flexcan.h"
36 
37 #define DRV_NAME			"flexcan"
38 
39 /* 8 for RX fifo and 2 error handling */
40 #define FLEXCAN_NAPI_WEIGHT		(8 + 2)
41 
42 /* FLEXCAN module configuration register (CANMCR) bits */
43 #define FLEXCAN_MCR_MDIS		BIT(31)
44 #define FLEXCAN_MCR_FRZ			BIT(30)
45 #define FLEXCAN_MCR_FEN			BIT(29)
46 #define FLEXCAN_MCR_HALT		BIT(28)
47 #define FLEXCAN_MCR_NOT_RDY		BIT(27)
48 #define FLEXCAN_MCR_WAK_MSK		BIT(26)
49 #define FLEXCAN_MCR_SOFTRST		BIT(25)
50 #define FLEXCAN_MCR_FRZ_ACK		BIT(24)
51 #define FLEXCAN_MCR_SUPV		BIT(23)
52 #define FLEXCAN_MCR_SLF_WAK		BIT(22)
53 #define FLEXCAN_MCR_WRN_EN		BIT(21)
54 #define FLEXCAN_MCR_LPM_ACK		BIT(20)
55 #define FLEXCAN_MCR_WAK_SRC		BIT(19)
56 #define FLEXCAN_MCR_DOZE		BIT(18)
57 #define FLEXCAN_MCR_SRX_DIS		BIT(17)
58 #define FLEXCAN_MCR_IRMQ		BIT(16)
59 #define FLEXCAN_MCR_LPRIO_EN		BIT(13)
60 #define FLEXCAN_MCR_AEN			BIT(12)
61 #define FLEXCAN_MCR_FDEN		BIT(11)
62 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
63 #define FLEXCAN_MCR_MAXMB(x)		((x) & 0x7f)
64 #define FLEXCAN_MCR_IDAM_A		(0x0 << 8)
65 #define FLEXCAN_MCR_IDAM_B		(0x1 << 8)
66 #define FLEXCAN_MCR_IDAM_C		(0x2 << 8)
67 #define FLEXCAN_MCR_IDAM_D		(0x3 << 8)
68 
69 /* FLEXCAN control register (CANCTRL) bits */
70 #define FLEXCAN_CTRL_PRESDIV(x)		(((x) & 0xff) << 24)
71 #define FLEXCAN_CTRL_RJW(x)		(((x) & 0x03) << 22)
72 #define FLEXCAN_CTRL_PSEG1(x)		(((x) & 0x07) << 19)
73 #define FLEXCAN_CTRL_PSEG2(x)		(((x) & 0x07) << 16)
74 #define FLEXCAN_CTRL_BOFF_MSK		BIT(15)
75 #define FLEXCAN_CTRL_ERR_MSK		BIT(14)
76 #define FLEXCAN_CTRL_CLK_SRC		BIT(13)
77 #define FLEXCAN_CTRL_LPB		BIT(12)
78 #define FLEXCAN_CTRL_TWRN_MSK		BIT(11)
79 #define FLEXCAN_CTRL_RWRN_MSK		BIT(10)
80 #define FLEXCAN_CTRL_SMP		BIT(7)
81 #define FLEXCAN_CTRL_BOFF_REC		BIT(6)
82 #define FLEXCAN_CTRL_TSYN		BIT(5)
83 #define FLEXCAN_CTRL_LBUF		BIT(4)
84 #define FLEXCAN_CTRL_LOM		BIT(3)
85 #define FLEXCAN_CTRL_PROPSEG(x)		((x) & 0x07)
86 #define FLEXCAN_CTRL_ERR_BUS		(FLEXCAN_CTRL_ERR_MSK)
87 #define FLEXCAN_CTRL_ERR_STATE \
88 	(FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
89 	 FLEXCAN_CTRL_BOFF_MSK)
90 #define FLEXCAN_CTRL_ERR_ALL \
91 	(FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
92 
93 /* FLEXCAN control register 2 (CTRL2) bits */
94 #define FLEXCAN_CTRL2_ECRWRE		BIT(29)
95 #define FLEXCAN_CTRL2_WRMFRZ		BIT(28)
96 #define FLEXCAN_CTRL2_RFFN(x)		(((x) & 0x0f) << 24)
97 #define FLEXCAN_CTRL2_TASD(x)		(((x) & 0x1f) << 19)
98 #define FLEXCAN_CTRL2_MRP		BIT(18)
99 #define FLEXCAN_CTRL2_RRS		BIT(17)
100 #define FLEXCAN_CTRL2_EACEN		BIT(16)
101 #define FLEXCAN_CTRL2_ISOCANFDEN	BIT(12)
102 
103 /* FLEXCAN memory error control register (MECR) bits */
104 #define FLEXCAN_MECR_ECRWRDIS		BIT(31)
105 #define FLEXCAN_MECR_HANCEI_MSK		BIT(19)
106 #define FLEXCAN_MECR_FANCEI_MSK		BIT(18)
107 #define FLEXCAN_MECR_CEI_MSK		BIT(16)
108 #define FLEXCAN_MECR_HAERRIE		BIT(15)
109 #define FLEXCAN_MECR_FAERRIE		BIT(14)
110 #define FLEXCAN_MECR_EXTERRIE		BIT(13)
111 #define FLEXCAN_MECR_RERRDIS		BIT(9)
112 #define FLEXCAN_MECR_ECCDIS		BIT(8)
113 #define FLEXCAN_MECR_NCEFAFRZ		BIT(7)
114 
115 /* FLEXCAN error and status register (ESR) bits */
116 #define FLEXCAN_ESR_TWRN_INT		BIT(17)
117 #define FLEXCAN_ESR_RWRN_INT		BIT(16)
118 #define FLEXCAN_ESR_BIT1_ERR		BIT(15)
119 #define FLEXCAN_ESR_BIT0_ERR		BIT(14)
120 #define FLEXCAN_ESR_ACK_ERR		BIT(13)
121 #define FLEXCAN_ESR_CRC_ERR		BIT(12)
122 #define FLEXCAN_ESR_FRM_ERR		BIT(11)
123 #define FLEXCAN_ESR_STF_ERR		BIT(10)
124 #define FLEXCAN_ESR_TX_WRN		BIT(9)
125 #define FLEXCAN_ESR_RX_WRN		BIT(8)
126 #define FLEXCAN_ESR_IDLE		BIT(7)
127 #define FLEXCAN_ESR_TXRX		BIT(6)
128 #define FLEXCAN_EST_FLT_CONF_SHIFT	(4)
129 #define FLEXCAN_ESR_FLT_CONF_MASK	(0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_FLT_CONF_ACTIVE	(0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_PASSIVE	(0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_BOFF_INT		BIT(2)
133 #define FLEXCAN_ESR_ERR_INT		BIT(1)
134 #define FLEXCAN_ESR_WAK_INT		BIT(0)
135 #define FLEXCAN_ESR_ERR_BUS \
136 	(FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
137 	 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
138 	 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
139 #define FLEXCAN_ESR_ERR_STATE \
140 	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
141 #define FLEXCAN_ESR_ERR_ALL \
142 	(FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
143 #define FLEXCAN_ESR_ALL_INT \
144 	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
145 	 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
146 
147 /* FLEXCAN Bit Timing register (CBT) bits */
148 #define FLEXCAN_CBT_BTF			BIT(31)
149 #define FLEXCAN_CBT_EPRESDIV_MASK	GENMASK(30, 21)
150 #define FLEXCAN_CBT_ERJW_MASK		GENMASK(20, 16)
151 #define FLEXCAN_CBT_EPROPSEG_MASK	GENMASK(15, 10)
152 #define FLEXCAN_CBT_EPSEG1_MASK		GENMASK(9, 5)
153 #define FLEXCAN_CBT_EPSEG2_MASK		GENMASK(4, 0)
154 
155 /* FLEXCAN FD control register (FDCTRL) bits */
156 #define FLEXCAN_FDCTRL_FDRATE		BIT(31)
157 #define FLEXCAN_FDCTRL_MBDSR1		GENMASK(20, 19)
158 #define FLEXCAN_FDCTRL_MBDSR0		GENMASK(17, 16)
159 #define FLEXCAN_FDCTRL_MBDSR_8		0x0
160 #define FLEXCAN_FDCTRL_MBDSR_12		0x1
161 #define FLEXCAN_FDCTRL_MBDSR_32		0x2
162 #define FLEXCAN_FDCTRL_MBDSR_64		0x3
163 #define FLEXCAN_FDCTRL_TDCEN		BIT(15)
164 #define FLEXCAN_FDCTRL_TDCFAIL		BIT(14)
165 #define FLEXCAN_FDCTRL_TDCOFF		GENMASK(12, 8)
166 #define FLEXCAN_FDCTRL_TDCVAL		GENMASK(5, 0)
167 
168 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
169 #define FLEXCAN_FDCBT_FPRESDIV_MASK	GENMASK(29, 20)
170 #define FLEXCAN_FDCBT_FRJW_MASK		GENMASK(18, 16)
171 #define FLEXCAN_FDCBT_FPROPSEG_MASK	GENMASK(14, 10)
172 #define FLEXCAN_FDCBT_FPSEG1_MASK	GENMASK(7, 5)
173 #define FLEXCAN_FDCBT_FPSEG2_MASK	GENMASK(2, 0)
174 
175 /* FLEXCAN interrupt flag register (IFLAG) bits */
176 /* Errata ERR005829 step7: Reserve first valid MB */
177 #define FLEXCAN_TX_MB_RESERVED_RX_FIFO	8
178 #define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX	0
179 #define FLEXCAN_RX_MB_RX_MAILBOX_FIRST	(FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1)
180 #define FLEXCAN_IFLAG_MB(x)		BIT_ULL(x)
181 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW	BIT(7)
182 #define FLEXCAN_IFLAG_RX_FIFO_WARN	BIT(6)
183 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE	BIT(5)
184 
185 /* FLEXCAN message buffers */
186 #define FLEXCAN_MB_CODE_MASK		(0xf << 24)
187 #define FLEXCAN_MB_CODE_RX_BUSY_BIT	(0x1 << 24)
188 #define FLEXCAN_MB_CODE_RX_INACTIVE	(0x0 << 24)
189 #define FLEXCAN_MB_CODE_RX_EMPTY	(0x4 << 24)
190 #define FLEXCAN_MB_CODE_RX_FULL		(0x2 << 24)
191 #define FLEXCAN_MB_CODE_RX_OVERRUN	(0x6 << 24)
192 #define FLEXCAN_MB_CODE_RX_RANSWER	(0xa << 24)
193 
194 #define FLEXCAN_MB_CODE_TX_INACTIVE	(0x8 << 24)
195 #define FLEXCAN_MB_CODE_TX_ABORT	(0x9 << 24)
196 #define FLEXCAN_MB_CODE_TX_DATA		(0xc << 24)
197 #define FLEXCAN_MB_CODE_TX_TANSWER	(0xe << 24)
198 
199 #define FLEXCAN_MB_CNT_EDL		BIT(31)
200 #define FLEXCAN_MB_CNT_BRS		BIT(30)
201 #define FLEXCAN_MB_CNT_ESI		BIT(29)
202 #define FLEXCAN_MB_CNT_SRR		BIT(22)
203 #define FLEXCAN_MB_CNT_IDE		BIT(21)
204 #define FLEXCAN_MB_CNT_RTR		BIT(20)
205 #define FLEXCAN_MB_CNT_LENGTH(x)	(((x) & 0xf) << 16)
206 #define FLEXCAN_MB_CNT_TIMESTAMP(x)	((x) & 0xffff)
207 
208 #define FLEXCAN_TIMEOUT_US		(250)
209 
210 /* Structure of the message buffer */
211 struct flexcan_mb {
212 	u32 can_ctrl;
213 	u32 can_id;
214 	u32 data[];
215 };
216 
217 /* Structure of the hardware registers */
218 struct flexcan_regs {
219 	u32 mcr;		/* 0x00 */
220 	u32 ctrl;		/* 0x04 - Not affected by Soft Reset */
221 	u32 timer;		/* 0x08 */
222 	u32 tcr;		/* 0x0c */
223 	u32 rxgmask;		/* 0x10 - Not affected by Soft Reset */
224 	u32 rx14mask;		/* 0x14 - Not affected by Soft Reset */
225 	u32 rx15mask;		/* 0x18 - Not affected by Soft Reset */
226 	u32 ecr;		/* 0x1c */
227 	u32 esr;		/* 0x20 */
228 	u32 imask2;		/* 0x24 */
229 	u32 imask1;		/* 0x28 */
230 	u32 iflag2;		/* 0x2c */
231 	u32 iflag1;		/* 0x30 */
232 	union {			/* 0x34 */
233 		u32 gfwr_mx28;	/* MX28, MX53 */
234 		u32 ctrl2;	/* MX6, VF610 - Not affected by Soft Reset */
235 	};
236 	u32 esr2;		/* 0x38 */
237 	u32 imeur;		/* 0x3c */
238 	u32 lrfr;		/* 0x40 */
239 	u32 crcr;		/* 0x44 */
240 	u32 rxfgmask;		/* 0x48 */
241 	u32 rxfir;		/* 0x4c - Not affected by Soft Reset */
242 	u32 cbt;		/* 0x50 - Not affected by Soft Reset */
243 	u32 _reserved2;		/* 0x54 */
244 	u32 dbg1;		/* 0x58 */
245 	u32 dbg2;		/* 0x5c */
246 	u32 _reserved3[8];	/* 0x60 */
247 	struct_group(init,
248 		u8 mb[2][512];		/* 0x80 - Not affected by Soft Reset */
249 		/* FIFO-mode:
250 		 *			MB
251 		 * 0x080...0x08f	0	RX message buffer
252 		 * 0x090...0x0df	1-5	reserved
253 		 * 0x0e0...0x0ff	6-7	8 entry ID table
254 		 *				(mx25, mx28, mx35, mx53)
255 		 * 0x0e0...0x2df	6-7..37	8..128 entry ID table
256 		 *				size conf'ed via ctrl2::RFFN
257 		 *				(mx6, vf610)
258 		 */
259 		u32 _reserved4[256];	/* 0x480 */
260 		u32 rximr[64];		/* 0x880 - Not affected by Soft Reset */
261 		u32 _reserved5[24];	/* 0x980 */
262 		u32 gfwr_mx6;		/* 0x9e0 - MX6 */
263 		u32 _reserved6[39];	/* 0x9e4 */
264 		u32 _rxfir[6];		/* 0xa80 */
265 		u32 _reserved8[2];	/* 0xa98 */
266 		u32 _rxmgmask;		/* 0xaa0 */
267 		u32 _rxfgmask;		/* 0xaa4 */
268 		u32 _rx14mask;		/* 0xaa8 */
269 		u32 _rx15mask;		/* 0xaac */
270 		u32 tx_smb[4];		/* 0xab0 */
271 		u32 rx_smb0[4];		/* 0xac0 */
272 		u32 rx_smb1[4];		/* 0xad0 */
273 	);
274 	u32 mecr;		/* 0xae0 */
275 	u32 erriar;		/* 0xae4 */
276 	u32 erridpr;		/* 0xae8 */
277 	u32 errippr;		/* 0xaec */
278 	u32 rerrar;		/* 0xaf0 */
279 	u32 rerrdr;		/* 0xaf4 */
280 	u32 rerrsynr;		/* 0xaf8 */
281 	u32 errsr;		/* 0xafc */
282 	u32 _reserved7[64];	/* 0xb00 */
283 	u32 fdctrl;		/* 0xc00 - Not affected by Soft Reset */
284 	u32 fdcbt;		/* 0xc04 - Not affected by Soft Reset */
285 	u32 fdcrc;		/* 0xc08 */
286 	u32 _reserved9[199];	/* 0xc0c */
287 	struct_group(init_fd,
288 		u32 tx_smb_fd[18];	/* 0xf28 */
289 		u32 rx_smb0_fd[18];	/* 0xf70 */
290 		u32 rx_smb1_fd[18];	/* 0xfb8 */
291 	);
292 };
293 
294 static_assert(sizeof(struct flexcan_regs) ==  0x4 * 18 + 0xfb8);
295 
296 static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = {
297 	.quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
298 		FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 |
299 		FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
300 };
301 
302 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
303 	.quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
304 		FLEXCAN_QUIRK_BROKEN_PERR_STATE |
305 		FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN |
306 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
307 		FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
308 };
309 
310 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
311 	.quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
312 		FLEXCAN_QUIRK_BROKEN_PERR_STATE |
313 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
314 		FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
315 };
316 
317 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
318 	.quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
319 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
320 		FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
321 };
322 
323 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
324 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
325 		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
326 		FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
327 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
328 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
329 };
330 
331 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
332 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
333 		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
334 		FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW |
335 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
336 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
337 };
338 
339 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
340 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
341 		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
342 		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
343 		FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
344 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
345 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
346 };
347 
348 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
349 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
350 		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
351 		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC |
352 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
353 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
354 };
355 
356 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
357 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
358 		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX |
359 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
360 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
361 };
362 
363 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
364 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
365 		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
366 		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
367 		FLEXCAN_QUIRK_SUPPORT_ECC |
368 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
369 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
370 };
371 
372 static const struct can_bittiming_const flexcan_bittiming_const = {
373 	.name = DRV_NAME,
374 	.tseg1_min = 4,
375 	.tseg1_max = 16,
376 	.tseg2_min = 2,
377 	.tseg2_max = 8,
378 	.sjw_max = 4,
379 	.brp_min = 1,
380 	.brp_max = 256,
381 	.brp_inc = 1,
382 };
383 
384 static const struct can_bittiming_const flexcan_fd_bittiming_const = {
385 	.name = DRV_NAME,
386 	.tseg1_min = 2,
387 	.tseg1_max = 96,
388 	.tseg2_min = 2,
389 	.tseg2_max = 32,
390 	.sjw_max = 16,
391 	.brp_min = 1,
392 	.brp_max = 1024,
393 	.brp_inc = 1,
394 };
395 
396 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
397 	.name = DRV_NAME,
398 	.tseg1_min = 2,
399 	.tseg1_max = 39,
400 	.tseg2_min = 2,
401 	.tseg2_max = 8,
402 	.sjw_max = 4,
403 	.brp_min = 1,
404 	.brp_max = 1024,
405 	.brp_inc = 1,
406 };
407 
408 /* FlexCAN module is essentially modelled as a little-endian IP in most
409  * SoCs, i.e the registers as well as the message buffer areas are
410  * implemented in a little-endian fashion.
411  *
412  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
413  * module in a big-endian fashion (i.e the registers as well as the
414  * message buffer areas are implemented in a big-endian way).
415  *
416  * In addition, the FlexCAN module can be found on SoCs having ARM or
417  * PPC cores. So, we need to abstract off the register read/write
418  * functions, ensuring that these cater to all the combinations of module
419  * endianness and underlying CPU endianness.
420  */
421 static inline u32 flexcan_read_be(void __iomem *addr)
422 {
423 	return ioread32be(addr);
424 }
425 
426 static inline void flexcan_write_be(u32 val, void __iomem *addr)
427 {
428 	iowrite32be(val, addr);
429 }
430 
431 static inline u32 flexcan_read_le(void __iomem *addr)
432 {
433 	return ioread32(addr);
434 }
435 
436 static inline void flexcan_write_le(u32 val, void __iomem *addr)
437 {
438 	iowrite32(val, addr);
439 }
440 
441 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
442 						 u8 mb_index)
443 {
444 	u8 bank_size;
445 	bool bank;
446 
447 	if (WARN_ON(mb_index >= priv->mb_count))
448 		return NULL;
449 
450 	bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
451 
452 	bank = mb_index >= bank_size;
453 	if (bank)
454 		mb_index -= bank_size;
455 
456 	return (struct flexcan_mb __iomem *)
457 		(&priv->regs->mb[bank][priv->mb_size * mb_index]);
458 }
459 
460 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
461 {
462 	struct flexcan_regs __iomem *regs = priv->regs;
463 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
464 
465 	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
466 		udelay(10);
467 
468 	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
469 		return -ETIMEDOUT;
470 
471 	return 0;
472 }
473 
474 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
475 {
476 	struct flexcan_regs __iomem *regs = priv->regs;
477 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
478 
479 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
480 		udelay(10);
481 
482 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
483 		return -ETIMEDOUT;
484 
485 	return 0;
486 }
487 
488 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
489 {
490 	struct flexcan_regs __iomem *regs = priv->regs;
491 	u32 reg_mcr;
492 
493 	reg_mcr = priv->read(&regs->mcr);
494 
495 	if (enable)
496 		reg_mcr |= FLEXCAN_MCR_WAK_MSK;
497 	else
498 		reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
499 
500 	priv->write(reg_mcr, &regs->mcr);
501 }
502 
503 static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
504 {
505 	u8 idx = priv->scu_idx;
506 	u32 rsrc_id, val;
507 
508 	rsrc_id = IMX_SC_R_CAN(idx);
509 
510 	if (enabled)
511 		val = 1;
512 	else
513 		val = 0;
514 
515 	/* stop mode request via scu firmware */
516 	return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
517 				       IMX_SC_C_IPG_STOP, val);
518 }
519 
520 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
521 {
522 	struct flexcan_regs __iomem *regs = priv->regs;
523 	u32 reg_mcr;
524 	int ret;
525 
526 	reg_mcr = priv->read(&regs->mcr);
527 	reg_mcr |= FLEXCAN_MCR_SLF_WAK;
528 	priv->write(reg_mcr, &regs->mcr);
529 
530 	/* enable stop request */
531 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
532 		ret = flexcan_stop_mode_enable_scfw(priv, true);
533 		if (ret < 0)
534 			return ret;
535 	} else {
536 		regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
537 				   1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
538 	}
539 
540 	return flexcan_low_power_enter_ack(priv);
541 }
542 
543 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
544 {
545 	struct flexcan_regs __iomem *regs = priv->regs;
546 	u32 reg_mcr;
547 	int ret;
548 
549 	/* remove stop request */
550 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
551 		ret = flexcan_stop_mode_enable_scfw(priv, false);
552 		if (ret < 0)
553 			return ret;
554 	} else {
555 		regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
556 				   1 << priv->stm.req_bit, 0);
557 	}
558 
559 	reg_mcr = priv->read(&regs->mcr);
560 	reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
561 	priv->write(reg_mcr, &regs->mcr);
562 
563 	return flexcan_low_power_exit_ack(priv);
564 }
565 
566 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
567 {
568 	struct flexcan_regs __iomem *regs = priv->regs;
569 	u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
570 
571 	priv->write(reg_ctrl, &regs->ctrl);
572 }
573 
574 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
575 {
576 	struct flexcan_regs __iomem *regs = priv->regs;
577 	u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
578 
579 	priv->write(reg_ctrl, &regs->ctrl);
580 }
581 
582 static int flexcan_clks_enable(const struct flexcan_priv *priv)
583 {
584 	int err = 0;
585 
586 	if (priv->clk_ipg) {
587 		err = clk_prepare_enable(priv->clk_ipg);
588 		if (err)
589 			return err;
590 	}
591 
592 	if (priv->clk_per) {
593 		err = clk_prepare_enable(priv->clk_per);
594 		if (err)
595 			clk_disable_unprepare(priv->clk_ipg);
596 	}
597 
598 	return err;
599 }
600 
601 static void flexcan_clks_disable(const struct flexcan_priv *priv)
602 {
603 	clk_disable_unprepare(priv->clk_per);
604 	clk_disable_unprepare(priv->clk_ipg);
605 }
606 
607 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
608 {
609 	if (!priv->reg_xceiver)
610 		return 0;
611 
612 	return regulator_enable(priv->reg_xceiver);
613 }
614 
615 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
616 {
617 	if (!priv->reg_xceiver)
618 		return 0;
619 
620 	return regulator_disable(priv->reg_xceiver);
621 }
622 
623 static int flexcan_chip_enable(struct flexcan_priv *priv)
624 {
625 	struct flexcan_regs __iomem *regs = priv->regs;
626 	u32 reg;
627 
628 	reg = priv->read(&regs->mcr);
629 	reg &= ~FLEXCAN_MCR_MDIS;
630 	priv->write(reg, &regs->mcr);
631 
632 	return flexcan_low_power_exit_ack(priv);
633 }
634 
635 static int flexcan_chip_disable(struct flexcan_priv *priv)
636 {
637 	struct flexcan_regs __iomem *regs = priv->regs;
638 	u32 reg;
639 
640 	reg = priv->read(&regs->mcr);
641 	reg |= FLEXCAN_MCR_MDIS;
642 	priv->write(reg, &regs->mcr);
643 
644 	return flexcan_low_power_enter_ack(priv);
645 }
646 
647 static int flexcan_chip_freeze(struct flexcan_priv *priv)
648 {
649 	struct flexcan_regs __iomem *regs = priv->regs;
650 	unsigned int timeout;
651 	u32 bitrate = priv->can.bittiming.bitrate;
652 	u32 reg;
653 
654 	if (bitrate)
655 		timeout = 1000 * 1000 * 10 / bitrate;
656 	else
657 		timeout = FLEXCAN_TIMEOUT_US / 10;
658 
659 	reg = priv->read(&regs->mcr);
660 	reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
661 	priv->write(reg, &regs->mcr);
662 
663 	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
664 		udelay(100);
665 
666 	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
667 		return -ETIMEDOUT;
668 
669 	return 0;
670 }
671 
672 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
673 {
674 	struct flexcan_regs __iomem *regs = priv->regs;
675 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
676 	u32 reg;
677 
678 	reg = priv->read(&regs->mcr);
679 	reg &= ~FLEXCAN_MCR_HALT;
680 	priv->write(reg, &regs->mcr);
681 
682 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
683 		udelay(10);
684 
685 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
686 		return -ETIMEDOUT;
687 
688 	return 0;
689 }
690 
691 static int flexcan_chip_softreset(struct flexcan_priv *priv)
692 {
693 	struct flexcan_regs __iomem *regs = priv->regs;
694 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
695 
696 	priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
697 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
698 		udelay(10);
699 
700 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
701 		return -ETIMEDOUT;
702 
703 	return 0;
704 }
705 
706 static int __flexcan_get_berr_counter(const struct net_device *dev,
707 				      struct can_berr_counter *bec)
708 {
709 	const struct flexcan_priv *priv = netdev_priv(dev);
710 	struct flexcan_regs __iomem *regs = priv->regs;
711 	u32 reg = priv->read(&regs->ecr);
712 
713 	bec->txerr = (reg >> 0) & 0xff;
714 	bec->rxerr = (reg >> 8) & 0xff;
715 
716 	return 0;
717 }
718 
719 static int flexcan_get_berr_counter(const struct net_device *dev,
720 				    struct can_berr_counter *bec)
721 {
722 	const struct flexcan_priv *priv = netdev_priv(dev);
723 	int err;
724 
725 	err = pm_runtime_get_sync(priv->dev);
726 	if (err < 0) {
727 		pm_runtime_put_noidle(priv->dev);
728 		return err;
729 	}
730 
731 	err = __flexcan_get_berr_counter(dev, bec);
732 
733 	pm_runtime_put(priv->dev);
734 
735 	return err;
736 }
737 
738 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
739 {
740 	const struct flexcan_priv *priv = netdev_priv(dev);
741 	struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
742 	u32 can_id;
743 	u32 data;
744 	u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
745 	int i;
746 
747 	if (can_dropped_invalid_skb(dev, skb))
748 		return NETDEV_TX_OK;
749 
750 	netif_stop_queue(dev);
751 
752 	if (cfd->can_id & CAN_EFF_FLAG) {
753 		can_id = cfd->can_id & CAN_EFF_MASK;
754 		ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
755 	} else {
756 		can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
757 	}
758 
759 	if (cfd->can_id & CAN_RTR_FLAG)
760 		ctrl |= FLEXCAN_MB_CNT_RTR;
761 
762 	if (can_is_canfd_skb(skb)) {
763 		ctrl |= FLEXCAN_MB_CNT_EDL;
764 
765 		if (cfd->flags & CANFD_BRS)
766 			ctrl |= FLEXCAN_MB_CNT_BRS;
767 	}
768 
769 	for (i = 0; i < cfd->len; i += sizeof(u32)) {
770 		data = be32_to_cpup((__be32 *)&cfd->data[i]);
771 		priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
772 	}
773 
774 	can_put_echo_skb(skb, dev, 0, 0);
775 
776 	priv->write(can_id, &priv->tx_mb->can_id);
777 	priv->write(ctrl, &priv->tx_mb->can_ctrl);
778 
779 	/* Errata ERR005829 step8:
780 	 * Write twice INACTIVE(0x8) code to first MB.
781 	 */
782 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
783 		    &priv->tx_mb_reserved->can_ctrl);
784 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
785 		    &priv->tx_mb_reserved->can_ctrl);
786 
787 	return NETDEV_TX_OK;
788 }
789 
790 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
791 {
792 	struct flexcan_priv *priv = netdev_priv(dev);
793 	struct flexcan_regs __iomem *regs = priv->regs;
794 	struct sk_buff *skb;
795 	struct can_frame *cf;
796 	bool rx_errors = false, tx_errors = false;
797 	u32 timestamp;
798 	int err;
799 
800 	timestamp = priv->read(&regs->timer) << 16;
801 
802 	skb = alloc_can_err_skb(dev, &cf);
803 	if (unlikely(!skb))
804 		return;
805 
806 	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
807 
808 	if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
809 		netdev_dbg(dev, "BIT1_ERR irq\n");
810 		cf->data[2] |= CAN_ERR_PROT_BIT1;
811 		tx_errors = true;
812 	}
813 	if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
814 		netdev_dbg(dev, "BIT0_ERR irq\n");
815 		cf->data[2] |= CAN_ERR_PROT_BIT0;
816 		tx_errors = true;
817 	}
818 	if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
819 		netdev_dbg(dev, "ACK_ERR irq\n");
820 		cf->can_id |= CAN_ERR_ACK;
821 		cf->data[3] = CAN_ERR_PROT_LOC_ACK;
822 		tx_errors = true;
823 	}
824 	if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
825 		netdev_dbg(dev, "CRC_ERR irq\n");
826 		cf->data[2] |= CAN_ERR_PROT_BIT;
827 		cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
828 		rx_errors = true;
829 	}
830 	if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
831 		netdev_dbg(dev, "FRM_ERR irq\n");
832 		cf->data[2] |= CAN_ERR_PROT_FORM;
833 		rx_errors = true;
834 	}
835 	if (reg_esr & FLEXCAN_ESR_STF_ERR) {
836 		netdev_dbg(dev, "STF_ERR irq\n");
837 		cf->data[2] |= CAN_ERR_PROT_STUFF;
838 		rx_errors = true;
839 	}
840 
841 	priv->can.can_stats.bus_error++;
842 	if (rx_errors)
843 		dev->stats.rx_errors++;
844 	if (tx_errors)
845 		dev->stats.tx_errors++;
846 
847 	err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
848 	if (err)
849 		dev->stats.rx_fifo_errors++;
850 }
851 
852 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
853 {
854 	struct flexcan_priv *priv = netdev_priv(dev);
855 	struct flexcan_regs __iomem *regs = priv->regs;
856 	struct sk_buff *skb;
857 	struct can_frame *cf;
858 	enum can_state new_state, rx_state, tx_state;
859 	int flt;
860 	struct can_berr_counter bec;
861 	u32 timestamp;
862 	int err;
863 
864 	flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
865 	if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
866 		tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
867 			CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
868 		rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
869 			CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
870 		new_state = max(tx_state, rx_state);
871 	} else {
872 		__flexcan_get_berr_counter(dev, &bec);
873 		new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
874 			CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
875 		rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
876 		tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
877 	}
878 
879 	/* state hasn't changed */
880 	if (likely(new_state == priv->can.state))
881 		return;
882 
883 	timestamp = priv->read(&regs->timer) << 16;
884 
885 	skb = alloc_can_err_skb(dev, &cf);
886 	if (unlikely(!skb))
887 		return;
888 
889 	can_change_state(dev, cf, tx_state, rx_state);
890 
891 	if (unlikely(new_state == CAN_STATE_BUS_OFF))
892 		can_bus_off(dev);
893 
894 	err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
895 	if (err)
896 		dev->stats.rx_fifo_errors++;
897 }
898 
899 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
900 {
901 	u64 reg = 0;
902 
903 	if (upper_32_bits(mask))
904 		reg = (u64)priv->read(addr - 4) << 32;
905 	if (lower_32_bits(mask))
906 		reg |= priv->read(addr);
907 
908 	return reg & mask;
909 }
910 
911 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
912 {
913 	if (upper_32_bits(val))
914 		priv->write(upper_32_bits(val), addr - 4);
915 	if (lower_32_bits(val))
916 		priv->write(lower_32_bits(val), addr);
917 }
918 
919 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
920 {
921 	return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
922 }
923 
924 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
925 {
926 	return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
927 }
928 
929 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
930 {
931 	return container_of(offload, struct flexcan_priv, offload);
932 }
933 
934 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
935 					    unsigned int n, u32 *timestamp,
936 					    bool drop)
937 {
938 	struct flexcan_priv *priv = rx_offload_to_priv(offload);
939 	struct flexcan_regs __iomem *regs = priv->regs;
940 	struct flexcan_mb __iomem *mb;
941 	struct sk_buff *skb;
942 	struct canfd_frame *cfd;
943 	u32 reg_ctrl, reg_id, reg_iflag1;
944 	int i;
945 
946 	if (unlikely(drop)) {
947 		skb = ERR_PTR(-ENOBUFS);
948 		goto mark_as_read;
949 	}
950 
951 	mb = flexcan_get_mb(priv, n);
952 
953 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
954 		u32 code;
955 
956 		do {
957 			reg_ctrl = priv->read(&mb->can_ctrl);
958 		} while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
959 
960 		/* is this MB empty? */
961 		code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
962 		if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
963 		    (code != FLEXCAN_MB_CODE_RX_OVERRUN))
964 			return NULL;
965 
966 		if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
967 			/* This MB was overrun, we lost data */
968 			offload->dev->stats.rx_over_errors++;
969 			offload->dev->stats.rx_errors++;
970 		}
971 	} else {
972 		reg_iflag1 = priv->read(&regs->iflag1);
973 		if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
974 			return NULL;
975 
976 		reg_ctrl = priv->read(&mb->can_ctrl);
977 	}
978 
979 	if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
980 		skb = alloc_canfd_skb(offload->dev, &cfd);
981 	else
982 		skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
983 	if (unlikely(!skb)) {
984 		skb = ERR_PTR(-ENOMEM);
985 		goto mark_as_read;
986 	}
987 
988 	/* increase timstamp to full 32 bit */
989 	*timestamp = reg_ctrl << 16;
990 
991 	reg_id = priv->read(&mb->can_id);
992 	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
993 		cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
994 	else
995 		cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
996 
997 	if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
998 		cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
999 
1000 		if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1001 			cfd->flags |= CANFD_BRS;
1002 	} else {
1003 		cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1004 
1005 		if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1006 			cfd->can_id |= CAN_RTR_FLAG;
1007 	}
1008 
1009 	if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1010 		cfd->flags |= CANFD_ESI;
1011 
1012 	for (i = 0; i < cfd->len; i += sizeof(u32)) {
1013 		__be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1014 		*(__be32 *)(cfd->data + i) = data;
1015 	}
1016 
1017  mark_as_read:
1018 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1019 		flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), &regs->iflag1);
1020 	else
1021 		priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
1022 
1023 	/* Read the Free Running Timer. It is optional but recommended
1024 	 * to unlock Mailbox as soon as possible and make it available
1025 	 * for reception.
1026 	 */
1027 	priv->read(&regs->timer);
1028 
1029 	return skb;
1030 }
1031 
1032 static irqreturn_t flexcan_irq(int irq, void *dev_id)
1033 {
1034 	struct net_device *dev = dev_id;
1035 	struct net_device_stats *stats = &dev->stats;
1036 	struct flexcan_priv *priv = netdev_priv(dev);
1037 	struct flexcan_regs __iomem *regs = priv->regs;
1038 	irqreturn_t handled = IRQ_NONE;
1039 	u64 reg_iflag_tx;
1040 	u32 reg_esr;
1041 	enum can_state last_state = priv->can.state;
1042 
1043 	/* reception interrupt */
1044 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1045 		u64 reg_iflag_rx;
1046 		int ret;
1047 
1048 		while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1049 			handled = IRQ_HANDLED;
1050 			ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1051 								   reg_iflag_rx);
1052 			if (!ret)
1053 				break;
1054 		}
1055 	} else {
1056 		u32 reg_iflag1;
1057 
1058 		reg_iflag1 = priv->read(&regs->iflag1);
1059 		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1060 			handled = IRQ_HANDLED;
1061 			can_rx_offload_irq_offload_fifo(&priv->offload);
1062 		}
1063 
1064 		/* FIFO overflow interrupt */
1065 		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1066 			handled = IRQ_HANDLED;
1067 			priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1068 				    &regs->iflag1);
1069 			dev->stats.rx_over_errors++;
1070 			dev->stats.rx_errors++;
1071 		}
1072 	}
1073 
1074 	reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1075 
1076 	/* transmission complete interrupt */
1077 	if (reg_iflag_tx & priv->tx_mask) {
1078 		u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1079 
1080 		handled = IRQ_HANDLED;
1081 		stats->tx_bytes +=
1082 			can_rx_offload_get_echo_skb(&priv->offload, 0,
1083 						    reg_ctrl << 16, NULL);
1084 		stats->tx_packets++;
1085 		can_led_event(dev, CAN_LED_EVENT_TX);
1086 
1087 		/* after sending a RTR frame MB is in RX mode */
1088 		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1089 			    &priv->tx_mb->can_ctrl);
1090 		flexcan_write64(priv, priv->tx_mask, &regs->iflag1);
1091 		netif_wake_queue(dev);
1092 	}
1093 
1094 	reg_esr = priv->read(&regs->esr);
1095 
1096 	/* ACK all bus error, state change and wake IRQ sources */
1097 	if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1098 		handled = IRQ_HANDLED;
1099 		priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), &regs->esr);
1100 	}
1101 
1102 	/* state change interrupt or broken error state quirk fix is enabled */
1103 	if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1104 	    (priv->devtype_data.quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1105 					   FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1106 		flexcan_irq_state(dev, reg_esr);
1107 
1108 	/* bus error IRQ - handle if bus error reporting is activated */
1109 	if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1110 	    (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1111 		flexcan_irq_bus_err(dev, reg_esr);
1112 
1113 	/* availability of error interrupt among state transitions in case
1114 	 * bus error reporting is de-activated and
1115 	 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1116 	 *  +--------------------------------------------------------------+
1117 	 *  | +----------------------------------------------+ [stopped /  |
1118 	 *  | |                                              |  sleeping] -+
1119 	 *  +-+-> active <-> warning <-> passive -> bus off -+
1120 	 *        ___________^^^^^^^^^^^^_______________________________
1121 	 *        disabled(1)  enabled             disabled
1122 	 *
1123 	 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1124 	 */
1125 	if ((last_state != priv->can.state) &&
1126 	    (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1127 	    !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1128 		switch (priv->can.state) {
1129 		case CAN_STATE_ERROR_ACTIVE:
1130 			if (priv->devtype_data.quirks &
1131 			    FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1132 				flexcan_error_irq_enable(priv);
1133 			else
1134 				flexcan_error_irq_disable(priv);
1135 			break;
1136 
1137 		case CAN_STATE_ERROR_WARNING:
1138 			flexcan_error_irq_enable(priv);
1139 			break;
1140 
1141 		case CAN_STATE_ERROR_PASSIVE:
1142 		case CAN_STATE_BUS_OFF:
1143 			flexcan_error_irq_disable(priv);
1144 			break;
1145 
1146 		default:
1147 			break;
1148 		}
1149 	}
1150 
1151 	if (handled)
1152 		can_rx_offload_irq_finish(&priv->offload);
1153 
1154 	return handled;
1155 }
1156 
1157 static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1158 {
1159 	const struct flexcan_priv *priv = netdev_priv(dev);
1160 	const struct can_bittiming *bt = &priv->can.bittiming;
1161 	struct flexcan_regs __iomem *regs = priv->regs;
1162 	u32 reg;
1163 
1164 	reg = priv->read(&regs->ctrl);
1165 	reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1166 		 FLEXCAN_CTRL_RJW(0x3) |
1167 		 FLEXCAN_CTRL_PSEG1(0x7) |
1168 		 FLEXCAN_CTRL_PSEG2(0x7) |
1169 		 FLEXCAN_CTRL_PROPSEG(0x7));
1170 
1171 	reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1172 		FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1173 		FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1174 		FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1175 		FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1176 
1177 	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1178 	priv->write(reg, &regs->ctrl);
1179 
1180 	/* print chip status */
1181 	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1182 		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1183 }
1184 
1185 static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1186 {
1187 	struct flexcan_priv *priv = netdev_priv(dev);
1188 	struct can_bittiming *bt = &priv->can.bittiming;
1189 	struct can_bittiming *dbt = &priv->can.data_bittiming;
1190 	struct flexcan_regs __iomem *regs = priv->regs;
1191 	u32 reg_cbt, reg_fdctrl;
1192 
1193 	/* CBT */
1194 	/* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1195 	 * long. The can_calc_bittiming() tries to divide the tseg1
1196 	 * equally between phase_seg1 and prop_seg, which may not fit
1197 	 * in CBT register. Therefore, if phase_seg1 is more than
1198 	 * possible value, increase prop_seg and decrease phase_seg1.
1199 	 */
1200 	if (bt->phase_seg1 > 0x20) {
1201 		bt->prop_seg += (bt->phase_seg1 - 0x20);
1202 		bt->phase_seg1 = 0x20;
1203 	}
1204 
1205 	reg_cbt = FLEXCAN_CBT_BTF |
1206 		FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1207 		FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1208 		FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1209 		FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1210 		FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1211 
1212 	netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1213 	priv->write(reg_cbt, &regs->cbt);
1214 
1215 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1216 		u32 reg_fdcbt, reg_ctrl2;
1217 
1218 		if (bt->brp != dbt->brp)
1219 			netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1220 				    dbt->brp, bt->brp);
1221 
1222 		/* FDCBT */
1223 		/* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1224 		 * 5 bit long. The can_calc_bittiming tries to divide
1225 		 * the tseg1 equally between phase_seg1 and prop_seg,
1226 		 * which may not fit in FDCBT register. Therefore, if
1227 		 * phase_seg1 is more than possible value, increase
1228 		 * prop_seg and decrease phase_seg1
1229 		 */
1230 		if (dbt->phase_seg1 > 0x8) {
1231 			dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1232 			dbt->phase_seg1 = 0x8;
1233 		}
1234 
1235 		reg_fdcbt = priv->read(&regs->fdcbt);
1236 		reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1237 			       FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1238 			       FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1239 			       FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1240 			       FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1241 
1242 		reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1243 			FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1244 			FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1245 			FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1246 			FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1247 
1248 		netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1249 		priv->write(reg_fdcbt, &regs->fdcbt);
1250 
1251 		/* CTRL2 */
1252 		reg_ctrl2 = priv->read(&regs->ctrl2);
1253 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1254 		if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1255 			reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1256 
1257 		netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1258 		priv->write(reg_ctrl2, &regs->ctrl2);
1259 	}
1260 
1261 	/* FDCTRL */
1262 	reg_fdctrl = priv->read(&regs->fdctrl);
1263 	reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1264 			FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1265 
1266 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1267 		reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1268 
1269 		if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1270 			/* TDC must be disabled for Loop Back mode */
1271 			reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1272 		} else {
1273 			reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1274 				FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1275 					   ((dbt->phase_seg1 - 1) +
1276 					    dbt->prop_seg + 2) *
1277 					   ((dbt->brp - 1 ) + 1));
1278 		}
1279 	}
1280 
1281 	netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1282 	priv->write(reg_fdctrl, &regs->fdctrl);
1283 
1284 	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1285 		   __func__,
1286 		   priv->read(&regs->mcr), priv->read(&regs->ctrl),
1287 		   priv->read(&regs->ctrl2), priv->read(&regs->fdctrl),
1288 		   priv->read(&regs->cbt), priv->read(&regs->fdcbt));
1289 }
1290 
1291 static void flexcan_set_bittiming(struct net_device *dev)
1292 {
1293 	const struct flexcan_priv *priv = netdev_priv(dev);
1294 	struct flexcan_regs __iomem *regs = priv->regs;
1295 	u32 reg;
1296 
1297 	reg = priv->read(&regs->ctrl);
1298 	reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1299 		 FLEXCAN_CTRL_LOM);
1300 
1301 	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1302 		reg |= FLEXCAN_CTRL_LPB;
1303 	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1304 		reg |= FLEXCAN_CTRL_LOM;
1305 	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1306 		reg |= FLEXCAN_CTRL_SMP;
1307 
1308 	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1309 	priv->write(reg, &regs->ctrl);
1310 
1311 	if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1312 		return flexcan_set_bittiming_cbt(dev);
1313 	else
1314 		return flexcan_set_bittiming_ctrl(dev);
1315 }
1316 
1317 static void flexcan_ram_init(struct net_device *dev)
1318 {
1319 	struct flexcan_priv *priv = netdev_priv(dev);
1320 	struct flexcan_regs __iomem *regs = priv->regs;
1321 	u32 reg_ctrl2;
1322 
1323 	/* 11.8.3.13 Detection and correction of memory errors:
1324 	 * CTRL2[WRMFRZ] grants write access to all memory positions
1325 	 * that require initialization, ranging from 0x080 to 0xADF
1326 	 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1327 	 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1328 	 * need to be initialized as well. MCR[RFEN] must not be set
1329 	 * during memory initialization.
1330 	 */
1331 	reg_ctrl2 = priv->read(&regs->ctrl2);
1332 	reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1333 	priv->write(reg_ctrl2, &regs->ctrl2);
1334 
1335 	memset_io(&regs->init, 0, sizeof(regs->init));
1336 
1337 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1338 		memset_io(&regs->init_fd, 0, sizeof(regs->init_fd));
1339 
1340 	reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1341 	priv->write(reg_ctrl2, &regs->ctrl2);
1342 }
1343 
1344 static int flexcan_rx_offload_setup(struct net_device *dev)
1345 {
1346 	struct flexcan_priv *priv = netdev_priv(dev);
1347 	int err;
1348 
1349 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1350 		priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1351 	else
1352 		priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1353 
1354 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_MB_16)
1355 		priv->mb_count = 16;
1356 	else
1357 		priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1358 				 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1359 
1360 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1361 		priv->tx_mb_reserved =
1362 			flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_MAILBOX);
1363 	else
1364 		priv->tx_mb_reserved =
1365 			flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_FIFO);
1366 	priv->tx_mb_idx = priv->mb_count - 1;
1367 	priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1368 	priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1369 
1370 	priv->offload.mailbox_read = flexcan_mailbox_read;
1371 
1372 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1373 		priv->offload.mb_first = FLEXCAN_RX_MB_RX_MAILBOX_FIRST;
1374 		priv->offload.mb_last = priv->mb_count - 2;
1375 
1376 		priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1377 					    priv->offload.mb_first);
1378 		err = can_rx_offload_add_timestamp(dev, &priv->offload);
1379 	} else {
1380 		priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1381 			FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1382 		err = can_rx_offload_add_fifo(dev, &priv->offload,
1383 					      FLEXCAN_NAPI_WEIGHT);
1384 	}
1385 
1386 	return err;
1387 }
1388 
1389 static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1390 {
1391 	const struct flexcan_priv *priv = netdev_priv(dev);
1392 	struct flexcan_regs __iomem *regs = priv->regs;
1393 	u64 reg_imask;
1394 
1395 	disable_irq(dev->irq);
1396 	priv->write(priv->reg_ctrl_default, &regs->ctrl);
1397 	reg_imask = priv->rx_mask | priv->tx_mask;
1398 	priv->write(upper_32_bits(reg_imask), &regs->imask2);
1399 	priv->write(lower_32_bits(reg_imask), &regs->imask1);
1400 	enable_irq(dev->irq);
1401 }
1402 
1403 static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1404 {
1405 	const struct flexcan_priv *priv = netdev_priv(dev);
1406 	struct flexcan_regs __iomem *regs = priv->regs;
1407 
1408 	priv->write(0, &regs->imask2);
1409 	priv->write(0, &regs->imask1);
1410 	priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1411 		    &regs->ctrl);
1412 }
1413 
1414 /* flexcan_chip_start
1415  *
1416  * this functions is entered with clocks enabled
1417  *
1418  */
1419 static int flexcan_chip_start(struct net_device *dev)
1420 {
1421 	struct flexcan_priv *priv = netdev_priv(dev);
1422 	struct flexcan_regs __iomem *regs = priv->regs;
1423 	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1424 	int err, i;
1425 	struct flexcan_mb __iomem *mb;
1426 
1427 	/* enable module */
1428 	err = flexcan_chip_enable(priv);
1429 	if (err)
1430 		return err;
1431 
1432 	/* soft reset */
1433 	err = flexcan_chip_softreset(priv);
1434 	if (err)
1435 		goto out_chip_disable;
1436 
1437 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1438 		flexcan_ram_init(dev);
1439 
1440 	flexcan_set_bittiming(dev);
1441 
1442 	/* set freeze, halt */
1443 	err = flexcan_chip_freeze(priv);
1444 	if (err)
1445 		goto out_chip_disable;
1446 
1447 	/* MCR
1448 	 *
1449 	 * only supervisor access
1450 	 * enable warning int
1451 	 * enable individual RX masking
1452 	 * choose format C
1453 	 * set max mailbox number
1454 	 */
1455 	reg_mcr = priv->read(&regs->mcr);
1456 	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1457 	reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
1458 		FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1459 
1460 	/* MCR
1461 	 *
1462 	 * FIFO:
1463 	 * - disable for mailbox mode
1464 	 * - enable for FIFO mode
1465 	 */
1466 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1467 		reg_mcr &= ~FLEXCAN_MCR_FEN;
1468 	else
1469 		reg_mcr |= FLEXCAN_MCR_FEN;
1470 
1471 	/* MCR
1472 	 *
1473 	 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1474 	 *       asserted because this will impede the self reception
1475 	 *       of a transmitted message. This is not documented in
1476 	 *       earlier versions of flexcan block guide.
1477 	 *
1478 	 * Self Reception:
1479 	 * - enable Self Reception for loopback mode
1480 	 *   (by clearing "Self Reception Disable" bit)
1481 	 * - disable for normal operation
1482 	 */
1483 	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1484 		reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1485 	else
1486 		reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1487 
1488 	/* MCR - CAN-FD */
1489 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1490 		reg_mcr |= FLEXCAN_MCR_FDEN;
1491 	else
1492 		reg_mcr &= ~FLEXCAN_MCR_FDEN;
1493 
1494 	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1495 	priv->write(reg_mcr, &regs->mcr);
1496 
1497 	/* CTRL
1498 	 *
1499 	 * disable timer sync feature
1500 	 *
1501 	 * disable auto busoff recovery
1502 	 * transmit lowest buffer first
1503 	 *
1504 	 * enable tx and rx warning interrupt
1505 	 * enable bus off interrupt
1506 	 * (== FLEXCAN_CTRL_ERR_STATE)
1507 	 */
1508 	reg_ctrl = priv->read(&regs->ctrl);
1509 	reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1510 	reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1511 		FLEXCAN_CTRL_ERR_STATE;
1512 
1513 	/* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1514 	 * on most Flexcan cores, too. Otherwise we don't get
1515 	 * any error warning or passive interrupts.
1516 	 */
1517 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1518 	    priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1519 		reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1520 	else
1521 		reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1522 
1523 	/* save for later use */
1524 	priv->reg_ctrl_default = reg_ctrl;
1525 	/* leave interrupts disabled for now */
1526 	reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1527 	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1528 	priv->write(reg_ctrl, &regs->ctrl);
1529 
1530 	if ((priv->devtype_data.quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1531 		reg_ctrl2 = priv->read(&regs->ctrl2);
1532 		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1533 		priv->write(reg_ctrl2, &regs->ctrl2);
1534 	}
1535 
1536 	if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1537 		u32 reg_fdctrl;
1538 
1539 		reg_fdctrl = priv->read(&regs->fdctrl);
1540 		reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1541 				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1542 
1543 		if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1544 			reg_fdctrl |=
1545 				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1546 					   FLEXCAN_FDCTRL_MBDSR_64) |
1547 				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1548 					   FLEXCAN_FDCTRL_MBDSR_64);
1549 		} else {
1550 			reg_fdctrl |=
1551 				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1552 					   FLEXCAN_FDCTRL_MBDSR_8) |
1553 				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1554 					   FLEXCAN_FDCTRL_MBDSR_8);
1555 		}
1556 
1557 		netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1558 			   __func__, reg_fdctrl);
1559 		priv->write(reg_fdctrl, &regs->fdctrl);
1560 	}
1561 
1562 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1563 		for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1564 			mb = flexcan_get_mb(priv, i);
1565 			priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1566 				    &mb->can_ctrl);
1567 		}
1568 	} else {
1569 		/* clear and invalidate unused mailboxes first */
1570 		for (i = FLEXCAN_TX_MB_RESERVED_RX_FIFO; i < priv->mb_count; i++) {
1571 			mb = flexcan_get_mb(priv, i);
1572 			priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1573 				    &mb->can_ctrl);
1574 		}
1575 	}
1576 
1577 	/* Errata ERR005829: mark first TX mailbox as INACTIVE */
1578 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1579 		    &priv->tx_mb_reserved->can_ctrl);
1580 
1581 	/* mark TX mailbox as INACTIVE */
1582 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1583 		    &priv->tx_mb->can_ctrl);
1584 
1585 	/* acceptance mask/acceptance code (accept everything) */
1586 	priv->write(0x0, &regs->rxgmask);
1587 	priv->write(0x0, &regs->rx14mask);
1588 	priv->write(0x0, &regs->rx15mask);
1589 
1590 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1591 		priv->write(0x0, &regs->rxfgmask);
1592 
1593 	/* clear acceptance filters */
1594 	for (i = 0; i < priv->mb_count; i++)
1595 		priv->write(0, &regs->rximr[i]);
1596 
1597 	/* On Vybrid, disable non-correctable errors interrupt and
1598 	 * freeze mode. It still can correct the correctable errors
1599 	 * when HW supports ECC.
1600 	 *
1601 	 * This also works around errata e5295 which generates false
1602 	 * positive memory errors and put the device in freeze mode.
1603 	 */
1604 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1605 		/* Follow the protocol as described in "Detection
1606 		 * and Correction of Memory Errors" to write to
1607 		 * MECR register (step 1 - 5)
1608 		 *
1609 		 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1610 		 * 2. set CTRL2[ECRWRE]
1611 		 */
1612 		reg_ctrl2 = priv->read(&regs->ctrl2);
1613 		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1614 		priv->write(reg_ctrl2, &regs->ctrl2);
1615 
1616 		/* 3. clear MECR[ECRWRDIS] */
1617 		reg_mecr = priv->read(&regs->mecr);
1618 		reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1619 		priv->write(reg_mecr, &regs->mecr);
1620 
1621 		/* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1622 		reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1623 			      FLEXCAN_MECR_FANCEI_MSK);
1624 		priv->write(reg_mecr, &regs->mecr);
1625 
1626 		/* 5. after configuration done, lock MECR by either
1627 		 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1628 		 */
1629 		reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1630 		priv->write(reg_mecr, &regs->mecr);
1631 
1632 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1633 		priv->write(reg_ctrl2, &regs->ctrl2);
1634 	}
1635 
1636 	/* synchronize with the can bus */
1637 	err = flexcan_chip_unfreeze(priv);
1638 	if (err)
1639 		goto out_chip_disable;
1640 
1641 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1642 
1643 	/* print chip status */
1644 	netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1645 		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1646 
1647 	return 0;
1648 
1649  out_chip_disable:
1650 	flexcan_chip_disable(priv);
1651 	return err;
1652 }
1653 
1654 /* __flexcan_chip_stop
1655  *
1656  * this function is entered with clocks enabled
1657  */
1658 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1659 {
1660 	struct flexcan_priv *priv = netdev_priv(dev);
1661 	int err;
1662 
1663 	/* freeze + disable module */
1664 	err = flexcan_chip_freeze(priv);
1665 	if (err && !disable_on_error)
1666 		return err;
1667 	err = flexcan_chip_disable(priv);
1668 	if (err && !disable_on_error)
1669 		goto out_chip_unfreeze;
1670 
1671 	priv->can.state = CAN_STATE_STOPPED;
1672 
1673 	return 0;
1674 
1675  out_chip_unfreeze:
1676 	flexcan_chip_unfreeze(priv);
1677 
1678 	return err;
1679 }
1680 
1681 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1682 {
1683 	return __flexcan_chip_stop(dev, true);
1684 }
1685 
1686 static inline int flexcan_chip_stop(struct net_device *dev)
1687 {
1688 	return __flexcan_chip_stop(dev, false);
1689 }
1690 
1691 static int flexcan_open(struct net_device *dev)
1692 {
1693 	struct flexcan_priv *priv = netdev_priv(dev);
1694 	int err;
1695 
1696 	if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1697 	    (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1698 		netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1699 		return -EINVAL;
1700 	}
1701 
1702 	err = pm_runtime_get_sync(priv->dev);
1703 	if (err < 0) {
1704 		pm_runtime_put_noidle(priv->dev);
1705 		return err;
1706 	}
1707 
1708 	err = open_candev(dev);
1709 	if (err)
1710 		goto out_runtime_put;
1711 
1712 	err = flexcan_transceiver_enable(priv);
1713 	if (err)
1714 		goto out_close;
1715 
1716 	err = flexcan_rx_offload_setup(dev);
1717 	if (err)
1718 		goto out_transceiver_disable;
1719 
1720 	err = flexcan_chip_start(dev);
1721 	if (err)
1722 		goto out_can_rx_offload_del;
1723 
1724 	can_rx_offload_enable(&priv->offload);
1725 
1726 	err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1727 	if (err)
1728 		goto out_can_rx_offload_disable;
1729 
1730 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1731 		err = request_irq(priv->irq_boff,
1732 				  flexcan_irq, IRQF_SHARED, dev->name, dev);
1733 		if (err)
1734 			goto out_free_irq;
1735 
1736 		err = request_irq(priv->irq_err,
1737 				  flexcan_irq, IRQF_SHARED, dev->name, dev);
1738 		if (err)
1739 			goto out_free_irq_boff;
1740 	}
1741 
1742 	flexcan_chip_interrupts_enable(dev);
1743 
1744 	can_led_event(dev, CAN_LED_EVENT_OPEN);
1745 
1746 	netif_start_queue(dev);
1747 
1748 	return 0;
1749 
1750  out_free_irq_boff:
1751 	free_irq(priv->irq_boff, dev);
1752  out_free_irq:
1753 	free_irq(dev->irq, dev);
1754  out_can_rx_offload_disable:
1755 	can_rx_offload_disable(&priv->offload);
1756 	flexcan_chip_stop(dev);
1757  out_can_rx_offload_del:
1758 	can_rx_offload_del(&priv->offload);
1759  out_transceiver_disable:
1760 	flexcan_transceiver_disable(priv);
1761  out_close:
1762 	close_candev(dev);
1763  out_runtime_put:
1764 	pm_runtime_put(priv->dev);
1765 
1766 	return err;
1767 }
1768 
1769 static int flexcan_close(struct net_device *dev)
1770 {
1771 	struct flexcan_priv *priv = netdev_priv(dev);
1772 
1773 	netif_stop_queue(dev);
1774 	flexcan_chip_interrupts_disable(dev);
1775 
1776 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1777 		free_irq(priv->irq_err, dev);
1778 		free_irq(priv->irq_boff, dev);
1779 	}
1780 
1781 	free_irq(dev->irq, dev);
1782 	can_rx_offload_disable(&priv->offload);
1783 	flexcan_chip_stop_disable_on_error(dev);
1784 
1785 	can_rx_offload_del(&priv->offload);
1786 	flexcan_transceiver_disable(priv);
1787 	close_candev(dev);
1788 
1789 	pm_runtime_put(priv->dev);
1790 
1791 	can_led_event(dev, CAN_LED_EVENT_STOP);
1792 
1793 	return 0;
1794 }
1795 
1796 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1797 {
1798 	int err;
1799 
1800 	switch (mode) {
1801 	case CAN_MODE_START:
1802 		err = flexcan_chip_start(dev);
1803 		if (err)
1804 			return err;
1805 
1806 		flexcan_chip_interrupts_enable(dev);
1807 
1808 		netif_wake_queue(dev);
1809 		break;
1810 
1811 	default:
1812 		return -EOPNOTSUPP;
1813 	}
1814 
1815 	return 0;
1816 }
1817 
1818 static const struct net_device_ops flexcan_netdev_ops = {
1819 	.ndo_open	= flexcan_open,
1820 	.ndo_stop	= flexcan_close,
1821 	.ndo_start_xmit	= flexcan_start_xmit,
1822 	.ndo_change_mtu = can_change_mtu,
1823 };
1824 
1825 static int register_flexcandev(struct net_device *dev)
1826 {
1827 	struct flexcan_priv *priv = netdev_priv(dev);
1828 	struct flexcan_regs __iomem *regs = priv->regs;
1829 	u32 reg, err;
1830 
1831 	err = flexcan_clks_enable(priv);
1832 	if (err)
1833 		return err;
1834 
1835 	/* select "bus clock", chip must be disabled */
1836 	err = flexcan_chip_disable(priv);
1837 	if (err)
1838 		goto out_clks_disable;
1839 
1840 	reg = priv->read(&regs->ctrl);
1841 	if (priv->clk_src)
1842 		reg |= FLEXCAN_CTRL_CLK_SRC;
1843 	else
1844 		reg &= ~FLEXCAN_CTRL_CLK_SRC;
1845 	priv->write(reg, &regs->ctrl);
1846 
1847 	err = flexcan_chip_enable(priv);
1848 	if (err)
1849 		goto out_chip_disable;
1850 
1851 	/* set freeze, halt */
1852 	err = flexcan_chip_freeze(priv);
1853 	if (err)
1854 		goto out_chip_disable;
1855 
1856 	/* activate FIFO, restrict register access */
1857 	reg = priv->read(&regs->mcr);
1858 	reg |=  FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1859 	priv->write(reg, &regs->mcr);
1860 
1861 	/* Currently we only support newer versions of this core
1862 	 * featuring a RX hardware FIFO (although this driver doesn't
1863 	 * make use of it on some cores). Older cores, found on some
1864 	 * Coldfire derivates are not tested.
1865 	 */
1866 	reg = priv->read(&regs->mcr);
1867 	if (!(reg & FLEXCAN_MCR_FEN)) {
1868 		netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1869 		err = -ENODEV;
1870 		goto out_chip_disable;
1871 	}
1872 
1873 	err = register_candev(dev);
1874 	if (err)
1875 		goto out_chip_disable;
1876 
1877 	/* Disable core and let pm_runtime_put() disable the clocks.
1878 	 * If CONFIG_PM is not enabled, the clocks will stay powered.
1879 	 */
1880 	flexcan_chip_disable(priv);
1881 	pm_runtime_put(priv->dev);
1882 
1883 	return 0;
1884 
1885  out_chip_disable:
1886 	flexcan_chip_disable(priv);
1887  out_clks_disable:
1888 	flexcan_clks_disable(priv);
1889 	return err;
1890 }
1891 
1892 static void unregister_flexcandev(struct net_device *dev)
1893 {
1894 	unregister_candev(dev);
1895 }
1896 
1897 static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1898 {
1899 	struct net_device *dev = platform_get_drvdata(pdev);
1900 	struct device_node *np = pdev->dev.of_node;
1901 	struct device_node *gpr_np;
1902 	struct flexcan_priv *priv;
1903 	phandle phandle;
1904 	u32 out_val[3];
1905 	int ret;
1906 
1907 	if (!np)
1908 		return -EINVAL;
1909 
1910 	/* stop mode property format is:
1911 	 * <&gpr req_gpr req_bit>.
1912 	 */
1913 	ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1914 					 ARRAY_SIZE(out_val));
1915 	if (ret) {
1916 		dev_dbg(&pdev->dev, "no stop-mode property\n");
1917 		return ret;
1918 	}
1919 	phandle = *out_val;
1920 
1921 	gpr_np = of_find_node_by_phandle(phandle);
1922 	if (!gpr_np) {
1923 		dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1924 		return -ENODEV;
1925 	}
1926 
1927 	priv = netdev_priv(dev);
1928 	priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1929 	if (IS_ERR(priv->stm.gpr)) {
1930 		dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1931 		ret = PTR_ERR(priv->stm.gpr);
1932 		goto out_put_node;
1933 	}
1934 
1935 	priv->stm.req_gpr = out_val[1];
1936 	priv->stm.req_bit = out_val[2];
1937 
1938 	dev_dbg(&pdev->dev,
1939 		"gpr %s req_gpr=0x02%x req_bit=%u\n",
1940 		gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1941 
1942 	return 0;
1943 
1944 out_put_node:
1945 	of_node_put(gpr_np);
1946 	return ret;
1947 }
1948 
1949 static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
1950 {
1951 	struct net_device *dev = platform_get_drvdata(pdev);
1952 	struct flexcan_priv *priv;
1953 	u8 scu_idx;
1954 	int ret;
1955 
1956 	ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
1957 	if (ret < 0) {
1958 		dev_dbg(&pdev->dev, "failed to get scu index\n");
1959 		return ret;
1960 	}
1961 
1962 	priv = netdev_priv(dev);
1963 	priv->scu_idx = scu_idx;
1964 
1965 	/* this function could be deferred probe, return -EPROBE_DEFER */
1966 	return imx_scu_get_handle(&priv->sc_ipc_handle);
1967 }
1968 
1969 /* flexcan_setup_stop_mode - Setup stop mode for wakeup
1970  *
1971  * Return: = 0 setup stop mode successfully or doesn't support this feature
1972  *         < 0 fail to setup stop mode (could be deferred probe)
1973  */
1974 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1975 {
1976 	struct net_device *dev = platform_get_drvdata(pdev);
1977 	struct flexcan_priv *priv;
1978 	int ret;
1979 
1980 	priv = netdev_priv(dev);
1981 
1982 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
1983 		ret = flexcan_setup_stop_mode_scfw(pdev);
1984 	else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
1985 		ret = flexcan_setup_stop_mode_gpr(pdev);
1986 	else
1987 		/* return 0 directly if doesn't support stop mode feature */
1988 		return 0;
1989 
1990 	if (ret)
1991 		return ret;
1992 
1993 	device_set_wakeup_capable(&pdev->dev, true);
1994 
1995 	if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
1996 		device_set_wakeup_enable(&pdev->dev, true);
1997 
1998 	return 0;
1999 }
2000 
2001 static const struct of_device_id flexcan_of_match[] = {
2002 	{ .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2003 	{ .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2004 	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2005 	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2006 	{ .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2007 	{ .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2008 	{ .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2009 	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2010 	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2011 	{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2012 	{ .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2013 	{ /* sentinel */ },
2014 };
2015 MODULE_DEVICE_TABLE(of, flexcan_of_match);
2016 
2017 static const struct platform_device_id flexcan_id_table[] = {
2018 	{
2019 		.name = "flexcan-mcf5441x",
2020 		.driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data,
2021 	}, {
2022 		/* sentinel */
2023 	},
2024 };
2025 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
2026 
2027 static int flexcan_probe(struct platform_device *pdev)
2028 {
2029 	const struct of_device_id *of_id;
2030 	const struct flexcan_devtype_data *devtype_data;
2031 	struct net_device *dev;
2032 	struct flexcan_priv *priv;
2033 	struct regulator *reg_xceiver;
2034 	struct clk *clk_ipg = NULL, *clk_per = NULL;
2035 	struct flexcan_regs __iomem *regs;
2036 	struct flexcan_platform_data *pdata;
2037 	int err, irq;
2038 	u8 clk_src = 1;
2039 	u32 clock_freq = 0;
2040 
2041 	reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2042 	if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2043 		return -EPROBE_DEFER;
2044 	else if (PTR_ERR(reg_xceiver) == -ENODEV)
2045 		reg_xceiver = NULL;
2046 	else if (IS_ERR(reg_xceiver))
2047 		return PTR_ERR(reg_xceiver);
2048 
2049 	if (pdev->dev.of_node) {
2050 		of_property_read_u32(pdev->dev.of_node,
2051 				     "clock-frequency", &clock_freq);
2052 		of_property_read_u8(pdev->dev.of_node,
2053 				    "fsl,clk-source", &clk_src);
2054 	} else {
2055 		pdata = dev_get_platdata(&pdev->dev);
2056 		if (pdata) {
2057 			clock_freq = pdata->clock_frequency;
2058 			clk_src = pdata->clk_src;
2059 		}
2060 	}
2061 
2062 	if (!clock_freq) {
2063 		clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2064 		if (IS_ERR(clk_ipg)) {
2065 			dev_err(&pdev->dev, "no ipg clock defined\n");
2066 			return PTR_ERR(clk_ipg);
2067 		}
2068 
2069 		clk_per = devm_clk_get(&pdev->dev, "per");
2070 		if (IS_ERR(clk_per)) {
2071 			dev_err(&pdev->dev, "no per clock defined\n");
2072 			return PTR_ERR(clk_per);
2073 		}
2074 		clock_freq = clk_get_rate(clk_per);
2075 	}
2076 
2077 	irq = platform_get_irq(pdev, 0);
2078 	if (irq <= 0)
2079 		return -ENODEV;
2080 
2081 	regs = devm_platform_ioremap_resource(pdev, 0);
2082 	if (IS_ERR(regs))
2083 		return PTR_ERR(regs);
2084 
2085 	of_id = of_match_device(flexcan_of_match, &pdev->dev);
2086 	if (of_id)
2087 		devtype_data = of_id->data;
2088 	else if (platform_get_device_id(pdev)->driver_data)
2089 		devtype_data = (struct flexcan_devtype_data *)
2090 			platform_get_device_id(pdev)->driver_data;
2091 	else
2092 		return -ENODEV;
2093 
2094 	if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2095 	    !((devtype_data->quirks &
2096 	       (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2097 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2098 		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR |
2099 		FLEXCAN_QUIRK_SUPPPORT_RX_FIFO)) ==
2100 	      (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2101 	       FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2102 	       FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR))) {
2103 		dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n");
2104 		return -EINVAL;
2105 	}
2106 
2107 	if ((devtype_data->quirks &
2108 	     (FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
2109 	      FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR)) ==
2110 	    FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR) {
2111 		dev_err(&pdev->dev,
2112 			"Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n",
2113 			devtype_data->quirks);
2114 		return -EINVAL;
2115 	}
2116 
2117 	dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2118 	if (!dev)
2119 		return -ENOMEM;
2120 
2121 	platform_set_drvdata(pdev, dev);
2122 	SET_NETDEV_DEV(dev, &pdev->dev);
2123 
2124 	dev->netdev_ops = &flexcan_netdev_ops;
2125 	flexcan_set_ethtool_ops(dev);
2126 	dev->irq = irq;
2127 	dev->flags |= IFF_ECHO;
2128 
2129 	priv = netdev_priv(dev);
2130 	priv->devtype_data = *devtype_data;
2131 
2132 	if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2133 	    priv->devtype_data.quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2134 		priv->read = flexcan_read_be;
2135 		priv->write = flexcan_write_be;
2136 	} else {
2137 		priv->read = flexcan_read_le;
2138 		priv->write = flexcan_write_le;
2139 	}
2140 
2141 	priv->dev = &pdev->dev;
2142 	priv->can.clock.freq = clock_freq;
2143 	priv->can.do_set_mode = flexcan_set_mode;
2144 	priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2145 	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2146 		CAN_CTRLMODE_LISTENONLY	| CAN_CTRLMODE_3_SAMPLES |
2147 		CAN_CTRLMODE_BERR_REPORTING;
2148 	priv->regs = regs;
2149 	priv->clk_ipg = clk_ipg;
2150 	priv->clk_per = clk_per;
2151 	priv->clk_src = clk_src;
2152 	priv->reg_xceiver = reg_xceiver;
2153 
2154 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
2155 		priv->irq_boff = platform_get_irq(pdev, 1);
2156 		if (priv->irq_boff <= 0) {
2157 			err = -ENODEV;
2158 			goto failed_platform_get_irq;
2159 		}
2160 		priv->irq_err = platform_get_irq(pdev, 2);
2161 		if (priv->irq_err <= 0) {
2162 			err = -ENODEV;
2163 			goto failed_platform_get_irq;
2164 		}
2165 	}
2166 
2167 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2168 		priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2169 			CAN_CTRLMODE_FD_NON_ISO;
2170 		priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2171 		priv->can.data_bittiming_const =
2172 			&flexcan_fd_data_bittiming_const;
2173 	} else {
2174 		priv->can.bittiming_const = &flexcan_bittiming_const;
2175 	}
2176 
2177 	pm_runtime_get_noresume(&pdev->dev);
2178 	pm_runtime_set_active(&pdev->dev);
2179 	pm_runtime_enable(&pdev->dev);
2180 
2181 	err = register_flexcandev(dev);
2182 	if (err) {
2183 		dev_err(&pdev->dev, "registering netdev failed\n");
2184 		goto failed_register;
2185 	}
2186 
2187 	err = flexcan_setup_stop_mode(pdev);
2188 	if (err < 0) {
2189 		if (err != -EPROBE_DEFER)
2190 			dev_err(&pdev->dev, "setup stop mode failed\n");
2191 		goto failed_setup_stop_mode;
2192 	}
2193 
2194 	of_can_transceiver(dev);
2195 	devm_can_led_init(dev);
2196 
2197 	return 0;
2198 
2199  failed_setup_stop_mode:
2200 	unregister_flexcandev(dev);
2201  failed_register:
2202 	pm_runtime_put_noidle(&pdev->dev);
2203 	pm_runtime_disable(&pdev->dev);
2204  failed_platform_get_irq:
2205 	free_candev(dev);
2206 	return err;
2207 }
2208 
2209 static int flexcan_remove(struct platform_device *pdev)
2210 {
2211 	struct net_device *dev = platform_get_drvdata(pdev);
2212 
2213 	device_set_wakeup_enable(&pdev->dev, false);
2214 	device_set_wakeup_capable(&pdev->dev, false);
2215 	unregister_flexcandev(dev);
2216 	pm_runtime_disable(&pdev->dev);
2217 	free_candev(dev);
2218 
2219 	return 0;
2220 }
2221 
2222 static int __maybe_unused flexcan_suspend(struct device *device)
2223 {
2224 	struct net_device *dev = dev_get_drvdata(device);
2225 	struct flexcan_priv *priv = netdev_priv(dev);
2226 	int err;
2227 
2228 	if (netif_running(dev)) {
2229 		/* if wakeup is enabled, enter stop mode
2230 		 * else enter disabled mode.
2231 		 */
2232 		if (device_may_wakeup(device)) {
2233 			enable_irq_wake(dev->irq);
2234 			err = flexcan_enter_stop_mode(priv);
2235 			if (err)
2236 				return err;
2237 		} else {
2238 			err = flexcan_chip_stop(dev);
2239 			if (err)
2240 				return err;
2241 
2242 			flexcan_chip_interrupts_disable(dev);
2243 
2244 			err = pinctrl_pm_select_sleep_state(device);
2245 			if (err)
2246 				return err;
2247 		}
2248 		netif_stop_queue(dev);
2249 		netif_device_detach(dev);
2250 	}
2251 	priv->can.state = CAN_STATE_SLEEPING;
2252 
2253 	return 0;
2254 }
2255 
2256 static int __maybe_unused flexcan_resume(struct device *device)
2257 {
2258 	struct net_device *dev = dev_get_drvdata(device);
2259 	struct flexcan_priv *priv = netdev_priv(dev);
2260 	int err;
2261 
2262 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
2263 	if (netif_running(dev)) {
2264 		netif_device_attach(dev);
2265 		netif_start_queue(dev);
2266 		if (device_may_wakeup(device)) {
2267 			disable_irq_wake(dev->irq);
2268 			err = flexcan_exit_stop_mode(priv);
2269 			if (err)
2270 				return err;
2271 		} else {
2272 			err = pinctrl_pm_select_default_state(device);
2273 			if (err)
2274 				return err;
2275 
2276 			err = flexcan_chip_start(dev);
2277 			if (err)
2278 				return err;
2279 
2280 			flexcan_chip_interrupts_enable(dev);
2281 		}
2282 	}
2283 
2284 	return 0;
2285 }
2286 
2287 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2288 {
2289 	struct net_device *dev = dev_get_drvdata(device);
2290 	struct flexcan_priv *priv = netdev_priv(dev);
2291 
2292 	flexcan_clks_disable(priv);
2293 
2294 	return 0;
2295 }
2296 
2297 static int __maybe_unused flexcan_runtime_resume(struct device *device)
2298 {
2299 	struct net_device *dev = dev_get_drvdata(device);
2300 	struct flexcan_priv *priv = netdev_priv(dev);
2301 
2302 	return flexcan_clks_enable(priv);
2303 }
2304 
2305 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2306 {
2307 	struct net_device *dev = dev_get_drvdata(device);
2308 	struct flexcan_priv *priv = netdev_priv(dev);
2309 
2310 	if (netif_running(dev)) {
2311 		int err;
2312 
2313 		if (device_may_wakeup(device))
2314 			flexcan_enable_wakeup_irq(priv, true);
2315 
2316 		err = pm_runtime_force_suspend(device);
2317 		if (err)
2318 			return err;
2319 	}
2320 
2321 	return 0;
2322 }
2323 
2324 static int __maybe_unused flexcan_noirq_resume(struct device *device)
2325 {
2326 	struct net_device *dev = dev_get_drvdata(device);
2327 	struct flexcan_priv *priv = netdev_priv(dev);
2328 
2329 	if (netif_running(dev)) {
2330 		int err;
2331 
2332 		err = pm_runtime_force_resume(device);
2333 		if (err)
2334 			return err;
2335 
2336 		if (device_may_wakeup(device))
2337 			flexcan_enable_wakeup_irq(priv, false);
2338 	}
2339 
2340 	return 0;
2341 }
2342 
2343 static const struct dev_pm_ops flexcan_pm_ops = {
2344 	SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2345 	SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2346 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2347 };
2348 
2349 static struct platform_driver flexcan_driver = {
2350 	.driver = {
2351 		.name = DRV_NAME,
2352 		.pm = &flexcan_pm_ops,
2353 		.of_match_table = flexcan_of_match,
2354 	},
2355 	.probe = flexcan_probe,
2356 	.remove = flexcan_remove,
2357 	.id_table = flexcan_id_table,
2358 };
2359 
2360 module_platform_driver(flexcan_driver);
2361 
2362 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2363 	      "Marc Kleine-Budde <kernel@pengutronix.de>");
2364 MODULE_LICENSE("GPL v2");
2365 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
2366