1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // flexcan.c - FLEXCAN CAN controller driver
4 //
5 // Copyright (c) 2005-2006 Varma Electronics Oy
6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2014 David Jander, Protonic Holland
9 //
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 
12 #include <dt-bindings/firmware/imx/rsrc.h>
13 #include <linux/bitfield.h>
14 #include <linux/can.h>
15 #include <linux/can/dev.h>
16 #include <linux/can/error.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/firmware/imx/sci.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/can/platform/flexcan.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/regmap.h>
32 #include <linux/regulator/consumer.h>
33 
34 #include "flexcan.h"
35 
36 #define DRV_NAME			"flexcan"
37 
38 /* 8 for RX fifo and 2 error handling */
39 #define FLEXCAN_NAPI_WEIGHT		(8 + 2)
40 
41 /* FLEXCAN module configuration register (CANMCR) bits */
42 #define FLEXCAN_MCR_MDIS		BIT(31)
43 #define FLEXCAN_MCR_FRZ			BIT(30)
44 #define FLEXCAN_MCR_FEN			BIT(29)
45 #define FLEXCAN_MCR_HALT		BIT(28)
46 #define FLEXCAN_MCR_NOT_RDY		BIT(27)
47 #define FLEXCAN_MCR_WAK_MSK		BIT(26)
48 #define FLEXCAN_MCR_SOFTRST		BIT(25)
49 #define FLEXCAN_MCR_FRZ_ACK		BIT(24)
50 #define FLEXCAN_MCR_SUPV		BIT(23)
51 #define FLEXCAN_MCR_SLF_WAK		BIT(22)
52 #define FLEXCAN_MCR_WRN_EN		BIT(21)
53 #define FLEXCAN_MCR_LPM_ACK		BIT(20)
54 #define FLEXCAN_MCR_WAK_SRC		BIT(19)
55 #define FLEXCAN_MCR_DOZE		BIT(18)
56 #define FLEXCAN_MCR_SRX_DIS		BIT(17)
57 #define FLEXCAN_MCR_IRMQ		BIT(16)
58 #define FLEXCAN_MCR_LPRIO_EN		BIT(13)
59 #define FLEXCAN_MCR_AEN			BIT(12)
60 #define FLEXCAN_MCR_FDEN		BIT(11)
61 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
62 #define FLEXCAN_MCR_MAXMB(x)		((x) & 0x7f)
63 #define FLEXCAN_MCR_IDAM_A		(0x0 << 8)
64 #define FLEXCAN_MCR_IDAM_B		(0x1 << 8)
65 #define FLEXCAN_MCR_IDAM_C		(0x2 << 8)
66 #define FLEXCAN_MCR_IDAM_D		(0x3 << 8)
67 
68 /* FLEXCAN control register (CANCTRL) bits */
69 #define FLEXCAN_CTRL_PRESDIV(x)		(((x) & 0xff) << 24)
70 #define FLEXCAN_CTRL_RJW(x)		(((x) & 0x03) << 22)
71 #define FLEXCAN_CTRL_PSEG1(x)		(((x) & 0x07) << 19)
72 #define FLEXCAN_CTRL_PSEG2(x)		(((x) & 0x07) << 16)
73 #define FLEXCAN_CTRL_BOFF_MSK		BIT(15)
74 #define FLEXCAN_CTRL_ERR_MSK		BIT(14)
75 #define FLEXCAN_CTRL_CLK_SRC		BIT(13)
76 #define FLEXCAN_CTRL_LPB		BIT(12)
77 #define FLEXCAN_CTRL_TWRN_MSK		BIT(11)
78 #define FLEXCAN_CTRL_RWRN_MSK		BIT(10)
79 #define FLEXCAN_CTRL_SMP		BIT(7)
80 #define FLEXCAN_CTRL_BOFF_REC		BIT(6)
81 #define FLEXCAN_CTRL_TSYN		BIT(5)
82 #define FLEXCAN_CTRL_LBUF		BIT(4)
83 #define FLEXCAN_CTRL_LOM		BIT(3)
84 #define FLEXCAN_CTRL_PROPSEG(x)		((x) & 0x07)
85 #define FLEXCAN_CTRL_ERR_BUS		(FLEXCAN_CTRL_ERR_MSK)
86 #define FLEXCAN_CTRL_ERR_STATE \
87 	(FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
88 	 FLEXCAN_CTRL_BOFF_MSK)
89 #define FLEXCAN_CTRL_ERR_ALL \
90 	(FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
91 
92 /* FLEXCAN control register 2 (CTRL2) bits */
93 #define FLEXCAN_CTRL2_ECRWRE		BIT(29)
94 #define FLEXCAN_CTRL2_WRMFRZ		BIT(28)
95 #define FLEXCAN_CTRL2_RFFN(x)		(((x) & 0x0f) << 24)
96 #define FLEXCAN_CTRL2_TASD(x)		(((x) & 0x1f) << 19)
97 #define FLEXCAN_CTRL2_MRP		BIT(18)
98 #define FLEXCAN_CTRL2_RRS		BIT(17)
99 #define FLEXCAN_CTRL2_EACEN		BIT(16)
100 #define FLEXCAN_CTRL2_ISOCANFDEN	BIT(12)
101 
102 /* FLEXCAN memory error control register (MECR) bits */
103 #define FLEXCAN_MECR_ECRWRDIS		BIT(31)
104 #define FLEXCAN_MECR_HANCEI_MSK		BIT(19)
105 #define FLEXCAN_MECR_FANCEI_MSK		BIT(18)
106 #define FLEXCAN_MECR_CEI_MSK		BIT(16)
107 #define FLEXCAN_MECR_HAERRIE		BIT(15)
108 #define FLEXCAN_MECR_FAERRIE		BIT(14)
109 #define FLEXCAN_MECR_EXTERRIE		BIT(13)
110 #define FLEXCAN_MECR_RERRDIS		BIT(9)
111 #define FLEXCAN_MECR_ECCDIS		BIT(8)
112 #define FLEXCAN_MECR_NCEFAFRZ		BIT(7)
113 
114 /* FLEXCAN error and status register (ESR) bits */
115 #define FLEXCAN_ESR_TWRN_INT		BIT(17)
116 #define FLEXCAN_ESR_RWRN_INT		BIT(16)
117 #define FLEXCAN_ESR_BIT1_ERR		BIT(15)
118 #define FLEXCAN_ESR_BIT0_ERR		BIT(14)
119 #define FLEXCAN_ESR_ACK_ERR		BIT(13)
120 #define FLEXCAN_ESR_CRC_ERR		BIT(12)
121 #define FLEXCAN_ESR_FRM_ERR		BIT(11)
122 #define FLEXCAN_ESR_STF_ERR		BIT(10)
123 #define FLEXCAN_ESR_TX_WRN		BIT(9)
124 #define FLEXCAN_ESR_RX_WRN		BIT(8)
125 #define FLEXCAN_ESR_IDLE		BIT(7)
126 #define FLEXCAN_ESR_TXRX		BIT(6)
127 #define FLEXCAN_EST_FLT_CONF_SHIFT	(4)
128 #define FLEXCAN_ESR_FLT_CONF_MASK	(0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
129 #define FLEXCAN_ESR_FLT_CONF_ACTIVE	(0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_FLT_CONF_PASSIVE	(0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_BOFF_INT		BIT(2)
132 #define FLEXCAN_ESR_ERR_INT		BIT(1)
133 #define FLEXCAN_ESR_WAK_INT		BIT(0)
134 #define FLEXCAN_ESR_ERR_BUS \
135 	(FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
136 	 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
137 	 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
138 #define FLEXCAN_ESR_ERR_STATE \
139 	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
140 #define FLEXCAN_ESR_ERR_ALL \
141 	(FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
142 #define FLEXCAN_ESR_ALL_INT \
143 	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
144 	 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
145 
146 /* FLEXCAN Bit Timing register (CBT) bits */
147 #define FLEXCAN_CBT_BTF			BIT(31)
148 #define FLEXCAN_CBT_EPRESDIV_MASK	GENMASK(30, 21)
149 #define FLEXCAN_CBT_ERJW_MASK		GENMASK(20, 16)
150 #define FLEXCAN_CBT_EPROPSEG_MASK	GENMASK(15, 10)
151 #define FLEXCAN_CBT_EPSEG1_MASK		GENMASK(9, 5)
152 #define FLEXCAN_CBT_EPSEG2_MASK		GENMASK(4, 0)
153 
154 /* FLEXCAN FD control register (FDCTRL) bits */
155 #define FLEXCAN_FDCTRL_FDRATE		BIT(31)
156 #define FLEXCAN_FDCTRL_MBDSR1		GENMASK(20, 19)
157 #define FLEXCAN_FDCTRL_MBDSR0		GENMASK(17, 16)
158 #define FLEXCAN_FDCTRL_MBDSR_8		0x0
159 #define FLEXCAN_FDCTRL_MBDSR_12		0x1
160 #define FLEXCAN_FDCTRL_MBDSR_32		0x2
161 #define FLEXCAN_FDCTRL_MBDSR_64		0x3
162 #define FLEXCAN_FDCTRL_TDCEN		BIT(15)
163 #define FLEXCAN_FDCTRL_TDCFAIL		BIT(14)
164 #define FLEXCAN_FDCTRL_TDCOFF		GENMASK(12, 8)
165 #define FLEXCAN_FDCTRL_TDCVAL		GENMASK(5, 0)
166 
167 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
168 #define FLEXCAN_FDCBT_FPRESDIV_MASK	GENMASK(29, 20)
169 #define FLEXCAN_FDCBT_FRJW_MASK		GENMASK(18, 16)
170 #define FLEXCAN_FDCBT_FPROPSEG_MASK	GENMASK(14, 10)
171 #define FLEXCAN_FDCBT_FPSEG1_MASK	GENMASK(7, 5)
172 #define FLEXCAN_FDCBT_FPSEG2_MASK	GENMASK(2, 0)
173 
174 /* FLEXCAN interrupt flag register (IFLAG) bits */
175 /* Errata ERR005829 step7: Reserve first valid MB */
176 #define FLEXCAN_TX_MB_RESERVED_RX_FIFO	8
177 #define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX	0
178 #define FLEXCAN_RX_MB_RX_MAILBOX_FIRST	(FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1)
179 #define FLEXCAN_IFLAG_MB(x)		BIT_ULL(x)
180 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW	BIT(7)
181 #define FLEXCAN_IFLAG_RX_FIFO_WARN	BIT(6)
182 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE	BIT(5)
183 
184 /* FLEXCAN message buffers */
185 #define FLEXCAN_MB_CODE_MASK		(0xf << 24)
186 #define FLEXCAN_MB_CODE_RX_BUSY_BIT	(0x1 << 24)
187 #define FLEXCAN_MB_CODE_RX_INACTIVE	(0x0 << 24)
188 #define FLEXCAN_MB_CODE_RX_EMPTY	(0x4 << 24)
189 #define FLEXCAN_MB_CODE_RX_FULL		(0x2 << 24)
190 #define FLEXCAN_MB_CODE_RX_OVERRUN	(0x6 << 24)
191 #define FLEXCAN_MB_CODE_RX_RANSWER	(0xa << 24)
192 
193 #define FLEXCAN_MB_CODE_TX_INACTIVE	(0x8 << 24)
194 #define FLEXCAN_MB_CODE_TX_ABORT	(0x9 << 24)
195 #define FLEXCAN_MB_CODE_TX_DATA		(0xc << 24)
196 #define FLEXCAN_MB_CODE_TX_TANSWER	(0xe << 24)
197 
198 #define FLEXCAN_MB_CNT_EDL		BIT(31)
199 #define FLEXCAN_MB_CNT_BRS		BIT(30)
200 #define FLEXCAN_MB_CNT_ESI		BIT(29)
201 #define FLEXCAN_MB_CNT_SRR		BIT(22)
202 #define FLEXCAN_MB_CNT_IDE		BIT(21)
203 #define FLEXCAN_MB_CNT_RTR		BIT(20)
204 #define FLEXCAN_MB_CNT_LENGTH(x)	(((x) & 0xf) << 16)
205 #define FLEXCAN_MB_CNT_TIMESTAMP(x)	((x) & 0xffff)
206 
207 #define FLEXCAN_TIMEOUT_US		(250)
208 
209 /* Structure of the message buffer */
210 struct flexcan_mb {
211 	u32 can_ctrl;
212 	u32 can_id;
213 	u32 data[];
214 };
215 
216 /* Structure of the hardware registers */
217 struct flexcan_regs {
218 	u32 mcr;		/* 0x00 */
219 	u32 ctrl;		/* 0x04 - Not affected by Soft Reset */
220 	u32 timer;		/* 0x08 */
221 	u32 tcr;		/* 0x0c */
222 	u32 rxgmask;		/* 0x10 - Not affected by Soft Reset */
223 	u32 rx14mask;		/* 0x14 - Not affected by Soft Reset */
224 	u32 rx15mask;		/* 0x18 - Not affected by Soft Reset */
225 	u32 ecr;		/* 0x1c */
226 	u32 esr;		/* 0x20 */
227 	u32 imask2;		/* 0x24 */
228 	u32 imask1;		/* 0x28 */
229 	u32 iflag2;		/* 0x2c */
230 	u32 iflag1;		/* 0x30 */
231 	union {			/* 0x34 */
232 		u32 gfwr_mx28;	/* MX28, MX53 */
233 		u32 ctrl2;	/* MX6, VF610 - Not affected by Soft Reset */
234 	};
235 	u32 esr2;		/* 0x38 */
236 	u32 imeur;		/* 0x3c */
237 	u32 lrfr;		/* 0x40 */
238 	u32 crcr;		/* 0x44 */
239 	u32 rxfgmask;		/* 0x48 */
240 	u32 rxfir;		/* 0x4c - Not affected by Soft Reset */
241 	u32 cbt;		/* 0x50 - Not affected by Soft Reset */
242 	u32 _reserved2;		/* 0x54 */
243 	u32 dbg1;		/* 0x58 */
244 	u32 dbg2;		/* 0x5c */
245 	u32 _reserved3[8];	/* 0x60 */
246 	struct_group(init,
247 		u8 mb[2][512];		/* 0x80 - Not affected by Soft Reset */
248 		/* FIFO-mode:
249 		 *			MB
250 		 * 0x080...0x08f	0	RX message buffer
251 		 * 0x090...0x0df	1-5	reserved
252 		 * 0x0e0...0x0ff	6-7	8 entry ID table
253 		 *				(mx25, mx28, mx35, mx53)
254 		 * 0x0e0...0x2df	6-7..37	8..128 entry ID table
255 		 *				size conf'ed via ctrl2::RFFN
256 		 *				(mx6, vf610)
257 		 */
258 		u32 _reserved4[256];	/* 0x480 */
259 		u32 rximr[64];		/* 0x880 - Not affected by Soft Reset */
260 		u32 _reserved5[24];	/* 0x980 */
261 		u32 gfwr_mx6;		/* 0x9e0 - MX6 */
262 		u32 _reserved6[39];	/* 0x9e4 */
263 		u32 _rxfir[6];		/* 0xa80 */
264 		u32 _reserved8[2];	/* 0xa98 */
265 		u32 _rxmgmask;		/* 0xaa0 */
266 		u32 _rxfgmask;		/* 0xaa4 */
267 		u32 _rx14mask;		/* 0xaa8 */
268 		u32 _rx15mask;		/* 0xaac */
269 		u32 tx_smb[4];		/* 0xab0 */
270 		u32 rx_smb0[4];		/* 0xac0 */
271 		u32 rx_smb1[4];		/* 0xad0 */
272 	);
273 	u32 mecr;		/* 0xae0 */
274 	u32 erriar;		/* 0xae4 */
275 	u32 erridpr;		/* 0xae8 */
276 	u32 errippr;		/* 0xaec */
277 	u32 rerrar;		/* 0xaf0 */
278 	u32 rerrdr;		/* 0xaf4 */
279 	u32 rerrsynr;		/* 0xaf8 */
280 	u32 errsr;		/* 0xafc */
281 	u32 _reserved7[64];	/* 0xb00 */
282 	u32 fdctrl;		/* 0xc00 - Not affected by Soft Reset */
283 	u32 fdcbt;		/* 0xc04 - Not affected by Soft Reset */
284 	u32 fdcrc;		/* 0xc08 */
285 	u32 _reserved9[199];	/* 0xc0c */
286 	struct_group(init_fd,
287 		u32 tx_smb_fd[18];	/* 0xf28 */
288 		u32 rx_smb0_fd[18];	/* 0xf70 */
289 		u32 rx_smb1_fd[18];	/* 0xfb8 */
290 	);
291 };
292 
293 static_assert(sizeof(struct flexcan_regs) ==  0x4 * 18 + 0xfb8);
294 
295 static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = {
296 	.quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
297 		FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 |
298 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
299 		FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
300 };
301 
302 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
303 	.quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
304 		FLEXCAN_QUIRK_BROKEN_PERR_STATE |
305 		FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN |
306 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
307 		FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
308 };
309 
310 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
311 	.quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
312 		FLEXCAN_QUIRK_BROKEN_PERR_STATE |
313 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
314 		FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
315 };
316 
317 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
318 	.quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
319 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
320 		FLEXCAN_QUIRK_SUPPORT_RX_FIFO,
321 };
322 
323 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
324 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
325 		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
326 		FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
327 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
328 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
329 };
330 
331 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
332 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
333 		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
334 		FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW |
335 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
336 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
337 };
338 
339 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
340 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
341 		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
342 		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
343 		FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
344 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
345 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
346 };
347 
348 static struct flexcan_devtype_data fsl_imx93_devtype_data = {
349 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
350 		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
351 		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
352 		FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
353 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
354 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
355 };
356 
357 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
358 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
359 		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
360 		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC |
361 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
362 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
363 };
364 
365 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
366 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
367 		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX |
368 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
369 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
370 };
371 
372 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
373 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
374 		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
375 		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
376 		FLEXCAN_QUIRK_SUPPORT_ECC |
377 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
378 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
379 };
380 
381 static const struct can_bittiming_const flexcan_bittiming_const = {
382 	.name = DRV_NAME,
383 	.tseg1_min = 4,
384 	.tseg1_max = 16,
385 	.tseg2_min = 2,
386 	.tseg2_max = 8,
387 	.sjw_max = 4,
388 	.brp_min = 1,
389 	.brp_max = 256,
390 	.brp_inc = 1,
391 };
392 
393 static const struct can_bittiming_const flexcan_fd_bittiming_const = {
394 	.name = DRV_NAME,
395 	.tseg1_min = 2,
396 	.tseg1_max = 96,
397 	.tseg2_min = 2,
398 	.tseg2_max = 32,
399 	.sjw_max = 16,
400 	.brp_min = 1,
401 	.brp_max = 1024,
402 	.brp_inc = 1,
403 };
404 
405 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
406 	.name = DRV_NAME,
407 	.tseg1_min = 2,
408 	.tseg1_max = 39,
409 	.tseg2_min = 2,
410 	.tseg2_max = 8,
411 	.sjw_max = 4,
412 	.brp_min = 1,
413 	.brp_max = 1024,
414 	.brp_inc = 1,
415 };
416 
417 /* FlexCAN module is essentially modelled as a little-endian IP in most
418  * SoCs, i.e the registers as well as the message buffer areas are
419  * implemented in a little-endian fashion.
420  *
421  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
422  * module in a big-endian fashion (i.e the registers as well as the
423  * message buffer areas are implemented in a big-endian way).
424  *
425  * In addition, the FlexCAN module can be found on SoCs having ARM or
426  * PPC cores. So, we need to abstract off the register read/write
427  * functions, ensuring that these cater to all the combinations of module
428  * endianness and underlying CPU endianness.
429  */
430 static inline u32 flexcan_read_be(void __iomem *addr)
431 {
432 	return ioread32be(addr);
433 }
434 
435 static inline void flexcan_write_be(u32 val, void __iomem *addr)
436 {
437 	iowrite32be(val, addr);
438 }
439 
440 static inline u32 flexcan_read_le(void __iomem *addr)
441 {
442 	return ioread32(addr);
443 }
444 
445 static inline void flexcan_write_le(u32 val, void __iomem *addr)
446 {
447 	iowrite32(val, addr);
448 }
449 
450 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
451 						 u8 mb_index)
452 {
453 	u8 bank_size;
454 	bool bank;
455 
456 	if (WARN_ON(mb_index >= priv->mb_count))
457 		return NULL;
458 
459 	bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
460 
461 	bank = mb_index >= bank_size;
462 	if (bank)
463 		mb_index -= bank_size;
464 
465 	return (struct flexcan_mb __iomem *)
466 		(&priv->regs->mb[bank][priv->mb_size * mb_index]);
467 }
468 
469 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
470 {
471 	struct flexcan_regs __iomem *regs = priv->regs;
472 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
473 
474 	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
475 		udelay(10);
476 
477 	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
478 		return -ETIMEDOUT;
479 
480 	return 0;
481 }
482 
483 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
484 {
485 	struct flexcan_regs __iomem *regs = priv->regs;
486 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
487 
488 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
489 		udelay(10);
490 
491 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
492 		return -ETIMEDOUT;
493 
494 	return 0;
495 }
496 
497 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
498 {
499 	struct flexcan_regs __iomem *regs = priv->regs;
500 	u32 reg_mcr;
501 
502 	reg_mcr = priv->read(&regs->mcr);
503 
504 	if (enable)
505 		reg_mcr |= FLEXCAN_MCR_WAK_MSK;
506 	else
507 		reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
508 
509 	priv->write(reg_mcr, &regs->mcr);
510 }
511 
512 static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
513 {
514 	u8 idx = priv->scu_idx;
515 	u32 rsrc_id, val;
516 
517 	rsrc_id = IMX_SC_R_CAN(idx);
518 
519 	if (enabled)
520 		val = 1;
521 	else
522 		val = 0;
523 
524 	/* stop mode request via scu firmware */
525 	return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
526 				       IMX_SC_C_IPG_STOP, val);
527 }
528 
529 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
530 {
531 	struct flexcan_regs __iomem *regs = priv->regs;
532 	u32 reg_mcr;
533 	int ret;
534 
535 	reg_mcr = priv->read(&regs->mcr);
536 	reg_mcr |= FLEXCAN_MCR_SLF_WAK;
537 	priv->write(reg_mcr, &regs->mcr);
538 
539 	/* enable stop request */
540 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
541 		ret = flexcan_stop_mode_enable_scfw(priv, true);
542 		if (ret < 0)
543 			return ret;
544 	} else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) {
545 		regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
546 				   1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
547 	}
548 
549 	return flexcan_low_power_enter_ack(priv);
550 }
551 
552 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
553 {
554 	struct flexcan_regs __iomem *regs = priv->regs;
555 	u32 reg_mcr;
556 	int ret;
557 
558 	/* remove stop request */
559 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
560 		ret = flexcan_stop_mode_enable_scfw(priv, false);
561 		if (ret < 0)
562 			return ret;
563 	} else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) {
564 		regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
565 				   1 << priv->stm.req_bit, 0);
566 	}
567 
568 	reg_mcr = priv->read(&regs->mcr);
569 	reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
570 	priv->write(reg_mcr, &regs->mcr);
571 
572 	return flexcan_low_power_exit_ack(priv);
573 }
574 
575 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
576 {
577 	struct flexcan_regs __iomem *regs = priv->regs;
578 	u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
579 
580 	priv->write(reg_ctrl, &regs->ctrl);
581 }
582 
583 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
584 {
585 	struct flexcan_regs __iomem *regs = priv->regs;
586 	u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
587 
588 	priv->write(reg_ctrl, &regs->ctrl);
589 }
590 
591 static int flexcan_clks_enable(const struct flexcan_priv *priv)
592 {
593 	int err = 0;
594 
595 	if (priv->clk_ipg) {
596 		err = clk_prepare_enable(priv->clk_ipg);
597 		if (err)
598 			return err;
599 	}
600 
601 	if (priv->clk_per) {
602 		err = clk_prepare_enable(priv->clk_per);
603 		if (err)
604 			clk_disable_unprepare(priv->clk_ipg);
605 	}
606 
607 	return err;
608 }
609 
610 static void flexcan_clks_disable(const struct flexcan_priv *priv)
611 {
612 	clk_disable_unprepare(priv->clk_per);
613 	clk_disable_unprepare(priv->clk_ipg);
614 }
615 
616 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
617 {
618 	if (!priv->reg_xceiver)
619 		return 0;
620 
621 	return regulator_enable(priv->reg_xceiver);
622 }
623 
624 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
625 {
626 	if (!priv->reg_xceiver)
627 		return 0;
628 
629 	return regulator_disable(priv->reg_xceiver);
630 }
631 
632 static int flexcan_chip_enable(struct flexcan_priv *priv)
633 {
634 	struct flexcan_regs __iomem *regs = priv->regs;
635 	u32 reg;
636 
637 	reg = priv->read(&regs->mcr);
638 	reg &= ~FLEXCAN_MCR_MDIS;
639 	priv->write(reg, &regs->mcr);
640 
641 	return flexcan_low_power_exit_ack(priv);
642 }
643 
644 static int flexcan_chip_disable(struct flexcan_priv *priv)
645 {
646 	struct flexcan_regs __iomem *regs = priv->regs;
647 	u32 reg;
648 
649 	reg = priv->read(&regs->mcr);
650 	reg |= FLEXCAN_MCR_MDIS;
651 	priv->write(reg, &regs->mcr);
652 
653 	return flexcan_low_power_enter_ack(priv);
654 }
655 
656 static int flexcan_chip_freeze(struct flexcan_priv *priv)
657 {
658 	struct flexcan_regs __iomem *regs = priv->regs;
659 	unsigned int timeout;
660 	u32 bitrate = priv->can.bittiming.bitrate;
661 	u32 reg;
662 
663 	if (bitrate)
664 		timeout = 1000 * 1000 * 10 / bitrate;
665 	else
666 		timeout = FLEXCAN_TIMEOUT_US / 10;
667 
668 	reg = priv->read(&regs->mcr);
669 	reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
670 	priv->write(reg, &regs->mcr);
671 
672 	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
673 		udelay(100);
674 
675 	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
676 		return -ETIMEDOUT;
677 
678 	return 0;
679 }
680 
681 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
682 {
683 	struct flexcan_regs __iomem *regs = priv->regs;
684 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
685 	u32 reg;
686 
687 	reg = priv->read(&regs->mcr);
688 	reg &= ~FLEXCAN_MCR_HALT;
689 	priv->write(reg, &regs->mcr);
690 
691 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
692 		udelay(10);
693 
694 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
695 		return -ETIMEDOUT;
696 
697 	return 0;
698 }
699 
700 static int flexcan_chip_softreset(struct flexcan_priv *priv)
701 {
702 	struct flexcan_regs __iomem *regs = priv->regs;
703 	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
704 
705 	priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
706 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
707 		udelay(10);
708 
709 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
710 		return -ETIMEDOUT;
711 
712 	return 0;
713 }
714 
715 static int __flexcan_get_berr_counter(const struct net_device *dev,
716 				      struct can_berr_counter *bec)
717 {
718 	const struct flexcan_priv *priv = netdev_priv(dev);
719 	struct flexcan_regs __iomem *regs = priv->regs;
720 	u32 reg = priv->read(&regs->ecr);
721 
722 	bec->txerr = (reg >> 0) & 0xff;
723 	bec->rxerr = (reg >> 8) & 0xff;
724 
725 	return 0;
726 }
727 
728 static int flexcan_get_berr_counter(const struct net_device *dev,
729 				    struct can_berr_counter *bec)
730 {
731 	const struct flexcan_priv *priv = netdev_priv(dev);
732 	int err;
733 
734 	err = pm_runtime_resume_and_get(priv->dev);
735 	if (err < 0)
736 		return err;
737 
738 	err = __flexcan_get_berr_counter(dev, bec);
739 
740 	pm_runtime_put(priv->dev);
741 
742 	return err;
743 }
744 
745 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
746 {
747 	const struct flexcan_priv *priv = netdev_priv(dev);
748 	struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
749 	u32 can_id;
750 	u32 data;
751 	u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
752 	int i;
753 
754 	if (can_dev_dropped_skb(dev, skb))
755 		return NETDEV_TX_OK;
756 
757 	netif_stop_queue(dev);
758 
759 	if (cfd->can_id & CAN_EFF_FLAG) {
760 		can_id = cfd->can_id & CAN_EFF_MASK;
761 		ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
762 	} else {
763 		can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
764 	}
765 
766 	if (cfd->can_id & CAN_RTR_FLAG)
767 		ctrl |= FLEXCAN_MB_CNT_RTR;
768 
769 	if (can_is_canfd_skb(skb)) {
770 		ctrl |= FLEXCAN_MB_CNT_EDL;
771 
772 		if (cfd->flags & CANFD_BRS)
773 			ctrl |= FLEXCAN_MB_CNT_BRS;
774 	}
775 
776 	for (i = 0; i < cfd->len; i += sizeof(u32)) {
777 		data = be32_to_cpup((__be32 *)&cfd->data[i]);
778 		priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
779 	}
780 
781 	can_put_echo_skb(skb, dev, 0, 0);
782 
783 	priv->write(can_id, &priv->tx_mb->can_id);
784 	priv->write(ctrl, &priv->tx_mb->can_ctrl);
785 
786 	/* Errata ERR005829 step8:
787 	 * Write twice INACTIVE(0x8) code to first MB.
788 	 */
789 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
790 		    &priv->tx_mb_reserved->can_ctrl);
791 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
792 		    &priv->tx_mb_reserved->can_ctrl);
793 
794 	return NETDEV_TX_OK;
795 }
796 
797 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
798 {
799 	struct flexcan_priv *priv = netdev_priv(dev);
800 	struct flexcan_regs __iomem *regs = priv->regs;
801 	struct sk_buff *skb;
802 	struct can_frame *cf;
803 	bool rx_errors = false, tx_errors = false;
804 	u32 timestamp;
805 	int err;
806 
807 	timestamp = priv->read(&regs->timer) << 16;
808 
809 	skb = alloc_can_err_skb(dev, &cf);
810 	if (unlikely(!skb))
811 		return;
812 
813 	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
814 
815 	if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
816 		netdev_dbg(dev, "BIT1_ERR irq\n");
817 		cf->data[2] |= CAN_ERR_PROT_BIT1;
818 		tx_errors = true;
819 	}
820 	if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
821 		netdev_dbg(dev, "BIT0_ERR irq\n");
822 		cf->data[2] |= CAN_ERR_PROT_BIT0;
823 		tx_errors = true;
824 	}
825 	if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
826 		netdev_dbg(dev, "ACK_ERR irq\n");
827 		cf->can_id |= CAN_ERR_ACK;
828 		cf->data[3] = CAN_ERR_PROT_LOC_ACK;
829 		tx_errors = true;
830 	}
831 	if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
832 		netdev_dbg(dev, "CRC_ERR irq\n");
833 		cf->data[2] |= CAN_ERR_PROT_BIT;
834 		cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
835 		rx_errors = true;
836 	}
837 	if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
838 		netdev_dbg(dev, "FRM_ERR irq\n");
839 		cf->data[2] |= CAN_ERR_PROT_FORM;
840 		rx_errors = true;
841 	}
842 	if (reg_esr & FLEXCAN_ESR_STF_ERR) {
843 		netdev_dbg(dev, "STF_ERR irq\n");
844 		cf->data[2] |= CAN_ERR_PROT_STUFF;
845 		rx_errors = true;
846 	}
847 
848 	priv->can.can_stats.bus_error++;
849 	if (rx_errors)
850 		dev->stats.rx_errors++;
851 	if (tx_errors)
852 		dev->stats.tx_errors++;
853 
854 	err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
855 	if (err)
856 		dev->stats.rx_fifo_errors++;
857 }
858 
859 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
860 {
861 	struct flexcan_priv *priv = netdev_priv(dev);
862 	struct flexcan_regs __iomem *regs = priv->regs;
863 	struct sk_buff *skb;
864 	struct can_frame *cf;
865 	enum can_state new_state, rx_state, tx_state;
866 	int flt;
867 	struct can_berr_counter bec;
868 	u32 timestamp;
869 	int err;
870 
871 	flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
872 	if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
873 		tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
874 			CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
875 		rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
876 			CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
877 		new_state = max(tx_state, rx_state);
878 	} else {
879 		__flexcan_get_berr_counter(dev, &bec);
880 		new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
881 			CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
882 		rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
883 		tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
884 	}
885 
886 	/* state hasn't changed */
887 	if (likely(new_state == priv->can.state))
888 		return;
889 
890 	timestamp = priv->read(&regs->timer) << 16;
891 
892 	skb = alloc_can_err_skb(dev, &cf);
893 	if (unlikely(!skb))
894 		return;
895 
896 	can_change_state(dev, cf, tx_state, rx_state);
897 
898 	if (unlikely(new_state == CAN_STATE_BUS_OFF))
899 		can_bus_off(dev);
900 
901 	err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
902 	if (err)
903 		dev->stats.rx_fifo_errors++;
904 }
905 
906 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
907 {
908 	u64 reg = 0;
909 
910 	if (upper_32_bits(mask))
911 		reg = (u64)priv->read(addr - 4) << 32;
912 	if (lower_32_bits(mask))
913 		reg |= priv->read(addr);
914 
915 	return reg & mask;
916 }
917 
918 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
919 {
920 	if (upper_32_bits(val))
921 		priv->write(upper_32_bits(val), addr - 4);
922 	if (lower_32_bits(val))
923 		priv->write(lower_32_bits(val), addr);
924 }
925 
926 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
927 {
928 	return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
929 }
930 
931 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
932 {
933 	return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
934 }
935 
936 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
937 {
938 	return container_of(offload, struct flexcan_priv, offload);
939 }
940 
941 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
942 					    unsigned int n, u32 *timestamp,
943 					    bool drop)
944 {
945 	struct flexcan_priv *priv = rx_offload_to_priv(offload);
946 	struct flexcan_regs __iomem *regs = priv->regs;
947 	struct flexcan_mb __iomem *mb;
948 	struct sk_buff *skb;
949 	struct canfd_frame *cfd;
950 	u32 reg_ctrl, reg_id, reg_iflag1;
951 	int i;
952 
953 	mb = flexcan_get_mb(priv, n);
954 
955 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
956 		u32 code;
957 
958 		do {
959 			reg_ctrl = priv->read(&mb->can_ctrl);
960 		} while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
961 
962 		/* is this MB empty? */
963 		code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
964 		if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
965 		    (code != FLEXCAN_MB_CODE_RX_OVERRUN))
966 			return NULL;
967 
968 		if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
969 			/* This MB was overrun, we lost data */
970 			offload->dev->stats.rx_over_errors++;
971 			offload->dev->stats.rx_errors++;
972 		}
973 	} else {
974 		reg_iflag1 = priv->read(&regs->iflag1);
975 		if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
976 			return NULL;
977 
978 		reg_ctrl = priv->read(&mb->can_ctrl);
979 	}
980 
981 	if (unlikely(drop)) {
982 		skb = ERR_PTR(-ENOBUFS);
983 		goto mark_as_read;
984 	}
985 
986 	if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
987 		skb = alloc_canfd_skb(offload->dev, &cfd);
988 	else
989 		skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
990 	if (unlikely(!skb)) {
991 		skb = ERR_PTR(-ENOMEM);
992 		goto mark_as_read;
993 	}
994 
995 	/* increase timstamp to full 32 bit */
996 	*timestamp = reg_ctrl << 16;
997 
998 	reg_id = priv->read(&mb->can_id);
999 	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
1000 		cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
1001 	else
1002 		cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
1003 
1004 	if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1005 		cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
1006 
1007 		if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1008 			cfd->flags |= CANFD_BRS;
1009 	} else {
1010 		cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1011 
1012 		if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1013 			cfd->can_id |= CAN_RTR_FLAG;
1014 	}
1015 
1016 	if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1017 		cfd->flags |= CANFD_ESI;
1018 
1019 	for (i = 0; i < cfd->len; i += sizeof(u32)) {
1020 		__be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1021 		*(__be32 *)(cfd->data + i) = data;
1022 	}
1023 
1024  mark_as_read:
1025 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1026 		flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), &regs->iflag1);
1027 	else
1028 		priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
1029 
1030 	/* Read the Free Running Timer. It is optional but recommended
1031 	 * to unlock Mailbox as soon as possible and make it available
1032 	 * for reception.
1033 	 */
1034 	priv->read(&regs->timer);
1035 
1036 	return skb;
1037 }
1038 
1039 static irqreturn_t flexcan_irq(int irq, void *dev_id)
1040 {
1041 	struct net_device *dev = dev_id;
1042 	struct net_device_stats *stats = &dev->stats;
1043 	struct flexcan_priv *priv = netdev_priv(dev);
1044 	struct flexcan_regs __iomem *regs = priv->regs;
1045 	irqreturn_t handled = IRQ_NONE;
1046 	u64 reg_iflag_tx;
1047 	u32 reg_esr;
1048 	enum can_state last_state = priv->can.state;
1049 
1050 	/* reception interrupt */
1051 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1052 		u64 reg_iflag_rx;
1053 		int ret;
1054 
1055 		while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1056 			handled = IRQ_HANDLED;
1057 			ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1058 								   reg_iflag_rx);
1059 			if (!ret)
1060 				break;
1061 		}
1062 	} else {
1063 		u32 reg_iflag1;
1064 
1065 		reg_iflag1 = priv->read(&regs->iflag1);
1066 		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1067 			handled = IRQ_HANDLED;
1068 			can_rx_offload_irq_offload_fifo(&priv->offload);
1069 		}
1070 
1071 		/* FIFO overflow interrupt */
1072 		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1073 			handled = IRQ_HANDLED;
1074 			priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1075 				    &regs->iflag1);
1076 			dev->stats.rx_over_errors++;
1077 			dev->stats.rx_errors++;
1078 		}
1079 	}
1080 
1081 	reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1082 
1083 	/* transmission complete interrupt */
1084 	if (reg_iflag_tx & priv->tx_mask) {
1085 		u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1086 
1087 		handled = IRQ_HANDLED;
1088 		stats->tx_bytes +=
1089 			can_rx_offload_get_echo_skb_queue_timestamp(&priv->offload, 0,
1090 								    reg_ctrl << 16, NULL);
1091 		stats->tx_packets++;
1092 
1093 		/* after sending a RTR frame MB is in RX mode */
1094 		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1095 			    &priv->tx_mb->can_ctrl);
1096 		flexcan_write64(priv, priv->tx_mask, &regs->iflag1);
1097 		netif_wake_queue(dev);
1098 	}
1099 
1100 	reg_esr = priv->read(&regs->esr);
1101 
1102 	/* ACK all bus error, state change and wake IRQ sources */
1103 	if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1104 		handled = IRQ_HANDLED;
1105 		priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), &regs->esr);
1106 	}
1107 
1108 	/* state change interrupt or broken error state quirk fix is enabled */
1109 	if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1110 	    (priv->devtype_data.quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1111 					   FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1112 		flexcan_irq_state(dev, reg_esr);
1113 
1114 	/* bus error IRQ - handle if bus error reporting is activated */
1115 	if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1116 	    (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1117 		flexcan_irq_bus_err(dev, reg_esr);
1118 
1119 	/* availability of error interrupt among state transitions in case
1120 	 * bus error reporting is de-activated and
1121 	 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1122 	 *  +--------------------------------------------------------------+
1123 	 *  | +----------------------------------------------+ [stopped /  |
1124 	 *  | |                                              |  sleeping] -+
1125 	 *  +-+-> active <-> warning <-> passive -> bus off -+
1126 	 *        ___________^^^^^^^^^^^^_______________________________
1127 	 *        disabled(1)  enabled             disabled
1128 	 *
1129 	 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1130 	 */
1131 	if ((last_state != priv->can.state) &&
1132 	    (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1133 	    !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1134 		switch (priv->can.state) {
1135 		case CAN_STATE_ERROR_ACTIVE:
1136 			if (priv->devtype_data.quirks &
1137 			    FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1138 				flexcan_error_irq_enable(priv);
1139 			else
1140 				flexcan_error_irq_disable(priv);
1141 			break;
1142 
1143 		case CAN_STATE_ERROR_WARNING:
1144 			flexcan_error_irq_enable(priv);
1145 			break;
1146 
1147 		case CAN_STATE_ERROR_PASSIVE:
1148 		case CAN_STATE_BUS_OFF:
1149 			flexcan_error_irq_disable(priv);
1150 			break;
1151 
1152 		default:
1153 			break;
1154 		}
1155 	}
1156 
1157 	if (handled)
1158 		can_rx_offload_irq_finish(&priv->offload);
1159 
1160 	return handled;
1161 }
1162 
1163 static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1164 {
1165 	const struct flexcan_priv *priv = netdev_priv(dev);
1166 	const struct can_bittiming *bt = &priv->can.bittiming;
1167 	struct flexcan_regs __iomem *regs = priv->regs;
1168 	u32 reg;
1169 
1170 	reg = priv->read(&regs->ctrl);
1171 	reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1172 		 FLEXCAN_CTRL_RJW(0x3) |
1173 		 FLEXCAN_CTRL_PSEG1(0x7) |
1174 		 FLEXCAN_CTRL_PSEG2(0x7) |
1175 		 FLEXCAN_CTRL_PROPSEG(0x7));
1176 
1177 	reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1178 		FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1179 		FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1180 		FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1181 		FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1182 
1183 	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1184 	priv->write(reg, &regs->ctrl);
1185 
1186 	/* print chip status */
1187 	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1188 		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1189 }
1190 
1191 static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1192 {
1193 	struct flexcan_priv *priv = netdev_priv(dev);
1194 	struct can_bittiming *bt = &priv->can.bittiming;
1195 	struct can_bittiming *dbt = &priv->can.data_bittiming;
1196 	struct flexcan_regs __iomem *regs = priv->regs;
1197 	u32 reg_cbt, reg_fdctrl;
1198 
1199 	/* CBT */
1200 	/* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1201 	 * long. The can_calc_bittiming() tries to divide the tseg1
1202 	 * equally between phase_seg1 and prop_seg, which may not fit
1203 	 * in CBT register. Therefore, if phase_seg1 is more than
1204 	 * possible value, increase prop_seg and decrease phase_seg1.
1205 	 */
1206 	if (bt->phase_seg1 > 0x20) {
1207 		bt->prop_seg += (bt->phase_seg1 - 0x20);
1208 		bt->phase_seg1 = 0x20;
1209 	}
1210 
1211 	reg_cbt = FLEXCAN_CBT_BTF |
1212 		FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1213 		FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1214 		FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1215 		FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1216 		FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1217 
1218 	netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1219 	priv->write(reg_cbt, &regs->cbt);
1220 
1221 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1222 		u32 reg_fdcbt, reg_ctrl2;
1223 
1224 		if (bt->brp != dbt->brp)
1225 			netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1226 				    dbt->brp, bt->brp);
1227 
1228 		/* FDCBT */
1229 		/* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1230 		 * 5 bit long. The can_calc_bittiming tries to divide
1231 		 * the tseg1 equally between phase_seg1 and prop_seg,
1232 		 * which may not fit in FDCBT register. Therefore, if
1233 		 * phase_seg1 is more than possible value, increase
1234 		 * prop_seg and decrease phase_seg1
1235 		 */
1236 		if (dbt->phase_seg1 > 0x8) {
1237 			dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1238 			dbt->phase_seg1 = 0x8;
1239 		}
1240 
1241 		reg_fdcbt = priv->read(&regs->fdcbt);
1242 		reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1243 			       FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1244 			       FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1245 			       FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1246 			       FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1247 
1248 		reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1249 			FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1250 			FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1251 			FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1252 			FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1253 
1254 		netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1255 		priv->write(reg_fdcbt, &regs->fdcbt);
1256 
1257 		/* CTRL2 */
1258 		reg_ctrl2 = priv->read(&regs->ctrl2);
1259 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1260 		if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1261 			reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1262 
1263 		netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1264 		priv->write(reg_ctrl2, &regs->ctrl2);
1265 	}
1266 
1267 	/* FDCTRL */
1268 	reg_fdctrl = priv->read(&regs->fdctrl);
1269 	reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1270 			FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1271 
1272 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1273 		reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1274 
1275 		if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1276 			/* TDC must be disabled for Loop Back mode */
1277 			reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1278 		} else {
1279 			reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1280 				FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1281 					   ((dbt->phase_seg1 - 1) +
1282 					    dbt->prop_seg + 2) *
1283 					   ((dbt->brp - 1 ) + 1));
1284 		}
1285 	}
1286 
1287 	netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1288 	priv->write(reg_fdctrl, &regs->fdctrl);
1289 
1290 	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1291 		   __func__,
1292 		   priv->read(&regs->mcr), priv->read(&regs->ctrl),
1293 		   priv->read(&regs->ctrl2), priv->read(&regs->fdctrl),
1294 		   priv->read(&regs->cbt), priv->read(&regs->fdcbt));
1295 }
1296 
1297 static void flexcan_set_bittiming(struct net_device *dev)
1298 {
1299 	const struct flexcan_priv *priv = netdev_priv(dev);
1300 	struct flexcan_regs __iomem *regs = priv->regs;
1301 	u32 reg;
1302 
1303 	reg = priv->read(&regs->ctrl);
1304 	reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1305 		 FLEXCAN_CTRL_LOM);
1306 
1307 	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1308 		reg |= FLEXCAN_CTRL_LPB;
1309 	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1310 		reg |= FLEXCAN_CTRL_LOM;
1311 	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1312 		reg |= FLEXCAN_CTRL_SMP;
1313 
1314 	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1315 	priv->write(reg, &regs->ctrl);
1316 
1317 	if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1318 		return flexcan_set_bittiming_cbt(dev);
1319 	else
1320 		return flexcan_set_bittiming_ctrl(dev);
1321 }
1322 
1323 static void flexcan_ram_init(struct net_device *dev)
1324 {
1325 	struct flexcan_priv *priv = netdev_priv(dev);
1326 	struct flexcan_regs __iomem *regs = priv->regs;
1327 	u32 reg_ctrl2;
1328 
1329 	/* 11.8.3.13 Detection and correction of memory errors:
1330 	 * CTRL2[WRMFRZ] grants write access to all memory positions
1331 	 * that require initialization, ranging from 0x080 to 0xADF
1332 	 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1333 	 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1334 	 * need to be initialized as well. MCR[RFEN] must not be set
1335 	 * during memory initialization.
1336 	 */
1337 	reg_ctrl2 = priv->read(&regs->ctrl2);
1338 	reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1339 	priv->write(reg_ctrl2, &regs->ctrl2);
1340 
1341 	memset_io(&regs->init, 0, sizeof(regs->init));
1342 
1343 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1344 		memset_io(&regs->init_fd, 0, sizeof(regs->init_fd));
1345 
1346 	reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1347 	priv->write(reg_ctrl2, &regs->ctrl2);
1348 }
1349 
1350 static int flexcan_rx_offload_setup(struct net_device *dev)
1351 {
1352 	struct flexcan_priv *priv = netdev_priv(dev);
1353 	int err;
1354 
1355 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1356 		priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1357 	else
1358 		priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1359 
1360 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_MB_16)
1361 		priv->mb_count = 16;
1362 	else
1363 		priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1364 				 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1365 
1366 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1367 		priv->tx_mb_reserved =
1368 			flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_MAILBOX);
1369 	else
1370 		priv->tx_mb_reserved =
1371 			flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_FIFO);
1372 	priv->tx_mb_idx = priv->mb_count - 1;
1373 	priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1374 	priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1375 
1376 	priv->offload.mailbox_read = flexcan_mailbox_read;
1377 
1378 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1379 		priv->offload.mb_first = FLEXCAN_RX_MB_RX_MAILBOX_FIRST;
1380 		priv->offload.mb_last = priv->mb_count - 2;
1381 
1382 		priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1383 					    priv->offload.mb_first);
1384 		err = can_rx_offload_add_timestamp(dev, &priv->offload);
1385 	} else {
1386 		priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1387 			FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1388 		err = can_rx_offload_add_fifo(dev, &priv->offload,
1389 					      FLEXCAN_NAPI_WEIGHT);
1390 	}
1391 
1392 	return err;
1393 }
1394 
1395 static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1396 {
1397 	const struct flexcan_priv *priv = netdev_priv(dev);
1398 	struct flexcan_regs __iomem *regs = priv->regs;
1399 	u64 reg_imask;
1400 
1401 	disable_irq(dev->irq);
1402 	priv->write(priv->reg_ctrl_default, &regs->ctrl);
1403 	reg_imask = priv->rx_mask | priv->tx_mask;
1404 	priv->write(upper_32_bits(reg_imask), &regs->imask2);
1405 	priv->write(lower_32_bits(reg_imask), &regs->imask1);
1406 	enable_irq(dev->irq);
1407 }
1408 
1409 static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1410 {
1411 	const struct flexcan_priv *priv = netdev_priv(dev);
1412 	struct flexcan_regs __iomem *regs = priv->regs;
1413 
1414 	priv->write(0, &regs->imask2);
1415 	priv->write(0, &regs->imask1);
1416 	priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1417 		    &regs->ctrl);
1418 }
1419 
1420 /* flexcan_chip_start
1421  *
1422  * this functions is entered with clocks enabled
1423  *
1424  */
1425 static int flexcan_chip_start(struct net_device *dev)
1426 {
1427 	struct flexcan_priv *priv = netdev_priv(dev);
1428 	struct flexcan_regs __iomem *regs = priv->regs;
1429 	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1430 	int err, i;
1431 	struct flexcan_mb __iomem *mb;
1432 
1433 	/* enable module */
1434 	err = flexcan_chip_enable(priv);
1435 	if (err)
1436 		return err;
1437 
1438 	/* soft reset */
1439 	err = flexcan_chip_softreset(priv);
1440 	if (err)
1441 		goto out_chip_disable;
1442 
1443 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1444 		flexcan_ram_init(dev);
1445 
1446 	flexcan_set_bittiming(dev);
1447 
1448 	/* set freeze, halt */
1449 	err = flexcan_chip_freeze(priv);
1450 	if (err)
1451 		goto out_chip_disable;
1452 
1453 	/* MCR
1454 	 *
1455 	 * only supervisor access
1456 	 * enable warning int
1457 	 * enable individual RX masking
1458 	 * choose format C
1459 	 * set max mailbox number
1460 	 */
1461 	reg_mcr = priv->read(&regs->mcr);
1462 	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1463 	reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
1464 		FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1465 
1466 	/* MCR
1467 	 *
1468 	 * FIFO:
1469 	 * - disable for mailbox mode
1470 	 * - enable for FIFO mode
1471 	 */
1472 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)
1473 		reg_mcr &= ~FLEXCAN_MCR_FEN;
1474 	else
1475 		reg_mcr |= FLEXCAN_MCR_FEN;
1476 
1477 	/* MCR
1478 	 *
1479 	 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1480 	 *       asserted because this will impede the self reception
1481 	 *       of a transmitted message. This is not documented in
1482 	 *       earlier versions of flexcan block guide.
1483 	 *
1484 	 * Self Reception:
1485 	 * - enable Self Reception for loopback mode
1486 	 *   (by clearing "Self Reception Disable" bit)
1487 	 * - disable for normal operation
1488 	 */
1489 	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1490 		reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1491 	else
1492 		reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1493 
1494 	/* MCR - CAN-FD */
1495 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1496 		reg_mcr |= FLEXCAN_MCR_FDEN;
1497 	else
1498 		reg_mcr &= ~FLEXCAN_MCR_FDEN;
1499 
1500 	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1501 	priv->write(reg_mcr, &regs->mcr);
1502 
1503 	/* CTRL
1504 	 *
1505 	 * disable timer sync feature
1506 	 *
1507 	 * disable auto busoff recovery
1508 	 * transmit lowest buffer first
1509 	 *
1510 	 * enable tx and rx warning interrupt
1511 	 * enable bus off interrupt
1512 	 * (== FLEXCAN_CTRL_ERR_STATE)
1513 	 */
1514 	reg_ctrl = priv->read(&regs->ctrl);
1515 	reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1516 	reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1517 		FLEXCAN_CTRL_ERR_STATE;
1518 
1519 	/* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1520 	 * on most Flexcan cores, too. Otherwise we don't get
1521 	 * any error warning or passive interrupts.
1522 	 */
1523 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1524 	    priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1525 		reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1526 	else
1527 		reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1528 
1529 	/* save for later use */
1530 	priv->reg_ctrl_default = reg_ctrl;
1531 	/* leave interrupts disabled for now */
1532 	reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1533 	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1534 	priv->write(reg_ctrl, &regs->ctrl);
1535 
1536 	if ((priv->devtype_data.quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1537 		reg_ctrl2 = priv->read(&regs->ctrl2);
1538 		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1539 		priv->write(reg_ctrl2, &regs->ctrl2);
1540 	}
1541 
1542 	if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1543 		u32 reg_fdctrl;
1544 
1545 		reg_fdctrl = priv->read(&regs->fdctrl);
1546 		reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1547 				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1548 
1549 		if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1550 			reg_fdctrl |=
1551 				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1552 					   FLEXCAN_FDCTRL_MBDSR_64) |
1553 				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1554 					   FLEXCAN_FDCTRL_MBDSR_64);
1555 		} else {
1556 			reg_fdctrl |=
1557 				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1558 					   FLEXCAN_FDCTRL_MBDSR_8) |
1559 				FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1560 					   FLEXCAN_FDCTRL_MBDSR_8);
1561 		}
1562 
1563 		netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1564 			   __func__, reg_fdctrl);
1565 		priv->write(reg_fdctrl, &regs->fdctrl);
1566 	}
1567 
1568 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {
1569 		for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1570 			mb = flexcan_get_mb(priv, i);
1571 			priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1572 				    &mb->can_ctrl);
1573 		}
1574 	} else {
1575 		/* clear and invalidate unused mailboxes first */
1576 		for (i = FLEXCAN_TX_MB_RESERVED_RX_FIFO; i < priv->mb_count; i++) {
1577 			mb = flexcan_get_mb(priv, i);
1578 			priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1579 				    &mb->can_ctrl);
1580 		}
1581 	}
1582 
1583 	/* Errata ERR005829: mark first TX mailbox as INACTIVE */
1584 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1585 		    &priv->tx_mb_reserved->can_ctrl);
1586 
1587 	/* mark TX mailbox as INACTIVE */
1588 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1589 		    &priv->tx_mb->can_ctrl);
1590 
1591 	/* acceptance mask/acceptance code (accept everything) */
1592 	priv->write(0x0, &regs->rxgmask);
1593 	priv->write(0x0, &regs->rx14mask);
1594 	priv->write(0x0, &regs->rx15mask);
1595 
1596 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1597 		priv->write(0x0, &regs->rxfgmask);
1598 
1599 	/* clear acceptance filters */
1600 	for (i = 0; i < priv->mb_count; i++)
1601 		priv->write(0, &regs->rximr[i]);
1602 
1603 	/* On Vybrid, disable non-correctable errors interrupt and
1604 	 * freeze mode. It still can correct the correctable errors
1605 	 * when HW supports ECC.
1606 	 *
1607 	 * This also works around errata e5295 which generates false
1608 	 * positive memory errors and put the device in freeze mode.
1609 	 */
1610 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1611 		/* Follow the protocol as described in "Detection
1612 		 * and Correction of Memory Errors" to write to
1613 		 * MECR register (step 1 - 5)
1614 		 *
1615 		 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1616 		 * 2. set CTRL2[ECRWRE]
1617 		 */
1618 		reg_ctrl2 = priv->read(&regs->ctrl2);
1619 		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1620 		priv->write(reg_ctrl2, &regs->ctrl2);
1621 
1622 		/* 3. clear MECR[ECRWRDIS] */
1623 		reg_mecr = priv->read(&regs->mecr);
1624 		reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1625 		priv->write(reg_mecr, &regs->mecr);
1626 
1627 		/* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1628 		reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1629 			      FLEXCAN_MECR_FANCEI_MSK);
1630 		priv->write(reg_mecr, &regs->mecr);
1631 
1632 		/* 5. after configuration done, lock MECR by either
1633 		 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1634 		 */
1635 		reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1636 		priv->write(reg_mecr, &regs->mecr);
1637 
1638 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1639 		priv->write(reg_ctrl2, &regs->ctrl2);
1640 	}
1641 
1642 	/* synchronize with the can bus */
1643 	err = flexcan_chip_unfreeze(priv);
1644 	if (err)
1645 		goto out_chip_disable;
1646 
1647 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1648 
1649 	/* print chip status */
1650 	netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1651 		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1652 
1653 	return 0;
1654 
1655  out_chip_disable:
1656 	flexcan_chip_disable(priv);
1657 	return err;
1658 }
1659 
1660 /* __flexcan_chip_stop
1661  *
1662  * this function is entered with clocks enabled
1663  */
1664 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1665 {
1666 	struct flexcan_priv *priv = netdev_priv(dev);
1667 	int err;
1668 
1669 	/* freeze + disable module */
1670 	err = flexcan_chip_freeze(priv);
1671 	if (err && !disable_on_error)
1672 		return err;
1673 	err = flexcan_chip_disable(priv);
1674 	if (err && !disable_on_error)
1675 		goto out_chip_unfreeze;
1676 
1677 	priv->can.state = CAN_STATE_STOPPED;
1678 
1679 	return 0;
1680 
1681  out_chip_unfreeze:
1682 	flexcan_chip_unfreeze(priv);
1683 
1684 	return err;
1685 }
1686 
1687 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1688 {
1689 	return __flexcan_chip_stop(dev, true);
1690 }
1691 
1692 static inline int flexcan_chip_stop(struct net_device *dev)
1693 {
1694 	return __flexcan_chip_stop(dev, false);
1695 }
1696 
1697 static int flexcan_open(struct net_device *dev)
1698 {
1699 	struct flexcan_priv *priv = netdev_priv(dev);
1700 	int err;
1701 
1702 	if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1703 	    (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1704 		netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1705 		return -EINVAL;
1706 	}
1707 
1708 	err = pm_runtime_resume_and_get(priv->dev);
1709 	if (err < 0)
1710 		return err;
1711 
1712 	err = open_candev(dev);
1713 	if (err)
1714 		goto out_runtime_put;
1715 
1716 	err = flexcan_transceiver_enable(priv);
1717 	if (err)
1718 		goto out_close;
1719 
1720 	err = flexcan_rx_offload_setup(dev);
1721 	if (err)
1722 		goto out_transceiver_disable;
1723 
1724 	err = flexcan_chip_start(dev);
1725 	if (err)
1726 		goto out_can_rx_offload_del;
1727 
1728 	can_rx_offload_enable(&priv->offload);
1729 
1730 	err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1731 	if (err)
1732 		goto out_can_rx_offload_disable;
1733 
1734 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1735 		err = request_irq(priv->irq_boff,
1736 				  flexcan_irq, IRQF_SHARED, dev->name, dev);
1737 		if (err)
1738 			goto out_free_irq;
1739 
1740 		err = request_irq(priv->irq_err,
1741 				  flexcan_irq, IRQF_SHARED, dev->name, dev);
1742 		if (err)
1743 			goto out_free_irq_boff;
1744 	}
1745 
1746 	flexcan_chip_interrupts_enable(dev);
1747 
1748 	netif_start_queue(dev);
1749 
1750 	return 0;
1751 
1752  out_free_irq_boff:
1753 	free_irq(priv->irq_boff, dev);
1754  out_free_irq:
1755 	free_irq(dev->irq, dev);
1756  out_can_rx_offload_disable:
1757 	can_rx_offload_disable(&priv->offload);
1758 	flexcan_chip_stop(dev);
1759  out_can_rx_offload_del:
1760 	can_rx_offload_del(&priv->offload);
1761  out_transceiver_disable:
1762 	flexcan_transceiver_disable(priv);
1763  out_close:
1764 	close_candev(dev);
1765  out_runtime_put:
1766 	pm_runtime_put(priv->dev);
1767 
1768 	return err;
1769 }
1770 
1771 static int flexcan_close(struct net_device *dev)
1772 {
1773 	struct flexcan_priv *priv = netdev_priv(dev);
1774 
1775 	netif_stop_queue(dev);
1776 	flexcan_chip_interrupts_disable(dev);
1777 
1778 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1779 		free_irq(priv->irq_err, dev);
1780 		free_irq(priv->irq_boff, dev);
1781 	}
1782 
1783 	free_irq(dev->irq, dev);
1784 	can_rx_offload_disable(&priv->offload);
1785 	flexcan_chip_stop_disable_on_error(dev);
1786 
1787 	can_rx_offload_del(&priv->offload);
1788 	flexcan_transceiver_disable(priv);
1789 	close_candev(dev);
1790 
1791 	pm_runtime_put(priv->dev);
1792 
1793 	return 0;
1794 }
1795 
1796 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1797 {
1798 	int err;
1799 
1800 	switch (mode) {
1801 	case CAN_MODE_START:
1802 		err = flexcan_chip_start(dev);
1803 		if (err)
1804 			return err;
1805 
1806 		flexcan_chip_interrupts_enable(dev);
1807 
1808 		netif_wake_queue(dev);
1809 		break;
1810 
1811 	default:
1812 		return -EOPNOTSUPP;
1813 	}
1814 
1815 	return 0;
1816 }
1817 
1818 static const struct net_device_ops flexcan_netdev_ops = {
1819 	.ndo_open	= flexcan_open,
1820 	.ndo_stop	= flexcan_close,
1821 	.ndo_start_xmit	= flexcan_start_xmit,
1822 	.ndo_change_mtu = can_change_mtu,
1823 };
1824 
1825 static int register_flexcandev(struct net_device *dev)
1826 {
1827 	struct flexcan_priv *priv = netdev_priv(dev);
1828 	struct flexcan_regs __iomem *regs = priv->regs;
1829 	u32 reg, err;
1830 
1831 	err = flexcan_clks_enable(priv);
1832 	if (err)
1833 		return err;
1834 
1835 	/* select "bus clock", chip must be disabled */
1836 	err = flexcan_chip_disable(priv);
1837 	if (err)
1838 		goto out_clks_disable;
1839 
1840 	reg = priv->read(&regs->ctrl);
1841 	if (priv->clk_src)
1842 		reg |= FLEXCAN_CTRL_CLK_SRC;
1843 	else
1844 		reg &= ~FLEXCAN_CTRL_CLK_SRC;
1845 	priv->write(reg, &regs->ctrl);
1846 
1847 	err = flexcan_chip_enable(priv);
1848 	if (err)
1849 		goto out_chip_disable;
1850 
1851 	/* set freeze, halt */
1852 	err = flexcan_chip_freeze(priv);
1853 	if (err)
1854 		goto out_chip_disable;
1855 
1856 	/* activate FIFO, restrict register access */
1857 	reg = priv->read(&regs->mcr);
1858 	reg |=  FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1859 	priv->write(reg, &regs->mcr);
1860 
1861 	/* Currently we only support newer versions of this core
1862 	 * featuring a RX hardware FIFO (although this driver doesn't
1863 	 * make use of it on some cores). Older cores, found on some
1864 	 * Coldfire derivates are not tested.
1865 	 */
1866 	reg = priv->read(&regs->mcr);
1867 	if (!(reg & FLEXCAN_MCR_FEN)) {
1868 		netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1869 		err = -ENODEV;
1870 		goto out_chip_disable;
1871 	}
1872 
1873 	err = register_candev(dev);
1874 	if (err)
1875 		goto out_chip_disable;
1876 
1877 	/* Disable core and let pm_runtime_put() disable the clocks.
1878 	 * If CONFIG_PM is not enabled, the clocks will stay powered.
1879 	 */
1880 	flexcan_chip_disable(priv);
1881 	pm_runtime_put(priv->dev);
1882 
1883 	return 0;
1884 
1885  out_chip_disable:
1886 	flexcan_chip_disable(priv);
1887  out_clks_disable:
1888 	flexcan_clks_disable(priv);
1889 	return err;
1890 }
1891 
1892 static void unregister_flexcandev(struct net_device *dev)
1893 {
1894 	unregister_candev(dev);
1895 }
1896 
1897 static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1898 {
1899 	struct net_device *dev = platform_get_drvdata(pdev);
1900 	struct device_node *np = pdev->dev.of_node;
1901 	struct device_node *gpr_np;
1902 	struct flexcan_priv *priv;
1903 	phandle phandle;
1904 	u32 out_val[3];
1905 	int ret;
1906 
1907 	if (!np)
1908 		return -EINVAL;
1909 
1910 	/* stop mode property format is:
1911 	 * <&gpr req_gpr req_bit>.
1912 	 */
1913 	ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1914 					 ARRAY_SIZE(out_val));
1915 	if (ret) {
1916 		dev_dbg(&pdev->dev, "no stop-mode property\n");
1917 		return ret;
1918 	}
1919 	phandle = *out_val;
1920 
1921 	gpr_np = of_find_node_by_phandle(phandle);
1922 	if (!gpr_np) {
1923 		dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1924 		return -ENODEV;
1925 	}
1926 
1927 	priv = netdev_priv(dev);
1928 	priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1929 	if (IS_ERR(priv->stm.gpr)) {
1930 		dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1931 		ret = PTR_ERR(priv->stm.gpr);
1932 		goto out_put_node;
1933 	}
1934 
1935 	priv->stm.req_gpr = out_val[1];
1936 	priv->stm.req_bit = out_val[2];
1937 
1938 	dev_dbg(&pdev->dev,
1939 		"gpr %s req_gpr=0x02%x req_bit=%u\n",
1940 		gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1941 
1942 	return 0;
1943 
1944 out_put_node:
1945 	of_node_put(gpr_np);
1946 	return ret;
1947 }
1948 
1949 static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
1950 {
1951 	struct net_device *dev = platform_get_drvdata(pdev);
1952 	struct flexcan_priv *priv;
1953 	u8 scu_idx;
1954 	int ret;
1955 
1956 	ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
1957 	if (ret < 0) {
1958 		dev_dbg(&pdev->dev, "failed to get scu index\n");
1959 		return ret;
1960 	}
1961 
1962 	priv = netdev_priv(dev);
1963 	priv->scu_idx = scu_idx;
1964 
1965 	/* this function could be deferred probe, return -EPROBE_DEFER */
1966 	return imx_scu_get_handle(&priv->sc_ipc_handle);
1967 }
1968 
1969 /* flexcan_setup_stop_mode - Setup stop mode for wakeup
1970  *
1971  * Return: = 0 setup stop mode successfully or doesn't support this feature
1972  *         < 0 fail to setup stop mode (could be deferred probe)
1973  */
1974 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1975 {
1976 	struct net_device *dev = platform_get_drvdata(pdev);
1977 	struct flexcan_priv *priv;
1978 	int ret;
1979 
1980 	priv = netdev_priv(dev);
1981 
1982 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
1983 		ret = flexcan_setup_stop_mode_scfw(pdev);
1984 	else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
1985 		ret = flexcan_setup_stop_mode_gpr(pdev);
1986 	else
1987 		/* return 0 directly if doesn't support stop mode feature */
1988 		return 0;
1989 
1990 	/* If ret is -EINVAL, this means SoC claim to support stop mode, but
1991 	 * dts file lack the stop mode property definition. For this case,
1992 	 * directly return 0, this will skip the wakeup capable setting and
1993 	 * will not block the driver probe.
1994 	 */
1995 	if (ret == -EINVAL)
1996 		return 0;
1997 	else if (ret)
1998 		return ret;
1999 
2000 	device_set_wakeup_capable(&pdev->dev, true);
2001 
2002 	if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
2003 		device_set_wakeup_enable(&pdev->dev, true);
2004 
2005 	return 0;
2006 }
2007 
2008 static const struct of_device_id flexcan_of_match[] = {
2009 	{ .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2010 	{ .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2011 	{ .compatible = "fsl,imx93-flexcan", .data = &fsl_imx93_devtype_data, },
2012 	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2013 	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2014 	{ .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2015 	{ .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2016 	{ .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2017 	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2018 	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2019 	{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2020 	{ .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2021 	{ /* sentinel */ },
2022 };
2023 MODULE_DEVICE_TABLE(of, flexcan_of_match);
2024 
2025 static const struct platform_device_id flexcan_id_table[] = {
2026 	{
2027 		.name = "flexcan-mcf5441x",
2028 		.driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data,
2029 	}, {
2030 		/* sentinel */
2031 	},
2032 };
2033 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
2034 
2035 static int flexcan_probe(struct platform_device *pdev)
2036 {
2037 	const struct of_device_id *of_id;
2038 	const struct flexcan_devtype_data *devtype_data;
2039 	struct net_device *dev;
2040 	struct flexcan_priv *priv;
2041 	struct regulator *reg_xceiver;
2042 	struct clk *clk_ipg = NULL, *clk_per = NULL;
2043 	struct flexcan_regs __iomem *regs;
2044 	struct flexcan_platform_data *pdata;
2045 	int err, irq;
2046 	u8 clk_src = 1;
2047 	u32 clock_freq = 0;
2048 
2049 	reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2050 	if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2051 		return -EPROBE_DEFER;
2052 	else if (PTR_ERR(reg_xceiver) == -ENODEV)
2053 		reg_xceiver = NULL;
2054 	else if (IS_ERR(reg_xceiver))
2055 		return PTR_ERR(reg_xceiver);
2056 
2057 	if (pdev->dev.of_node) {
2058 		of_property_read_u32(pdev->dev.of_node,
2059 				     "clock-frequency", &clock_freq);
2060 		of_property_read_u8(pdev->dev.of_node,
2061 				    "fsl,clk-source", &clk_src);
2062 	} else {
2063 		pdata = dev_get_platdata(&pdev->dev);
2064 		if (pdata) {
2065 			clock_freq = pdata->clock_frequency;
2066 			clk_src = pdata->clk_src;
2067 		}
2068 	}
2069 
2070 	if (!clock_freq) {
2071 		clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2072 		if (IS_ERR(clk_ipg)) {
2073 			dev_err(&pdev->dev, "no ipg clock defined\n");
2074 			return PTR_ERR(clk_ipg);
2075 		}
2076 
2077 		clk_per = devm_clk_get(&pdev->dev, "per");
2078 		if (IS_ERR(clk_per)) {
2079 			dev_err(&pdev->dev, "no per clock defined\n");
2080 			return PTR_ERR(clk_per);
2081 		}
2082 		clock_freq = clk_get_rate(clk_per);
2083 	}
2084 
2085 	irq = platform_get_irq(pdev, 0);
2086 	if (irq < 0)
2087 		return irq;
2088 
2089 	regs = devm_platform_ioremap_resource(pdev, 0);
2090 	if (IS_ERR(regs))
2091 		return PTR_ERR(regs);
2092 
2093 	of_id = of_match_device(flexcan_of_match, &pdev->dev);
2094 	if (of_id)
2095 		devtype_data = of_id->data;
2096 	else if (platform_get_device_id(pdev)->driver_data)
2097 		devtype_data = (struct flexcan_devtype_data *)
2098 			platform_get_device_id(pdev)->driver_data;
2099 	else
2100 		return -ENODEV;
2101 
2102 	if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2103 	    !((devtype_data->quirks &
2104 	       (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2105 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
2106 		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR |
2107 		FLEXCAN_QUIRK_SUPPORT_RX_FIFO)) ==
2108 	      (FLEXCAN_QUIRK_USE_RX_MAILBOX |
2109 	       FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
2110 	       FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR))) {
2111 		dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n");
2112 		return -EINVAL;
2113 	}
2114 
2115 	if ((devtype_data->quirks &
2116 	     (FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
2117 	      FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR)) ==
2118 	    FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR) {
2119 		dev_err(&pdev->dev,
2120 			"Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n",
2121 			devtype_data->quirks);
2122 		return -EINVAL;
2123 	}
2124 
2125 	dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2126 	if (!dev)
2127 		return -ENOMEM;
2128 
2129 	platform_set_drvdata(pdev, dev);
2130 	SET_NETDEV_DEV(dev, &pdev->dev);
2131 
2132 	dev->netdev_ops = &flexcan_netdev_ops;
2133 	dev->ethtool_ops = &flexcan_ethtool_ops;
2134 	dev->irq = irq;
2135 	dev->flags |= IFF_ECHO;
2136 
2137 	priv = netdev_priv(dev);
2138 	priv->devtype_data = *devtype_data;
2139 
2140 	if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2141 	    priv->devtype_data.quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2142 		priv->read = flexcan_read_be;
2143 		priv->write = flexcan_write_be;
2144 	} else {
2145 		priv->read = flexcan_read_le;
2146 		priv->write = flexcan_write_le;
2147 	}
2148 
2149 	priv->dev = &pdev->dev;
2150 	priv->can.clock.freq = clock_freq;
2151 	priv->can.do_set_mode = flexcan_set_mode;
2152 	priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2153 	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2154 		CAN_CTRLMODE_LISTENONLY	| CAN_CTRLMODE_3_SAMPLES |
2155 		CAN_CTRLMODE_BERR_REPORTING;
2156 	priv->regs = regs;
2157 	priv->clk_ipg = clk_ipg;
2158 	priv->clk_per = clk_per;
2159 	priv->clk_src = clk_src;
2160 	priv->reg_xceiver = reg_xceiver;
2161 
2162 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
2163 		priv->irq_boff = platform_get_irq(pdev, 1);
2164 		if (priv->irq_boff < 0) {
2165 			err = priv->irq_boff;
2166 			goto failed_platform_get_irq;
2167 		}
2168 		priv->irq_err = platform_get_irq(pdev, 2);
2169 		if (priv->irq_err < 0) {
2170 			err = priv->irq_err;
2171 			goto failed_platform_get_irq;
2172 		}
2173 	}
2174 
2175 	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2176 		priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2177 			CAN_CTRLMODE_FD_NON_ISO;
2178 		priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2179 		priv->can.data_bittiming_const =
2180 			&flexcan_fd_data_bittiming_const;
2181 	} else {
2182 		priv->can.bittiming_const = &flexcan_bittiming_const;
2183 	}
2184 
2185 	pm_runtime_get_noresume(&pdev->dev);
2186 	pm_runtime_set_active(&pdev->dev);
2187 	pm_runtime_enable(&pdev->dev);
2188 
2189 	err = register_flexcandev(dev);
2190 	if (err) {
2191 		dev_err(&pdev->dev, "registering netdev failed\n");
2192 		goto failed_register;
2193 	}
2194 
2195 	err = flexcan_setup_stop_mode(pdev);
2196 	if (err < 0) {
2197 		dev_err_probe(&pdev->dev, err, "setup stop mode failed\n");
2198 		goto failed_setup_stop_mode;
2199 	}
2200 
2201 	of_can_transceiver(dev);
2202 
2203 	return 0;
2204 
2205  failed_setup_stop_mode:
2206 	unregister_flexcandev(dev);
2207  failed_register:
2208 	pm_runtime_put_noidle(&pdev->dev);
2209 	pm_runtime_disable(&pdev->dev);
2210  failed_platform_get_irq:
2211 	free_candev(dev);
2212 	return err;
2213 }
2214 
2215 static void flexcan_remove(struct platform_device *pdev)
2216 {
2217 	struct net_device *dev = platform_get_drvdata(pdev);
2218 
2219 	device_set_wakeup_enable(&pdev->dev, false);
2220 	device_set_wakeup_capable(&pdev->dev, false);
2221 	unregister_flexcandev(dev);
2222 	pm_runtime_disable(&pdev->dev);
2223 	free_candev(dev);
2224 }
2225 
2226 static int __maybe_unused flexcan_suspend(struct device *device)
2227 {
2228 	struct net_device *dev = dev_get_drvdata(device);
2229 	struct flexcan_priv *priv = netdev_priv(dev);
2230 	int err;
2231 
2232 	if (netif_running(dev)) {
2233 		/* if wakeup is enabled, enter stop mode
2234 		 * else enter disabled mode.
2235 		 */
2236 		if (device_may_wakeup(device)) {
2237 			enable_irq_wake(dev->irq);
2238 			err = flexcan_enter_stop_mode(priv);
2239 			if (err)
2240 				return err;
2241 		} else {
2242 			err = flexcan_chip_stop(dev);
2243 			if (err)
2244 				return err;
2245 
2246 			flexcan_chip_interrupts_disable(dev);
2247 
2248 			err = pinctrl_pm_select_sleep_state(device);
2249 			if (err)
2250 				return err;
2251 		}
2252 		netif_stop_queue(dev);
2253 		netif_device_detach(dev);
2254 	}
2255 	priv->can.state = CAN_STATE_SLEEPING;
2256 
2257 	return 0;
2258 }
2259 
2260 static int __maybe_unused flexcan_resume(struct device *device)
2261 {
2262 	struct net_device *dev = dev_get_drvdata(device);
2263 	struct flexcan_priv *priv = netdev_priv(dev);
2264 	int err;
2265 
2266 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
2267 	if (netif_running(dev)) {
2268 		netif_device_attach(dev);
2269 		netif_start_queue(dev);
2270 		if (device_may_wakeup(device)) {
2271 			disable_irq_wake(dev->irq);
2272 			err = flexcan_exit_stop_mode(priv);
2273 			if (err)
2274 				return err;
2275 		} else {
2276 			err = pinctrl_pm_select_default_state(device);
2277 			if (err)
2278 				return err;
2279 
2280 			err = flexcan_chip_start(dev);
2281 			if (err)
2282 				return err;
2283 
2284 			flexcan_chip_interrupts_enable(dev);
2285 		}
2286 	}
2287 
2288 	return 0;
2289 }
2290 
2291 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2292 {
2293 	struct net_device *dev = dev_get_drvdata(device);
2294 	struct flexcan_priv *priv = netdev_priv(dev);
2295 
2296 	flexcan_clks_disable(priv);
2297 
2298 	return 0;
2299 }
2300 
2301 static int __maybe_unused flexcan_runtime_resume(struct device *device)
2302 {
2303 	struct net_device *dev = dev_get_drvdata(device);
2304 	struct flexcan_priv *priv = netdev_priv(dev);
2305 
2306 	return flexcan_clks_enable(priv);
2307 }
2308 
2309 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2310 {
2311 	struct net_device *dev = dev_get_drvdata(device);
2312 	struct flexcan_priv *priv = netdev_priv(dev);
2313 
2314 	if (netif_running(dev)) {
2315 		int err;
2316 
2317 		if (device_may_wakeup(device))
2318 			flexcan_enable_wakeup_irq(priv, true);
2319 
2320 		err = pm_runtime_force_suspend(device);
2321 		if (err)
2322 			return err;
2323 	}
2324 
2325 	return 0;
2326 }
2327 
2328 static int __maybe_unused flexcan_noirq_resume(struct device *device)
2329 {
2330 	struct net_device *dev = dev_get_drvdata(device);
2331 	struct flexcan_priv *priv = netdev_priv(dev);
2332 
2333 	if (netif_running(dev)) {
2334 		int err;
2335 
2336 		err = pm_runtime_force_resume(device);
2337 		if (err)
2338 			return err;
2339 
2340 		if (device_may_wakeup(device))
2341 			flexcan_enable_wakeup_irq(priv, false);
2342 	}
2343 
2344 	return 0;
2345 }
2346 
2347 static const struct dev_pm_ops flexcan_pm_ops = {
2348 	SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2349 	SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2350 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2351 };
2352 
2353 static struct platform_driver flexcan_driver = {
2354 	.driver = {
2355 		.name = DRV_NAME,
2356 		.pm = &flexcan_pm_ops,
2357 		.of_match_table = flexcan_of_match,
2358 	},
2359 	.probe = flexcan_probe,
2360 	.remove_new = flexcan_remove,
2361 	.id_table = flexcan_id_table,
2362 };
2363 
2364 module_platform_driver(flexcan_driver);
2365 
2366 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2367 	      "Marc Kleine-Budde <kernel@pengutronix.de>");
2368 MODULE_LICENSE("GPL v2");
2369 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
2370