1 /* 2 * Platform CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 13 * Bosch C_CAN user manual can be obtained from: 14 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 15 * users_manual_c_can.pdf 16 * 17 * This file is licensed under the terms of the GNU General Public 18 * License version 2. This program is licensed "as is" without any 19 * warranty of any kind, whether express or implied. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/delay.h> 26 #include <linux/netdevice.h> 27 #include <linux/if_arp.h> 28 #include <linux/if_ether.h> 29 #include <linux/list.h> 30 #include <linux/io.h> 31 #include <linux/platform_device.h> 32 #include <linux/clk.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/regmap.h> 37 38 #include <linux/can/dev.h> 39 40 #include "c_can.h" 41 42 #define DCAN_RAM_INIT_BIT (1 << 3) 43 static DEFINE_SPINLOCK(raminit_lock); 44 /* 45 * 16-bit c_can registers can be arranged differently in the memory 46 * architecture of different implementations. For example: 16-bit 47 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc. 48 * Handle the same by providing a common read/write interface. 49 */ 50 static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv, 51 enum reg index) 52 { 53 return readw(priv->base + priv->regs[index]); 54 } 55 56 static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv, 57 enum reg index, u16 val) 58 { 59 writew(val, priv->base + priv->regs[index]); 60 } 61 62 static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv, 63 enum reg index) 64 { 65 return readw(priv->base + 2 * priv->regs[index]); 66 } 67 68 static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, 69 enum reg index, u16 val) 70 { 71 writew(val, priv->base + 2 * priv->regs[index]); 72 } 73 74 static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv, 75 u32 mask, u32 val) 76 { 77 const struct c_can_raminit *raminit = &priv->raminit_sys; 78 int timeout = 0; 79 u32 ctrl = 0; 80 81 /* We look only at the bits of our instance. */ 82 val &= mask; 83 do { 84 udelay(1); 85 timeout++; 86 87 regmap_read(raminit->syscon, raminit->reg, &ctrl); 88 if (timeout == 1000) { 89 dev_err(&priv->dev->dev, "%s: time out\n", __func__); 90 break; 91 } 92 } while ((ctrl & mask) != val); 93 } 94 95 static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable) 96 { 97 const struct c_can_raminit *raminit = &priv->raminit_sys; 98 u32 ctrl = 0; 99 u32 mask; 100 101 spin_lock(&raminit_lock); 102 103 mask = 1 << raminit->bits.start | 1 << raminit->bits.done; 104 regmap_read(raminit->syscon, raminit->reg, &ctrl); 105 106 /* We clear the done and start bit first. The start bit is 107 * looking at the 0 -> transition, but is not self clearing; 108 * And we clear the init done bit as well. 109 * NOTE: DONE must be written with 1 to clear it. 110 */ 111 ctrl &= ~(1 << raminit->bits.start); 112 ctrl |= 1 << raminit->bits.done; 113 regmap_write(raminit->syscon, raminit->reg, ctrl); 114 115 ctrl &= ~(1 << raminit->bits.done); 116 c_can_hw_raminit_wait_syscon(priv, mask, ctrl); 117 118 if (enable) { 119 /* Set start bit and wait for the done bit. */ 120 ctrl |= 1 << raminit->bits.start; 121 regmap_write(raminit->syscon, raminit->reg, ctrl); 122 123 /* clear START bit if start pulse is needed */ 124 if (raminit->needs_pulse) { 125 ctrl &= ~(1 << raminit->bits.start); 126 regmap_write(raminit->syscon, raminit->reg, ctrl); 127 } 128 129 ctrl |= 1 << raminit->bits.done; 130 c_can_hw_raminit_wait_syscon(priv, mask, ctrl); 131 } 132 spin_unlock(&raminit_lock); 133 } 134 135 static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index) 136 { 137 u32 val; 138 139 val = priv->read_reg(priv, index); 140 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 141 142 return val; 143 } 144 145 static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index, 146 u32 val) 147 { 148 priv->write_reg(priv, index + 1, val >> 16); 149 priv->write_reg(priv, index, val); 150 } 151 152 static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index) 153 { 154 return readl(priv->base + priv->regs[index]); 155 } 156 157 static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index, 158 u32 val) 159 { 160 writel(val, priv->base + priv->regs[index]); 161 } 162 163 static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask) 164 { 165 while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask) 166 udelay(1); 167 } 168 169 static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable) 170 { 171 u32 ctrl; 172 173 ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG); 174 ctrl &= ~DCAN_RAM_INIT_BIT; 175 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl); 176 c_can_hw_raminit_wait(priv, ctrl); 177 178 if (enable) { 179 ctrl |= DCAN_RAM_INIT_BIT; 180 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl); 181 c_can_hw_raminit_wait(priv, ctrl); 182 } 183 } 184 185 static const struct c_can_driver_data c_can_drvdata = { 186 .id = BOSCH_C_CAN, 187 }; 188 189 static const struct c_can_driver_data d_can_drvdata = { 190 .id = BOSCH_D_CAN, 191 }; 192 193 static const struct raminit_bits dra7_raminit_bits[] = { 194 [0] = { .start = 3, .done = 1, }, 195 [1] = { .start = 5, .done = 2, }, 196 }; 197 198 static const struct c_can_driver_data dra7_dcan_drvdata = { 199 .id = BOSCH_D_CAN, 200 .raminit_num = ARRAY_SIZE(dra7_raminit_bits), 201 .raminit_bits = dra7_raminit_bits, 202 .raminit_pulse = true, 203 }; 204 205 static const struct raminit_bits am3352_raminit_bits[] = { 206 [0] = { .start = 0, .done = 8, }, 207 [1] = { .start = 1, .done = 9, }, 208 }; 209 210 static const struct c_can_driver_data am3352_dcan_drvdata = { 211 .id = BOSCH_D_CAN, 212 .raminit_num = ARRAY_SIZE(am3352_raminit_bits), 213 .raminit_bits = am3352_raminit_bits, 214 }; 215 216 static struct platform_device_id c_can_id_table[] = { 217 { 218 .name = KBUILD_MODNAME, 219 .driver_data = (kernel_ulong_t)&c_can_drvdata, 220 }, 221 { 222 .name = "c_can", 223 .driver_data = (kernel_ulong_t)&c_can_drvdata, 224 }, 225 { 226 .name = "d_can", 227 .driver_data = (kernel_ulong_t)&d_can_drvdata, 228 }, 229 { /* sentinel */ }, 230 }; 231 MODULE_DEVICE_TABLE(platform, c_can_id_table); 232 233 static const struct of_device_id c_can_of_table[] = { 234 { .compatible = "bosch,c_can", .data = &c_can_drvdata }, 235 { .compatible = "bosch,d_can", .data = &d_can_drvdata }, 236 { .compatible = "ti,dra7-d_can", .data = &dra7_dcan_drvdata }, 237 { .compatible = "ti,am3352-d_can", .data = &am3352_dcan_drvdata }, 238 { .compatible = "ti,am4372-d_can", .data = &am3352_dcan_drvdata }, 239 { /* sentinel */ }, 240 }; 241 MODULE_DEVICE_TABLE(of, c_can_of_table); 242 243 static int c_can_plat_probe(struct platform_device *pdev) 244 { 245 int ret; 246 void __iomem *addr; 247 struct net_device *dev; 248 struct c_can_priv *priv; 249 const struct of_device_id *match; 250 struct resource *mem; 251 int irq; 252 struct clk *clk; 253 const struct c_can_driver_data *drvdata; 254 struct device_node *np = pdev->dev.of_node; 255 256 match = of_match_device(c_can_of_table, &pdev->dev); 257 if (match) { 258 drvdata = match->data; 259 } else if (pdev->id_entry->driver_data) { 260 drvdata = (struct c_can_driver_data *) 261 platform_get_device_id(pdev)->driver_data; 262 } else { 263 return -ENODEV; 264 } 265 266 /* get the appropriate clk */ 267 clk = devm_clk_get(&pdev->dev, NULL); 268 if (IS_ERR(clk)) { 269 ret = PTR_ERR(clk); 270 goto exit; 271 } 272 273 /* get the platform data */ 274 irq = platform_get_irq(pdev, 0); 275 if (irq <= 0) { 276 ret = -ENODEV; 277 goto exit; 278 } 279 280 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 281 addr = devm_ioremap_resource(&pdev->dev, mem); 282 if (IS_ERR(addr)) { 283 ret = PTR_ERR(addr); 284 goto exit; 285 } 286 287 /* allocate the c_can device */ 288 dev = alloc_c_can_dev(); 289 if (!dev) { 290 ret = -ENOMEM; 291 goto exit; 292 } 293 294 priv = netdev_priv(dev); 295 switch (drvdata->id) { 296 case BOSCH_C_CAN: 297 priv->regs = reg_map_c_can; 298 switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) { 299 case IORESOURCE_MEM_32BIT: 300 priv->read_reg = c_can_plat_read_reg_aligned_to_32bit; 301 priv->write_reg = c_can_plat_write_reg_aligned_to_32bit; 302 priv->read_reg32 = c_can_plat_read_reg32; 303 priv->write_reg32 = c_can_plat_write_reg32; 304 break; 305 case IORESOURCE_MEM_16BIT: 306 default: 307 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit; 308 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; 309 priv->read_reg32 = c_can_plat_read_reg32; 310 priv->write_reg32 = c_can_plat_write_reg32; 311 break; 312 } 313 break; 314 case BOSCH_D_CAN: 315 priv->regs = reg_map_d_can; 316 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES; 317 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit; 318 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; 319 priv->read_reg32 = d_can_plat_read_reg32; 320 priv->write_reg32 = d_can_plat_write_reg32; 321 322 /* Check if we need custom RAMINIT via syscon. Mostly for TI 323 * platforms. Only supported with DT boot. 324 */ 325 if (np && of_property_read_bool(np, "syscon-raminit")) { 326 u32 id; 327 struct c_can_raminit *raminit = &priv->raminit_sys; 328 329 ret = -EINVAL; 330 raminit->syscon = syscon_regmap_lookup_by_phandle(np, 331 "syscon-raminit"); 332 if (IS_ERR(raminit->syscon)) { 333 /* can fail with -EPROBE_DEFER */ 334 ret = PTR_ERR(raminit->syscon); 335 free_c_can_dev(dev); 336 return ret; 337 } 338 339 if (of_property_read_u32_index(np, "syscon-raminit", 1, 340 &raminit->reg)) { 341 dev_err(&pdev->dev, 342 "couldn't get the RAMINIT reg. offset!\n"); 343 goto exit_free_device; 344 } 345 346 if (of_property_read_u32_index(np, "syscon-raminit", 2, 347 &id)) { 348 dev_err(&pdev->dev, 349 "couldn't get the CAN instance ID\n"); 350 goto exit_free_device; 351 } 352 353 if (id >= drvdata->raminit_num) { 354 dev_err(&pdev->dev, 355 "Invalid CAN instance ID\n"); 356 goto exit_free_device; 357 } 358 359 raminit->bits = drvdata->raminit_bits[id]; 360 raminit->needs_pulse = drvdata->raminit_pulse; 361 362 priv->raminit = c_can_hw_raminit_syscon; 363 } else { 364 priv->raminit = c_can_hw_raminit; 365 } 366 break; 367 default: 368 ret = -EINVAL; 369 goto exit_free_device; 370 } 371 372 dev->irq = irq; 373 priv->base = addr; 374 priv->device = &pdev->dev; 375 priv->can.clock.freq = clk_get_rate(clk); 376 priv->priv = clk; 377 priv->type = drvdata->id; 378 379 platform_set_drvdata(pdev, dev); 380 SET_NETDEV_DEV(dev, &pdev->dev); 381 382 ret = register_c_can_dev(dev); 383 if (ret) { 384 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 385 KBUILD_MODNAME, ret); 386 goto exit_free_device; 387 } 388 389 dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n", 390 KBUILD_MODNAME, priv->base, dev->irq); 391 return 0; 392 393 exit_free_device: 394 free_c_can_dev(dev); 395 exit: 396 dev_err(&pdev->dev, "probe failed\n"); 397 398 return ret; 399 } 400 401 static int c_can_plat_remove(struct platform_device *pdev) 402 { 403 struct net_device *dev = platform_get_drvdata(pdev); 404 405 unregister_c_can_dev(dev); 406 407 free_c_can_dev(dev); 408 409 return 0; 410 } 411 412 #ifdef CONFIG_PM 413 static int c_can_suspend(struct platform_device *pdev, pm_message_t state) 414 { 415 int ret; 416 struct net_device *ndev = platform_get_drvdata(pdev); 417 struct c_can_priv *priv = netdev_priv(ndev); 418 419 if (priv->type != BOSCH_D_CAN) { 420 dev_warn(&pdev->dev, "Not supported\n"); 421 return 0; 422 } 423 424 if (netif_running(ndev)) { 425 netif_stop_queue(ndev); 426 netif_device_detach(ndev); 427 } 428 429 ret = c_can_power_down(ndev); 430 if (ret) { 431 netdev_err(ndev, "failed to enter power down mode\n"); 432 return ret; 433 } 434 435 priv->can.state = CAN_STATE_SLEEPING; 436 437 return 0; 438 } 439 440 static int c_can_resume(struct platform_device *pdev) 441 { 442 int ret; 443 struct net_device *ndev = platform_get_drvdata(pdev); 444 struct c_can_priv *priv = netdev_priv(ndev); 445 446 if (priv->type != BOSCH_D_CAN) { 447 dev_warn(&pdev->dev, "Not supported\n"); 448 return 0; 449 } 450 451 ret = c_can_power_up(ndev); 452 if (ret) { 453 netdev_err(ndev, "Still in power down mode\n"); 454 return ret; 455 } 456 457 priv->can.state = CAN_STATE_ERROR_ACTIVE; 458 459 if (netif_running(ndev)) { 460 netif_device_attach(ndev); 461 netif_start_queue(ndev); 462 } 463 464 return 0; 465 } 466 #else 467 #define c_can_suspend NULL 468 #define c_can_resume NULL 469 #endif 470 471 static struct platform_driver c_can_plat_driver = { 472 .driver = { 473 .name = KBUILD_MODNAME, 474 .of_match_table = c_can_of_table, 475 }, 476 .probe = c_can_plat_probe, 477 .remove = c_can_plat_remove, 478 .suspend = c_can_suspend, 479 .resume = c_can_resume, 480 .id_table = c_can_id_table, 481 }; 482 483 module_platform_driver(c_can_plat_driver); 484 485 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 486 MODULE_LICENSE("GPL v2"); 487 MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller"); 488