1 /* 2 * Platform CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 13 * Bosch C_CAN user manual can be obtained from: 14 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 15 * users_manual_c_can.pdf 16 * 17 * This file is licensed under the terms of the GNU General Public 18 * License version 2. This program is licensed "as is" without any 19 * warranty of any kind, whether express or implied. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/delay.h> 26 #include <linux/netdevice.h> 27 #include <linux/if_arp.h> 28 #include <linux/if_ether.h> 29 #include <linux/list.h> 30 #include <linux/io.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/clk.h> 34 #include <linux/of.h> 35 #include <linux/of_device.h> 36 #include <linux/mfd/syscon.h> 37 #include <linux/regmap.h> 38 39 #include <linux/can/dev.h> 40 41 #include "c_can.h" 42 43 #define DCAN_RAM_INIT_BIT BIT(3) 44 45 static DEFINE_SPINLOCK(raminit_lock); 46 47 /* 16-bit c_can registers can be arranged differently in the memory 48 * architecture of different implementations. For example: 16-bit 49 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc. 50 * Handle the same by providing a common read/write interface. 51 */ 52 static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv, 53 enum reg index) 54 { 55 return readw(priv->base + priv->regs[index]); 56 } 57 58 static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv, 59 enum reg index, u16 val) 60 { 61 writew(val, priv->base + priv->regs[index]); 62 } 63 64 static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv, 65 enum reg index) 66 { 67 return readw(priv->base + 2 * priv->regs[index]); 68 } 69 70 static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, 71 enum reg index, u16 val) 72 { 73 writew(val, priv->base + 2 * priv->regs[index]); 74 } 75 76 static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv, 77 u32 mask, u32 val) 78 { 79 const struct c_can_raminit *raminit = &priv->raminit_sys; 80 int timeout = 0; 81 u32 ctrl = 0; 82 83 /* We look only at the bits of our instance. */ 84 val &= mask; 85 do { 86 udelay(1); 87 timeout++; 88 89 regmap_read(raminit->syscon, raminit->reg, &ctrl); 90 if (timeout == 1000) { 91 dev_err(&priv->dev->dev, "%s: time out\n", __func__); 92 break; 93 } 94 } while ((ctrl & mask) != val); 95 } 96 97 static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable) 98 { 99 const struct c_can_raminit *raminit = &priv->raminit_sys; 100 u32 ctrl = 0; 101 u32 mask; 102 103 spin_lock(&raminit_lock); 104 105 mask = 1 << raminit->bits.start | 1 << raminit->bits.done; 106 regmap_read(raminit->syscon, raminit->reg, &ctrl); 107 108 /* We clear the start bit first. The start bit is 109 * looking at the 0 -> transition, but is not self clearing; 110 * NOTE: DONE must be written with 1 to clear it. 111 * We can't clear the DONE bit here using regmap_update_bits() 112 * as it will bypass the write if initial condition is START:0 DONE:1 113 * e.g. on DRA7 which needs START pulse. 114 */ 115 ctrl &= ~mask; /* START = 0, DONE = 0 */ 116 regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); 117 118 /* check if START bit is 0. Ignore DONE bit for now 119 * as it can be either 0 or 1. 120 */ 121 c_can_hw_raminit_wait_syscon(priv, 1 << raminit->bits.start, ctrl); 122 123 if (enable) { 124 /* Clear DONE bit & set START bit. */ 125 ctrl |= 1 << raminit->bits.start; 126 /* DONE must be written with 1 to clear it */ 127 ctrl |= 1 << raminit->bits.done; 128 regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); 129 /* prevent further clearing of DONE bit */ 130 ctrl &= ~(1 << raminit->bits.done); 131 /* clear START bit if start pulse is needed */ 132 if (raminit->needs_pulse) { 133 ctrl &= ~(1 << raminit->bits.start); 134 regmap_update_bits(raminit->syscon, raminit->reg, 135 mask, ctrl); 136 } 137 138 ctrl |= 1 << raminit->bits.done; 139 c_can_hw_raminit_wait_syscon(priv, mask, ctrl); 140 } 141 spin_unlock(&raminit_lock); 142 } 143 144 static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index) 145 { 146 u32 val; 147 148 val = priv->read_reg(priv, index); 149 val |= ((u32)priv->read_reg(priv, index + 1)) << 16; 150 151 return val; 152 } 153 154 static void c_can_plat_write_reg32(const struct c_can_priv *priv, 155 enum reg index, u32 val) 156 { 157 priv->write_reg(priv, index + 1, val >> 16); 158 priv->write_reg(priv, index, val); 159 } 160 161 static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index) 162 { 163 return readl(priv->base + priv->regs[index]); 164 } 165 166 static void d_can_plat_write_reg32(const struct c_can_priv *priv, 167 enum reg index, u32 val) 168 { 169 writel(val, priv->base + priv->regs[index]); 170 } 171 172 static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask) 173 { 174 while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask) 175 udelay(1); 176 } 177 178 static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable) 179 { 180 u32 ctrl; 181 182 ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG); 183 ctrl &= ~DCAN_RAM_INIT_BIT; 184 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl); 185 c_can_hw_raminit_wait(priv, ctrl); 186 187 if (enable) { 188 ctrl |= DCAN_RAM_INIT_BIT; 189 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl); 190 c_can_hw_raminit_wait(priv, ctrl); 191 } 192 } 193 194 static const struct c_can_driver_data c_can_drvdata = { 195 .id = BOSCH_C_CAN, 196 }; 197 198 static const struct c_can_driver_data d_can_drvdata = { 199 .id = BOSCH_D_CAN, 200 }; 201 202 static const struct raminit_bits dra7_raminit_bits[] = { 203 [0] = { .start = 3, .done = 1, }, 204 [1] = { .start = 5, .done = 2, }, 205 }; 206 207 static const struct c_can_driver_data dra7_dcan_drvdata = { 208 .id = BOSCH_D_CAN, 209 .raminit_num = ARRAY_SIZE(dra7_raminit_bits), 210 .raminit_bits = dra7_raminit_bits, 211 .raminit_pulse = true, 212 }; 213 214 static const struct raminit_bits am3352_raminit_bits[] = { 215 [0] = { .start = 0, .done = 8, }, 216 [1] = { .start = 1, .done = 9, }, 217 }; 218 219 static const struct c_can_driver_data am3352_dcan_drvdata = { 220 .id = BOSCH_D_CAN, 221 .raminit_num = ARRAY_SIZE(am3352_raminit_bits), 222 .raminit_bits = am3352_raminit_bits, 223 }; 224 225 static const struct platform_device_id c_can_id_table[] = { 226 { 227 .name = KBUILD_MODNAME, 228 .driver_data = (kernel_ulong_t)&c_can_drvdata, 229 }, 230 { 231 .name = "c_can", 232 .driver_data = (kernel_ulong_t)&c_can_drvdata, 233 }, 234 { 235 .name = "d_can", 236 .driver_data = (kernel_ulong_t)&d_can_drvdata, 237 }, 238 { /* sentinel */ }, 239 }; 240 MODULE_DEVICE_TABLE(platform, c_can_id_table); 241 242 static const struct of_device_id c_can_of_table[] = { 243 { .compatible = "bosch,c_can", .data = &c_can_drvdata }, 244 { .compatible = "bosch,d_can", .data = &d_can_drvdata }, 245 { .compatible = "ti,dra7-d_can", .data = &dra7_dcan_drvdata }, 246 { .compatible = "ti,am3352-d_can", .data = &am3352_dcan_drvdata }, 247 { .compatible = "ti,am4372-d_can", .data = &am3352_dcan_drvdata }, 248 { /* sentinel */ }, 249 }; 250 MODULE_DEVICE_TABLE(of, c_can_of_table); 251 252 static int c_can_plat_probe(struct platform_device *pdev) 253 { 254 int ret; 255 void __iomem *addr; 256 struct net_device *dev; 257 struct c_can_priv *priv; 258 const struct of_device_id *match; 259 struct resource *mem; 260 int irq; 261 struct clk *clk; 262 const struct c_can_driver_data *drvdata; 263 struct device_node *np = pdev->dev.of_node; 264 265 match = of_match_device(c_can_of_table, &pdev->dev); 266 if (match) { 267 drvdata = match->data; 268 } else if (pdev->id_entry->driver_data) { 269 drvdata = (struct c_can_driver_data *) 270 platform_get_device_id(pdev)->driver_data; 271 } else { 272 return -ENODEV; 273 } 274 275 /* get the appropriate clk */ 276 clk = devm_clk_get(&pdev->dev, NULL); 277 if (IS_ERR(clk)) { 278 ret = PTR_ERR(clk); 279 goto exit; 280 } 281 282 /* get the platform data */ 283 irq = platform_get_irq(pdev, 0); 284 if (irq <= 0) { 285 ret = -ENODEV; 286 goto exit; 287 } 288 289 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 290 addr = devm_ioremap_resource(&pdev->dev, mem); 291 if (IS_ERR(addr)) { 292 ret = PTR_ERR(addr); 293 goto exit; 294 } 295 296 /* allocate the c_can device */ 297 dev = alloc_c_can_dev(); 298 if (!dev) { 299 ret = -ENOMEM; 300 goto exit; 301 } 302 303 priv = netdev_priv(dev); 304 switch (drvdata->id) { 305 case BOSCH_C_CAN: 306 priv->regs = reg_map_c_can; 307 switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) { 308 case IORESOURCE_MEM_32BIT: 309 priv->read_reg = c_can_plat_read_reg_aligned_to_32bit; 310 priv->write_reg = c_can_plat_write_reg_aligned_to_32bit; 311 priv->read_reg32 = c_can_plat_read_reg32; 312 priv->write_reg32 = c_can_plat_write_reg32; 313 break; 314 case IORESOURCE_MEM_16BIT: 315 default: 316 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit; 317 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; 318 priv->read_reg32 = c_can_plat_read_reg32; 319 priv->write_reg32 = c_can_plat_write_reg32; 320 break; 321 } 322 break; 323 case BOSCH_D_CAN: 324 priv->regs = reg_map_d_can; 325 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit; 326 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; 327 priv->read_reg32 = d_can_plat_read_reg32; 328 priv->write_reg32 = d_can_plat_write_reg32; 329 330 /* Check if we need custom RAMINIT via syscon. Mostly for TI 331 * platforms. Only supported with DT boot. 332 */ 333 if (np && of_property_read_bool(np, "syscon-raminit")) { 334 u32 id; 335 struct c_can_raminit *raminit = &priv->raminit_sys; 336 337 ret = -EINVAL; 338 raminit->syscon = syscon_regmap_lookup_by_phandle(np, 339 "syscon-raminit"); 340 if (IS_ERR(raminit->syscon)) { 341 /* can fail with -EPROBE_DEFER */ 342 ret = PTR_ERR(raminit->syscon); 343 free_c_can_dev(dev); 344 return ret; 345 } 346 347 if (of_property_read_u32_index(np, "syscon-raminit", 1, 348 &raminit->reg)) { 349 dev_err(&pdev->dev, 350 "couldn't get the RAMINIT reg. offset!\n"); 351 goto exit_free_device; 352 } 353 354 if (of_property_read_u32_index(np, "syscon-raminit", 2, 355 &id)) { 356 dev_err(&pdev->dev, 357 "couldn't get the CAN instance ID\n"); 358 goto exit_free_device; 359 } 360 361 if (id >= drvdata->raminit_num) { 362 dev_err(&pdev->dev, 363 "Invalid CAN instance ID\n"); 364 goto exit_free_device; 365 } 366 367 raminit->bits = drvdata->raminit_bits[id]; 368 raminit->needs_pulse = drvdata->raminit_pulse; 369 370 priv->raminit = c_can_hw_raminit_syscon; 371 } else { 372 priv->raminit = c_can_hw_raminit; 373 } 374 break; 375 default: 376 ret = -EINVAL; 377 goto exit_free_device; 378 } 379 380 dev->irq = irq; 381 priv->base = addr; 382 priv->device = &pdev->dev; 383 priv->can.clock.freq = clk_get_rate(clk); 384 priv->priv = clk; 385 priv->type = drvdata->id; 386 387 platform_set_drvdata(pdev, dev); 388 SET_NETDEV_DEV(dev, &pdev->dev); 389 390 pm_runtime_enable(priv->device); 391 ret = register_c_can_dev(dev); 392 if (ret) { 393 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 394 KBUILD_MODNAME, ret); 395 goto exit_free_device; 396 } 397 398 dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n", 399 KBUILD_MODNAME, priv->base, dev->irq); 400 return 0; 401 402 exit_free_device: 403 pm_runtime_disable(priv->device); 404 free_c_can_dev(dev); 405 exit: 406 dev_err(&pdev->dev, "probe failed\n"); 407 408 return ret; 409 } 410 411 static int c_can_plat_remove(struct platform_device *pdev) 412 { 413 struct net_device *dev = platform_get_drvdata(pdev); 414 struct c_can_priv *priv = netdev_priv(dev); 415 416 unregister_c_can_dev(dev); 417 pm_runtime_disable(priv->device); 418 free_c_can_dev(dev); 419 420 return 0; 421 } 422 423 #ifdef CONFIG_PM 424 static int c_can_suspend(struct platform_device *pdev, pm_message_t state) 425 { 426 int ret; 427 struct net_device *ndev = platform_get_drvdata(pdev); 428 struct c_can_priv *priv = netdev_priv(ndev); 429 430 if (priv->type != BOSCH_D_CAN) { 431 dev_warn(&pdev->dev, "Not supported\n"); 432 return 0; 433 } 434 435 if (netif_running(ndev)) { 436 netif_stop_queue(ndev); 437 netif_device_detach(ndev); 438 } 439 440 ret = c_can_power_down(ndev); 441 if (ret) { 442 netdev_err(ndev, "failed to enter power down mode\n"); 443 return ret; 444 } 445 446 priv->can.state = CAN_STATE_SLEEPING; 447 448 return 0; 449 } 450 451 static int c_can_resume(struct platform_device *pdev) 452 { 453 int ret; 454 struct net_device *ndev = platform_get_drvdata(pdev); 455 struct c_can_priv *priv = netdev_priv(ndev); 456 457 if (priv->type != BOSCH_D_CAN) { 458 dev_warn(&pdev->dev, "Not supported\n"); 459 return 0; 460 } 461 462 ret = c_can_power_up(ndev); 463 if (ret) { 464 netdev_err(ndev, "Still in power down mode\n"); 465 return ret; 466 } 467 468 priv->can.state = CAN_STATE_ERROR_ACTIVE; 469 470 if (netif_running(ndev)) { 471 netif_device_attach(ndev); 472 netif_start_queue(ndev); 473 } 474 475 return 0; 476 } 477 #else 478 #define c_can_suspend NULL 479 #define c_can_resume NULL 480 #endif 481 482 static struct platform_driver c_can_plat_driver = { 483 .driver = { 484 .name = KBUILD_MODNAME, 485 .of_match_table = c_can_of_table, 486 }, 487 .probe = c_can_plat_probe, 488 .remove = c_can_plat_remove, 489 .suspend = c_can_suspend, 490 .resume = c_can_resume, 491 .id_table = c_can_id_table, 492 }; 493 494 module_platform_driver(c_can_plat_driver); 495 496 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 497 MODULE_LICENSE("GPL v2"); 498 MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller"); 499