1 /* 2 * Platform CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 13 * Bosch C_CAN user manual can be obtained from: 14 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 15 * users_manual_c_can.pdf 16 * 17 * This file is licensed under the terms of the GNU General Public 18 * License version 2. This program is licensed "as is" without any 19 * warranty of any kind, whether express or implied. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/delay.h> 26 #include <linux/netdevice.h> 27 #include <linux/if_arp.h> 28 #include <linux/if_ether.h> 29 #include <linux/list.h> 30 #include <linux/io.h> 31 #include <linux/platform_device.h> 32 #include <linux/clk.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/regmap.h> 37 38 #include <linux/can/dev.h> 39 40 #include "c_can.h" 41 42 #define DCAN_RAM_INIT_BIT (1 << 3) 43 static DEFINE_SPINLOCK(raminit_lock); 44 /* 45 * 16-bit c_can registers can be arranged differently in the memory 46 * architecture of different implementations. For example: 16-bit 47 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc. 48 * Handle the same by providing a common read/write interface. 49 */ 50 static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv, 51 enum reg index) 52 { 53 return readw(priv->base + priv->regs[index]); 54 } 55 56 static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv, 57 enum reg index, u16 val) 58 { 59 writew(val, priv->base + priv->regs[index]); 60 } 61 62 static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv, 63 enum reg index) 64 { 65 return readw(priv->base + 2 * priv->regs[index]); 66 } 67 68 static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, 69 enum reg index, u16 val) 70 { 71 writew(val, priv->base + 2 * priv->regs[index]); 72 } 73 74 static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv, 75 u32 mask, u32 val) 76 { 77 const struct c_can_raminit *raminit = &priv->raminit_sys; 78 int timeout = 0; 79 u32 ctrl = 0; 80 81 /* We look only at the bits of our instance. */ 82 val &= mask; 83 do { 84 udelay(1); 85 timeout++; 86 87 regmap_read(raminit->syscon, raminit->reg, &ctrl); 88 if (timeout == 1000) { 89 dev_err(&priv->dev->dev, "%s: time out\n", __func__); 90 break; 91 } 92 } while ((ctrl & mask) != val); 93 } 94 95 static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable) 96 { 97 const struct c_can_raminit *raminit = &priv->raminit_sys; 98 u32 ctrl = 0; 99 u32 mask; 100 101 spin_lock(&raminit_lock); 102 103 mask = 1 << raminit->bits.start | 1 << raminit->bits.done; 104 regmap_read(raminit->syscon, raminit->reg, &ctrl); 105 106 /* We clear the start bit first. The start bit is 107 * looking at the 0 -> transition, but is not self clearing; 108 * NOTE: DONE must be written with 1 to clear it. 109 * We can't clear the DONE bit here using regmap_update_bits() 110 * as it will bypass the write if initial condition is START:0 DONE:1 111 * e.g. on DRA7 which needs START pulse. 112 */ 113 ctrl &= ~mask; /* START = 0, DONE = 0 */ 114 regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); 115 116 /* check if START bit is 0. Ignore DONE bit for now 117 * as it can be either 0 or 1. 118 */ 119 c_can_hw_raminit_wait_syscon(priv, 1 << raminit->bits.start, ctrl); 120 121 if (enable) { 122 /* Clear DONE bit & set START bit. */ 123 ctrl |= 1 << raminit->bits.start; 124 /* DONE must be written with 1 to clear it */ 125 ctrl |= 1 << raminit->bits.done; 126 regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); 127 /* prevent further clearing of DONE bit */ 128 ctrl &= ~(1 << raminit->bits.done); 129 /* clear START bit if start pulse is needed */ 130 if (raminit->needs_pulse) { 131 ctrl &= ~(1 << raminit->bits.start); 132 regmap_update_bits(raminit->syscon, raminit->reg, 133 mask, ctrl); 134 } 135 136 ctrl |= 1 << raminit->bits.done; 137 c_can_hw_raminit_wait_syscon(priv, mask, ctrl); 138 } 139 spin_unlock(&raminit_lock); 140 } 141 142 static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index) 143 { 144 u32 val; 145 146 val = priv->read_reg(priv, index); 147 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 148 149 return val; 150 } 151 152 static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index, 153 u32 val) 154 { 155 priv->write_reg(priv, index + 1, val >> 16); 156 priv->write_reg(priv, index, val); 157 } 158 159 static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index) 160 { 161 return readl(priv->base + priv->regs[index]); 162 } 163 164 static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index, 165 u32 val) 166 { 167 writel(val, priv->base + priv->regs[index]); 168 } 169 170 static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask) 171 { 172 while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask) 173 udelay(1); 174 } 175 176 static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable) 177 { 178 u32 ctrl; 179 180 ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG); 181 ctrl &= ~DCAN_RAM_INIT_BIT; 182 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl); 183 c_can_hw_raminit_wait(priv, ctrl); 184 185 if (enable) { 186 ctrl |= DCAN_RAM_INIT_BIT; 187 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl); 188 c_can_hw_raminit_wait(priv, ctrl); 189 } 190 } 191 192 static const struct c_can_driver_data c_can_drvdata = { 193 .id = BOSCH_C_CAN, 194 }; 195 196 static const struct c_can_driver_data d_can_drvdata = { 197 .id = BOSCH_D_CAN, 198 }; 199 200 static const struct raminit_bits dra7_raminit_bits[] = { 201 [0] = { .start = 3, .done = 1, }, 202 [1] = { .start = 5, .done = 2, }, 203 }; 204 205 static const struct c_can_driver_data dra7_dcan_drvdata = { 206 .id = BOSCH_D_CAN, 207 .raminit_num = ARRAY_SIZE(dra7_raminit_bits), 208 .raminit_bits = dra7_raminit_bits, 209 .raminit_pulse = true, 210 }; 211 212 static const struct raminit_bits am3352_raminit_bits[] = { 213 [0] = { .start = 0, .done = 8, }, 214 [1] = { .start = 1, .done = 9, }, 215 }; 216 217 static const struct c_can_driver_data am3352_dcan_drvdata = { 218 .id = BOSCH_D_CAN, 219 .raminit_num = ARRAY_SIZE(am3352_raminit_bits), 220 .raminit_bits = am3352_raminit_bits, 221 }; 222 223 static const struct platform_device_id c_can_id_table[] = { 224 { 225 .name = KBUILD_MODNAME, 226 .driver_data = (kernel_ulong_t)&c_can_drvdata, 227 }, 228 { 229 .name = "c_can", 230 .driver_data = (kernel_ulong_t)&c_can_drvdata, 231 }, 232 { 233 .name = "d_can", 234 .driver_data = (kernel_ulong_t)&d_can_drvdata, 235 }, 236 { /* sentinel */ }, 237 }; 238 MODULE_DEVICE_TABLE(platform, c_can_id_table); 239 240 static const struct of_device_id c_can_of_table[] = { 241 { .compatible = "bosch,c_can", .data = &c_can_drvdata }, 242 { .compatible = "bosch,d_can", .data = &d_can_drvdata }, 243 { .compatible = "ti,dra7-d_can", .data = &dra7_dcan_drvdata }, 244 { .compatible = "ti,am3352-d_can", .data = &am3352_dcan_drvdata }, 245 { .compatible = "ti,am4372-d_can", .data = &am3352_dcan_drvdata }, 246 { /* sentinel */ }, 247 }; 248 MODULE_DEVICE_TABLE(of, c_can_of_table); 249 250 static int c_can_plat_probe(struct platform_device *pdev) 251 { 252 int ret; 253 void __iomem *addr; 254 struct net_device *dev; 255 struct c_can_priv *priv; 256 const struct of_device_id *match; 257 struct resource *mem; 258 int irq; 259 struct clk *clk; 260 const struct c_can_driver_data *drvdata; 261 struct device_node *np = pdev->dev.of_node; 262 263 match = of_match_device(c_can_of_table, &pdev->dev); 264 if (match) { 265 drvdata = match->data; 266 } else if (pdev->id_entry->driver_data) { 267 drvdata = (struct c_can_driver_data *) 268 platform_get_device_id(pdev)->driver_data; 269 } else { 270 return -ENODEV; 271 } 272 273 /* get the appropriate clk */ 274 clk = devm_clk_get(&pdev->dev, NULL); 275 if (IS_ERR(clk)) { 276 ret = PTR_ERR(clk); 277 goto exit; 278 } 279 280 /* get the platform data */ 281 irq = platform_get_irq(pdev, 0); 282 if (irq <= 0) { 283 ret = -ENODEV; 284 goto exit; 285 } 286 287 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 288 addr = devm_ioremap_resource(&pdev->dev, mem); 289 if (IS_ERR(addr)) { 290 ret = PTR_ERR(addr); 291 goto exit; 292 } 293 294 /* allocate the c_can device */ 295 dev = alloc_c_can_dev(); 296 if (!dev) { 297 ret = -ENOMEM; 298 goto exit; 299 } 300 301 priv = netdev_priv(dev); 302 switch (drvdata->id) { 303 case BOSCH_C_CAN: 304 priv->regs = reg_map_c_can; 305 switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) { 306 case IORESOURCE_MEM_32BIT: 307 priv->read_reg = c_can_plat_read_reg_aligned_to_32bit; 308 priv->write_reg = c_can_plat_write_reg_aligned_to_32bit; 309 priv->read_reg32 = c_can_plat_read_reg32; 310 priv->write_reg32 = c_can_plat_write_reg32; 311 break; 312 case IORESOURCE_MEM_16BIT: 313 default: 314 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit; 315 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; 316 priv->read_reg32 = c_can_plat_read_reg32; 317 priv->write_reg32 = c_can_plat_write_reg32; 318 break; 319 } 320 break; 321 case BOSCH_D_CAN: 322 priv->regs = reg_map_d_can; 323 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit; 324 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; 325 priv->read_reg32 = d_can_plat_read_reg32; 326 priv->write_reg32 = d_can_plat_write_reg32; 327 328 /* Check if we need custom RAMINIT via syscon. Mostly for TI 329 * platforms. Only supported with DT boot. 330 */ 331 if (np && of_property_read_bool(np, "syscon-raminit")) { 332 u32 id; 333 struct c_can_raminit *raminit = &priv->raminit_sys; 334 335 ret = -EINVAL; 336 raminit->syscon = syscon_regmap_lookup_by_phandle(np, 337 "syscon-raminit"); 338 if (IS_ERR(raminit->syscon)) { 339 /* can fail with -EPROBE_DEFER */ 340 ret = PTR_ERR(raminit->syscon); 341 free_c_can_dev(dev); 342 return ret; 343 } 344 345 if (of_property_read_u32_index(np, "syscon-raminit", 1, 346 &raminit->reg)) { 347 dev_err(&pdev->dev, 348 "couldn't get the RAMINIT reg. offset!\n"); 349 goto exit_free_device; 350 } 351 352 if (of_property_read_u32_index(np, "syscon-raminit", 2, 353 &id)) { 354 dev_err(&pdev->dev, 355 "couldn't get the CAN instance ID\n"); 356 goto exit_free_device; 357 } 358 359 if (id >= drvdata->raminit_num) { 360 dev_err(&pdev->dev, 361 "Invalid CAN instance ID\n"); 362 goto exit_free_device; 363 } 364 365 raminit->bits = drvdata->raminit_bits[id]; 366 raminit->needs_pulse = drvdata->raminit_pulse; 367 368 priv->raminit = c_can_hw_raminit_syscon; 369 } else { 370 priv->raminit = c_can_hw_raminit; 371 } 372 break; 373 default: 374 ret = -EINVAL; 375 goto exit_free_device; 376 } 377 378 dev->irq = irq; 379 priv->base = addr; 380 priv->device = &pdev->dev; 381 priv->can.clock.freq = clk_get_rate(clk); 382 priv->priv = clk; 383 priv->type = drvdata->id; 384 385 platform_set_drvdata(pdev, dev); 386 SET_NETDEV_DEV(dev, &pdev->dev); 387 388 ret = register_c_can_dev(dev); 389 if (ret) { 390 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 391 KBUILD_MODNAME, ret); 392 goto exit_free_device; 393 } 394 395 dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n", 396 KBUILD_MODNAME, priv->base, dev->irq); 397 return 0; 398 399 exit_free_device: 400 free_c_can_dev(dev); 401 exit: 402 dev_err(&pdev->dev, "probe failed\n"); 403 404 return ret; 405 } 406 407 static int c_can_plat_remove(struct platform_device *pdev) 408 { 409 struct net_device *dev = platform_get_drvdata(pdev); 410 411 unregister_c_can_dev(dev); 412 413 free_c_can_dev(dev); 414 415 return 0; 416 } 417 418 #ifdef CONFIG_PM 419 static int c_can_suspend(struct platform_device *pdev, pm_message_t state) 420 { 421 int ret; 422 struct net_device *ndev = platform_get_drvdata(pdev); 423 struct c_can_priv *priv = netdev_priv(ndev); 424 425 if (priv->type != BOSCH_D_CAN) { 426 dev_warn(&pdev->dev, "Not supported\n"); 427 return 0; 428 } 429 430 if (netif_running(ndev)) { 431 netif_stop_queue(ndev); 432 netif_device_detach(ndev); 433 } 434 435 ret = c_can_power_down(ndev); 436 if (ret) { 437 netdev_err(ndev, "failed to enter power down mode\n"); 438 return ret; 439 } 440 441 priv->can.state = CAN_STATE_SLEEPING; 442 443 return 0; 444 } 445 446 static int c_can_resume(struct platform_device *pdev) 447 { 448 int ret; 449 struct net_device *ndev = platform_get_drvdata(pdev); 450 struct c_can_priv *priv = netdev_priv(ndev); 451 452 if (priv->type != BOSCH_D_CAN) { 453 dev_warn(&pdev->dev, "Not supported\n"); 454 return 0; 455 } 456 457 ret = c_can_power_up(ndev); 458 if (ret) { 459 netdev_err(ndev, "Still in power down mode\n"); 460 return ret; 461 } 462 463 priv->can.state = CAN_STATE_ERROR_ACTIVE; 464 465 if (netif_running(ndev)) { 466 netif_device_attach(ndev); 467 netif_start_queue(ndev); 468 } 469 470 return 0; 471 } 472 #else 473 #define c_can_suspend NULL 474 #define c_can_resume NULL 475 #endif 476 477 static struct platform_driver c_can_plat_driver = { 478 .driver = { 479 .name = KBUILD_MODNAME, 480 .of_match_table = c_can_of_table, 481 }, 482 .probe = c_can_plat_probe, 483 .remove = c_can_plat_remove, 484 .suspend = c_can_suspend, 485 .resume = c_can_resume, 486 .id_table = c_can_id_table, 487 }; 488 489 module_platform_driver(c_can_plat_driver); 490 491 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 492 MODULE_LICENSE("GPL v2"); 493 MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller"); 494