1 /* 2 * Platform CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 13 * Bosch C_CAN user manual can be obtained from: 14 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 15 * users_manual_c_can.pdf 16 * 17 * This file is licensed under the terms of the GNU General Public 18 * License version 2. This program is licensed "as is" without any 19 * warranty of any kind, whether express or implied. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/delay.h> 26 #include <linux/netdevice.h> 27 #include <linux/if_arp.h> 28 #include <linux/if_ether.h> 29 #include <linux/list.h> 30 #include <linux/io.h> 31 #include <linux/platform_device.h> 32 #include <linux/clk.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 36 #include <linux/can/dev.h> 37 38 #include "c_can.h" 39 40 #define CAN_RAMINIT_START_MASK(i) (0x001 << (i)) 41 #define CAN_RAMINIT_DONE_MASK(i) (0x100 << (i)) 42 #define CAN_RAMINIT_ALL_MASK(i) (0x101 << (i)) 43 #define DCAN_RAM_INIT_BIT (1 << 3) 44 static DEFINE_SPINLOCK(raminit_lock); 45 /* 46 * 16-bit c_can registers can be arranged differently in the memory 47 * architecture of different implementations. For example: 16-bit 48 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc. 49 * Handle the same by providing a common read/write interface. 50 */ 51 static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv, 52 enum reg index) 53 { 54 return readw(priv->base + priv->regs[index]); 55 } 56 57 static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv, 58 enum reg index, u16 val) 59 { 60 writew(val, priv->base + priv->regs[index]); 61 } 62 63 static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv, 64 enum reg index) 65 { 66 return readw(priv->base + 2 * priv->regs[index]); 67 } 68 69 static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, 70 enum reg index, u16 val) 71 { 72 writew(val, priv->base + 2 * priv->regs[index]); 73 } 74 75 static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask, 76 u32 val) 77 { 78 /* We look only at the bits of our instance. */ 79 val &= mask; 80 while ((readl(priv->raminit_ctrlreg) & mask) != val) 81 udelay(1); 82 } 83 84 static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable) 85 { 86 u32 mask = CAN_RAMINIT_ALL_MASK(priv->instance); 87 u32 ctrl; 88 89 spin_lock(&raminit_lock); 90 91 ctrl = readl(priv->raminit_ctrlreg); 92 /* We clear the done and start bit first. The start bit is 93 * looking at the 0 -> transition, but is not self clearing; 94 * And we clear the init done bit as well. 95 */ 96 ctrl &= ~CAN_RAMINIT_START_MASK(priv->instance); 97 ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance); 98 writel(ctrl, priv->raminit_ctrlreg); 99 ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance); 100 c_can_hw_raminit_wait_ti(priv, ctrl, mask); 101 102 if (enable) { 103 /* Set start bit and wait for the done bit. */ 104 ctrl |= CAN_RAMINIT_START_MASK(priv->instance); 105 writel(ctrl, priv->raminit_ctrlreg); 106 ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance); 107 c_can_hw_raminit_wait_ti(priv, ctrl, mask); 108 } 109 spin_unlock(&raminit_lock); 110 } 111 112 static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index) 113 { 114 u32 val; 115 116 val = priv->read_reg(priv, index); 117 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 118 119 return val; 120 } 121 122 static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index, 123 u32 val) 124 { 125 priv->write_reg(priv, index + 1, val >> 16); 126 priv->write_reg(priv, index, val); 127 } 128 129 static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index) 130 { 131 return readl(priv->base + priv->regs[index]); 132 } 133 134 static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index, 135 u32 val) 136 { 137 writel(val, priv->base + priv->regs[index]); 138 } 139 140 static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask) 141 { 142 while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask) 143 udelay(1); 144 } 145 146 static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable) 147 { 148 u32 ctrl; 149 150 ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG); 151 ctrl &= ~DCAN_RAM_INIT_BIT; 152 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl); 153 c_can_hw_raminit_wait(priv, ctrl); 154 155 if (enable) { 156 ctrl |= DCAN_RAM_INIT_BIT; 157 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl); 158 c_can_hw_raminit_wait(priv, ctrl); 159 } 160 } 161 162 static struct platform_device_id c_can_id_table[] = { 163 [BOSCH_C_CAN_PLATFORM] = { 164 .name = KBUILD_MODNAME, 165 .driver_data = BOSCH_C_CAN, 166 }, 167 [BOSCH_C_CAN] = { 168 .name = "c_can", 169 .driver_data = BOSCH_C_CAN, 170 }, 171 [BOSCH_D_CAN] = { 172 .name = "d_can", 173 .driver_data = BOSCH_D_CAN, 174 }, { 175 } 176 }; 177 MODULE_DEVICE_TABLE(platform, c_can_id_table); 178 179 static const struct of_device_id c_can_of_table[] = { 180 { .compatible = "bosch,c_can", .data = &c_can_id_table[BOSCH_C_CAN] }, 181 { .compatible = "bosch,d_can", .data = &c_can_id_table[BOSCH_D_CAN] }, 182 { /* sentinel */ }, 183 }; 184 MODULE_DEVICE_TABLE(of, c_can_of_table); 185 186 static int c_can_plat_probe(struct platform_device *pdev) 187 { 188 int ret; 189 void __iomem *addr; 190 struct net_device *dev; 191 struct c_can_priv *priv; 192 const struct of_device_id *match; 193 const struct platform_device_id *id; 194 struct resource *mem, *res; 195 int irq; 196 struct clk *clk; 197 198 if (pdev->dev.of_node) { 199 match = of_match_device(c_can_of_table, &pdev->dev); 200 if (!match) { 201 dev_err(&pdev->dev, "Failed to find matching dt id\n"); 202 ret = -EINVAL; 203 goto exit; 204 } 205 id = match->data; 206 } else { 207 id = platform_get_device_id(pdev); 208 } 209 210 /* get the appropriate clk */ 211 clk = clk_get(&pdev->dev, NULL); 212 if (IS_ERR(clk)) { 213 dev_err(&pdev->dev, "no clock defined\n"); 214 ret = -ENODEV; 215 goto exit; 216 } 217 218 /* get the platform data */ 219 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 220 irq = platform_get_irq(pdev, 0); 221 if (!mem || irq <= 0) { 222 ret = -ENODEV; 223 goto exit_free_clk; 224 } 225 226 if (!request_mem_region(mem->start, resource_size(mem), 227 KBUILD_MODNAME)) { 228 dev_err(&pdev->dev, "resource unavailable\n"); 229 ret = -ENODEV; 230 goto exit_free_clk; 231 } 232 233 addr = ioremap(mem->start, resource_size(mem)); 234 if (!addr) { 235 dev_err(&pdev->dev, "failed to map can port\n"); 236 ret = -ENOMEM; 237 goto exit_release_mem; 238 } 239 240 /* allocate the c_can device */ 241 dev = alloc_c_can_dev(); 242 if (!dev) { 243 ret = -ENOMEM; 244 goto exit_iounmap; 245 } 246 247 priv = netdev_priv(dev); 248 switch (id->driver_data) { 249 case BOSCH_C_CAN: 250 priv->regs = reg_map_c_can; 251 switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) { 252 case IORESOURCE_MEM_32BIT: 253 priv->read_reg = c_can_plat_read_reg_aligned_to_32bit; 254 priv->write_reg = c_can_plat_write_reg_aligned_to_32bit; 255 priv->read_reg32 = c_can_plat_read_reg32; 256 priv->write_reg32 = c_can_plat_write_reg32; 257 break; 258 case IORESOURCE_MEM_16BIT: 259 default: 260 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit; 261 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; 262 priv->read_reg32 = c_can_plat_read_reg32; 263 priv->write_reg32 = c_can_plat_write_reg32; 264 break; 265 } 266 break; 267 case BOSCH_D_CAN: 268 priv->regs = reg_map_d_can; 269 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES; 270 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit; 271 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; 272 priv->read_reg32 = d_can_plat_read_reg32; 273 priv->write_reg32 = d_can_plat_write_reg32; 274 275 if (pdev->dev.of_node) 276 priv->instance = of_alias_get_id(pdev->dev.of_node, "d_can"); 277 else 278 priv->instance = pdev->id; 279 280 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 281 /* Not all D_CAN modules have a separate register for the D_CAN 282 * RAM initialization. Use default RAM init bit in D_CAN module 283 * if not specified in DT. 284 */ 285 if (!res) { 286 priv->raminit = c_can_hw_raminit; 287 break; 288 } 289 290 priv->raminit_ctrlreg = devm_ioremap_resource(&pdev->dev, res); 291 if (IS_ERR(priv->raminit_ctrlreg) || priv->instance < 0) 292 dev_info(&pdev->dev, "control memory is not used for raminit\n"); 293 else 294 priv->raminit = c_can_hw_raminit_ti; 295 break; 296 default: 297 ret = -EINVAL; 298 goto exit_free_device; 299 } 300 301 dev->irq = irq; 302 priv->base = addr; 303 priv->device = &pdev->dev; 304 priv->can.clock.freq = clk_get_rate(clk); 305 priv->priv = clk; 306 priv->type = id->driver_data; 307 308 platform_set_drvdata(pdev, dev); 309 SET_NETDEV_DEV(dev, &pdev->dev); 310 311 ret = register_c_can_dev(dev); 312 if (ret) { 313 dev_err(&pdev->dev, "registering %s failed (err=%d)\n", 314 KBUILD_MODNAME, ret); 315 goto exit_free_device; 316 } 317 318 dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n", 319 KBUILD_MODNAME, priv->base, dev->irq); 320 return 0; 321 322 exit_free_device: 323 free_c_can_dev(dev); 324 exit_iounmap: 325 iounmap(addr); 326 exit_release_mem: 327 release_mem_region(mem->start, resource_size(mem)); 328 exit_free_clk: 329 clk_put(clk); 330 exit: 331 dev_err(&pdev->dev, "probe failed\n"); 332 333 return ret; 334 } 335 336 static int c_can_plat_remove(struct platform_device *pdev) 337 { 338 struct net_device *dev = platform_get_drvdata(pdev); 339 struct c_can_priv *priv = netdev_priv(dev); 340 struct resource *mem; 341 342 unregister_c_can_dev(dev); 343 344 free_c_can_dev(dev); 345 iounmap(priv->base); 346 347 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 348 release_mem_region(mem->start, resource_size(mem)); 349 350 clk_put(priv->priv); 351 352 return 0; 353 } 354 355 #ifdef CONFIG_PM 356 static int c_can_suspend(struct platform_device *pdev, pm_message_t state) 357 { 358 int ret; 359 struct net_device *ndev = platform_get_drvdata(pdev); 360 struct c_can_priv *priv = netdev_priv(ndev); 361 362 if (priv->type != BOSCH_D_CAN) { 363 dev_warn(&pdev->dev, "Not supported\n"); 364 return 0; 365 } 366 367 if (netif_running(ndev)) { 368 netif_stop_queue(ndev); 369 netif_device_detach(ndev); 370 } 371 372 ret = c_can_power_down(ndev); 373 if (ret) { 374 netdev_err(ndev, "failed to enter power down mode\n"); 375 return ret; 376 } 377 378 priv->can.state = CAN_STATE_SLEEPING; 379 380 return 0; 381 } 382 383 static int c_can_resume(struct platform_device *pdev) 384 { 385 int ret; 386 struct net_device *ndev = platform_get_drvdata(pdev); 387 struct c_can_priv *priv = netdev_priv(ndev); 388 389 if (priv->type != BOSCH_D_CAN) { 390 dev_warn(&pdev->dev, "Not supported\n"); 391 return 0; 392 } 393 394 ret = c_can_power_up(ndev); 395 if (ret) { 396 netdev_err(ndev, "Still in power down mode\n"); 397 return ret; 398 } 399 400 priv->can.state = CAN_STATE_ERROR_ACTIVE; 401 402 if (netif_running(ndev)) { 403 netif_device_attach(ndev); 404 netif_start_queue(ndev); 405 } 406 407 return 0; 408 } 409 #else 410 #define c_can_suspend NULL 411 #define c_can_resume NULL 412 #endif 413 414 static struct platform_driver c_can_plat_driver = { 415 .driver = { 416 .name = KBUILD_MODNAME, 417 .owner = THIS_MODULE, 418 .of_match_table = c_can_of_table, 419 }, 420 .probe = c_can_plat_probe, 421 .remove = c_can_plat_remove, 422 .suspend = c_can_suspend, 423 .resume = c_can_resume, 424 .id_table = c_can_id_table, 425 }; 426 427 module_platform_driver(c_can_plat_driver); 428 429 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 430 MODULE_LICENSE("GPL v2"); 431 MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller"); 432